; -------------------------------------------------------------------------------- ; @Title: STM32U5 On-Chip Peripherals ; @Props: Released ; @Author: KOL, KWI, RSA, ADR, NEJ ; @Changelog: 2020-01-14 KOL ; 2020-04-06 KWI ; 2020-12-29 KWI ; 2021-02-22 KWI ; 2021-03-08 KWI ; 2021-12-06 RSA ; 2022-01-17 ADR ; 2023-09-19 NEJ ; 2024-01-24 NEJ ; @Manufacturer: STM - ST Microelectronics N.V. ; @Doc: Generated (TRACE32, build: 166176.), based on: ; STM32U535.svd (Ver. 1.0), STM32U545.svd (Ver. 1.0), ; STM32U575.svd (Ver. 1.4), STM32U585.svd (Ver. 1.4), ; STM32U595.svd (Ver. 1.0), STM32U599.svd (Ver. 1.0), ; STM32U5A5.svd (Ver. 1.0), STM32U5A9.svd (Ver. 2.0), ; STM32U5Fx.svd (Ver. 1.0), STM32U5Gx.svd (Ver. 1.0) ; @Core: Cortex-M33F ; @Chip: STM32U535CB, STM32U535CC, STM32U535CE, STM32U535JE ; STM32U535NC, STM32U535NE, STM32U535RB, STM32U535RC ; STM32U535RE, STM32U535VC, STM32U535VE, STM32U545CE ; STM32U545RE, STM32U545NE, STM32U545JE, STM32U545VE ; STM32U575AG, STM32U575AI, STM32U575CG, STM32U575CI ; STM32U575OG, STM32U575OI, STM32U575QG, STM32U575QI ; STM32U575RG, STM32U575RI, STM32U575VG, STM32U575VI ; STM32U575ZG, STM32U575ZI, STM32U585AI, STM32U585CI ; STM32U585OI, STM32U585QI, STM32U585RI, STM32U585VI ; STM32U585ZI, STM32U595AI, STM32U595AJ, STM32U595QI ; STM32U595QJ, STM32U595RI, STM32U595RJ, STM32U595VI ; STM32U595VJ, STM32U595ZI, STM32U595ZJ, STM32U599BJ ; STM32U599NI, STM32U599NJ, STM32U599VI, STM32U599VJ ; STM32U599ZI, STM32U599ZJ, STM32U5A5AJ, STM32U5A5QI ; STM32U5A5QJ, STM32U5A5RJ, STM32U5A5VJ, STM32U5A5ZJ ; STM32U5A9BJ, STM32U5A9NJ, STM32U5A9VJ, STM32U5A9ZJ ; STM32U5F7VJ, STM32U5F9BJ, STM32U5F9NJ, STM32U5F9VJ ; STM32U5F9ZJ, STM32U5G7VJ, STM32U5G9BJ, STM32U5G9NJ ; STM32U5G9VJ, STM32U5G9ZJ ; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perstm32u5.per 17394 2024-01-25 15:06:22Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M33F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes" bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes" bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes" textline " " bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes" group.long 0x0C++0x0F line.long 0x00 "CPPWR,Coprocessor Power Control Register" bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only" textline " " bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted" textline " " bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only" textline " " bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted" textline " " bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only" textline " " bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted" line.long 0x04 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x08 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x0C "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPUID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Reserved,Patch 2,?..." group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control and State Register" setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" textline " " bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure" rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled" rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending" textline " " hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt" rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent" hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key" rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian" bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled" bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration and Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored" bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored" bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled" line.long 0x14 "SHPR1,System Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV" hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending" bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending" bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled" textline " " bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active" bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active" textline " " bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active" bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "UFSR,Usage Fault Status Register" eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error" textline " " eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error" textline " " eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x03 line.long 0x00 "HFSR,HardFault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full" if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48) group.long 0xD8C++0x03 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled" bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled" bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled" bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled" bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled" bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled" bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled" else hgroup.long 0xD8C++0x03 hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)" endif wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Triggered Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended" tree "Memory System" width 10. rgroup.long 0xD78++0x03 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest" bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..." textline " " bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..." bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..." bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..." textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..." bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..." bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..." textline " " bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000) rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..." bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..." textline " " bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..." endif rgroup.long 0xD80++0x03 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported" bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported" hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512" group.long 0xD84++0x03 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..." bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction" wgroup.long 0xF50++0x03 line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU" wgroup.long 0xF58++0x23 line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU" line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC" line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way" hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU" line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC" line.long 0x14 "DCCSW,D-Cache Clean by Set-Way" hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC" line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way" hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x20 "BPIALL,Branch Predictor Invalidate All" tree.end tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..." rgroup.long 0xD4C++0x03 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..." rgroup.long 0xD54++0x03 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD5C++0x03 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..." rgroup.long 0xD60++0x03 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." rgroup.long 0xD64++0x03 line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..." rgroup.long 0xD68++0x03 line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..." textline " " bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..." bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..." rgroup.long 0xD6C++0x03 line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..." textline " " bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..." rgroup.long 0xD70++0x03 line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..." bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..." bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..." textline " " bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..." bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..." tree.end tree "CoreSight Identification Registers" base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 11. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFE0++0x0F line.long 0x00 "DPIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "DPIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "DPIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "DPIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "DCIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DCIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "DCIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0c "DCIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15" endif tree.end newline group.long 0xDC0++0x07 line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1" bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Security Attribution Unit (SAU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. group.long 0xDD0++0x03 line.long 0x00 "SAU_CTRL,SAU Control Register" bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure" bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled" rgroup.long 0xDD4++0x03 line.long 0x00 "SAU_TYPE,SAU Type Register" bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..." group.long 0xDD8++0x03 line.long 0x00 "SAU_RNR,SAU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR" tree.close "SAU regions" if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0) if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0 group.long 0xDDC++0x03 "Region 0" saveout 0xDD8 %l 0x0 line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x0 line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 0 (not implemented)" saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1 group.long 0xDDC++0x03 "Region 1" saveout 0xDD8 %l 0x1 line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x1 line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 1 (not implemented)" saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2 group.long 0xDDC++0x03 "Region 2" saveout 0xDD8 %l 0x2 line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x2 line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 2 (not implemented)" saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3 group.long 0xDDC++0x03 "Region 3" saveout 0xDD8 %l 0x3 line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x3 line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 3 (not implemented)" saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4 group.long 0xDDC++0x03 "Region 4" saveout 0xDD8 %l 0x4 line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x4 line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 4 (not implemented)" saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5 group.long 0xDDC++0x03 "Region 5" saveout 0xDD8 %l 0x5 line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x5 line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 5 (not implemented)" saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6 group.long 0xDDC++0x03 "Region 6" saveout 0xDD8 %l 0x6 line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x6 line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 6 (not implemented)" saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7 group.long 0xDDC++0x03 "Region 7" saveout 0xDD8 %l 0x7 line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x7 line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 7 (not implemented)" saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" endif else hgroup.long 0xDDC++0x03 "Region 0 (not accessible)" saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" hgroup.long 0xDDC++0x03 "Region 1 (not accessible)" saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" hgroup.long 0xDDC++0x03 "Region 2 (not accessible)" saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" hgroup.long 0xDDC++0x03 "Region 3 (not accessible)" saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" hgroup.long 0xDDC++0x03 "Region 4 (not accessible)" saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" hgroup.long 0xDDC++0x03 "Region 5 (not accessible)" saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" hgroup.long 0xDDC++0x03 "Region 6 (not accessible)" saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" hgroup.long 0xDDC++0x03 "Region 7 (not accessible)" saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" endif tree.end group.long 0xDE4++0x03 line.long 0x00 "SFSR,Secure Fault Status Register" bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred" bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid" bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred" bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred" bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred" bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred" group.long 0xDE8++0x03 line.long 0x00 "SFAR,Secure Fault Address Register" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. group.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511" width 24. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x104++0x03 line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x104++0x03 hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x108++0x03 line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x108++0x03 hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x10C++0x03 line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x10C++0x03 hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x110++0x03 line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x110++0x03 hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x114++0x03 line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x114++0x03 hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x118++0x03 line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x118++0x03 hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x11C++0x03 line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x11C++0x03 hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x120++0x03 line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x120++0x03 hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x124++0x03 line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x124++0x03 hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x128++0x03 line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x128++0x03 hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x12C++0x03 line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x12C++0x03 hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x130++0x03 line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x130++0x03 hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x134++0x03 line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x134++0x03 hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x138++0x03 line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x138++0x03 hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F) group.long 0x13C++0x03 line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x13C++0x03 hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register" endif tree.end width 24. tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x204++0x03 line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x204++0x03 hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x208++0x03 line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x208++0x03 hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x20C++0x03 line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x20C++0x03 hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x210++0x03 line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x210++0x03 hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x214++0x03 line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x214++0x03 hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x218++0x03 line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x218++0x03 hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x21C++0x03 line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x21C++0x03 hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x220++0x03 line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x220++0x03 hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x224++0x03 line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x224++0x03 hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x228++0x03 line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x228++0x03 hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x22C++0x03 line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x22C++0x03 hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x230++0x03 line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x230++0x03 hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x234++0x03 line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x234++0x03 hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x238++0x03 line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x238++0x03 hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F) group.long 0x23C++0x03 line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x23C++0x03 hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register" endif tree.end width 11. tree "Interrupt Active Bit Registers" rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE0,Active Bit Register 0" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) rgroup.long 0x304++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x304++0x03 hide.long 0x00 "ACTIVE1,Active Bit Register 1" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) rgroup.long 0x308++0x03 line.long 0x00 "ACTIVE2,Active Bit Register 2" bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x308++0x03 hide.long 0x00 "ACTIVE2,Active Bit Register 2" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) rgroup.long 0x30C++0x03 line.long 0x00 "ACTIVE3,Active Bit Register 3" bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x30C++0x03 hide.long 0x00 "ACTIVE3,Active Bit Register 3" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) rgroup.long 0x310++0x03 line.long 0x00 "ACTIVE4,Active Bit Register 4" bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x310++0x03 hide.long 0x00 "ACTIVE4,Active Bit Register 4" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) rgroup.long 0x314++0x03 line.long 0x00 "ACTIVE5,Active Bit Register 5" bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x314++0x03 hide.long 0x00 "ACTIVE5,Active Bit Register 5" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) rgroup.long 0x318++0x03 line.long 0x00 "ACTIVE6,Active Bit Register 6" bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x318++0x03 hide.long 0x00 "ACTIVE6,Active Bit Register 6" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) rgroup.long 0x31C++0x03 line.long 0x00 "ACTIVE7,Active Bit Register 7" bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x31C++0x03 hide.long 0x00 "ACTIVE7,Active Bit Register 7" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) rgroup.long 0x320++0x03 line.long 0x00 "ACTIVE8,Active Bit Register 8" bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x320++0x03 hide.long 0x00 "ACTIVE8,Active Bit Register 8" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) rgroup.long 0x324++0x03 line.long 0x00 "ACTIVE9,Active Bit Register 9" bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x324++0x03 hide.long 0x00 "ACTIVE9,Active Bit Register 9" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) rgroup.long 0x328++0x03 line.long 0x00 "ACTIVE10,Active Bit Register 10" bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x328++0x03 hide.long 0x00 "ACTIVE10,Active Bit Register 10" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) rgroup.long 0x32C++0x03 line.long 0x00 "ACTIVE11,Active Bit Register 11" bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x32C++0x03 hide.long 0x00 "ACTIVE11,Active Bit Register 11" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) rgroup.long 0x330++0x03 line.long 0x00 "ACTIVE12,Active Bit Register 12" bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x330++0x03 hide.long 0x00 "ACTIVE12,Active Bit Register 12" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) rgroup.long 0x334++0x03 line.long 0x00 "ACTIVE13,Active Bit Register 13" bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x334++0x03 hide.long 0x00 "ACTIVE13,Active Bit Register 13" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) rgroup.long 0x338++0x03 line.long 0x00 "ACTIVE14,Active Bit Register 14" bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x338++0x03 hide.long 0x00 "ACTIVE14,Active Bit Register 14" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F) rgroup.long 0x33C++0x03 line.long 0x00 "ACTIVE15,Active Bit Register 15" bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x33C++0x03 hide.long 0x00 "ACTIVE15,Active Bit Register 15" endif tree.end width 13. tree "Interrupt Target Non-Secure Registers" group.long 0x380++0x03 line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0" bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x384++0x03 line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure" else hgroup.long 0x384++0x03 hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x388++0x03 line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure" else hgroup.long 0x388++0x03 hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x38C++0x03 line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure" else hgroup.long 0x38C++0x03 hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x390++0x03 line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure" else hgroup.long 0x390++0x03 hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x394++0x03 line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure" else hgroup.long 0x394++0x03 hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x398++0x03 line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure" else hgroup.long 0x398++0x03 hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x39C++0x03 line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure" else hgroup.long 0x39C++0x03 hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x3A0++0x03 line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure" else hgroup.long 0x3A0++0x03 hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x3A4++0x03 line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure" else hgroup.long 0x3A4++0x03 hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x3A8++0x03 line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure" else hgroup.long 0x3A8++0x03 hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x3AC++0x03 line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure" else hgroup.long 0x3AC++0x03 hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x3B0++0x03 line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure" else hgroup.long 0x3B0++0x03 hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x3B4++0x03 line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure" else hgroup.long 0x3B4++0x03 hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x3B8++0x03 line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure" else hgroup.long 0x3B8++0x03 hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F) group.long 0x3BC++0x03 line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15" bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure" else hgroup.long 0x3BC++0x03 hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15" endif tree.end tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x420++0x1F line.long 0x0 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x4 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x8 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0xC "IPR11,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x10 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x14 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x18 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x1C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" else hgroup.long 0x420++0x1F hide.long 0x0 "IPR8,Interrupt Priority Register" hide.long 0x4 "IPR9,Interrupt Priority Register" hide.long 0x8 "IPR10,Interrupt Priority Register" hide.long 0xC "IPR11,Interrupt Priority Register" hide.long 0x10 "IPR12,Interrupt Priority Register" hide.long 0x14 "IPR13,Interrupt Priority Register" hide.long 0x18 "IPR14,Interrupt Priority Register" hide.long 0x1C "IPR15,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x440++0x1F line.long 0x0 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x4 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x8 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0xC "IPR19,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x10 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x14 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x18 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x1C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" else hgroup.long 0x440++0x1F hide.long 0x0 "IPR16,Interrupt Priority Register" hide.long 0x4 "IPR17,Interrupt Priority Register" hide.long 0x8 "IPR18,Interrupt Priority Register" hide.long 0xC "IPR19,Interrupt Priority Register" hide.long 0x10 "IPR20,Interrupt Priority Register" hide.long 0x14 "IPR21,Interrupt Priority Register" hide.long 0x18 "IPR22,Interrupt Priority Register" hide.long 0x1C "IPR23,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x460++0x1F line.long 0x0 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x4 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x8 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0xC "IPR27,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x10 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x14 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x18 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x1C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" else hgroup.long 0x460++0x1F hide.long 0x0 "IPR24,Interrupt Priority Register" hide.long 0x4 "IPR25,Interrupt Priority Register" hide.long 0x8 "IPR26,Interrupt Priority Register" hide.long 0xC "IPR27,Interrupt Priority Register" hide.long 0x10 "IPR28,Interrupt Priority Register" hide.long 0x14 "IPR29,Interrupt Priority Register" hide.long 0x18 "IPR30,Interrupt Priority Register" hide.long 0x1C "IPR31,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x480++0x1F line.long 0x0 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x4 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x8 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0xC "IPR35,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x10 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x14 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x18 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x1C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" else hgroup.long 0x480++0x1F hide.long 0x0 "IPR32,Interrupt Priority Register" hide.long 0x4 "IPR33,Interrupt Priority Register" hide.long 0x8 "IPR34,Interrupt Priority Register" hide.long 0xC "IPR35,Interrupt Priority Register" hide.long 0x10 "IPR36,Interrupt Priority Register" hide.long 0x14 "IPR37,Interrupt Priority Register" hide.long 0x18 "IPR38,Interrupt Priority Register" hide.long 0x1C "IPR39,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x4A0++0x1F line.long 0x0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0x4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0x8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0x10 "IPR44,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0x14 "IPR45,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0x18 "IPR46,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0x1C "IPR47,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" else hgroup.long 0x4A0++0x1F hide.long 0x0 "IPR40,Interrupt Priority Register" hide.long 0x4 "IPR41,Interrupt Priority Register" hide.long 0x8 "IPR42,Interrupt Priority Register" hide.long 0xC "IPR43,Interrupt Priority Register" hide.long 0x10 "IPR44,Interrupt Priority Register" hide.long 0x14 "IPR45,Interrupt Priority Register" hide.long 0x18 "IPR46,Interrupt Priority Register" hide.long 0x1C "IPR47,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x4C0++0x1F line.long 0x0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0x4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0x8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0x10 "IPR52,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0x14 "IPR53,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0x18 "IPR54,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0x1C "IPR55,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" else hgroup.long 0x4C0++0x1F hide.long 0x0 "IPR48,Interrupt Priority Register" hide.long 0x4 "IPR49,Interrupt Priority Register" hide.long 0x8 "IPR50,Interrupt Priority Register" hide.long 0xC "IPR51,Interrupt Priority Register" hide.long 0x10 "IPR52,Interrupt Priority Register" hide.long 0x14 "IPR53,Interrupt Priority Register" hide.long 0x18 "IPR54,Interrupt Priority Register" hide.long 0x1C "IPR55,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x4E0++0x1F line.long 0x0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0x4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0x8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" line.long 0x10 "IPR60,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority" line.long 0x14 "IPR61,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority" line.long 0x18 "IPR62,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority" line.long 0x1C "IPR63,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority" else hgroup.long 0x4E0++0x1F hide.long 0x0 "IPR56,Interrupt Priority Register" hide.long 0x4 "IPR57,Interrupt Priority Register" hide.long 0x8 "IPR58,Interrupt Priority Register" hide.long 0xC "IPR59,Interrupt Priority Register" hide.long 0x10 "IPR60,Interrupt Priority Register" hide.long 0x14 "IPR61,Interrupt Priority Register" hide.long 0x18 "IPR62,Interrupt Priority Register" hide.long 0x1C "IPR63,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x500++0x1F line.long 0x0 "IPR64,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority" line.long 0x4 "IPR65,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority" line.long 0x8 "IPR66,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority" line.long 0xC "IPR67,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority" line.long 0x10 "IPR68,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority" line.long 0x14 "IPR69,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority" line.long 0x18 "IPR70,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority" line.long 0x1C "IPR71,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority" else hgroup.long 0x500++0x1F hide.long 0x0 "IPR64,Interrupt Priority Register" hide.long 0x4 "IPR65,Interrupt Priority Register" hide.long 0x8 "IPR66,Interrupt Priority Register" hide.long 0xC "IPR67,Interrupt Priority Register" hide.long 0x10 "IPR68,Interrupt Priority Register" hide.long 0x14 "IPR69,Interrupt Priority Register" hide.long 0x18 "IPR70,Interrupt Priority Register" hide.long 0x1C "IPR71,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x520++0x1F line.long 0x0 "IPR72,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority" line.long 0x4 "IPR73,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority" line.long 0x8 "IPR74,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority" line.long 0xC "IPR75,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority" line.long 0x10 "IPR76,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority" line.long 0x14 "IPR77,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority" line.long 0x18 "IPR78,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority" line.long 0x1C "IPR79,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority" else hgroup.long 0x520++0x1F hide.long 0x0 "IPR72,Interrupt Priority Register" hide.long 0x4 "IPR73,Interrupt Priority Register" hide.long 0x8 "IPR74,Interrupt Priority Register" hide.long 0xC "IPR75,Interrupt Priority Register" hide.long 0x10 "IPR76,Interrupt Priority Register" hide.long 0x14 "IPR77,Interrupt Priority Register" hide.long 0x18 "IPR78,Interrupt Priority Register" hide.long 0x1C "IPR79,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x540++0x1F line.long 0x0 "IPR80,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority" line.long 0x4 "IPR81,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority" line.long 0x8 "IPR82,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority" line.long 0xC "IPR83,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority" line.long 0x10 "IPR84,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority" line.long 0x14 "IPR85,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority" line.long 0x18 "IPR86,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority" line.long 0x1C "IPR87,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority" else hgroup.long 0x540++0x1F hide.long 0x0 "IPR80,Interrupt Priority Register" hide.long 0x4 "IPR81,Interrupt Priority Register" hide.long 0x8 "IPR82,Interrupt Priority Register" hide.long 0xC "IPR83,Interrupt Priority Register" hide.long 0x10 "IPR84,Interrupt Priority Register" hide.long 0x14 "IPR85,Interrupt Priority Register" hide.long 0x18 "IPR86,Interrupt Priority Register" hide.long 0x1C "IPR87,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x560++0x1F line.long 0x0 "IPR88,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority" line.long 0x4 "IPR89,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority" line.long 0x8 "IPR90,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority" line.long 0xC "IPR91,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority" line.long 0x10 "IPR92,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority" line.long 0x14 "IPR93,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority" line.long 0x18 "IPR94,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority" line.long 0x1C "IPR95,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority" else hgroup.long 0x560++0x1F hide.long 0x0 "IPR88,Interrupt Priority Register" hide.long 0x4 "IPR89,Interrupt Priority Register" hide.long 0x8 "IPR90,Interrupt Priority Register" hide.long 0xC "IPR91,Interrupt Priority Register" hide.long 0x10 "IPR92,Interrupt Priority Register" hide.long 0x14 "IPR93,Interrupt Priority Register" hide.long 0x18 "IPR94,Interrupt Priority Register" hide.long 0x1C "IPR95,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x580++0x1F line.long 0x0 "IPR96,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority" line.long 0x4 "IPR97,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority" line.long 0x8 "IPR98,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority" line.long 0xC "IPR99,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority" line.long 0x10 "IPR100,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority" line.long 0x14 "IPR101,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority" line.long 0x18 "IPR102,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority" line.long 0x1C "IPR103,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority" else hgroup.long 0x580++0x1F hide.long 0x0 "IPR96,Interrupt Priority Register" hide.long 0x4 "IPR97,Interrupt Priority Register" hide.long 0x8 "IPR98,Interrupt Priority Register" hide.long 0xC "IPR99,Interrupt Priority Register" hide.long 0x10 "IPR100,Interrupt Priority Register" hide.long 0x14 "IPR101,Interrupt Priority Register" hide.long 0x18 "IPR102,Interrupt Priority Register" hide.long 0x1C "IPR103,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x5A0++0x1F line.long 0x0 "IPR104,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority" line.long 0x4 "IPR105,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority" line.long 0x8 "IPR106,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority" line.long 0xC "IPR107,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority" line.long 0x10 "IPR108,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority" line.long 0x14 "IPR109,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority" line.long 0x18 "IPR110,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority" line.long 0x1C "IPR111,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority" else hgroup.long 0x5A0++0x1F hide.long 0x0 "IPR104,Interrupt Priority Register" hide.long 0x4 "IPR105,Interrupt Priority Register" hide.long 0x8 "IPR106,Interrupt Priority Register" hide.long 0xC "IPR107,Interrupt Priority Register" hide.long 0x10 "IPR108,Interrupt Priority Register" hide.long 0x14 "IPR109,Interrupt Priority Register" hide.long 0x18 "IPR110,Interrupt Priority Register" hide.long 0x1C "IPR111,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x5C0++0x1F line.long 0x0 "IPR112,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority" line.long 0x4 "IPR113,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority" line.long 0x8 "IPR114,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority" line.long 0xC "IPR115,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority" line.long 0x10 "IPR116,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority" line.long 0x14 "IPR117,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority" line.long 0x18 "IPR118,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority" line.long 0x1C "IPR119,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority" else hgroup.long 0x5C0++0x1F hide.long 0x0 "IPR112,Interrupt Priority Register" hide.long 0x4 "IPR113,Interrupt Priority Register" hide.long 0x8 "IPR114,Interrupt Priority Register" hide.long 0xC "IPR115,Interrupt Priority Register" hide.long 0x10 "IPR116,Interrupt Priority Register" hide.long 0x14 "IPR117,Interrupt Priority Register" hide.long 0x18 "IPR118,Interrupt Priority Register" hide.long 0x1C "IPR119,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif (CORENAME()=="CORTEXM33F") tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored" newline bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled" bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only" bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled" newline bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able" bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" newline bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able" bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" newline bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure" newline bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" newline bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x0B line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." newline bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." newline bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..." line.long 0x08 "MVFR2,Media and FP Feature Register 2" bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 13. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" newline bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" newline bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif newline group.long 0xE04++0x07 line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register" bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN" bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN" line.long 0x04 "DSCSR,Debug Security Control and Status Register" bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure" bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure" bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled" rgroup.long 0xFB8++0x03 line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented" bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1" bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented" bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1" newline bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented" bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1" bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented" bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 12. group.long 0x00++0x03 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline " " if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000) rgroup.long 0x04++0x03 line.long 0x00 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported" hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address" else rgroup.long 0x04++0x03 line.long 0x00 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif tree "CoreSight Identification Registers" width 12. rgroup.long 0xFCC++0x03 line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type" hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFE0++0x0F line.long 0x00 "FP_PIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "FP_PIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "FP_PIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "FP_PIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "FP_CIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "FP_CIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0c "FP_CIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0b else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 16. group.long 0x00++0x03 line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..." rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" textline " " rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000) group.long 0x04++0x03 line.long 0x00 "DWT_CYCCNT,Cycle Count register" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000) group.long 0x08++0x17 line.long 0x00 "DWT_CPICNT,CPI Count register" hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter" line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x10 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter" line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register" hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter" endif rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" endif group.long (0x20+0x08)++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" endif group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" endif group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" endif group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" tree "CoreSight Identification Registers" width 13. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFCC++0x03 line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register" hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type" hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type" rgroup.long 0xFE0++0x0F line.long 0x00 "DWT_PIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "DWT_PIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "DWT_PIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "DWT_PIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DWT_CIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "DWT_CIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0c "DWT_CIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0b else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ADC (Analog-to-Digital Converter)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "ADC1" base ad:0x42028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" newline bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" newline bitfld.long 0x0 6. "JEOS,JEOS" "0,1" bitfld.long 0x0 5. "JEOC,JEOC" "0,1" newline bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" newline bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 12. "LDORDY,ADC voltage regulator ready" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" newline bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" newline bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" newline bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" newline bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" endif line.long 0x4 "ADC_IER,ADC interrupt enable register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" newline bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" newline bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" newline bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" newline bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." newline bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." newline bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." endif line.long 0x8 "ADC_CR,ADC control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" newline bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" newline bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" newline rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" newline rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in deep-power down,1: ADC in Deep-power-down (default reset state)" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled." newline hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,Calibration factor" endif sif (cpuis("STM32U575*")) bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0: Writing ADCAL launches a calibration without the..,1: Writing ADCAL launches a calibration with he.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." newline bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." newline bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." endif line.long 0xC "ADC_CFGR1,ADC configuration register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" newline bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" newline bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" newline bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" newline bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" newline bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" endif sif (cpuis("STM32U575*")) hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" newline bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" endif sif (cpuis("STM32U575*")) bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" newline bitfld.long 0xC 13. "CONT,Single / continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" bitfld.long 0xC 12. "OVRMOD,Overrun Mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." newline bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" newline endif sif (cpuis("STM32U575*")) bitfld.long 0xC 2.--3. "RES,Data resolution" "0: 14 bits,1: 12 bits,2: 10 bits,3: 8bits" endif line.long 0x10 "ADC_CFGR2,ADC configuration register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" newline hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" newline bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" bitfld.long 0x10 13. "BULB,BULB" "0,1" newline bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" newline hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" newline bitfld.long 0x10 27. "LFTRIG,Low-frequency trigger" "0: Low-frequency trigger mode disabled,1: Low-frequency trigger mode enabled" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" newline bitfld.long 0x10 15. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" bitfld.long 0x10 14. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." newline bitfld.long 0x10 13. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." endif sif (cpuis("STM32U575*")) bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." newline bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling right shift" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected oversampling disabled,1: Injected oversampling enabled" endif line.long 0x14 "ADC_SMPR1,ADC sample time register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" endif line.long 0x18 "ADC_SMPR2,ADC sample time register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" endif line.long 0x1C "ADC_PCSEL,ADC channel preselection register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" newline bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" newline bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" newline bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" newline bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" newline bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" newline bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" newline bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" newline bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x1C 19. "PCSEL19,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 18. "PCSEL18,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 17. "PCSEL17,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 16. "PCSEL16,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 15. "PCSEL15,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 14. "PCSEL14,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 13. "PCSEL13,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 12. "PCSEL12,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 11. "PCSEL11,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 10. "PCSEL10,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 9. "PCSEL9,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 8. "PCSEL8,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 7. "PCSEL7,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 6. "PCSEL6,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 5. "PCSEL5,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 4. "PCSEL4,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 3. "PCSEL3,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 2. "PCSEL2,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 1. "PCSEL1,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." endif group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 0.--3. 1. "L,L" endif line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "RDATA,Regular data converted" endif group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" newline sif (cpuis("STM32U575*")) bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" newline bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" endif group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" sif (cpuis("STM32U575*")) bitfld.long 0x0 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x0 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x0 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" newline bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" endif hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" sif (cpuis("STM32U575*")) bitfld.long 0x4 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x4 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x4 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" newline bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" endif hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" sif (cpuis("STM32U575*")) bitfld.long 0x8 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x8 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x8 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" newline bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" endif hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" sif (cpuis("STM32U575*")) bitfld.long 0xC 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0xC 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0xC 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" newline bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" endif hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x10 31. "GCOMP,Gain compensation mode" "0: Regular ADC operating mode,1: Gain compensation enabled and applied on all.." endif rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" endif line.long 0x4 "ADC_JDR2,ADC injected data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" endif line.long 0x8 "ADC_JDR3,ADC injected data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" endif line.long 0xC "ADC_JDR4,ADC injected data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" endif group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32U575*")) bitfld.long 0xC 29.--31. "AWDFILT1,Analog watchdog filtering parameter" "0: No filtering,1: two consecutive detection generates an AWDx flag..,?,?,?,?,?,7: Eight consecutive detection generates an AWDx.." newline endif hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" newline rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x24 25. "CAPTURE_COEF,Calibration factor capture enable bit" "0: Calibration factor not captured,1: Calibration factor available in CALFACT[31:0].." newline bitfld.long 0x24 24. "LATCH_COEF,Calibration factor latch enable bit" "0: No effect,1: Calibration factor latched in the analog block.." endif sif (cpuis("STM32U575*")) rbitfld.long 0x24 16. "VALIDITY,Delayed write access status bit" "0: Operation still in progress,1: Operation complete" newline endif hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" sif (cpuis("STM32U575*")) group.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" endif sif (cpuis("STM32U575*")) group.long 0x80++0x3 line.long 0x0 "ADC_JDR1,ADC injected data register" endif sif (cpuis("STM32U575*")) group.long 0x84++0x3 line.long 0x0 "ADC_JDR2,ADC injected data register" endif sif (cpuis("STM32U575*")) group.long 0x88++0x3 line.long 0x0 "ADC_JDR3,ADC injected data register" endif sif (cpuis("STM32U575*")) group.long 0x8C++0x3 line.long 0x0 "ADC_JDR4,ADC injected data register" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_ADC1" base ad:0x52028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" newline bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" newline bitfld.long 0x0 6. "JEOS,JEOS" "0,1" bitfld.long 0x0 5. "JEOC,JEOC" "0,1" newline bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" newline bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 12. "LDORDY,ADC voltage regulator ready" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" newline bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" newline bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" newline bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" newline bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" endif line.long 0x4 "ADC_IER,ADC interrupt enable register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" newline bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" newline bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" newline bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" newline bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." newline bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." newline bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." endif line.long 0x8 "ADC_CR,ADC control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" newline bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" newline bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" newline rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" newline rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in deep-power down,1: ADC in Deep-power-down (default reset state)" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled." newline hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,Calibration factor" endif sif (cpuis("STM32U575*")) bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0: Writing ADCAL launches a calibration without the..,1: Writing ADCAL launches a calibration with he.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." newline bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." newline bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." endif line.long 0xC "ADC_CFGR1,ADC configuration register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" newline bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" newline bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" newline bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" newline bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" newline bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" endif sif (cpuis("STM32U575*")) hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" newline bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" endif sif (cpuis("STM32U575*")) bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" newline bitfld.long 0xC 13. "CONT,Single / continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" bitfld.long 0xC 12. "OVRMOD,Overrun Mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." newline bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" newline endif sif (cpuis("STM32U575*")) bitfld.long 0xC 2.--3. "RES,Data resolution" "0: 14 bits,1: 12 bits,2: 10 bits,3: 8bits" endif line.long 0x10 "ADC_CFGR2,ADC configuration register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" newline hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" newline bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" bitfld.long 0x10 13. "BULB,BULB" "0,1" newline bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" newline hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" newline bitfld.long 0x10 27. "LFTRIG,Low-frequency trigger" "0: Low-frequency trigger mode disabled,1: Low-frequency trigger mode enabled" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" newline bitfld.long 0x10 15. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" bitfld.long 0x10 14. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." newline bitfld.long 0x10 13. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." endif sif (cpuis("STM32U575*")) bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." newline bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling right shift" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected oversampling disabled,1: Injected oversampling enabled" endif line.long 0x14 "ADC_SMPR1,ADC sample time register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" endif line.long 0x18 "ADC_SMPR2,ADC sample time register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" endif line.long 0x1C "ADC_PCSEL,ADC channel preselection register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" newline bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" newline bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" newline bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" newline bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" newline bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" newline bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" newline bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" newline bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x1C 19. "PCSEL19,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 18. "PCSEL18,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 17. "PCSEL17,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 16. "PCSEL16,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 15. "PCSEL15,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 14. "PCSEL14,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 13. "PCSEL13,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 12. "PCSEL12,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 11. "PCSEL11,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 10. "PCSEL10,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 9. "PCSEL9,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 8. "PCSEL8,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 7. "PCSEL7,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 6. "PCSEL6,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 5. "PCSEL5,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 4. "PCSEL4,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 3. "PCSEL3,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 2. "PCSEL2,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 1. "PCSEL1,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." endif group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 0.--3. 1. "L,L" endif line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "RDATA,Regular data converted" endif group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" newline sif (cpuis("STM32U575*")) bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" newline bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" endif group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" sif (cpuis("STM32U575*")) bitfld.long 0x0 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x0 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x0 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" newline bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" endif hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" sif (cpuis("STM32U575*")) bitfld.long 0x4 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x4 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x4 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" newline bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" endif hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" sif (cpuis("STM32U575*")) bitfld.long 0x8 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x8 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x8 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" newline bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" endif hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" sif (cpuis("STM32U575*")) bitfld.long 0xC 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0xC 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0xC 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" newline bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" endif hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x10 31. "GCOMP,Gain compensation mode" "0: Regular ADC operating mode,1: Gain compensation enabled and applied on all.." endif rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" endif line.long 0x4 "ADC_JDR2,ADC injected data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" endif line.long 0x8 "ADC_JDR3,ADC injected data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" endif line.long 0xC "ADC_JDR4,ADC injected data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" endif sif (cpuis("STM32U575*")) hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" endif group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32U575*")) bitfld.long 0xC 29.--31. "AWDFILT1,Analog watchdog filtering parameter" "0: No filtering,1: two consecutive detection generates an AWDx flag..,?,?,?,?,?,7: Eight consecutive detection generates an AWDx.." newline endif hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" newline rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x24 25. "CAPTURE_COEF,Calibration factor capture enable bit" "0: Calibration factor not captured,1: Calibration factor available in CALFACT[31:0].." newline bitfld.long 0x24 24. "LATCH_COEF,Calibration factor latch enable bit" "0: No effect,1: Calibration factor latched in the analog block.." endif sif (cpuis("STM32U575*")) rbitfld.long 0x24 16. "VALIDITY,Delayed write access status bit" "0: Operation still in progress,1: Operation complete" newline endif hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" sif (cpuis("STM32U575*")) group.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" endif sif (cpuis("STM32U575*")) group.long 0x80++0x3 line.long 0x0 "ADC_JDR1,ADC injected data register" endif sif (cpuis("STM32U575*")) group.long 0x84++0x3 line.long 0x0 "ADC_JDR2,ADC injected data register" endif sif (cpuis("STM32U575*")) group.long 0x88++0x3 line.long 0x0 "ADC_JDR3,ADC injected data register" endif sif (cpuis("STM32U575*")) group.long 0x8C++0x3 line.long 0x0 "ADC_JDR4,ADC injected data register" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "ADC12_Common" base ad:0x42028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end tree "SEC_ADC12_Common" base ad:0x52028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "ADC4" base ad:0x46021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" endif sif (cpuis("STM32U575*")) group.long 0xC4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" endif group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 23. "VSENSESEL,VSENSESEL" "0,1" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 23. "TSEN,TSEN" "0,1" endif bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_ADC4" base ad:0x56021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" endif sif (cpuis("STM32U575*")) group.long 0xC4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" endif group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 23. "VSENSESEL,VSENSESEL" "0,1" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 23. "TSEN,TSEN" "0,1" endif bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end endif sif (cpuis("STM32U575*")) tree "ADC12" base ad:0x42028300 group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" tree.end tree "SEC_ADC12" base ad:0x52028300 group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" tree.end endif sif (cpuis("STM32U585*")) tree "ADC1" base ad:0x42028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,ADC voltage regulator ready" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled" bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" newline bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" newline bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" newline bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" newline bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" newline bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" newline bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." newline bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." newline bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.." bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in deep-power down,1: ADC in Deep-power-down (default reset state)" newline bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled." hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,Calibration factor" newline bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0: Writing ADCAL launches a calibration without the..,1: Writing ADCAL launches a calibration with he.." bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." newline bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." newline bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." newline bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" newline bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" newline bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" bitfld.long 0xC 13. "CONT,Single / continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" newline bitfld.long 0xC 12. "OVRMOD,Overrun Mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" bitfld.long 0xC 2.--3. "RES,Data resolution" "0: 14 bits,1: 12 bits,2: 10 bits,3: 8bits" newline bitfld.long 0xC 0.--1. "DMNGT,Data management configuration" "0: Regular conversion data stored in DR only,1: DMA One -shot mode selected,2: MDF mode selected,3: DMA Circular mode selected" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" bitfld.long 0x10 27. "LFTRIG,Low-frequency trigger" "0: Low-frequency trigger mode disabled,1: Low-frequency trigger mode enabled" newline hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 15. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" newline bitfld.long 0x10 14. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." bitfld.long 0x10 13. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." newline bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." newline hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling right shift" bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected oversampling disabled,1: Injected oversampling enabled" newline bitfld.long 0x10 0. "ROVSE,Regular Oversampling Enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 18. "PCSEL18,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 17. "PCSEL17,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 16. "PCSEL16,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 15. "PCSEL15,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 14. "PCSEL14,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 13. "PCSEL13,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 12. "PCSEL12,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 11. "PCSEL11,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 10. "PCSEL10,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 9. "PCSEL9,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 8. "PCSEL8,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 7. "PCSEL7,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 6. "PCSEL6,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 5. "PCSEL5,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 4. "PCSEL4,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 3. "PCSEL3,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 2. "PCSEL2,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 1. "PCSEL1,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 0. "PCSEL0,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,Regular data converted" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x0 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x0 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x0 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x4 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x4 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x4 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x8 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x8 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x8 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0xC 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0xC 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0xC 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,Gain compensation mode" "0: Regular ADC operating mode,1: Gain compensation enabled and applied on all.." hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,Gain compensation coefficient" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,Analog watchdog 3 channel selection" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,Analog watchdog 1 lower threshold" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,Analog watchdog filtering parameter" "0: No filtering,1: two consecutive detection generates an AWDx flag..,?,?,?,?,?,7: Eight consecutive detection generates an AWDx.." hexmask.long 0xC 0.--24. 1. "HTR1,Analog watchdog 1 higher threshold" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,Analog watchdog 2 lower threshold" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,Analog watchdog 2 higher threshold" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,Analog watchdog 3 lower threshold" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,Analog watchdog 3 higher threshold" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,Differential mode for channels 19 to 0" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,Calibration factor capture enable bit" "0: Calibration factor not captured,1: Calibration factor available in CALFACT[31:0].." bitfld.long 0x24 24. "LATCH_COEF,Calibration factor latch enable bit" "0: No effect,1: Calibration factor latched in the analog block.." newline rbitfld.long 0x24 16. "VALIDITY,Delayed write access status bit" "0: Operation still in progress,1: Operation complete" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,Delayed write access data" newline hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,Delayed write access address" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,Linearity or offset calibration factor" tree.end tree "SEC_ADC1" base ad:0x52028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,ADC voltage regulator ready" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled" bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" newline bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" newline bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" newline bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" newline bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" newline bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" newline bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." newline bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." newline bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.." bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in deep-power down,1: ADC in Deep-power-down (default reset state)" newline bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled." hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,Calibration factor" newline bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0: Writing ADCAL launches a calibration without the..,1: Writing ADCAL launches a calibration with he.." bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." newline bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." newline bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." newline bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" newline bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" newline bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" bitfld.long 0xC 13. "CONT,Single / continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" newline bitfld.long 0xC 12. "OVRMOD,Overrun Mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" bitfld.long 0xC 2.--3. "RES,Data resolution" "0: 14 bits,1: 12 bits,2: 10 bits,3: 8bits" newline bitfld.long 0xC 0.--1. "DMNGT,Data management configuration" "0: Regular conversion data stored in DR only,1: DMA One -shot mode selected,2: MDF mode selected,3: DMA Circular mode selected" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" bitfld.long 0x10 27. "LFTRIG,Low-frequency trigger" "0: Low-frequency trigger mode disabled,1: Low-frequency trigger mode enabled" newline hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 15. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" newline bitfld.long 0x10 14. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." bitfld.long 0x10 13. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." newline bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." newline hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling right shift" bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected oversampling disabled,1: Injected oversampling enabled" newline bitfld.long 0x10 0. "ROVSE,Regular Oversampling Enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection (x = 0 to 9)" "0: 5 ADC clock cycles,1: 6 ADC clock cycles,2: 12 ADC clock cycles,3: 20 ADC clock cycles,4: 36 ADC clock cycles,5: 68 ADC clock cycles,6: 391 ADC clock cycles,7: 814 ADC clock cycles" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 18. "PCSEL18,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 17. "PCSEL17,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 16. "PCSEL16,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 15. "PCSEL15,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 14. "PCSEL14,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 13. "PCSEL13,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 12. "PCSEL12,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 11. "PCSEL11,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 10. "PCSEL10,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 9. "PCSEL9,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 8. "PCSEL8,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 7. "PCSEL7,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 6. "PCSEL6,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 5. "PCSEL5,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 4. "PCSEL4,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 3. "PCSEL3,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 2. "PCSEL2,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." newline bitfld.long 0x1C 1. "PCSEL1,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." bitfld.long 0x1C 0. "PCSEL0,Channel i (VINP[i]) preselection" "0: Input channel i (VINP[i]) is not preselected for..,1: Input channel i (VINP[i]) is preselected for.." group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,Regular data converted" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x0 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x0 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x0 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x4 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x4 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x4 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x8 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x8 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x8 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0xC 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0xC 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." bitfld.long 0xC 24. "POSOFF,offset sign" "0: Negative offset,1: Positive offset" newline hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,Gain compensation mode" "0: Regular ADC operating mode,1: Gain compensation enabled and applied on all.." hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,Gain compensation coefficient" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,Analog watchdog 3 channel selection" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,Analog watchdog 1 lower threshold" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,Analog watchdog filtering parameter" "0: No filtering,1: two consecutive detection generates an AWDx flag..,?,?,?,?,?,7: Eight consecutive detection generates an AWDx.." hexmask.long 0xC 0.--24. 1. "HTR1,Analog watchdog 1 higher threshold" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,Analog watchdog 2 lower threshold" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,Analog watchdog 2 higher threshold" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,Analog watchdog 3 lower threshold" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,Analog watchdog 3 higher threshold" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,Differential mode for channels 19 to 0" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,Calibration factor capture enable bit" "0: Calibration factor not captured,1: Calibration factor available in CALFACT[31:0].." bitfld.long 0x24 24. "LATCH_COEF,Calibration factor latch enable bit" "0: No effect,1: Calibration factor latched in the analog block.." newline rbitfld.long 0x24 16. "VALIDITY,Delayed write access status bit" "0: Operation still in progress,1: Operation complete" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,Delayed write access data" newline hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,Delayed write access address" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,Linearity or offset calibration factor" tree.end endif sif (cpuis("STM32U585*")) tree "ADC4" base ad:0x46021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xC4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "VSENSESEL,VSENSESEL" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end tree "SEC_ADC4" base ad:0x56021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xC4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "VSENSESEL,VSENSESEL" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end endif sif (cpuis("STM32U585*")) tree "ADC12" base ad:0x42028300 group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" tree.end tree "SEC_ADC12" base ad:0x52028300 group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" tree.end endif sif (cpuis("STM32U595*")) tree "ADC1" base ad:0x42028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC1" base ad:0x52028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U595*")) tree "ADC2" base ad:0x42028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC2" base ad:0x52028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U595*")) tree "ADC12_Common" base ad:0x42028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end tree "SEC_ADC12_Common" base ad:0x52028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end endif sif (cpuis("STM32U595*")) tree "ADC4" base ad:0x46021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end tree "SEC_ADC4" base ad:0x56021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end endif sif (cpuis("STM32U599*")) tree "ADC1" base ad:0x42028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC1" base ad:0x52028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U599*")) tree "ADC2" base ad:0x42028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC2" base ad:0x52028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U599*")) tree "ADC12_Common" base ad:0x42028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end tree "SEC_ADC12_Common" base ad:0x52028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end endif sif (cpuis("STM32U599*")) tree "ADC4" base ad:0x46021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end tree "SEC_ADC4" base ad:0x56021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end endif sif (cpuis("STM32U5A5*")) tree "ADC1" base ad:0x42028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC1" base ad:0x52028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U5A5*")) tree "ADC2" base ad:0x42028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC2" base ad:0x52028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U5A5*")) tree "ADC12_Common" base ad:0x42028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end tree "SEC_ADC12_Common" base ad:0x52028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end endif sif (cpuis("STM32U5A5*")) tree "ADC4" base ad:0x46021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end tree "SEC_ADC4" base ad:0x56021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end endif sif (cpuis("STM32U5A9*")) tree "ADC1" base ad:0x42028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC1" base ad:0x52028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U5A9*")) tree "ADC2" base ad:0x42028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC2" base ad:0x52028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U5A9*")) tree "ADC12_Common" base ad:0x42028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end tree "SEC_ADC12_Common" base ad:0x52028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end endif sif (cpuis("STM32U5A9*")) tree "ADC4" base ad:0x46021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end tree "SEC_ADC4" base ad:0x56021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end endif sif (cpuis("STM32U5F*")) tree "ADC1" base ad:0x42028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC1" base ad:0x52028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U5F*")) tree "ADC2" base ad:0x42028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC2" base ad:0x52028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U5F*")) tree "ADC12_Common" base ad:0x42028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end tree "SEC_ADC12_Common" base ad:0x52028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end endif sif (cpuis("STM32U5F*")) tree "ADC4" base ad:0x46021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end tree "SEC_ADC4" base ad:0x56021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end endif sif (cpuis("STM32U5G*")) tree "ADC1" base ad:0x42028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC1" base ad:0x52028000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U5G*")) tree "ADC2" base ad:0x42028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end tree "SEC_ADC2" base ad:0x52028100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" newline bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" newline bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" hexmask.long.byte 0x8 24.--27. 1. "CALINDEX,CALINDEX" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" newline rbitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" newline rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" newline bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" bitfld.long 0x10 27. "LFTRIG,LFTRIG" "0,1" hexmask.long.word 0x10 16.--25. 1. "OSR,OSR" bitfld.long 0x10 15. "SMPTRIG,SMPTRIG" "0,1" bitfld.long 0x10 14. "SWTRIG,SWTRIG" "0,1" newline bitfld.long 0x10 13. "BULB,BULB" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" newline bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" newline bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" newline bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" newline bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0x13 line.long 0x0 "ADC_OFR1,ADC offset register" hexmask.long.byte 0x0 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x0 26. "SSAT,SSAT" "0,1" bitfld.long 0x0 25. "USAT,USAT" "0,1" bitfld.long 0x0 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "OFFSET,OFFSET" line.long 0x4 "ADC_OFR2,ADC offset register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x4 26. "SSAT,SSAT" "0,1" bitfld.long 0x4 25. "USAT,USAT" "0,1" bitfld.long 0x4 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "OFFSET,OFFSET" line.long 0x8 "ADC_OFR3,ADC offset register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0x8 26. "SSAT,SSAT" "0,1" bitfld.long 0x8 25. "USAT,USAT" "0,1" bitfld.long 0x8 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0x8 0.--23. 1. "OFFSET,OFFSET" line.long 0xC "ADC_OFR4,ADC offset register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,OFFSET_CH" bitfld.long 0xC 26. "SSAT,SSAT" "0,1" bitfld.long 0xC 25. "USAT,USAT" "0,1" bitfld.long 0xC 24. "POSOFF,POSOFF" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "OFFSET,OFFSET" line.long 0x10 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x10 31. "GCOMP,GCOMP" "0,1" hexmask.long.word 0x10 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x2B line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" line.long 0x8 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x8 0.--24. 1. "LTR1,LTR1" line.long 0xC "ADC_HTR1,ADC watchdog threshold register 1" bitfld.long 0xC 29.--31. "AWDFILT1,AWDFILT1" "0,1,2,3,4,5,6,7" hexmask.long 0xC 0.--24. 1. "HTR1,HTR1" line.long 0x10 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x10 0.--24. 1. "LTR2,LTR2" line.long 0x14 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x14 0.--24. 1. "HTR2,HTR2" line.long 0x18 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x18 0.--24. 1. "LTR3,LTR3" line.long 0x1C "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0x1C 0.--24. 1. "HTR3,HTR3" line.long 0x20 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x24 "ADC_CALFACT,ADC user control register" bitfld.long 0x24 25. "CAPTURE_COEF,CAPTURE_COEF" "0,1" bitfld.long 0x24 24. "LATCH_COEF,LATCH_COEF" "0,1" rbitfld.long 0x24 16. "VALIDITY,VALIDITY" "0,1" hexmask.long.byte 0x24 8.--15. 1. "I_APB_DATA,I_APB_DATA" hexmask.long.byte 0x24 0.--7. 1. "I_APB_ADDR,I_APB_ADDR" line.long 0x28 "ADC_CALFACT2,ADC calibration factor register" hexmask.long 0x28 0.--31. 1. "CALFACT,CALFACT" tree.end endif sif (cpuis("STM32U5G*")) tree "ADC12_Common" base ad:0x42028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end tree "SEC_ADC12_Common" base ad:0x52028300 rgroup.long 0x0++0x3 line.long 0x0 "ADC12_CSR,ADC common status register" bitfld.long 0x0 28. "LDORDY_SLV,ADC voltage regulator ready flag of the slave ADC" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 12. "LDORDY_MST,ADC voltage regulator ready flag of the master ADC" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC12_CCR,ADC_CCR system control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "VSENSESEL,Temperature sensor voltage selection" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0: Dual ADC mode without data packing (ADC12_CDR..,?,2: Data formatting mode for 32 down to 10-bit..,3: Data formatting mode for 8-bit resolution" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between the end of the master ADC sampling phase and the beginning of" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "ADC12_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC common regular data register for 32-bit dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs" tree.end endif sif (cpuis("STM32U5G*")) tree "ADC4" base ad:0x46021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end tree "SEC_ADC4" base ad:0x56021000 group.long 0x0++0x17 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 12. "LDORDY,LDORDY" "0,1" bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" newline bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 12. "LDORDYIE,LDORDYIE" "0,1" bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" newline bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" rbitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" rbitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" rbitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" rbitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" rbitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR1,ADC configuration register" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "CHSELRMOD,CHSELRMOD" "0,1" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "WAIT,WAIT" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" newline bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" bitfld.long 0xC 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7" bitfld.long 0xC 5. "ALIGN,ALIGN" "0,1" bitfld.long 0xC 4. "SCANDIR,SCANDIR" "0,1" bitfld.long 0xC 2.--3. "RES,RES" "0,1,2,3" bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1" bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 29. "LFTRIG,LFTRIG" "0,1" bitfld.long 0x10 9. "TOVS,TOVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "OVSE,OVSE" "0,1" line.long 0x14 "ADC_SMPR,ADC sample time register" bitfld.long 0x14 31. "SMPSEL23,SMPSEL23" "0,1" bitfld.long 0x14 30. "SMPSEL22,SMPSEL22" "0,1" bitfld.long 0x14 29. "SMPSEL21,SMPSEL21" "0,1" bitfld.long 0x14 28. "SMPSEL20,SMPSEL20" "0,1" bitfld.long 0x14 27. "SMPSEL19,SMPSEL19" "0,1" bitfld.long 0x14 26. "SMPSEL18,SMPSEL18" "0,1" bitfld.long 0x14 25. "SMPSEL17,SMPSEL17" "0,1" bitfld.long 0x14 24. "SMPSEL16,SMPSEL16" "0,1" newline bitfld.long 0x14 23. "SMPSEL15,SMPSEL15" "0,1" bitfld.long 0x14 22. "SMPSEL14,SMPSEL14" "0,1" bitfld.long 0x14 21. "SMPSEL13,SMPSEL13" "0,1" bitfld.long 0x14 20. "SMPSEL12,SMPSEL12" "0,1" bitfld.long 0x14 19. "SMPSEL11,SMPSEL11" "0,1" bitfld.long 0x14 18. "SMPSEL10,SMPSEL10" "0,1" bitfld.long 0x14 17. "SMPSEL9,SMPSEL9" "0,1" bitfld.long 0x14 16. "SMPSEL8,SMPSEL8" "0,1" newline bitfld.long 0x14 15. "SMPSEL7,SMPSEL7" "0,1" bitfld.long 0x14 14. "SMPSEL6,SMPSEL6" "0,1" bitfld.long 0x14 13. "SMPSEL5,SMPSEL5" "0,1" bitfld.long 0x14 12. "SMPSEL4,SMPSEL4" "0,1" bitfld.long 0x14 11. "SMPSEL3,SMPSEL3" "0,1" bitfld.long 0x14 10. "SMPSEL2,SMPSEL2" "0,1" bitfld.long 0x14 9. "SMPSEL1,SMPSEL1" "0,1" bitfld.long 0x14 8. "SMPSEL0,SMPSEL0" "0,1" newline bitfld.long 0x14 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7" group.long 0x20++0xB line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register" hexmask.long.word 0x0 16.--27. 1. "HT1,HT1" hexmask.long.word 0x0 0.--11. 1. "LT1,LT1" line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT2,HT2" hexmask.long.word 0x4 0.--11. 1. "LT2,LT2" line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register [alternate]" hexmask.long.tbyte 0x8 0.--23. 1. "CHSEL,CHSEL" group.long 0x28++0x7 line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register [alternate]" hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8" hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7" hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6" hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5" hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4" hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3" hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2" hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1" line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register" hexmask.long.word 0x4 16.--27. 1. "HT3,HT3" hexmask.long.word 0x4 0.--11. 1. "LT3,LT3" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC data register" hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" group.long 0x44++0x3 line.long 0x0 "ADC_PWR,ADC data register" bitfld.long 0x0 3. "VREFSECSMP,VREFSECSMP" "0,1" bitfld.long 0x0 2. "VREFPROT,VREFPROT" "0,1" bitfld.long 0x0 1. "DPD,DPD" "0,1" bitfld.long 0x0 0. "AUTOFF,AUTOFF" "0,1" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register" bitfld.long 0x0 23. "AWD2CH23,AWD2CH23" "0,1" bitfld.long 0x0 22. "AWD2CH22,AWD2CH22" "0,1" bitfld.long 0x0 21. "AWD2CH21,AWD2CH21" "0,1" bitfld.long 0x0 20. "AWD2CH20,AWD2CH20" "0,1" bitfld.long 0x0 19. "AWD2CH19,AWD2CH19" "0,1" bitfld.long 0x0 18. "AWD2CH18,AWD2CH18" "0,1" bitfld.long 0x0 17. "AWD2CH17,AWD2CH17" "0,1" bitfld.long 0x0 16. "AWD2CH16,AWD2CH16" "0,1" newline bitfld.long 0x0 15. "AWD2CH15,AWD2CH15" "0,1" bitfld.long 0x0 14. "AWD2CH14,AWD2CH14" "0,1" bitfld.long 0x0 13. "AWD2CH13,AWD2CH13" "0,1" bitfld.long 0x0 12. "AWD2CH12,AWD2CH12" "0,1" bitfld.long 0x0 11. "AWD2CH11,AWD2CH11" "0,1" bitfld.long 0x0 10. "AWD2CH10,AWD2CH10" "0,1" bitfld.long 0x0 9. "AWD2CH9,AWD2CH9" "0,1" bitfld.long 0x0 8. "AWD2CH8,AWD2CH8" "0,1" newline bitfld.long 0x0 7. "AWD2CH7,AWD2CH7" "0,1" bitfld.long 0x0 6. "AWD2CH6,AWD2CH6" "0,1" bitfld.long 0x0 5. "AWD2CH5,AWD2CH5" "0,1" bitfld.long 0x0 4. "AWD2CH4,AWD2CH4" "0,1" bitfld.long 0x0 3. "AWD2CH3,AWD2CH3" "0,1" bitfld.long 0x0 2. "AWD2CH2,AWD2CH2" "0,1" bitfld.long 0x0 1. "AWD2CH1,AWD2CH1" "0,1" bitfld.long 0x0 0. "AWD2CH0,AWD2CH0" "0,1" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register" bitfld.long 0x4 23. "AWD3CH23,AWD3CH23" "0,1" bitfld.long 0x4 22. "AWD3CH22,AWD3CH22" "0,1" bitfld.long 0x4 21. "AWD3CH21,AWD3CH21" "0,1" bitfld.long 0x4 20. "AWD3CH20,AWD3CH20" "0,1" bitfld.long 0x4 19. "AWD3CH19,AWD3CH19" "0,1" bitfld.long 0x4 18. "AWD3CH18,AWD3CH18" "0,1" bitfld.long 0x4 17. "AWD3CH17,AWD3CH17" "0,1" bitfld.long 0x4 16. "AWD3CH16,AWD3CH16" "0,1" newline bitfld.long 0x4 15. "AWD3CH15,AWD3CH15" "0,1" bitfld.long 0x4 14. "AWD3CH14,AWD3CH14" "0,1" bitfld.long 0x4 13. "AWD3CH13,AWD3CH13" "0,1" bitfld.long 0x4 12. "AWD3CH12,AWD3CH12" "0,1" bitfld.long 0x4 11. "AWD3CH11,AWD3CH11" "0,1" bitfld.long 0x4 10. "AWD3CH10,AWD3CH10" "0,1" bitfld.long 0x4 9. "AWD3CH9,AWD3CH9" "0,1" bitfld.long 0x4 8. "AWD3CH8,AWD3CH8" "0,1" newline bitfld.long 0x4 7. "AWD3CH7,AWD3CH7" "0,1" bitfld.long 0x4 6. "AWD3CH6,AWD3CH6" "0,1" bitfld.long 0x4 5. "AWD3CH5,AWD3CH5" "0,1" bitfld.long 0x4 4. "AWD3CH4,AWD3CH4" "0,1" bitfld.long 0x4 3. "AWD3CH3,AWD3CH3" "0,1" bitfld.long 0x4 2. "AWD3CH2,AWD3CH2" "0,1" bitfld.long 0x4 1. "AWD3CH1,AWD3CH1" "0,1" bitfld.long 0x4 0. "AWD3CH0,AWD3CH0" "0,1" group.long 0xB4++0x3 line.long 0x0 "ADC_CALFACT,ADC Calibration factor" hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 0. "CHN21SEL,CHN21SEL" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common configuration register" bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1" bitfld.long 0x0 23. "TSEN,TSEN" "0,1" bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC" tree.end endif tree.end tree "ADF (Audio Digital Filter)" base ad:0x0 tree "ADF1" base ad:0x46024000 group.long 0x0++0x7 line.long 0x0 "ADF_GCR,ADF Global Control Register" bitfld.long 0x0 0. "TRGO,Trigger output control Set by software and reset by" "0,1" line.long 0x4 "ADF_CKGCR,ADF clock generator control register" bitfld.long 0x4 31. "CKGACTIVE,Clock generator active flag" "0,1" hexmask.long.byte 0x4 24.--30. 1. "PROCDIV,Divider to control the serial interface clock" hexmask.long.byte 0x4 16.--19. 1. "CCKDIV,Divider to control the ADF_CCK clock" hexmask.long.byte 0x4 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x4 8. "TRGSENS,CKGEN trigger sensitivity selection" "0,1" bitfld.long 0x4 6. "CCK1DIR,ADF_CCK1 direction" "0,1" bitfld.long 0x4 5. "CCK0DIR,ADF_CCK0 direction" "0,1" bitfld.long 0x4 4. "CKGMOD,Clock generator mode" "0,1" newline bitfld.long 0x4 2. "CCK1EN,ADF_CCK1 clock enable" "0,1" bitfld.long 0x4 1. "CCK0EN,ADF_CCK0 clock enable" "0,1" bitfld.long 0x4 0. "CKGDEN,CKGEN dividers enable" "0,1" group.long 0x80++0x13 line.long 0x0 "ADF_SITF0CR,ADF serial interface control register 0" bitfld.long 0x0 31. "SITFACTIVE,SITFACTIVE" "0,1" hexmask.long.byte 0x0 8.--12. 1. "STH,STH" bitfld.long 0x0 4.--5. "SITFMOD,SITFMOD" "0,1,2,3" bitfld.long 0x0 1.--2. "SCKSRC,SCKSRC" "0,1,2,3" bitfld.long 0x0 0. "SITFEN,SITFEN" "0,1" line.long 0x4 "ADF_BSMX0CR,ADF bitstream matrix control register 0" bitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0,1" hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream selection" line.long 0x8 "ADF_DFLT0CR,ADF digital filter control register 0" bitfld.long 0x8 31. "DFLTACTIVE,DFLT0 active flag" "0,1" bitfld.long 0x8 30. "DFLTRUN,DFLT0 run status flag" "0,1" hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,DFLT0 trigger signal selection" bitfld.long 0x8 4.--6. "ACQMOD,DFLT0 trigger mode" "0,1,2,3,4,5,6,7" bitfld.long 0x8 2. "FTH,RXFIFO threshold selection" "0,1" bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0,1" bitfld.long 0x8 0. "DFLTEN,DFLT0 enable" "0,1" line.long 0xC "ADF_DFLT0CICR,ADF digital filer configuration register 0" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" hexmask.long.word 0xC 8.--16. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC order" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "0,1,2,3" line.long 0x10 "ADF_DFLT0RSFR,ADF reshape filter configuration register 0" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0,1,2,3" bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0,1" bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0,1" bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0,1" group.long 0xA4++0x3 line.long 0x0 "ADF_DLY0CR,ADF delay control register 0" bitfld.long 0x0 31. "SKPBF,Skip busy flag" "0,1" hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" group.long 0xAC++0x7 line.long 0x0 "ADF_DFLT0IER,ADF DFLT0 interrupt enable register" bitfld.long 0x0 13. "SDLVLIE,SAD sound-level value ready enable" "0,1" bitfld.long 0x0 12. "SDDETIE,Sound activity detection interrupt enable" "0,1" bitfld.long 0x0 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0,1" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable" "0,1" bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable" "0,1" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable" "0,1" bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable" "0,1" line.long 0x4 "ADF_DFLT0ISR,ADF DFLT0 interrupt status register 0" bitfld.long 0x4 13. "SDLVLF,Sound level value ready flag" "0,1" bitfld.long 0x4 12. "SDDETF,Sound activity detection flag" "0,1" bitfld.long 0x4 11. "RFOVRF,Reshape filter overrun detection flag" "0,1" bitfld.long 0x4 10. "CKABF,Clock absence detection flag" "0,1" bitfld.long 0x4 9. "SATF,Saturation detection flag" "0,1" rbitfld.long 0x4 3. "RXNEF,RXFIFO not empty flag" "0,1" bitfld.long 0x4 1. "DOVRF,Data overflow flag" "0,1" rbitfld.long 0x4 0. "FTHF,RXFIFO threshold flag" "0,1" group.long 0xB8++0x7 line.long 0x0 "ADF_SADCR,ADF SAD control register" rbitfld.long 0x0 31. "SADACTIVE,SAD Active flag" "0,1" bitfld.long 0x0 12.--13. "SADMOD,SAD working mode" "0,1,2,3" bitfld.long 0x0 8.--10. "FRSIZE,Frame size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "HYSTEN,Hysteresis enable" "0,1" rbitfld.long 0x0 4.--5. "SADST,SAD state" "0,1,2,3" bitfld.long 0x0 3. "DETCFG,Sound trigger event configuration" "0,1" bitfld.long 0x0 1.--2. "DATCAP,Data capture mode" "0,1,2,3" bitfld.long 0x0 0. "SADEN,Sound activity detector enable" "0,1" line.long 0x4 "ADF_SADCFGR,ADF SAD configuration register" hexmask.long.word 0x4 16.--28. 1. "ANMIN,ANMIN" bitfld.long 0x4 12.--14. "HGOVR,Hangover time window" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "LFRNB,LFRNB" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "ANSLP,ANSLP" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--3. 1. "SNTHR,SNTHR" rgroup.long 0xC0++0x7 line.long 0x0 "ADF_SADSDLVR,ADF SAD sound level register" hexmask.long.word 0x0 0.--14. 1. "SDLVL,SDLVL" line.long 0x4 "ADF_SADANLVR,ADF SAD ambient noise level register" hexmask.long.word 0x4 0.--14. 1. "ANLVL,ANLVL" rgroup.long 0xF0++0x3 line.long 0x0 "ADF_DFLT0DR,ADF digital filter data register 0" hexmask.long.tbyte 0x0 8.--31. 1. "DR,DR" tree.end tree "SEC_ADF1" base ad:0x56024000 group.long 0x0++0x7 line.long 0x0 "ADF_GCR,ADF Global Control Register" bitfld.long 0x0 0. "TRGO,Trigger output control Set by software and reset by" "0,1" line.long 0x4 "ADF_CKGCR,ADF clock generator control register" bitfld.long 0x4 31. "CKGACTIVE,Clock generator active flag" "0,1" hexmask.long.byte 0x4 24.--30. 1. "PROCDIV,Divider to control the serial interface clock" hexmask.long.byte 0x4 16.--19. 1. "CCKDIV,Divider to control the ADF_CCK clock" hexmask.long.byte 0x4 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x4 8. "TRGSENS,CKGEN trigger sensitivity selection" "0,1" bitfld.long 0x4 6. "CCK1DIR,ADF_CCK1 direction" "0,1" bitfld.long 0x4 5. "CCK0DIR,ADF_CCK0 direction" "0,1" bitfld.long 0x4 4. "CKGMOD,Clock generator mode" "0,1" newline bitfld.long 0x4 2. "CCK1EN,ADF_CCK1 clock enable" "0,1" bitfld.long 0x4 1. "CCK0EN,ADF_CCK0 clock enable" "0,1" bitfld.long 0x4 0. "CKGDEN,CKGEN dividers enable" "0,1" group.long 0x80++0x13 line.long 0x0 "ADF_SITF0CR,ADF serial interface control register 0" bitfld.long 0x0 31. "SITFACTIVE,SITFACTIVE" "0,1" hexmask.long.byte 0x0 8.--12. 1. "STH,STH" bitfld.long 0x0 4.--5. "SITFMOD,SITFMOD" "0,1,2,3" bitfld.long 0x0 1.--2. "SCKSRC,SCKSRC" "0,1,2,3" bitfld.long 0x0 0. "SITFEN,SITFEN" "0,1" line.long 0x4 "ADF_BSMX0CR,ADF bitstream matrix control register 0" bitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0,1" hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream selection" line.long 0x8 "ADF_DFLT0CR,ADF digital filter control register 0" bitfld.long 0x8 31. "DFLTACTIVE,DFLT0 active flag" "0,1" bitfld.long 0x8 30. "DFLTRUN,DFLT0 run status flag" "0,1" hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,DFLT0 trigger signal selection" bitfld.long 0x8 4.--6. "ACQMOD,DFLT0 trigger mode" "0,1,2,3,4,5,6,7" bitfld.long 0x8 2. "FTH,RXFIFO threshold selection" "0,1" bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0,1" bitfld.long 0x8 0. "DFLTEN,DFLT0 enable" "0,1" line.long 0xC "ADF_DFLT0CICR,ADF digital filer configuration register 0" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" hexmask.long.word 0xC 8.--16. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC order" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "0,1,2,3" line.long 0x10 "ADF_DFLT0RSFR,ADF reshape filter configuration register 0" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0,1,2,3" bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0,1" bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0,1" bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0,1" group.long 0xA4++0x3 line.long 0x0 "ADF_DLY0CR,ADF delay control register 0" bitfld.long 0x0 31. "SKPBF,Skip busy flag" "0,1" hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" group.long 0xAC++0x7 line.long 0x0 "ADF_DFLT0IER,ADF DFLT0 interrupt enable register" bitfld.long 0x0 13. "SDLVLIE,SAD sound-level value ready enable" "0,1" bitfld.long 0x0 12. "SDDETIE,Sound activity detection interrupt enable" "0,1" bitfld.long 0x0 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0,1" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable" "0,1" bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable" "0,1" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable" "0,1" bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable" "0,1" line.long 0x4 "ADF_DFLT0ISR,ADF DFLT0 interrupt status register 0" bitfld.long 0x4 13. "SDLVLF,Sound level value ready flag" "0,1" bitfld.long 0x4 12. "SDDETF,Sound activity detection flag" "0,1" bitfld.long 0x4 11. "RFOVRF,Reshape filter overrun detection flag" "0,1" bitfld.long 0x4 10. "CKABF,Clock absence detection flag" "0,1" bitfld.long 0x4 9. "SATF,Saturation detection flag" "0,1" rbitfld.long 0x4 3. "RXNEF,RXFIFO not empty flag" "0,1" bitfld.long 0x4 1. "DOVRF,Data overflow flag" "0,1" rbitfld.long 0x4 0. "FTHF,RXFIFO threshold flag" "0,1" group.long 0xB8++0x7 line.long 0x0 "ADF_SADCR,ADF SAD control register" rbitfld.long 0x0 31. "SADACTIVE,SAD Active flag" "0,1" bitfld.long 0x0 12.--13. "SADMOD,SAD working mode" "0,1,2,3" bitfld.long 0x0 8.--10. "FRSIZE,Frame size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "HYSTEN,Hysteresis enable" "0,1" rbitfld.long 0x0 4.--5. "SADST,SAD state" "0,1,2,3" bitfld.long 0x0 3. "DETCFG,Sound trigger event configuration" "0,1" bitfld.long 0x0 1.--2. "DATCAP,Data capture mode" "0,1,2,3" bitfld.long 0x0 0. "SADEN,Sound activity detector enable" "0,1" line.long 0x4 "ADF_SADCFGR,ADF SAD configuration register" hexmask.long.word 0x4 16.--28. 1. "ANMIN,ANMIN" bitfld.long 0x4 12.--14. "HGOVR,Hangover time window" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "LFRNB,LFRNB" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "ANSLP,ANSLP" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--3. 1. "SNTHR,SNTHR" rgroup.long 0xC0++0x7 line.long 0x0 "ADF_SADSDLVR,ADF SAD sound level register" hexmask.long.word 0x0 0.--14. 1. "SDLVL,SDLVL" line.long 0x4 "ADF_SADANLVR,ADF SAD ambient noise level register" hexmask.long.word 0x4 0.--14. 1. "ANLVL,ANLVL" rgroup.long 0xF0++0x3 line.long 0x0 "ADF_DFLT0DR,ADF digital filter data register 0" hexmask.long.tbyte 0x0 8.--31. 1. "DR,DR" tree.end tree.end sif (cpuis("STM32U545*")||cpuis("STM32U585*")||cpuis("STM32U5A5*")||cpuis("STM32U5A9*")||cpuis("STM32U5G*")) tree "AES (Advanced Encryption Standard Hardware Accelerator)" base ad:0x0 sif (cpuis("STM32U545*")||cpuis("STM32U585*")) tree "AES" base ad:0x420C0000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 16. "CHMOD_2,CHMOD_2" "0,1" bitfld.long 0x0 13.--14. "GCMPH,GCMPH" "0,1,2,3" bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1" bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1" bitfld.long 0x0 5.--6. "CHMOD,AES chaining mode" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3" bitfld.long 0x0 0. "EN,AES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "AES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0x2F line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" line.long 0x10 "SUSP0R,suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP0,AES suspend" line.long 0x14 "SUSP1R,suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP1,AES suspend" line.long 0x18 "SUSP2R,suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP2,AES suspend" line.long 0x1C "SUSP3R,suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP3,AES suspend" line.long 0x20 "SUSP4R,suspend registers" hexmask.long 0x20 0.--31. 1. "SUSP4,AES suspend" line.long 0x24 "SUSP5R,suspend registers" hexmask.long 0x24 0.--31. 1. "SUSP5,AES suspend" line.long 0x28 "SUSP6R,suspend registers" hexmask.long 0x28 0.--31. 1. "SUSP6,AES suspend" line.long 0x2C "SUSP7R,suspend registers" hexmask.long 0x2C 0.--31. 1. "SUSP7,AES suspend" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" sif (cpuis("STM32U585*")) bitfld.long 0x0 3. "RNGEIE,Key error interrupt flag" "0,1" endif bitfld.long 0x0 2. "KEIE,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" sif (cpuis("STM32U585*")) bitfld.long 0x0 3. "RNGEIF,Key error interrupt flag" "0,1" endif bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end endif sif (cpuis("STM32U545*")||cpuis("STM32U585*")) tree "SEC_AES" base ad:0x520C0000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 16. "CHMOD_2,CHMOD_2" "0,1" bitfld.long 0x0 13.--14. "GCMPH,GCMPH" "0,1,2,3" bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1" bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1" bitfld.long 0x0 5.--6. "CHMOD,AES chaining mode" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3" bitfld.long 0x0 0. "EN,AES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "AES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0x2F line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" line.long 0x10 "SUSP0R,suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP0,AES suspend" line.long 0x14 "SUSP1R,suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP1,AES suspend" line.long 0x18 "SUSP2R,suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP2,AES suspend" line.long 0x1C "SUSP3R,suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP3,AES suspend" line.long 0x20 "SUSP4R,suspend registers" hexmask.long 0x20 0.--31. 1. "SUSP4,AES suspend" line.long 0x24 "SUSP5R,suspend registers" hexmask.long 0x24 0.--31. 1. "SUSP5,AES suspend" line.long 0x28 "SUSP6R,suspend registers" hexmask.long 0x28 0.--31. 1. "SUSP6,AES suspend" line.long 0x2C "SUSP7R,suspend registers" hexmask.long 0x2C 0.--31. 1. "SUSP7,AES suspend" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" sif (cpuis("STM32U585*")) bitfld.long 0x0 3. "RNGEIE,Key error interrupt flag" "0,1" endif bitfld.long 0x0 2. "KEIE,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" sif (cpuis("STM32U585*")) bitfld.long 0x0 3. "RNGEIF,Key error interrupt flag" "0,1" endif bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "AES" base ad:0x420C0000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 16. "CHMOD_2,CHMOD_2" "0,1" bitfld.long 0x0 13.--14. "GCMPH,GCMPH" "0,1,2,3" bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1" bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1" bitfld.long 0x0 5.--6. "CHMOD,AES chaining mode" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3" bitfld.long 0x0 0. "EN,AES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "AES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0x2F line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" line.long 0x10 "SUSP0R,suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP0,AES suspend" line.long 0x14 "SUSP1R,suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP1,AES suspend" line.long 0x18 "SUSP2R,suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP2,AES suspend" line.long 0x1C "SUSP3R,suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP3,AES suspend" line.long 0x20 "SUSP4R,suspend registers" hexmask.long 0x20 0.--31. 1. "SUSP4,AES suspend" line.long 0x24 "SUSP5R,suspend registers" hexmask.long 0x24 0.--31. 1. "SUSP5,AES suspend" line.long 0x28 "SUSP6R,suspend registers" hexmask.long 0x28 0.--31. 1. "SUSP6,AES suspend" line.long 0x2C "SUSP7R,suspend registers" hexmask.long 0x2C 0.--31. 1. "SUSP7,AES suspend" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 2. "KEIE,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end tree "SEC_AES" base ad:0x520C0000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 16. "CHMOD_2,CHMOD_2" "0,1" bitfld.long 0x0 13.--14. "GCMPH,GCMPH" "0,1,2,3" bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1" bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1" bitfld.long 0x0 5.--6. "CHMOD,AES chaining mode" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3" bitfld.long 0x0 0. "EN,AES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "AES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0x2F line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" line.long 0x10 "SUSP0R,suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP0,AES suspend" line.long 0x14 "SUSP1R,suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP1,AES suspend" line.long 0x18 "SUSP2R,suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP2,AES suspend" line.long 0x1C "SUSP3R,suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP3,AES suspend" line.long 0x20 "SUSP4R,suspend registers" hexmask.long 0x20 0.--31. 1. "SUSP4,AES suspend" line.long 0x24 "SUSP5R,suspend registers" hexmask.long 0x24 0.--31. 1. "SUSP5,AES suspend" line.long 0x28 "SUSP6R,suspend registers" hexmask.long 0x28 0.--31. 1. "SUSP6,AES suspend" line.long 0x2C "SUSP7R,suspend registers" hexmask.long 0x2C 0.--31. 1. "SUSP7,AES suspend" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 2. "KEIE,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "AES" base ad:0x420C0000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 16. "CHMOD_2,CHMOD_2" "0,1" bitfld.long 0x0 13.--14. "GCMPH,GCMPH" "0,1,2,3" bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1" bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1" bitfld.long 0x0 5.--6. "CHMOD,AES chaining mode" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3" bitfld.long 0x0 0. "EN,AES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "AES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0x2F line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" line.long 0x10 "SUSP0R,suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP0,AES suspend" line.long 0x14 "SUSP1R,suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP1,AES suspend" line.long 0x18 "SUSP2R,suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP2,AES suspend" line.long 0x1C "SUSP3R,suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP3,AES suspend" line.long 0x20 "SUSP4R,suspend registers" hexmask.long 0x20 0.--31. 1. "SUSP4,AES suspend" line.long 0x24 "SUSP5R,suspend registers" hexmask.long 0x24 0.--31. 1. "SUSP5,AES suspend" line.long 0x28 "SUSP6R,suspend registers" hexmask.long 0x28 0.--31. 1. "SUSP6,AES suspend" line.long 0x2C "SUSP7R,suspend registers" hexmask.long 0x2C 0.--31. 1. "SUSP7,AES suspend" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 2. "KEIE,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end tree "SEC_AES" base ad:0x520C0000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 16. "CHMOD_2,CHMOD_2" "0,1" bitfld.long 0x0 13.--14. "GCMPH,GCMPH" "0,1,2,3" bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1" bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1" bitfld.long 0x0 5.--6. "CHMOD,AES chaining mode" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3" bitfld.long 0x0 0. "EN,AES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "AES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0x2F line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" line.long 0x10 "SUSP0R,suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP0,AES suspend" line.long 0x14 "SUSP1R,suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP1,AES suspend" line.long 0x18 "SUSP2R,suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP2,AES suspend" line.long 0x1C "SUSP3R,suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP3,AES suspend" line.long 0x20 "SUSP4R,suspend registers" hexmask.long 0x20 0.--31. 1. "SUSP4,AES suspend" line.long 0x24 "SUSP5R,suspend registers" hexmask.long 0x24 0.--31. 1. "SUSP5,AES suspend" line.long 0x28 "SUSP6R,suspend registers" hexmask.long 0x28 0.--31. 1. "SUSP6,AES suspend" line.long 0x2C "SUSP7R,suspend registers" hexmask.long 0x2C 0.--31. 1. "SUSP7,AES suspend" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 2. "KEIE,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "AES" base ad:0x420C0000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 16. "CHMOD_2,CHMOD_2" "0,1" bitfld.long 0x0 13.--14. "GCMPH,GCMPH" "0,1,2,3" bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1" bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1" bitfld.long 0x0 5.--6. "CHMOD,AES chaining mode" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3" bitfld.long 0x0 0. "EN,AES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "AES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0x2F line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" line.long 0x10 "SUSP0R,suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP0,AES suspend" line.long 0x14 "SUSP1R,suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP1,AES suspend" line.long 0x18 "SUSP2R,suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP2,AES suspend" line.long 0x1C "SUSP3R,suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP3,AES suspend" line.long 0x20 "SUSP4R,suspend registers" hexmask.long 0x20 0.--31. 1. "SUSP4,AES suspend" line.long 0x24 "SUSP5R,suspend registers" hexmask.long 0x24 0.--31. 1. "SUSP5,AES suspend" line.long 0x28 "SUSP6R,suspend registers" hexmask.long 0x28 0.--31. 1. "SUSP6,AES suspend" line.long 0x2C "SUSP7R,suspend registers" hexmask.long 0x2C 0.--31. 1. "SUSP7,AES suspend" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 2. "KEIE,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end tree "SEC_AES" base ad:0x520C0000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 16. "CHMOD_2,CHMOD_2" "0,1" bitfld.long 0x0 13.--14. "GCMPH,GCMPH" "0,1,2,3" bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1" bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1" bitfld.long 0x0 5.--6. "CHMOD,AES chaining mode" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3" bitfld.long 0x0 0. "EN,AES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "AES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0x2F line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" line.long 0x10 "SUSP0R,suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP0,AES suspend" line.long 0x14 "SUSP1R,suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP1,AES suspend" line.long 0x18 "SUSP2R,suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP2,AES suspend" line.long 0x1C "SUSP3R,suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP3,AES suspend" line.long 0x20 "SUSP4R,suspend registers" hexmask.long 0x20 0.--31. 1. "SUSP4,AES suspend" line.long 0x24 "SUSP5R,suspend registers" hexmask.long 0x24 0.--31. 1. "SUSP5,AES suspend" line.long 0x28 "SUSP6R,suspend registers" hexmask.long 0x28 0.--31. 1. "SUSP6,AES suspend" line.long 0x2C "SUSP7R,suspend registers" hexmask.long 0x2C 0.--31. 1. "SUSP7,AES suspend" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 2. "KEIE,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end endif tree.end endif tree "COMP (Comparator)" base ad:0x0 tree "COMP" base ad:0x46005400 group.long 0x0++0x7 line.long 0x0 "COMP1_CSR,Comparator 1 control and status" bitfld.long 0x0 31. "COMP1_LOCK,COMP1_CSR register lock" "0,1" rbitfld.long 0x0 30. "COMP1_VALUE,Comparator 1 output status" "0,1" hexmask.long.byte 0x0 20.--24. 1. "COMP1_BLANKSEL,COMP1_BLANKSEL" bitfld.long 0x0 18.--19. "COMP1_PWRMODE,COMP1_PWRMODE" "0,1,2,3" bitfld.long 0x0 16.--17. "COMP1_HYST,Comparator 1 hysteresis selection" "0,1,2,3" bitfld.long 0x0 15. "COMP1_POLARITY,Comparator 1 polarity selection" "0,1" bitfld.long 0x0 14. "COMP1_WINOUT,COMP1_WINOUT" "0,1" newline bitfld.long 0x0 11. "COMP1_WINMODE,COMP1_WINMODE" "0,1" bitfld.long 0x0 8.--9. "COMP1_INPSEL,Comparator1 input plus selection" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "COMP1_INMSEL,Comparator 1 Input Minus connection" bitfld.long 0x0 0. "COMP1_EN,Comparator 1 enable bit" "0,1" line.long 0x4 "COMP2_CSR,Comparator 2 control and status" bitfld.long 0x4 31. "COM2_LOCK,COMP2_CSR register lock" "0,1" rbitfld.long 0x4 30. "COM2_VALUE,Comparator 2 output status" "0,1" hexmask.long.byte 0x4 20.--24. 1. "COM2_BLANKSEL,COM2_BLANKSEL" bitfld.long 0x4 18.--19. "COM2_PWRMODE,COM2_PWRMODE" "0,1,2,3" bitfld.long 0x4 16.--17. "COM2_HYST,Comparator 2 hysteresis selection" "0,1,2,3" bitfld.long 0x4 15. "COM2_POLARITY,Comparator 2 polarity selection" "0,1" bitfld.long 0x4 14. "COM2_WINOUT,COM2_WINOUT" "0,1" newline bitfld.long 0x4 11. "COM2_WINMODE,COM2_WINMODE" "0,1" bitfld.long 0x4 8.--9. "COM2_INPSEL,Comparator 2 input plus selection" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "COM2_INMSEL,Comparator 2 Input Minus connection" bitfld.long 0x4 0. "COM2_EN,Comparator 2 enable bit" "0,1" tree.end tree "SEC_COMP" base ad:0x56005400 group.long 0x0++0x7 line.long 0x0 "COMP1_CSR,Comparator 1 control and status" bitfld.long 0x0 31. "COMP1_LOCK,COMP1_CSR register lock" "0,1" rbitfld.long 0x0 30. "COMP1_VALUE,Comparator 1 output status" "0,1" hexmask.long.byte 0x0 20.--24. 1. "COMP1_BLANKSEL,COMP1_BLANKSEL" bitfld.long 0x0 18.--19. "COMP1_PWRMODE,COMP1_PWRMODE" "0,1,2,3" bitfld.long 0x0 16.--17. "COMP1_HYST,Comparator 1 hysteresis selection" "0,1,2,3" bitfld.long 0x0 15. "COMP1_POLARITY,Comparator 1 polarity selection" "0,1" bitfld.long 0x0 14. "COMP1_WINOUT,COMP1_WINOUT" "0,1" newline bitfld.long 0x0 11. "COMP1_WINMODE,COMP1_WINMODE" "0,1" bitfld.long 0x0 8.--9. "COMP1_INPSEL,Comparator1 input plus selection" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "COMP1_INMSEL,Comparator 1 Input Minus connection" bitfld.long 0x0 0. "COMP1_EN,Comparator 1 enable bit" "0,1" line.long 0x4 "COMP2_CSR,Comparator 2 control and status" bitfld.long 0x4 31. "COM2_LOCK,COMP2_CSR register lock" "0,1" rbitfld.long 0x4 30. "COM2_VALUE,Comparator 2 output status" "0,1" hexmask.long.byte 0x4 20.--24. 1. "COM2_BLANKSEL,COM2_BLANKSEL" bitfld.long 0x4 18.--19. "COM2_PWRMODE,COM2_PWRMODE" "0,1,2,3" bitfld.long 0x4 16.--17. "COM2_HYST,Comparator 2 hysteresis selection" "0,1,2,3" bitfld.long 0x4 15. "COM2_POLARITY,Comparator 2 polarity selection" "0,1" bitfld.long 0x4 14. "COM2_WINOUT,COM2_WINOUT" "0,1" newline bitfld.long 0x4 11. "COM2_WINMODE,COM2_WINMODE" "0,1" bitfld.long 0x4 8.--9. "COM2_INPSEL,Comparator 2 input plus selection" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "COM2_INMSEL,Comparator 2 Input Minus connection" bitfld.long 0x4 0. "COM2_EN,Comparator 2 enable bit" "0,1" tree.end tree.end tree "CORDIC (CORDIC co-processor)" base ad:0x0 tree "CORDIC" base ad:0x40021000 group.long 0x0++0x3 line.long 0x0 "CSR,CORDIC Control Status register" rbitfld.long 0x0 31. "RRDY,Result ready flag" "0,1" bitfld.long 0x0 22. "ARGSIZE,Width of input data" "0,1" bitfld.long 0x0 21. "RESSIZE,Width of output data" "0,1" bitfld.long 0x0 20. "NARGS,Number of arguments expected by the CORDIC_WDATA register" "0,1" bitfld.long 0x0 19. "NRES,Number of results in the CORDIC_RDATA register" "0,1" bitfld.long 0x0 18. "DMAWEN,Enable DMA write channel" "0,1" bitfld.long 0x0 17. "DMAREN,Enable DMA read channel" "0,1" bitfld.long 0x0 16. "IEN,Enable interrupt" "0,1" bitfld.long 0x0 8.--10. "SCALE,Scaling factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 4.--7. 1. "PRECISION,Precision required (number of iterations)" hexmask.long.byte 0x0 0.--3. 1. "FUNC,Function" wgroup.long 0x4++0x3 line.long 0x0 "WDATA,FMAC Write Data register" hexmask.long 0x0 0.--31. 1. "ARG,Function input arguments" rgroup.long 0x8++0x3 line.long 0x0 "RDATA,FMAC Read Data register" hexmask.long 0x0 0.--31. 1. "RES,Function result" tree.end tree "SEC_CORDIC" base ad:0x50021000 group.long 0x0++0x3 line.long 0x0 "CSR,CORDIC Control Status register" rbitfld.long 0x0 31. "RRDY,Result ready flag" "0,1" bitfld.long 0x0 22. "ARGSIZE,Width of input data" "0,1" bitfld.long 0x0 21. "RESSIZE,Width of output data" "0,1" bitfld.long 0x0 20. "NARGS,Number of arguments expected by the CORDIC_WDATA register" "0,1" bitfld.long 0x0 19. "NRES,Number of results in the CORDIC_RDATA register" "0,1" bitfld.long 0x0 18. "DMAWEN,Enable DMA write channel" "0,1" bitfld.long 0x0 17. "DMAREN,Enable DMA read channel" "0,1" bitfld.long 0x0 16. "IEN,Enable interrupt" "0,1" bitfld.long 0x0 8.--10. "SCALE,Scaling factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 4.--7. 1. "PRECISION,Precision required (number of iterations)" hexmask.long.byte 0x0 0.--3. 1. "FUNC,Function" wgroup.long 0x4++0x3 line.long 0x0 "WDATA,FMAC Write Data register" hexmask.long 0x0 0.--31. 1. "ARG,Function input arguments" rgroup.long 0x8++0x3 line.long 0x0 "RDATA,FMAC Read Data register" hexmask.long 0x0 0.--31. 1. "RES,Function result" tree.end tree.end tree "CRC (Cyclic Redundancy Check Calculation Unit)" base ad:0x0 tree "CRC" base ad:0x40023000 group.long 0x0++0xB line.long 0x0 "DR,Data register" hexmask.long 0x0 0.--31. 1. "DR,Data register bits" line.long 0x4 "IDR,Independent data register" hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 8-bit data register" line.long 0x8 "CR,Control register" bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1" bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3" bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3" bitfld.long 0x8 0. "RESET,RESET bit" "0,1" group.long 0x10++0x7 line.long 0x0 "INIT,Initial CRC value" hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC" line.long 0x4 "POL,polynomial" hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial" tree.end tree "SEC_CRC" base ad:0x50023000 group.long 0x0++0xB line.long 0x0 "DR,Data register" hexmask.long 0x0 0.--31. 1. "DR,Data register bits" line.long 0x4 "IDR,Independent data register" hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 8-bit data register" line.long 0x8 "CR,Control register" bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1" bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3" bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3" bitfld.long 0x8 0. "RESET,RESET bit" "0,1" group.long 0x10++0x7 line.long 0x0 "INIT,Initial CRC value" hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC" line.long 0x4 "POL,polynomial" hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial" tree.end tree.end tree "CRS (Clock Recovery System)" base ad:0x0 tree "CRS" base ad:0x40006000 group.long 0x0++0x7 line.long 0x0 "CR,control register" hexmask.long.byte 0x0 8.--14. 1. "TRIM,HSI48 oscillator smooth" bitfld.long 0x0 7. "SWSYNC,Generate software SYNC" "0,1" bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable" "0,1" bitfld.long 0x0 5. "CEN,Frequency error counter" "0,1" bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CFGR,configuration register" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source" "0,1,2,3" bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit" hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value" rgroup.long 0x8++0x3 line.long 0x0 "ISR,interrupt and status register" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture" bitfld.long 0x0 15. "FEDIR,Frequency error direction" "0,1" bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed" "0,1" bitfld.long 0x0 8. "SYNCERR,SYNC error" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag" "0,1" bitfld.long 0x0 2. "ERRF,Error flag" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag" "0,1" bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag" "0,1" group.long 0xC++0x3 line.long 0x0 "ICR,interrupt flag clear register" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag" "0,1" bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag" "0,1" tree.end tree "SEC_CRS" base ad:0x50006000 group.long 0x0++0x7 line.long 0x0 "CR,control register" hexmask.long.byte 0x0 8.--14. 1. "TRIM,HSI48 oscillator smooth" bitfld.long 0x0 7. "SWSYNC,Generate software SYNC" "0,1" bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable" "0,1" bitfld.long 0x0 5. "CEN,Frequency error counter" "0,1" bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CFGR,configuration register" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source" "0,1,2,3" bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit" hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value" rgroup.long 0x8++0x3 line.long 0x0 "ISR,interrupt and status register" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture" bitfld.long 0x0 15. "FEDIR,Frequency error direction" "0,1" bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed" "0,1" bitfld.long 0x0 8. "SYNCERR,SYNC error" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag" "0,1" bitfld.long 0x0 2. "ERRF,Error flag" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag" "0,1" bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag" "0,1" group.long 0xC++0x3 line.long 0x0 "ICR,interrupt flag clear register" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag" "0,1" bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag" "0,1" tree.end tree.end tree "DAC (Digital-to-Analog Converter)" base ad:0x0 tree "DAC1" base ad:0x46021800 group.long 0x0++0x3 line.long 0x0 "DAC_CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC channel2 calibration enable" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable" "0,1,2,3" hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger enable" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable" "0,1" newline bitfld.long 0x0 14. "CEN1,DAC channel1 calibration enable" "0,1" bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable" "0,1,2,3" hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DAC_SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger" "0,1" group.long 0x8++0x23 line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register" hexmask.long.word 0x0 16.--27. 1. "DACC1DHRB,DAC channel1 12-bit right-aligned data B" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register" hexmask.long.word 0x4 20.--31. 1. "DACC1DHRB,DAC channel1 12-bit left-aligned data B" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register" hexmask.long.byte 0x8 8.--15. 1. "DACC1DHRB,DAC channel1 8-bit right-aligned Sdata" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DAC_DHR12R2,DAC channel2 12-bit right aligned data holding register" hexmask.long.word 0xC 16.--27. 1. "DACC2DHRB,DAC channel2 12-bit right-aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DAC_DHR12L2,DAC channel2 12-bit left aligned data holding register" hexmask.long.word 0x10 20.--31. 1. "DACC2DHRB,DAC channel2 12-bit left-aligned data B" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data holding register" hexmask.long.byte 0x14 8.--15. 1. "DACC2DHRB,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding register" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding register" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DAC_DOR1,DAC channel1 data output register" hexmask.long.word 0x0 16.--27. 1. "DACC1DORB,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output" line.long 0x4 "DAC_DOR2,DAC channel2 data output register" hexmask.long.word 0x4 16.--27. 1. "DACC2DORB,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output" group.long 0x34++0x1B line.long 0x0 "DAC_SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time flag" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag" "0,1" rbitfld.long 0x0 28. "DORSTAT2,DAC channel 2 output register status bit" "0,1" rbitfld.long 0x0 27. "DAC2RDY,DAC channel 2 ready status bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time flag" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag" "0,1" newline rbitfld.long 0x0 12. "DORSTAT1,DAC channel1 output register status bit" "0,1" rbitfld.long 0x0 11. "DAC1RDY,DAC channel1 ready status bit" "0,1" line.long 0x4 "DAC_CCR,DAC calibration control register" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming value" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming value" line.long 0x8 "DAC_MCR,DAC mode control register" bitfld.long 0x8 25. "SINFORMAT2,Enable signed format for DAC channel2" "0,1" bitfld.long 0x8 24. "DMADOUBLE2,DAC Channel2 DMA double data mode" "0,1" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x8 14.--15. "HFSEL,High frequency interface mode selection" "0,1,2,3" bitfld.long 0x8 9. "SINFORMAT1,Enable signed format for DAC channel1" "0,1" bitfld.long 0x8 8. "DMADOUBLE1,DAC Channel1 DMA double data mode" "0,1" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode" "0,1,2,3,4,5,6,7" line.long 0xC "DAC_SHSR1,DAC Sample and Hold sample time register 1" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in sample & hold mode)" line.long 0x10 "DAC_SHSR2,DAC channel2 sample and hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in sample and hold mode)" line.long 0x14 "DAC_SHHR,DAC Sample and Hold hold time register" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in sample and hold mode)" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in sample and hold mode)" line.long 0x18 "DAC_SHRR,DAC Sample and Hold refresh time register" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid in sample and hold mode)" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid in sample and hold mode)" group.long 0x54++0x3 line.long 0x0 "DAC_AUTOCR,Autonomous mode control register" bitfld.long 0x0 22. "AUTOMODE,DAC Autonomous mode" "0,1" tree.end tree "SEC_DAC1" base ad:0x56021800 group.long 0x0++0x3 line.long 0x0 "DAC_CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC channel2 calibration enable" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable" "0,1,2,3" hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger enable" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable" "0,1" newline bitfld.long 0x0 14. "CEN1,DAC channel1 calibration enable" "0,1" bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable" "0,1,2,3" hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DAC_SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger" "0,1" group.long 0x8++0x23 line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register" hexmask.long.word 0x0 16.--27. 1. "DACC1DHRB,DAC channel1 12-bit right-aligned data B" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register" hexmask.long.word 0x4 20.--31. 1. "DACC1DHRB,DAC channel1 12-bit left-aligned data B" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register" hexmask.long.byte 0x8 8.--15. 1. "DACC1DHRB,DAC channel1 8-bit right-aligned Sdata" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DAC_DHR12R2,DAC channel2 12-bit right aligned data holding register" hexmask.long.word 0xC 16.--27. 1. "DACC2DHRB,DAC channel2 12-bit right-aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DAC_DHR12L2,DAC channel2 12-bit left aligned data holding register" hexmask.long.word 0x10 20.--31. 1. "DACC2DHRB,DAC channel2 12-bit left-aligned data B" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data holding register" hexmask.long.byte 0x14 8.--15. 1. "DACC2DHRB,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding register" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding register" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DAC_DOR1,DAC channel1 data output register" hexmask.long.word 0x0 16.--27. 1. "DACC1DORB,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output" line.long 0x4 "DAC_DOR2,DAC channel2 data output register" hexmask.long.word 0x4 16.--27. 1. "DACC2DORB,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output" group.long 0x34++0x1B line.long 0x0 "DAC_SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time flag" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag" "0,1" rbitfld.long 0x0 28. "DORSTAT2,DAC channel 2 output register status bit" "0,1" rbitfld.long 0x0 27. "DAC2RDY,DAC channel 2 ready status bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time flag" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag" "0,1" newline rbitfld.long 0x0 12. "DORSTAT1,DAC channel1 output register status bit" "0,1" rbitfld.long 0x0 11. "DAC1RDY,DAC channel1 ready status bit" "0,1" line.long 0x4 "DAC_CCR,DAC calibration control register" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming value" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming value" line.long 0x8 "DAC_MCR,DAC mode control register" bitfld.long 0x8 25. "SINFORMAT2,Enable signed format for DAC channel2" "0,1" bitfld.long 0x8 24. "DMADOUBLE2,DAC Channel2 DMA double data mode" "0,1" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x8 14.--15. "HFSEL,High frequency interface mode selection" "0,1,2,3" bitfld.long 0x8 9. "SINFORMAT1,Enable signed format for DAC channel1" "0,1" bitfld.long 0x8 8. "DMADOUBLE1,DAC Channel1 DMA double data mode" "0,1" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode" "0,1,2,3,4,5,6,7" line.long 0xC "DAC_SHSR1,DAC Sample and Hold sample time register 1" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in sample & hold mode)" line.long 0x10 "DAC_SHSR2,DAC channel2 sample and hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in sample and hold mode)" line.long 0x14 "DAC_SHHR,DAC Sample and Hold hold time register" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in sample and hold mode)" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in sample and hold mode)" line.long 0x18 "DAC_SHRR,DAC Sample and Hold refresh time register" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid in sample and hold mode)" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid in sample and hold mode)" group.long 0x54++0x3 line.long 0x0 "DAC_AUTOCR,Autonomous mode control register" bitfld.long 0x0 22. "AUTOMODE,DAC Autonomous mode" "0,1" tree.end tree.end tree "DBGMCU (MCU Debug Component)" base ad:0xE0044000 rgroup.long 0x0++0x3 line.long 0x0 "IDCODE,DBGMCU_IDCODE" hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision" hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device dentification" group.long 0x4++0x13 line.long 0x0 "CR,Debug MCU configuration" bitfld.long 0x0 6.--7. "TRACE_MODE,Trace pin assignment" "0,1,2,3" bitfld.long 0x0 5. "TRACE_EN,trace port and clock" "0,1" bitfld.long 0x0 4. "TRACE_IOEN,Trace pin assignment" "0,1" bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby mode" "0,1" bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0,1" line.long 0x4 "APB1LFZR,Debug MCU APB1L peripheral freeze" bitfld.long 0x4 22. "DBG_I2C2_STOP,I2C2 SMBUS timeout stop in debug" "0,1" bitfld.long 0x4 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stop in debug" "0,1" bitfld.long 0x4 12. "DBG_IWDG_STOP,Independent watchdog counter stop in debug" "0,1" bitfld.long 0x4 11. "DBG_WWDG_STOP,Window watchdog counter stop in debug" "0,1" bitfld.long 0x4 5. "DBG_TIM7_STOP,TIM7 stop in debug" "0,1" newline bitfld.long 0x4 4. "DBG_TIM6_STOP,TIM6 stop in debug" "0,1" bitfld.long 0x4 3. "DBG_TIM5_STOP,TIM5 stop in debug" "0,1" bitfld.long 0x4 2. "DBG_TIM4_STOP,TIM4 stop in debug" "0,1" bitfld.long 0x4 1. "DBG_TIM3_STOP,TIM3 stop in debug" "0,1" bitfld.long 0x4 0. "DBG_TIM2_STOP,TIM2 stop in debug" "0,1" line.long 0x8 "APB1HFZR,Debug MCU APB1H peripheral freeze register" bitfld.long 0x8 5. "DBG_LPTIM2_STOP,LPTIM2 stop in debug" "0,1" bitfld.long 0x8 1. "DBG_I2C4_STOP,I2C4 stop in debug" "0,1" line.long 0xC "APB2FZR,Debug MCU APB2 peripheral freeze register" bitfld.long 0xC 18. "DBG_TIM17_STOP,DBG_TIM17_STOP" "0,1" bitfld.long 0xC 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is" "0,1" bitfld.long 0xC 16. "DBG_TIM15_STOP,TIM15 counter stopped when core is" "0,1" bitfld.long 0xC 13. "DBG_TIM8_STOP,TIM8 stop in debug" "0,1" bitfld.long 0xC 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is" "0,1" line.long 0x10 "APB3FZR,Debug MCU APB3 peripheral freeze register" bitfld.long 0x10 30. "DBG_RTC_STOP,RTC stop in debug" "0,1" bitfld.long 0x10 19. "DBG_LPTIM4_STOP,LPTIM4 stop in debug" "0,1" bitfld.long 0x10 18. "DBG_LPTIM3_STOP,LPTIM3 stop in debug" "0,1" bitfld.long 0x10 17. "DBG_LPTIM1_STOP,LPTIM1 stop in debug" "0,1" bitfld.long 0x10 10. "DBG_I2C3_STOP,I2C3 stop in debug" "0,1" group.long 0x20++0x3 line.long 0x0 "AHB1FZR,Debug MCU AHB1 peripheral freeze register" bitfld.long 0x0 15. "DBG_GPDMA15_STOP,GPDMA channel 15 stop in debug" "0,1" bitfld.long 0x0 14. "DBG_GPDMA14_STOP,GPDMA channel 14 stop in debug" "0,1" bitfld.long 0x0 13. "DBG_GPDMA13_STOP,GPDMA channel 13 stop in debug" "0,1" bitfld.long 0x0 12. "DBG_GPDMA12_STOP,GPDMA channel 12 stop in debug" "0,1" bitfld.long 0x0 11. "DBG_GPDMA11_STOP,GPDMA channel 11 stop in debug" "0,1" newline bitfld.long 0x0 10. "DBG_GPDMA10_STOP,GPDMA channel 10 stop in debug" "0,1" bitfld.long 0x0 9. "DBG_GPDMA9_STOP,GPDMA channel 9 stop in debug" "0,1" bitfld.long 0x0 8. "DBG_GPDMA8_STOP,GPDMA channel 8 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_GPDMA7_STOP,GPDMA channel 7 stop in debug" "0,1" bitfld.long 0x0 6. "DBG_GPDMA6_STOP,GPDMA channel 6 stop in debug" "0,1" newline bitfld.long 0x0 5. "DBG_GPDMA5_STOP,GPDMA channel 5 stop in debug" "0,1" bitfld.long 0x0 4. "DBG_GPDMA4_STOP,GPDMA channel 4 stop in debug" "0,1" bitfld.long 0x0 3. "DBG_GPDMA3_STOP,GPDMA channel 3 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_GPDMA2_STOP,GPDMA channel 2 stop in debug" "0,1" bitfld.long 0x0 1. "DBG_GPDMA1_STOP,GPDMA channel 1 stop in debug" "0,1" newline bitfld.long 0x0 0. "DBG_GPDMA0_STOP,GPDMA channel 0 stop in debug" "0,1" group.long 0x28++0x3 line.long 0x0 "AHB3FZR,Debug MCU AHB3 peripheral freeze register" bitfld.long 0x0 3. "DBG_LPDMA3_STOP,LPDMA channel 3 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_LPDMA2_STOP,LPDMA channel 2 stop in debug" "0,1" bitfld.long 0x0 1. "DBG_LPDMA1_STOP,LPDMA channel 1 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_LPDMA0_STOP,LPDMA channel 0 stop in debug" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rgroup.long 0xFC++0x3 line.long 0x0 "SR,DBGMCU status register" hexmask.long.byte 0x0 8.--15. 1. "AP_LOCKED,AP_LOCKED" hexmask.long.byte 0x0 0.--7. 1. "AP_PRESENT,AP_PRESENT" rgroup.long 0x104++0x3 line.long 0x0 "DBG_AUTH_DEVICE,DBGMCU debug device authentication register" hexmask.long.word 0x0 0.--15. 1. "AUTH_ID,AUTH_ID" endif sif (cpuis("STM32U575*")) rgroup.long 0xFC++0x3 line.long 0x0 "DBGMCU_SR,DBGMCU status register" hexmask.long.byte 0x0 8.--15. 1. "AP_LOCKED,DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)" hexmask.long.byte 0x0 0.--7. 1. "AP_PRESENT,Bit n identifies whether access port AP n is present in device" rgroup.long 0x104++0x3 line.long 0x0 "DBGMCU_DBG_AUTH_DEVICE,DBGMCU debug device authentication register" hexmask.long 0x0 0.--31. 1. "AUTH_ID,Device specific ID" endif sif (cpuis("STM32U585*")) rgroup.long 0xFC++0x3 line.long 0x0 "DBGMCU_SR,DBGMCU status register" hexmask.long.byte 0x0 8.--15. 1. "AP_LOCKED,DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)" hexmask.long.byte 0x0 0.--7. 1. "AP_PRESENT,Bit n identifies whether access port AP n is present in device" rgroup.long 0x104++0x3 line.long 0x0 "DBGMCU_DBG_AUTH_DEVICE,DBGMCU debug device authentication register" hexmask.long 0x0 0.--31. 1. "AUTH_ID,Device specific ID" endif sif (cpuis("STM32U595*")) rgroup.long 0xFC++0x3 line.long 0x0 "SR,DBGMCU status register" hexmask.long.byte 0x0 8.--15. 1. "AP_LOCKED,AP_LOCKED" hexmask.long.byte 0x0 0.--7. 1. "AP_PRESENT,AP_PRESENT" rgroup.long 0x104++0x3 line.long 0x0 "DBG_AUTH_DEVICE,DBGMCU debug device authentication register" hexmask.long.word 0x0 0.--15. 1. "AUTH_ID,AUTH_ID" endif sif (cpuis("STM32U599*")) rgroup.long 0xFC++0x3 line.long 0x0 "SR,DBGMCU status register" hexmask.long.byte 0x0 8.--15. 1. "AP_LOCKED,AP_LOCKED" hexmask.long.byte 0x0 0.--7. 1. "AP_PRESENT,AP_PRESENT" rgroup.long 0x104++0x3 line.long 0x0 "DBG_AUTH_DEVICE,DBGMCU debug device authentication register" hexmask.long.word 0x0 0.--15. 1. "AUTH_ID,AUTH_ID" endif sif (cpuis("STM32U5A5*")) rgroup.long 0xFC++0x3 line.long 0x0 "SR,DBGMCU status register" hexmask.long.byte 0x0 8.--15. 1. "AP_LOCKED,AP_LOCKED" hexmask.long.byte 0x0 0.--7. 1. "AP_PRESENT,AP_PRESENT" rgroup.long 0x104++0x3 line.long 0x0 "DBG_AUTH_DEVICE,DBGMCU debug device authentication register" hexmask.long.word 0x0 0.--15. 1. "AUTH_ID,AUTH_ID" endif sif (cpuis("STM32U5A9*")) rgroup.long 0xFC++0x3 line.long 0x0 "SR,DBGMCU status register" hexmask.long.byte 0x0 8.--15. 1. "AP_LOCKED,AP_LOCKED" hexmask.long.byte 0x0 0.--7. 1. "AP_PRESENT,AP_PRESENT" rgroup.long 0x104++0x3 line.long 0x0 "DBG_AUTH_DEVICE,DBGMCU debug device authentication register" hexmask.long.word 0x0 0.--15. 1. "AUTH_ID,AUTH_ID" endif sif (cpuis("STM32U5F*")) rgroup.long 0xFC++0x3 line.long 0x0 "SR,DBGMCU status register" hexmask.long.byte 0x0 8.--15. 1. "AP_LOCKED,AP_LOCKED" hexmask.long.byte 0x0 0.--7. 1. "AP_PRESENT,AP_PRESENT" rgroup.long 0x104++0x3 line.long 0x0 "DBG_AUTH_DEVICE,DBGMCU debug device authentication register" hexmask.long.word 0x0 0.--15. 1. "AUTH_ID,AUTH_ID" endif sif (cpuis("STM32U5G*")) rgroup.long 0xFC++0x3 line.long 0x0 "SR,DBGMCU status register" hexmask.long.byte 0x0 8.--15. 1. "AP_LOCKED,AP_LOCKED" hexmask.long.byte 0x0 0.--7. 1. "AP_PRESENT,AP_PRESENT" rgroup.long 0x104++0x3 line.long 0x0 "DBG_AUTH_DEVICE,DBGMCU debug device authentication register" hexmask.long.word 0x0 0.--15. 1. "AUTH_ID,AUTH_ID" endif rgroup.long 0x100++0x3 line.long 0x0 "DBGMCU_DBG_AUTH_HOST,DBGMCU debug host authentication register" hexmask.long 0x0 0.--31. 1. "AUTH_KEY,AUTH_KEY" rgroup.long 0xFD0++0x3 line.long 0x0 "PIDR4,Debug MCU CoreSight peripheral identity register 4" hexmask.long.byte 0x0 4.--7. 1. "KCOUNT_4,register file size" hexmask.long.byte 0x0 0.--3. 1. "JEP106CON,JEP106 continuation code" rgroup.long 0xFE0++0x1F line.long 0x0 "PIDR0,Debug MCU CoreSight peripheral identity register 0" hexmask.long.byte 0x0 0.--7. 1. "PARTNUM,part number bits [7:0]" line.long 0x4 "PIDR1,Debug MCU CoreSight peripheral identity register 1" hexmask.long.byte 0x4 4.--7. 1. "JEP106ID,JEP106 identity code bits [3:0]" hexmask.long.byte 0x4 0.--3. 1. "PARTNUM,part number bits [11:8]" line.long 0x8 "PIDR2,Debug MCU CoreSight peripheral identity register 2" hexmask.long.byte 0x8 4.--7. 1. "REVISION,component revision number" bitfld.long 0x8 3. "JEDEC,JEDEC assigned value" "0,1" bitfld.long 0x8 0.--2. "JEP106ID,JEP106 identity code bits [6:4]" "0,1,2,3,4,5,6,7" line.long 0xC "PIDR3,Debug MCU CoreSight peripheral identity register 3" hexmask.long.byte 0xC 4.--7. 1. "REVAND,metal fix version" hexmask.long.byte 0xC 0.--3. 1. "CMOD,customer modified" line.long 0x10 "CIDR0,Debug MCU CoreSight component identity register 0" hexmask.long.byte 0x10 0.--7. 1. "PREAMBLE,component identification bits [7:0]" line.long 0x14 "CIDR1,Debug MCU CoreSight component identity register 1" hexmask.long.byte 0x14 4.--7. 1. "CLASS,component identification bits [15:12] - component class" hexmask.long.byte 0x14 0.--3. 1. "PREAMBLE,component identification bits [11:8]" line.long 0x18 "CIDR2,Debug MCU CoreSight component identity register 2" hexmask.long.byte 0x18 0.--7. 1. "PREAMBLE,component identification bits [23:16]" line.long 0x1C "CIDR3,Debug MCU CoreSight component identity register 3" hexmask.long.byte 0x1C 0.--7. 1. "PREAMBLE,component identification bits [31:24]" tree.end tree "DCACHE (Data Cache)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "DCACHE" base ad:0x40031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" newline bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" endif line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" endif sif (cpuis("STM32U575*")) hexmask.long 0x4 0.--31. 1. "CMDENDADDR,CMDENDADDR" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_DCACHE" base ad:0x50031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" newline bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" endif line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" endif sif (cpuis("STM32U575*")) hexmask.long 0x4 0.--31. 1. "CMDENDADDR,CMDENDADDR" endif tree.end endif sif (cpuis("STM32U585*")) tree "DCACHE" base ad:0x40031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 0.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 0.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE" base ad:0x50031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 0.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 0.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U595*")) tree "DCACHE1" base ad:0x40031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE1" base ad:0x50031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U599*")) tree "DCACHE1" base ad:0x40031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE1" base ad:0x50031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U599*")) tree "DCACHE2" base ad:0x40031800 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE2" base ad:0x50031800 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U5A5*")) tree "DCACHE1" base ad:0x40031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE1" base ad:0x50031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U5A9*")) tree "DCACHE1" base ad:0x40031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE1" base ad:0x50031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U5A9*")) tree "DCACHE2" base ad:0x40031800 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE2" base ad:0x50031800 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U5F*")) tree "DCACHE1" base ad:0x40031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE1" base ad:0x50031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U5F*")) tree "DCACHE2" base ad:0x40031800 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE2" base ad:0x50031800 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U5G*")) tree "DCACHE1" base ad:0x40031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE1" base ad:0x50031400 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif sif (cpuis("STM32U5G*")) tree "DCACHE2" base ad:0x40031800 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end tree "SEC_DCACHE2" base ad:0x50031800 group.long 0x0++0x3 line.long 0x0 "DCACHE_CR,DCACHE control register" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 23. "WMISSMRST,WMISSMRST" "0,1" bitfld.long 0x0 22. "WHITMRST,WHITMRST" "0,1" bitfld.long 0x0 21. "WMISSMEN,WMISSMEN" "0,1" bitfld.long 0x0 20. "WHITMEN,WHITMEN" "0,1" bitfld.long 0x0 19. "RMISSMRST,RMISSMRST" "0,1" bitfld.long 0x0 18. "RHITMRST,RHITMRST" "0,1" newline bitfld.long 0x0 17. "RMISSMEN,RMISSMEN" "0,1" bitfld.long 0x0 16. "RHITMEN,RHITMEN" "0,1" bitfld.long 0x0 11. "STARTCMD,STARTCMD" "0,1" bitfld.long 0x0 8.--10. "CACHECMD,CACHECMD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DCACHE_SR,DCACHE status register" bitfld.long 0x0 4. "CMDENDF,CMDENDF" "0,1" bitfld.long 0x0 3. "BUSYCMDF,BUSYCMDF" "0,1" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "DCACHE_IER,DCACHE interrupt enable" bitfld.long 0x0 4. "CMDENDIE,CMDENDIE" "0,1" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "DCACHE_FCR,DCACHE flag clear register" bitfld.long 0x0 4. "CCMDENDF,CCMDENDF" "0,1" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "DCACHE_RHMONR,DCACHE read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,RHITMON" line.long 0x4 "DCACHE_RMMONR,DCACHE read-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MRISSMON,RMISSMON" rgroup.long 0x20++0x7 line.long 0x0 "DCACHE_WHMONR,write-hit monitor register" hexmask.long 0x0 0.--31. 1. "WHITMON,WHITMON" line.long 0x4 "DCACHE_WMMONR,write-miss monitor register" hexmask.long.word 0x4 0.--15. 1. "WMISSMON,WMISSMON" group.long 0x28++0x7 line.long 0x0 "DCACHE_CMDRSADDRR,command range start address register" hexmask.long 0x0 4.--31. 1. "CMDSTARTADDR,CMDSTARTADDR" line.long 0x4 "DCACHE_CMDREADDRR,command range start address register" hexmask.long 0x4 4.--31. 1. "CMDENDADDR,CMDENDADDR" tree.end endif tree.end tree "DCB (Debug Control Block)" base ad:0xE000EE08 group.long 0x0++0x3 line.long 0x0 "DSCSR,Debug Security Control and Status Register" bitfld.long 0x0 16. "CDS,Current domain Secure" "0,1" tree.end tree "DCMI (Digital Camera Interface)" base ad:0x0 tree "DCMI" base ad:0x4202C000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 20. "OELS,Odd/Even Line Select (Line Select Start)" "0,1" bitfld.long 0x0 19. "LSM,Line Select mode" "0,1" bitfld.long 0x0 18. "OEBS,Odd/Even Byte Select (Byte Select Start)" "0,1" bitfld.long 0x0 16.--17. "BSM,Byte Select mode" "0,1,2,3" bitfld.long 0x0 14. "ENABLE,DCMI enable" "0,1" bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0,1,2,3" bitfld.long 0x0 8.--9. "FCRC,Frame capture rate control" "0,1,2,3" bitfld.long 0x0 7. "VSPOL,Vertical synchronization polarity" "0,1" bitfld.long 0x0 6. "HSPOL,Horizontal synchronization polarity" "0,1" newline bitfld.long 0x0 5. "PCKPOL,Pixel clock polarity" "0,1" bitfld.long 0x0 4. "ESS,Embedded synchronization select" "0,1" bitfld.long 0x0 3. "JPEG,JPEG format" "0,1" bitfld.long 0x0 2. "CROP,Crop feature" "0,1" bitfld.long 0x0 1. "CM,Capture mode" "0,1" bitfld.long 0x0 0. "CAPTURE,Capture enable" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "SR,status register" bitfld.long 0x0 2. "FNE,FIFO not empty" "0,1" bitfld.long 0x0 1. "VSYNC,Vertical synchronization" "0,1" bitfld.long 0x0 0. "HSYNC,Horizontal synchronization" "0,1" line.long 0x4 "RIS,raw interrupt status register" bitfld.long 0x4 4. "LINE_RIS,Line raw interrupt status" "0,1" bitfld.long 0x4 3. "VSYNC_RIS,DCMI_VSYNC raw interrupt status" "0,1" bitfld.long 0x4 2. "ERR_RIS,Synchronization error raw interrupt status" "0,1" bitfld.long 0x4 1. "OVR_RIS,Overrun raw interrupt status" "0,1" bitfld.long 0x4 0. "FRAME_RIS,Capture complete raw interrupt status" "0,1" group.long 0xC++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 4. "LINE_IE,Line interrupt enable" "0,1" bitfld.long 0x0 3. "VSYNC_IE,DCMI_VSYNC interrupt enable" "0,1" bitfld.long 0x0 2. "ERR_IE,Synchronization error interrupt enable" "0,1" bitfld.long 0x0 1. "OVR_IE,Overrun interrupt enable" "0,1" bitfld.long 0x0 0. "FRAME_IE,Capture complete interrupt enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MIS,masked interrupt status register" bitfld.long 0x0 4. "LINE_MIS,Line masked interrupt status" "0,1" bitfld.long 0x0 3. "VSYNC_MIS,VSYNC masked interrupt status" "0,1" bitfld.long 0x0 2. "ERR_MIS,Synchronization error masked interrupt status" "0,1" bitfld.long 0x0 1. "OVR_MIS,Overrun masked interrupt status" "0,1" bitfld.long 0x0 0. "FRAME_MIS,Capture complete masked interrupt status" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 4. "LINE_ISC,line interrupt status clear" "0,1" bitfld.long 0x0 3. "VSYNC_ISC,Vertical Synchronization interrupt status clear" "0,1" bitfld.long 0x0 2. "ERR_ISC,Synchronization error interrupt status clear" "0,1" bitfld.long 0x0 1. "OVR_ISC,Overrun interrupt status clear" "0,1" bitfld.long 0x0 0. "FRAME_ISC,Capture complete interrupt status clear" "0,1" group.long 0x18++0xF line.long 0x0 "ESCR,background offset register" hexmask.long.byte 0x0 24.--31. 1. "FEC,Frame end delimiter code" hexmask.long.byte 0x0 16.--23. 1. "LEC,Line end delimiter code" hexmask.long.byte 0x0 8.--15. 1. "LSC,Line start delimiter code" hexmask.long.byte 0x0 0.--7. 1. "FSC,Frame start delimiter code" line.long 0x4 "ESUR,embedded synchronization unmask register" hexmask.long.byte 0x4 24.--31. 1. "FEU,Frame end delimiter unmask" hexmask.long.byte 0x4 16.--23. 1. "LEU,Line end delimiter unmask" hexmask.long.byte 0x4 8.--15. 1. "LSU,Line start delimiter unmask" hexmask.long.byte 0x4 0.--7. 1. "FSU,Frame start delimiter unmask" line.long 0x8 "CWSTRT,crop window start" hexmask.long.word 0x8 16.--28. 1. "VST,Vertical start line count" hexmask.long.word 0x8 0.--13. 1. "HOFFCNT,Horizontal offset count" line.long 0xC "CWSIZE,crop window size" hexmask.long.word 0xC 16.--29. 1. "VLINE,Vertical line count" hexmask.long.word 0xC 0.--13. 1. "CAPCNT,Capture count" rgroup.long 0x28++0x3 line.long 0x0 "DR,data register" hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0" tree.end tree "SEC_DCMI" base ad:0x5202C000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 20. "OELS,Odd/Even Line Select (Line Select Start)" "0,1" bitfld.long 0x0 19. "LSM,Line Select mode" "0,1" bitfld.long 0x0 18. "OEBS,Odd/Even Byte Select (Byte Select Start)" "0,1" bitfld.long 0x0 16.--17. "BSM,Byte Select mode" "0,1,2,3" bitfld.long 0x0 14. "ENABLE,DCMI enable" "0,1" bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0,1,2,3" bitfld.long 0x0 8.--9. "FCRC,Frame capture rate control" "0,1,2,3" bitfld.long 0x0 7. "VSPOL,Vertical synchronization polarity" "0,1" bitfld.long 0x0 6. "HSPOL,Horizontal synchronization polarity" "0,1" newline bitfld.long 0x0 5. "PCKPOL,Pixel clock polarity" "0,1" bitfld.long 0x0 4. "ESS,Embedded synchronization select" "0,1" bitfld.long 0x0 3. "JPEG,JPEG format" "0,1" bitfld.long 0x0 2. "CROP,Crop feature" "0,1" bitfld.long 0x0 1. "CM,Capture mode" "0,1" bitfld.long 0x0 0. "CAPTURE,Capture enable" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "SR,status register" bitfld.long 0x0 2. "FNE,FIFO not empty" "0,1" bitfld.long 0x0 1. "VSYNC,Vertical synchronization" "0,1" bitfld.long 0x0 0. "HSYNC,Horizontal synchronization" "0,1" line.long 0x4 "RIS,raw interrupt status register" bitfld.long 0x4 4. "LINE_RIS,Line raw interrupt status" "0,1" bitfld.long 0x4 3. "VSYNC_RIS,DCMI_VSYNC raw interrupt status" "0,1" bitfld.long 0x4 2. "ERR_RIS,Synchronization error raw interrupt status" "0,1" bitfld.long 0x4 1. "OVR_RIS,Overrun raw interrupt status" "0,1" bitfld.long 0x4 0. "FRAME_RIS,Capture complete raw interrupt status" "0,1" group.long 0xC++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 4. "LINE_IE,Line interrupt enable" "0,1" bitfld.long 0x0 3. "VSYNC_IE,DCMI_VSYNC interrupt enable" "0,1" bitfld.long 0x0 2. "ERR_IE,Synchronization error interrupt enable" "0,1" bitfld.long 0x0 1. "OVR_IE,Overrun interrupt enable" "0,1" bitfld.long 0x0 0. "FRAME_IE,Capture complete interrupt enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MIS,masked interrupt status register" bitfld.long 0x0 4. "LINE_MIS,Line masked interrupt status" "0,1" bitfld.long 0x0 3. "VSYNC_MIS,VSYNC masked interrupt status" "0,1" bitfld.long 0x0 2. "ERR_MIS,Synchronization error masked interrupt status" "0,1" bitfld.long 0x0 1. "OVR_MIS,Overrun masked interrupt status" "0,1" bitfld.long 0x0 0. "FRAME_MIS,Capture complete masked interrupt status" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 4. "LINE_ISC,line interrupt status clear" "0,1" bitfld.long 0x0 3. "VSYNC_ISC,Vertical Synchronization interrupt status clear" "0,1" bitfld.long 0x0 2. "ERR_ISC,Synchronization error interrupt status clear" "0,1" bitfld.long 0x0 1. "OVR_ISC,Overrun interrupt status clear" "0,1" bitfld.long 0x0 0. "FRAME_ISC,Capture complete interrupt status clear" "0,1" group.long 0x18++0xF line.long 0x0 "ESCR,background offset register" hexmask.long.byte 0x0 24.--31. 1. "FEC,Frame end delimiter code" hexmask.long.byte 0x0 16.--23. 1. "LEC,Line end delimiter code" hexmask.long.byte 0x0 8.--15. 1. "LSC,Line start delimiter code" hexmask.long.byte 0x0 0.--7. 1. "FSC,Frame start delimiter code" line.long 0x4 "ESUR,embedded synchronization unmask register" hexmask.long.byte 0x4 24.--31. 1. "FEU,Frame end delimiter unmask" hexmask.long.byte 0x4 16.--23. 1. "LEU,Line end delimiter unmask" hexmask.long.byte 0x4 8.--15. 1. "LSU,Line start delimiter unmask" hexmask.long.byte 0x4 0.--7. 1. "FSU,Frame start delimiter unmask" line.long 0x8 "CWSTRT,crop window start" hexmask.long.word 0x8 16.--28. 1. "VST,Vertical start line count" hexmask.long.word 0x8 0.--13. 1. "HOFFCNT,Horizontal offset count" line.long 0xC "CWSIZE,crop window size" hexmask.long.word 0xC 16.--29. 1. "VLINE,Vertical line count" hexmask.long.word 0xC 0.--13. 1. "CAPCNT,Capture count" rgroup.long 0x28++0x3 line.long 0x0 "DR,data register" hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0" tree.end tree.end tree "DLYB (Delay Block)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "DLYBOS" base ad:0x420CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS" base ad:0x520CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "DLYBSD" base ad:0x420C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD" base ad:0x520C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U575*")) tree "DLYBOS1" base ad:0x420CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS1" base ad:0x520CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U575*")) tree "DLYBOS2" base ad:0x420CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS2" base ad:0x520CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U575*")) tree "DLYBSD1" base ad:0x420C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD1" base ad:0x520C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U575*")) tree "DLYBSD2" base ad:0x420C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD2" base ad:0x520C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U585*")) tree "DLYBOS1" base ad:0x420CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS1" base ad:0x520CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U585*")) tree "DLYBOS2" base ad:0x420CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS2" base ad:0x520CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U585*")) tree "DLYBSD1" base ad:0x420C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD1" base ad:0x520C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U585*")) tree "DLYBSD2" base ad:0x420C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD2" base ad:0x520C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U595*")) tree "DLYBOS1" base ad:0x420CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS1" base ad:0x520CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U595*")) tree "DLYBOS2" base ad:0x420CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS2" base ad:0x520CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U595*")) tree "DLYBSD1" base ad:0x420C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD1" base ad:0x520C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U595*")) tree "DLYBSD2" base ad:0x420C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD2" base ad:0x520C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U599*")) tree "DLYBOS1" base ad:0x420CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS1" base ad:0x520CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U599*")) tree "DLYBOS2" base ad:0x420CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS2" base ad:0x520CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U599*")) tree "DLYBSD1" base ad:0x420C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD1" base ad:0x520C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U599*")) tree "DLYBSD2" base ad:0x420C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD2" base ad:0x520C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5A5*")) tree "DLYBOS1" base ad:0x420CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS1" base ad:0x520CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5A5*")) tree "DLYBOS2" base ad:0x420CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS2" base ad:0x520CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5A5*")) tree "DLYBSD1" base ad:0x420C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD1" base ad:0x520C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5A5*")) tree "DLYBSD2" base ad:0x420C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD2" base ad:0x520C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5A9*")) tree "DLYBOS1" base ad:0x420CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS1" base ad:0x520CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5A9*")) tree "DLYBOS2" base ad:0x420CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS2" base ad:0x520CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5A9*")) tree "DLYBSD1" base ad:0x420C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD1" base ad:0x520C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5A9*")) tree "DLYBSD2" base ad:0x420C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD2" base ad:0x520C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5F*")) tree "DLYBOS1" base ad:0x420CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS1" base ad:0x520CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5F*")) tree "DLYBOS2" base ad:0x420CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS2" base ad:0x520CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5F*")) tree "DLYBSD1" base ad:0x420C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD1" base ad:0x520C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5F*")) tree "DLYBSD2" base ad:0x420C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD2" base ad:0x520C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5G*")) tree "DLYBOS1" base ad:0x420CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS1" base ad:0x520CF000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5G*")) tree "DLYBOS2" base ad:0x420CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBOS2" base ad:0x520CF400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5G*")) tree "DLYBSD1" base ad:0x420C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD1" base ad:0x520C8400 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif sif (cpuis("STM32U5G*")) tree "DLYBSD2" base ad:0x420C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end tree "SEC_DLYBSD2" base ad:0x520C8800 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,control register" bitfld.long 0x0 1. "SEN,OPALPM" "0,1" bitfld.long 0x0 0. "DEN,Operational amplifier Enable" "0,1" line.long 0x4 "DLYB_CFGR,configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" tree.end endif tree.end sif (cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U595*")||cpuis("STM32U599*")||cpuis("STM32U5A5*")||cpuis("STM32U5A9*")||cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "DMA2D (Chrom-ART Accelerator Controller)" base ad:0x0 sif (cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U595*")) tree "DMA2D" base ad:0x4002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" sif (cpuis("STM32U575*")||cpuis("STM32U585*")) bitfld.long 0x0 16.--17. "MODE,DMA2D mode" "0,1,2,3" endif sif (cpuis("STM32U595*")) bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" endif bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend" "0,1" bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end endif sif (cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U595*")) tree "SEC_DMA2D" base ad:0x5002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" sif (cpuis("STM32U575*")||cpuis("STM32U585*")) bitfld.long 0x0 16.--17. "MODE,DMA2D mode" "0,1,2,3" endif sif (cpuis("STM32U595*")) bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" endif bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend" "0,1" bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end endif sif (cpuis("STM32U599*")) tree "DMA2D" base ad:0x4002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end tree "SEC_DMA2D" base ad:0x5002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end endif sif (cpuis("STM32U5A5*")) tree "DMA2D" base ad:0x4002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end tree "SEC_DMA2D" base ad:0x5002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end endif sif (cpuis("STM32U5A9*")) tree "DMA2D" base ad:0x4002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end tree "SEC_DMA2D" base ad:0x5002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end endif sif (cpuis("STM32U5F*")) tree "DMA2D" base ad:0x4002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end tree "SEC_DMA2D" base ad:0x5002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end endif sif (cpuis("STM32U5G*")) tree "DMA2D" base ad:0x4002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end tree "SEC_DMA2D" base ad:0x5002B000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt" "0,1" bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable" "0,1" bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable" "0,1" bitfld.long 0x0 6. "LOM,Line Offset Mode" "0,1" bitfld.long 0x0 2. "ABORT,Abort" "0,1" bitfld.long 0x0 1. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "IFCR,interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "FGOR,foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "BGMAR,background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address" line.long 0x10 "BGOR,background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "FGPFCCR,foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x14 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x14 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0,1" hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "FGCOLR,foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value" line.long 0x1C "BGPFCCR,background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x1C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0,1,2,3" hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" bitfld.long 0x1C 4. "CCM,CLUT Color mode" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "BGCOLR,background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value" line.long 0x24 "FGCMAR,foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address" line.long 0x28 "BGCMAR,background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "OPFCCR,output PFC control register" bitfld.long 0x2C 21. "RBS,Red Blue Swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0,1" bitfld.long 0x2C 9. "SB,Swap Bytes" "0,1" bitfld.long 0x2C 0.--2. "CM,Color mode" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR_RGB888,output color register" hexmask.long.byte 0x30 24.--31. 1. "APLHA,Alpha Channel Value" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value" hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value" group.long 0x38++0x3 line.long 0x0 "OCOLR_RGB565,output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value in RGB565 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "OCOLR_ARGB1555,output color register" bitfld.long 0x0 15. "A,Alpha channel value in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value in ARGB1555 mode" hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "OCOLR_ARGB4444,output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value in ARGB4444 mode" hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value in ARGB4444 mode" line.long 0x4 "OMAR,output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory Address" line.long 0x8 "OOR,output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line Offset" line.long 0xC "NLR,number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines" line.long 0x10 "LWR,line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark" line.long 0x14 "AMTCR,AHB master timer configuration" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead Time" bitfld.long 0x14 0. "EN,Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "FGCLUT,FGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x800++0x3 line.long 0x0 "BGCLUT,BGCLUT" hexmask.long.byte 0x0 24.--31. 1. "APLHA,APLHA" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" tree.end endif tree.end endif sif (cpuis("STM32U599*")||cpuis("STM32U5A9*")||cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "DSI (Display Serial Interface)" base ad:0x0 tree "DSI" base ad:0x40016C00 rgroup.long 0x0++0x3 line.long 0x0 "DSI_VR,DSI Host version register" hexmask.long 0x0 0.--31. 1. "VERSION,Version of the DSI Host" group.long 0x4++0x17 line.long 0x0 "DSI_CR,DSI Host control register" bitfld.long 0x0 0. "EN,Enable" "0: DSI Host disabled (under reset),1: DSI Host enabled" line.long 0x4 "DSI_CCR,DSI Host clock control register" hexmask.long.byte 0x4 8.--15. 1. "TOCKDIV,Timeout clock division" hexmask.long.byte 0x4 0.--7. 1. "TXECKDIV,TX escape clock division" line.long 0x8 "DSI_LVCIDR,DSI Host LTDC VCID register" bitfld.long 0x8 0.--1. "VCID,Virtual channel ID" "0,1,2,3" line.long 0xC "DSI_LCOLCR,DSI Host LTDC color coding register" bitfld.long 0xC 8. "LPE,Loosely packet enable" "0: Loosely packet variant disabled,1: Loosely packet variant enabled" hexmask.long.byte 0xC 0.--3. 1. "COLC,Color coding" line.long 0x10 "DSI_LPCR,DSI Host LTDC polarity configuration register" bitfld.long 0x10 2. "HSP,HSYNC polarity" "0: HSYNC pin active high (default),1: VSYNC pin active low" bitfld.long 0x10 1. "VSP,VSYNC polarity" "0: Shutdown pin active high (default),1: Shutdown pin active low" newline bitfld.long 0x10 0. "DEP,Data enable polarity" "0: Data enable pin active high (default),1: Data enable pin active low" line.long 0x14 "DSI_LPMCR,DSI Host low-power mode configuration register" hexmask.long.byte 0x14 16.--23. 1. "LPSIZE,Largest packet size" hexmask.long.byte 0x14 0.--7. 1. "VLPSIZE,VACT largest packet size" group.long 0x2C++0x47 line.long 0x0 "DSI_PCR,DSI Host protocol configuration register" bitfld.long 0x0 5. "ETTXLPE,EoTp transmission in low-power enable" "0: EoTp transmission in low-power is disabled.,1: EoTp transmission in low-power is enabled." bitfld.long 0x0 4. "CRCRXE,CRC reception enable" "0: CRC reception is disabled.,1: CRC reception is enabled." newline bitfld.long 0x0 3. "ECCRXE,ECC reception enable" "0: ECC reception is disabled.,1: ECC reception is enabled." bitfld.long 0x0 2. "BTAE,Bus-turn-around enable" "0: Bus-turn-around request is disabled.,1: Bus-turn-around request is enabled." newline bitfld.long 0x0 1. "ETRXE,EoTp reception enable" "0: EoTp reception is disabled.,1: EoTp reception is enabled." bitfld.long 0x0 0. "ETTXE,EoTp transmission enable" "0: EoTp transmission is disabled.,1: EoTp transmission is enabled." line.long 0x4 "DSI_GVCIDR,DSI Host generic VCID register" bitfld.long 0x4 16.--17. "VCIDTX,Virtual channel ID for transmission" "0,1,2,3" bitfld.long 0x4 0.--1. "VCIDRX,Virtual channel ID for reception" "0,1,2,3" line.long 0x8 "DSI_MCR,DSI Host mode configuration register" bitfld.long 0x8 0. "CMDM,Command mode" "0: DSI Host is configured in video mode.,1: DSI Host is configured in command mode." line.long 0xC "DSI_VMCR,DSI Host video mode configuration register" bitfld.long 0xC 24. "PGO,Pattern generator orientation" "0: Vertical color bars.,1: Horizontal color bars." bitfld.long 0xC 20. "PGM,Pattern generator mode" "0: Color bars (horizontal or vertical).,1: BER pattern (vertical only)." newline bitfld.long 0xC 16. "PGE,Pattern generator enable" "0: Pattern generator is disabled.,1: Pattern generator is enabled." bitfld.long 0xC 15. "LPCE,Low-power command enable" "0: Command transmission in low-power mode is..,1: Command transmission in low-power mode is enabled." newline bitfld.long 0xC 14. "FBTAAE,Frame bus-turn-around acknowledge enable" "0: Acknowledge response at the end of a frame is..,1: Acknowledge response at the end of a frame is.." bitfld.long 0xC 13. "LPHFPE,Low-power horizontal front-porch enable" "0: Return to low-power inside the HFP period is..,1: Return to low-power inside the HFP period is.." newline bitfld.long 0xC 12. "LPHBPE,Low-power horizontal back-porch enable" "0: Return to low-power inside the HBP period is..,1: Return to low-power inside the HBP period is.." bitfld.long 0xC 11. "LPVAE,Low-power vertical active enable" "0: Return to low-power inside the VACT is disabled.,1: Return to low-power inside the VACT is enabled." newline bitfld.long 0xC 10. "LPVFPE,Low-power vertical front-porch enable" "0: Return to low-power inside the VFP is disabled.,1: Return to low-power inside the VFP is enabled." bitfld.long 0xC 9. "LPVBPE,Low-power vertical back-porch enable" "0: Return to low-power inside the VBP is disabled.,1: Return to low-power inside the VBP is enabled." newline bitfld.long 0xC 8. "LPVSAE,Low-power vertical sync active enable" "0: Return to low-power inside the VSA is disabled.,1: Return to low-power inside the VSA is enabled" bitfld.long 0xC 0.--1. "VMT,Video mode type" "0: Non-burst with sync pulses.,1: Non-burst with sync events.,?,?" line.long 0x10 "DSI_VPCR,DSI Host video packet configuration register" hexmask.long.word 0x10 0.--13. 1. "VPSIZE,Video packet size" line.long 0x14 "DSI_VCCR,DSI Host video chunks configuration register" hexmask.long.word 0x14 0.--12. 1. "NUMC,Number of chunks" line.long 0x18 "DSI_VNPCR,DSI Host video null packet configuration register" hexmask.long.word 0x18 0.--12. 1. "NPSIZE,Null packet size" line.long 0x1C "DSI_VHSACR,DSI Host video HSA configuration register" hexmask.long.word 0x1C 0.--11. 1. "HSA,Horizontal synchronism active duration" line.long 0x20 "DSI_VHBPCR,DSI Host video HBP configuration register" hexmask.long.word 0x20 0.--11. 1. "HBP,Horizontal back-porch duration" line.long 0x24 "DSI_VLCR,DSI Host video line configuration register" hexmask.long.word 0x24 0.--14. 1. "HLINE,Horizontal line duration" line.long 0x28 "DSI_VVSACR,DSI Host video VSA configuration register" hexmask.long.word 0x28 0.--9. 1. "VSA,Vertical synchronism active duration" line.long 0x2C "DSI_VVBPCR,DSI Host video VBP configuration register" hexmask.long.word 0x2C 0.--9. 1. "VBP,Vertical back-porch duration" line.long 0x30 "DSI_VVFPCR,DSI Host video VFP configuration register" hexmask.long.word 0x30 0.--9. 1. "VFP,Vertical front-porch duration" line.long 0x34 "DSI_VVACR,DSI Host video VA configuration register" hexmask.long.word 0x34 0.--13. 1. "VA,Vertical active duration" line.long 0x38 "DSI_LCCR,DSI Host LTDC command configuration register" hexmask.long.word 0x38 0.--15. 1. "CMDSIZE,Command size" line.long 0x3C "DSI_CMCR,DSI Host command mode configuration register" bitfld.long 0x3C 24. "MRDPS,Maximum read packet size" "0: High-speed,1: Low-power" bitfld.long 0x3C 19. "DLWTX,DCS long write transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 18. "DSR0TX,DCS short read zero parameter transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 17. "DSW1TX,DCS short read one parameter transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 16. "DSW0TX,DCS short write zero parameter transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 14. "GLWTX,Generic long write transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 13. "GSR2TX,Generic short read two parameters transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 12. "GSR1TX,Generic short read one parameters transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 11. "GSR0TX,Generic short read zero parameters transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 10. "GSW2TX,Generic short write two parameters transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 9. "GSW1TX,Generic short write one parameters transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 8. "GSW0TX,Generic short write zero parameters transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 1. "ARE,Acknowledge request enable" "0: Acknowledge request is disabled.,1: Acknowledge request is enabled." bitfld.long 0x3C 0. "TEARE,Tearing effect acknowledge request enable" "0: Tearing effect acknowledge request is disabled.,1: Tearing effect acknowledge request is enabled." line.long 0x40 "DSI_GHCR,DSI Host generic header configuration register" hexmask.long.byte 0x40 16.--23. 1. "WCMSB,WordCount MSB" hexmask.long.byte 0x40 8.--15. 1. "WCLSB,WordCount LSB" newline bitfld.long 0x40 6.--7. "VCID,Channel" "0,1,2,3" hexmask.long.byte 0x40 0.--5. 1. "DT,Type" line.long 0x44 "DSI_GPDR,DSI Host generic payload data register" hexmask.long.byte 0x44 24.--31. 1. "DATA4,Payload byte 4" hexmask.long.byte 0x44 16.--23. 1. "DATA3,Payload byte 3" newline hexmask.long.byte 0x44 8.--15. 1. "DATA2,Payload byte 2" hexmask.long.byte 0x44 0.--7. 1. "DATA1,Payload byte 1" rgroup.long 0x74++0x3 line.long 0x0 "DSI_GPSR,DSI Host generic packet status register" bitfld.long 0x0 19. "PBF,Payload buffer full" "0: Payload internal buffer not full,1: Payload internal buffer full" bitfld.long 0x0 18. "PBE,Payload buffer empty" "0: Payload internal buffer not empty,1: Payload internal buffer empty" newline bitfld.long 0x0 17. "CMDBF,Command buffer full" "0: Command internal buffer not full,1: Command internal buffer full" bitfld.long 0x0 16. "CMDBE,Command buffer empty" "0: Payload internal buffer not full,1: Payload internal buffer full" newline bitfld.long 0x0 6. "RCB,Read command busy" "0: No read command on going,1: Read command on going" bitfld.long 0x0 5. "PRDFF,Payload read FIFO full" "0: Read payload FIFO not full,1: Read payload FIFO ful." newline bitfld.long 0x0 4. "PRDFE,Payload read FIFO empty" "0: Read payload FIFO not empty,1: Read payload FIFO empty" bitfld.long 0x0 3. "PWRFF,Payload write FIFO full" "0: Write payload FIFO not full,1: Write payload FIFO full" newline bitfld.long 0x0 2. "PWRFE,Payload write FIFO empty" "0: Write payload FIFO not empty,1: Write payload FIFO empty" bitfld.long 0x0 1. "CMDFF,Command FIFO full" "0: Write payload FIFO not full,1: Write payload FIFO full" newline bitfld.long 0x0 0. "CMDFE,Command FIFO empty" "0: Write payload FIFO not empty,1: Write payload FIFO empty" group.long 0x78++0x17 line.long 0x0 "DSI_TCCR0,DSI Host timeout counter configuration register 0" hexmask.long.word 0x0 16.--31. 1. "HSTX_TOCNT,High-speed transmission timeout counter" hexmask.long.word 0x0 0.--15. 1. "LPRX_TOCNT,Low-power reception timeout counter" line.long 0x4 "DSI_TCCR1,DSI Host timeout counter configuration register 1" hexmask.long.word 0x4 0.--15. 1. "HSRD_TOCNT,High-speed read timeout counter" line.long 0x8 "DSI_TCCR2,DSI Host timeout counter configuration register 2" hexmask.long.word 0x8 0.--15. 1. "LPRD_TOCNT,Low-power read timeout counter" line.long 0xC "DSI_TCCR3,DSI Host timeout counter configuration register 3" bitfld.long 0xC 24. "PM,Presp mode" "0,1" hexmask.long.word 0xC 0.--15. 1. "HSWR_TOCNT,High-speed write timeout counter" line.long 0x10 "DSI_TCCR4,DSI Host timeout counter configuration register 4" hexmask.long.word 0x10 0.--15. 1. "LPWR_TOCNT,Low-power write timeout counter" line.long 0x14 "DSI_TCCR5,DSI Host timeout counter configuration register 5" hexmask.long.word 0x14 0.--15. 1. "BTA_TOCNT,Bus-turn-around timeout counter" group.long 0x94++0x1B line.long 0x0 "DSI_CLCR,DSI Host clock lane configuration register" bitfld.long 0x0 1. "ACR,Automatic clock lane control" "0: Automatic clock lane control disabled,1: Automatic clock lane control enabled" bitfld.long 0x0 0. "DPCC,D-PHY clock control" "0: Clock lane is in low-power mode.,1: Clock lane runs in high-speed mode." line.long 0x4 "DSI_CLTCR,DSI Host clock lane timer configuration register" hexmask.long.word 0x4 16.--25. 1. "HS2LP_TIME,High-speed to low-power time" hexmask.long.word 0x4 0.--9. 1. "LP2HS_TIME,Low-power to high-speed time" line.long 0x8 "DSI_DLTCR,DSI Host data lane timer configuration register" hexmask.long.word 0x8 16.--25. 1. "HS2LP_TIME,High-speed to low-power time" hexmask.long.word 0x8 0.--9. 1. "LP2HS_TIME,Low-power to high-speed time" line.long 0xC "DSI_PCTLR,DSI Host PHY control register" bitfld.long 0xC 2. "CKE,Clock enable" "0: D-PHY clock lane module is disabled.,1: D-PHY clock lane module is enabled." bitfld.long 0xC 1. "DEN,Digital enable" "0: The digital section of the D-PHY is in the reset..,1: The digital section of the D-PHY is enabled." line.long 0x10 "DSI_PCONFR,DSI Host PHY configuration register" hexmask.long.byte 0x10 8.--15. 1. "SW_TIME,Stop wait time" bitfld.long 0x10 0.--1. "NL,Number of lanes" "0: One data lane (lane 0),1: Two data lanes (lanes 0 and 1) - Reset value,?,?" line.long 0x14 "DSI_PUCR,DSI Host PHY ULPS control register" bitfld.long 0x14 3. "UEDL,ULPS exit on data lane" "0: No exit request,1: Exit ULPS mode on all active data lane URDL" bitfld.long 0x14 2. "URDL,ULPS request on data lane" "0: No ULPS request,1: Request ULPS mode on all active data lane UECL" newline bitfld.long 0x14 1. "UECL,ULPS exit on clock lane" "0: No exit request,1: Exit ULPS mode on clock lane" bitfld.long 0x14 0. "URCL,ULPS request on clock lane" "0: No ULPS request,1: Request ULPS mode on clock lane" line.long 0x18 "DSI_PTTCR,DSI Host PHY TX triggers configuration register" hexmask.long.byte 0x18 0.--3. 1. "TX_TRIG,Transmission trigger" rgroup.long 0xB0++0x3 line.long 0x0 "DSI_PSR,DSI Host PHY status register" bitfld.long 0x0 8. "UAN1,ULPS active not lane 1" "0,1" bitfld.long 0x0 7. "PSS1,PHY stop state lane 1" "0,1" newline bitfld.long 0x0 6. "RUE0,RX ULPS escape lane 0" "0,1" bitfld.long 0x0 5. "UAN0,ULPS active not lane 1" "0,1" newline bitfld.long 0x0 4. "PSS0,PHY stop state lane 0" "0,1" bitfld.long 0x0 3. "UANC,ULPS active not clock lane" "0,1" newline bitfld.long 0x0 2. "PSSC,PHY stop state clock lane" "0,1" bitfld.long 0x0 1. "PD,PHY direction" "0,1" rgroup.long 0xBC++0x7 line.long 0x0 "DSI_ISR0,DSI Host interrupt and status register 0" bitfld.long 0x0 20. "PE4,PHY error 4" "0,1" bitfld.long 0x0 19. "PE3,PHY error 3" "0,1" newline bitfld.long 0x0 18. "PE2,PHY error 2" "0,1" bitfld.long 0x0 17. "PE1,PHY error 1" "0,1" newline bitfld.long 0x0 16. "PE0,PHY error 0" "0,1" bitfld.long 0x0 15. "AE15,Acknowledge error 15" "0,1" newline bitfld.long 0x0 14. "AE14,Acknowledge error 14" "0,1" bitfld.long 0x0 13. "AE13,Acknowledge error 13" "0,1" newline bitfld.long 0x0 12. "AE12,Acknowledge error 12" "0,1" bitfld.long 0x0 11. "AE11,Acknowledge error 11" "0,1" newline bitfld.long 0x0 10. "AE10,Acknowledge error 10" "0,1" bitfld.long 0x0 9. "AE9,Acknowledge error 9" "0,1" newline bitfld.long 0x0 8. "AE8,Acknowledge error 8" "0,1" bitfld.long 0x0 7. "AE7,Acknowledge error 7" "0,1" newline bitfld.long 0x0 6. "AE6,Acknowledge error 6" "0,1" bitfld.long 0x0 5. "AE5,Acknowledge error 5" "0,1" newline bitfld.long 0x0 4. "AE4,Acknowledge error 4" "0,1" bitfld.long 0x0 3. "AE3,Acknowledge error 3" "0,1" newline bitfld.long 0x0 2. "AE2,Acknowledge error 2" "0,1" bitfld.long 0x0 1. "AE1,Acknowledge error 1" "0,1" newline bitfld.long 0x0 0. "AE0,Acknowledge error 0" "0,1" line.long 0x4 "DSI_ISR1,DSI Host interrupt and status register 1" bitfld.long 0x4 19. "PBUE,Payload buffer underflow error" "0,1" bitfld.long 0x4 12. "GPRXE,Generic payload receive error" "0,1" newline bitfld.long 0x4 11. "GPRDE,Generic payload read error" "0,1" bitfld.long 0x4 10. "GPTXE,Generic payload transmit error" "0,1" newline bitfld.long 0x4 9. "GPWRE,Generic payload write error" "0,1" bitfld.long 0x4 8. "GCWRE,Generic command write error" "0,1" newline bitfld.long 0x4 7. "LPWRE,LTDC payload write error" "0,1" bitfld.long 0x4 6. "EOTPE,EoTp error" "0,1" newline bitfld.long 0x4 5. "PSE,Packet size error" "0,1" bitfld.long 0x4 4. "CRCE,CRC error" "0,1" newline bitfld.long 0x4 3. "ECCME,ECC multi-bit error" "0,1" bitfld.long 0x4 2. "ECCSE,ECC single-bit error" "0,1" newline bitfld.long 0x4 1. "TOLPRX,Timeout low-power reception" "0,1" bitfld.long 0x4 0. "TOHSTX,Timeout high-speed transmission" "0,1" group.long 0xC4++0x7 line.long 0x0 "DSI_IER0,DSI Host interrupt enable register 0" bitfld.long 0x0 20. "PE4IE,PHY error 4 interrupt enable" "0: Interrupt on PHY error 4 disabled,1: Interrupt on PHY error 4 enabled" bitfld.long 0x0 19. "PE3IE,PHY error 3 interrupt enable" "0: Interrupt on PHY error 3 disabled,1: Interrupt on PHY error 3 enabled" newline bitfld.long 0x0 18. "PE2IE,PHY error 2 interrupt enable" "0: Interrupt on PHY error 2 disabled,1: Interrupt on PHY error 2 enabled" bitfld.long 0x0 17. "PE1IE,PHY error 1 interrupt enable" "0: Interrupt on PHY error 1 disabled,1: Interrupt on PHY error 1 enabled" newline bitfld.long 0x0 16. "PE0IE,PHY error 0 interrupt enable" "0: Interrupt on PHY error 0 disabled,1: Interrupt on PHY error 0 enabled" bitfld.long 0x0 15. "AE15IE,Acknowledge error 15 interrupt enable" "0: Interrupt on acknowledge error 15 disabled,1: Interrupt on acknowledge error 15 enabled" newline bitfld.long 0x0 14. "AE14IE,Acknowledge error 14 interrupt enable" "0: Interrupt on acknowledge error 14 disabled,1: Interrupt on acknowledge error 14 enabled" bitfld.long 0x0 13. "AE13IE,Acknowledge error 13 interrupt enable" "0: Interrupt on acknowledge error 13 disabled,1: Interrupt on acknowledge error 13 enabled" newline bitfld.long 0x0 12. "AE12IE,Acknowledge error 12 interrupt enable" "0: Interrupt on acknowledge error 12 disabled,1: Interrupt on acknowledge error 12 enabled" bitfld.long 0x0 11. "AE11IE,Acknowledge error 11 interrupt enable" "0: Interrupt on acknowledge error 11 disabled,1: Interrupt on acknowledge error 11 enabled" newline bitfld.long 0x0 10. "AE10IE,Acknowledge error 10 interrupt enable" "0: Interrupt on acknowledge error 10 disabled,1: Interrupt on acknowledge error 10 enable." bitfld.long 0x0 9. "AE9IE,Acknowledge error 9 interrupt enable" "0: Interrupt on acknowledge error 9 disabled,1: Interrupt on acknowledge error 9 enabled" newline bitfld.long 0x0 8. "AE8IE,Acknowledge error 8 interrupt enable" "0: Interrupt on acknowledge error 8 disabled,1: Interrupt on acknowledge error 8 enabled" bitfld.long 0x0 7. "AE7IE,Acknowledge error 7 interrupt enable" "0: Interrupt on acknowledge error 7 disabled,1: Interrupt on acknowledge error 7 enabled" newline bitfld.long 0x0 6. "AE6IE,Acknowledge error 6 interrupt enable" "0: Interrupt on acknowledge error 6 disabled,1: Interrupt on acknowledge error 6 enabled" bitfld.long 0x0 5. "AE5IE,Acknowledge error 5 interrupt enable" "0: Interrupt on acknowledge error 5 disabled,1: Interrupt on acknowledge error 5 enabled" newline bitfld.long 0x0 4. "AE4IE,Acknowledge error 4 interrupt enable" "0: Interrupt on acknowledge error 4 disabled,1: Interrupt on acknowledge error 4 enabled" bitfld.long 0x0 3. "AE3IE,Acknowledge error 3 interrupt enable" "0: Interrupt on acknowledge error 3 disabled,1: Interrupt on acknowledge error 3 enabled" newline bitfld.long 0x0 2. "AE2IE,Acknowledge error 2 interrupt enable" "0: Interrupt on acknowledge error 2 disabled,1: Interrupt on acknowledge error 2 enabled" bitfld.long 0x0 1. "AE1IE,Acknowledge error 1 interrupt enable" "0: Interrupt on acknowledge error 1 disabled,1: Interrupt on acknowledge error 1 enabled" newline bitfld.long 0x0 0. "AE0IE,Acknowledge error 0 interrupt enable" "0: Interrupt on acknowledge error 0 disabled,1: Interrupt on acknowledge error 0 enabled" line.long 0x4 "DSI_IER1,DSI Host interrupt enable register 1" bitfld.long 0x4 19. "PBUEIE,Payload buffer underflow error interrupt enable" "0: Interrupt on payload buffer underflow error..,1: Interrupt on payload buffer underflow error.." bitfld.long 0x4 12. "GPRXEIE,Generic payload receive error interrupt enable" "0: Interrupt on generic payload receive error..,1: Interrupt on generic payload receive error enabled" newline bitfld.long 0x4 11. "GPRDEIE,Generic payload read error interrupt enable" "0: Interrupt on generic payload read error disabled,1: Interrupt on generic payload read error enabled" bitfld.long 0x4 10. "GPTXEIE,Generic payload transmit error interrupt enable" "0: Interrupt on generic payload transmit error..,1: Interrupt on generic payload transmit error.." newline bitfld.long 0x4 9. "GPWREIE,Generic payload write error interrupt enable" "0: Interrupt on generic payload write error disabled,1: Interrupt on generic payload write error enabled" bitfld.long 0x4 8. "GCWREIE,Generic command write error interrupt enable" "0: Interrupt on generic command write error disabled,1: Interrupt on generic command write error enabled" newline bitfld.long 0x4 7. "LPWREIE,LTDC payload write error interrupt enable" "0: Interrupt on LTDC payload write error disabled,1: Interrupt on LTDC payload write error enabled" bitfld.long 0x4 6. "EOTPEIE,EoTp error interrupt enable" "0: Interrupt on EoTp error disabled,1: Interrupt on EoTp error enabled" newline bitfld.long 0x4 5. "PSEIE,Packet size error interrupt enable" "0: Interrupt on packet size error disabled,1: Interrupt on packet size error enabled" bitfld.long 0x4 4. "CRCEIE,CRC error interrupt enable" "0: Interrupt on CRC error disabled,1: Interrupt on CRC error enabled" newline bitfld.long 0x4 3. "ECCMEIE,ECC multi-bit error interrupt enable" "0: Interrupt on ECC multi-bit error disabled,1: Interrupt on ECC multi-bit error enabled" bitfld.long 0x4 2. "ECCSEIE,ECC single-bit error interrupt enable" "0: Interrupt on ECC single-bit error disabled,1: Interrupt on ECC single-bit error enabled" newline bitfld.long 0x4 1. "TOLPRXIE,Timeout low-power reception interrupt enable" "0: Interrupt on timeout low-power reception disabled,1: Interrupt on timeout low-power reception enabled" bitfld.long 0x4 0. "TOHSTXIE,Timeout high-speed transmission interrupt enable" "0: Interrupt on timeout high-speed transmission..,1: Interrupt on timeout high-speed transmission.." wgroup.long 0xD8++0x7 line.long 0x0 "DSI_FIR0,DSI Host force interrupt register 0" bitfld.long 0x0 20. "FPE4,Force PHY error 4" "0,1" bitfld.long 0x0 19. "FPE3,Force PHY error 3" "0,1" newline bitfld.long 0x0 18. "FPE2,Force PHY error 2" "0,1" bitfld.long 0x0 17. "FPE1,Force PHY error 1" "0,1" newline bitfld.long 0x0 16. "FPE0,Force PHY error 0" "0,1" bitfld.long 0x0 15. "FAE15,Force acknowledge error 15" "0,1" newline bitfld.long 0x0 14. "FAE14,Force acknowledge error 14" "0,1" bitfld.long 0x0 13. "FAE13,Force acknowledge error 13" "0,1" newline bitfld.long 0x0 12. "FAE12,Force acknowledge error 12" "0,1" bitfld.long 0x0 11. "FAE11,Force acknowledge error 11" "0,1" newline bitfld.long 0x0 10. "FAE10,Force acknowledge error 10" "0,1" bitfld.long 0x0 9. "FAE9,Force acknowledge error 9" "0,1" newline bitfld.long 0x0 8. "FAE8,Force acknowledge error 8" "0,1" bitfld.long 0x0 7. "FAE7,Force acknowledge error 7" "0,1" newline bitfld.long 0x0 6. "FAE6,Force acknowledge error 6" "0,1" bitfld.long 0x0 5. "FAE5,Force acknowledge error 5" "0,1" newline bitfld.long 0x0 4. "FAE4,Force acknowledge error 4" "0,1" bitfld.long 0x0 3. "FAE3,Force acknowledge error 3" "0,1" newline bitfld.long 0x0 2. "FAE2,Force acknowledge error 2" "0,1" bitfld.long 0x0 1. "FAE1,Force acknowledge error 1" "0,1" newline bitfld.long 0x0 0. "FAE0,Force acknowledge error 0" "0,1" line.long 0x4 "DSI_FIR1,DSI Host force interrupt register 1" bitfld.long 0x4 19. "FPBUE,Force payload buffer underflow error" "0,1" bitfld.long 0x4 12. "FGPRXE,Force generic payload receive error" "0,1" newline bitfld.long 0x4 11. "FGPRDE,Force generic payload read error" "0,1" bitfld.long 0x4 10. "FGPTXE,Force generic payload transmit error" "0,1" newline bitfld.long 0x4 9. "FGPWRE,Force generic payload write error" "0,1" bitfld.long 0x4 8. "FGCWRE,Force generic command write error" "0,1" newline bitfld.long 0x4 7. "FLPWRE,Force LTDC payload write error" "0,1" bitfld.long 0x4 6. "FEOTPE,Force EoTp error" "0,1" newline bitfld.long 0x4 5. "FPSE,Force packet size error" "0,1" bitfld.long 0x4 4. "FCRCE,Force CRC error" "0,1" newline bitfld.long 0x4 3. "FECCME,Force ECC multi-bit error" "0,1" bitfld.long 0x4 2. "FECCSE,Force ECC single-bit error" "0,1" newline bitfld.long 0x4 1. "FTOLPRX,Force timeout low-power reception" "0,1" bitfld.long 0x4 0. "FTOHSTX,Force timeout high-speed transmission" "0,1" group.long 0xF4++0x3 line.long 0x0 "DSI_DLTRCR,DSI Host data lane timer read configuration register" hexmask.long.word 0x0 0.--14. 1. "MRD_TIME,Maximum read time" group.long 0x100++0x3 line.long 0x0 "DSI_VSCR,DSI Host video shadow control register" bitfld.long 0x0 8. "UR,Update register" "0: No update requested,1: Register update requested" bitfld.long 0x0 0. "EN,Enable" "0: Register update is disabled.,1: Register update is enabled." group.long 0x10C++0x3 line.long 0x0 "DSI_LCVCIDR,DSI Host LTDC current VCID register" bitfld.long 0x0 0.--1. "VCID,Virtual channel ID" "0,1,2,3" rgroup.long 0x110++0x3 line.long 0x0 "DSI_LCCCR,DSI Host LTDC current color coding register" bitfld.long 0x0 8. "LPE,Loosely packed enable" "0: Loosely packed variant disabled,1: Loosely packed variant enabled" hexmask.long.byte 0x0 0.--3. 1. "COLC,Color coding" rgroup.long 0x118++0x3 line.long 0x0 "DSI_LPMCCR,DSI Host low-power mode current configuration register" hexmask.long.byte 0x0 16.--23. 1. "LPSIZE,Largest packet size" hexmask.long.byte 0x0 0.--7. 1. "VLPSIZE,VACT largest packet size" rgroup.long 0x138++0x2B line.long 0x0 "DSI_VMCCR,DSI Host video mode current configuration register" bitfld.long 0x0 9. "LPCE,Low-power command enable" "0: Command transmission in low-power mode is..,1: Command transmission in low-power mode is enabled." bitfld.long 0x0 8. "FBTAAE,Frame BTA acknowledge enable" "0: Acknowledge response at the end of a frame is..,1: Acknowledge response at the end of a frame is.." newline bitfld.long 0x0 7. "LPHFE,Low-power horizontal front-porch enable" "0: Return to low-power inside the HFP period is..,1: Return to low-power inside the HFP period is.." bitfld.long 0x0 6. "LPHBPE,Low-power horizontal back-porch enable" "0: Return to low-power inside the HBP period is..,1: Return to low-power inside the HBP period is.." newline bitfld.long 0x0 5. "LPVAE,Low-power vertical active enable" "0: Return to low-power inside the VACT is disabled.,1: Return to low-power inside the VACT is enabled." bitfld.long 0x0 4. "LPVFPE,Low-power vertical front-porch enable" "0: Return to low-power inside the VFP is disabled.,1: Return to low-power inside the VFP is enabled." newline bitfld.long 0x0 3. "LPVBPE,Low-power vertical back-porch enable" "0: Return to low-power inside the VBP is disabled.,1: Return to low-power inside the VBP is enabled." bitfld.long 0x0 2. "LPVSAE,Low-power vertical sync time enable" "0: Return to low-power inside the VSA is disabled.,1: Return to low-power inside the VSA is enabled" newline bitfld.long 0x0 0.--1. "VMT,Video mode type" "0: Non-burst with sync pulses,1: Non-burst with sync events,?,?" line.long 0x4 "DSI_VPCCR,DSI Host video packet current configuration register" hexmask.long.word 0x4 0.--13. 1. "VPSIZE,Video packet size" line.long 0x8 "DSI_VCCCR,DSI Host video chunks current configuration register" hexmask.long.word 0x8 0.--12. 1. "NUMC,Number of chunks" line.long 0xC "DSI_VNPCCR,DSI Host video null packet current configuration register" hexmask.long.word 0xC 0.--12. 1. "NPSIZE,Null packet size" line.long 0x10 "DSI_VHSACCR,DSI Host video HSA current configuration register" hexmask.long.word 0x10 0.--11. 1. "HSA,Horizontal synchronism active duration" line.long 0x14 "DSI_VHBPCCR,DSI Host video HBP current configuration register" hexmask.long.word 0x14 0.--11. 1. "HBP,Horizontal back-porch duration" line.long 0x18 "DSI_VLCCR,DSI Host video line current configuration register" hexmask.long.word 0x18 0.--14. 1. "HLINE,Horizontal line duration" line.long 0x1C "DSI_VVSACCR,DSI Host video VSA current configuration register" hexmask.long.word 0x1C 0.--9. 1. "VSA,Vertical synchronism active duration" line.long 0x20 "DSI_VVBPCCR,DSI Host video VBP current configuration register" hexmask.long.word 0x20 0.--9. 1. "VBP,Vertical back-porch duration" line.long 0x24 "DSI_VVFPCCR,DSI Host video VFP current configuration register" hexmask.long.word 0x24 0.--9. 1. "VFP,Vertical front-porch duration" line.long 0x28 "DSI_VVACCR,DSI Host video VA current configuration register" hexmask.long.word 0x28 0.--13. 1. "VA,Vertical active duration" rgroup.long 0x168++0x3 line.long 0x0 "DSI_FBSR,DSI Host FIFO and buffer status register" bitfld.long 0x0 23. "APBF,Adapted command mode payload buffer full" "0: Payload internal buffer not full,1: Payload internal buffer full" bitfld.long 0x0 22. "APBE,Adapted command mode payload buffer empty" "0: Payload internal buffer not empty,1: Payload internal buffer empty" newline bitfld.long 0x0 21. "ACBF,Adapted command mode command buffer full" "0: Command internal buffer not full,1: Command internal buffer full" bitfld.long 0x0 20. "ACBE,Adapted command mode command buffer empty" "0: Command internal buffer not empty,1: Command internal buffer empty" newline bitfld.long 0x0 17. "VPBF,Video mode payload buffer full" "0: Payload internal buffer not full,1: Payload internal buffer full" bitfld.long 0x0 16. "VPBE,Video mode payload buffer empty" "0: Payload internal buffer not empty,1: Payload internal buffer empty" newline bitfld.long 0x0 7. "APWFF,Adapted command mode payload write FIFO full" "0: Write payload FIFO not full,1: Write payload FIFO full" bitfld.long 0x0 6. "APWFE,Adapted command mode payload write FIFO empty" "0: Write payload FIFO not empty,1: Write payload FIFO empty" newline bitfld.long 0x0 5. "ACWFF,Adapted command mode command write FIFO full" "0: Write command FIFO not full,1: Write command FIFO full" bitfld.long 0x0 4. "ACWFE,Adapted command mode command write FIFO empty" "0: Write command FIFO not empty,1: Write command FIFO empty" newline bitfld.long 0x0 3. "VPWFF,Video mode payload write FIFO full" "0: Write payload FIFO not full,1: Write payload FIFO full" bitfld.long 0x0 2. "VPWFE,Video mode payload write FIFO empty" "0: Write payload FIFO not empty,1: Write payload FIFO empty" newline bitfld.long 0x0 1. "VCWFF,Video mode command write FIFO full" "0: Write command FIFO not full,1: Write command FIFO full" bitfld.long 0x0 0. "VCWFE,Video mode command write FIFO empty" "0: Write command FIFO not empty,1: Write command FIFO empty" group.long 0x400++0xB line.long 0x0 "DSI_WCFGR,DSI Wrapper configuration register" bitfld.long 0x0 7. "VSPOL,VSync polarity" "0: LTDC halted on a falling edge,1: LTDC halted on a rising edge" bitfld.long 0x0 6. "AR,Automatic refresh" "0: automatic refresh mode disabled,1: automatic refresh mode enabled" newline bitfld.long 0x0 5. "TEPOL,TE polarity" "0: rising edge.,1: falling edge." bitfld.long 0x0 4. "TESRC,TE source" "0: DSI Link,1: External pin" newline bitfld.long 0x0 1.--3. "COLMUX,Color multiplexing" "0: 16-bit configuration 1,1: 16-bit configuration 2,2: 16-bit configuration 3,3: 18-bit configuration 1,4: 18-bit configuration 2,5: 24-bit,?,?" bitfld.long 0x0 0. "DSIM,DSI mode" "0: Video mode,1: Adapted command mode" line.long 0x4 "DSI_WCR,DSI Wrapper control register" bitfld.long 0x4 3. "DSIEN,DSI enable" "0: DSI disabled,1: DSI enabled" bitfld.long 0x4 2. "LTDCEN,LTDC enable" "0: LTDC disabled,1: LTDC enabled" newline bitfld.long 0x4 1. "SHTDN,Shutdown" "0: display ON,1: display OFF" bitfld.long 0x4 0. "COLM,Color mode" "0: Full color mode,1: Eight color mode" line.long 0x8 "DSI_WIER,DSI Wrapper interrupt enable register" bitfld.long 0x8 10. "PLLUIE,PLL unlock interrupt enable" "0: PLL unlock interrupt disabled,1: PLL unlock interrupt enabled" bitfld.long 0x8 9. "PLLLIE,PLL lock interrupt enable" "0: PLL lock interrupt disabled,1: PLL lock interrupt enabled" newline bitfld.long 0x8 1. "ERIE,End of refresh interrupt enable" "0: End of refresh interrupt disabled,1: End of refresh interrupt enabled" bitfld.long 0x8 0. "TEIE,Tearing effect interrupt enable" "0: Tearing effect interrupt disabled,1: Tearing effect interrupt enabled" rgroup.long 0x40C++0x3 line.long 0x0 "DSI_WISR,DSI Wrapper interrupt and status register" bitfld.long 0x0 10. "PLLUIF,PLL unlock interrupt flag" "0: No PLL unlock event occurred,1: PLL unlock event occurred" bitfld.long 0x0 9. "PLLLIF,PLL lock interrupt flag" "0: No PLL lock event occurred,1: PLL lock event occurred" newline bitfld.long 0x0 8. "PLLLS,PLL lock status" "0: PLL is unlocked.,1: PLL is locked." bitfld.long 0x0 2. "BUSY,Busy flag" "0: No transfer on going,1: Transfer on going" newline bitfld.long 0x0 1. "ERIF,End of refresh interrupt flag" "0: No end of refresh event occurred,1: End of refresh event occurred" bitfld.long 0x0 0. "TEIF,Tearing effect interrupt flag" "0: No tearing effect event occurred,1: Tearing effect event occurred" wgroup.long 0x410++0x3 line.long 0x0 "DSI_WIFCR,DSI Wrapper interrupt flag clear register" bitfld.long 0x0 10. "CPLLUIF,Clear PLL unlock interrupt flag" "0,1" bitfld.long 0x0 9. "CPLLLIF,Clear PLL lock interrupt flag" "0,1" newline bitfld.long 0x0 1. "CERIF,Clear end of refresh interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear tearing effect interrupt flag" "0,1" group.long 0x418++0x3 line.long 0x0 "DSI_WPCR0,DSI Wrapper PHY configuration register 0" bitfld.long 0x0 13. "FTXSMDL,Force in TX Stop mode the data lanes" "0: No effect,1: Force the data lanes in TX Stop mode" bitfld.long 0x0 12. "FTXSMCL,Force in TX Stop mode the clock lane" "0: No effect,1: Force the clock lane in TX Stop mode" newline bitfld.long 0x0 8. "SWDL1,Swap data lane 1 pins" "0: Regular clock lane pin configuration,1: Swapped clock lane pin" bitfld.long 0x0 7. "SWDL0,Swap data lane 0 pins" "0: Regular clock lane pin configuration,1: Swapped clock lane pin" newline bitfld.long 0x0 6. "SWCL,Swap clock lane pins" "0: Regular clock lane pin configuration,1: Swapped clock lane pin" group.long 0x430++0x3 line.long 0x0 "DSI_WRPCR,DSI Wrapper regulator and PLL control register" hexmask.long.word 0x0 20.--28. 1. "ODF,PLL output division factor" hexmask.long.word 0x0 11.--19. 1. "IDF,PLL input division factor" newline hexmask.long.word 0x0 2.--10. 1. "NDIV,PLL loop division factor" bitfld.long 0x0 0. "PLLEN,PLL enable" "0: PLL disabled,1: PLL enabled" group.long 0x808++0x3 line.long 0x0 "DSI_BCFGR,DSI bias configuration register" bitfld.long 0x0 6. "PWRUP,Power-up" "0: Reference bias is powered down.,1: Reference bias is powered up." group.long 0xC04++0x3 line.long 0x0 "DSI_DPCBCR,DSI D-PHY clock band control register" hexmask.long.byte 0x0 3.--7. 1. "BC,Band control" group.long 0xC34++0x3 line.long 0x0 "DSI_DPCSRCR,DSI D-PHY clock skew rate control register" hexmask.long.byte 0x0 0.--7. 1. "SRC,Slew rate control" group.long 0xC70++0x3 line.long 0x0 "DSI_DPDL0BCR,DSI D-PHY data lane 0 band control register" hexmask.long.byte 0x0 0.--4. 1. "BC,Band control" group.long 0xCA0++0x3 line.long 0x0 "DSI_DPDL0SRCR,DSI D-PHY data lane 0 skew rate control register" hexmask.long.byte 0x0 0.--7. 1. "SRC,Slew rate control" group.long 0xD08++0x3 line.long 0x0 "DSI_DPDL1BCR,DSI D-PHY data lane 1 band control register" hexmask.long.byte 0x0 0.--4. 1. "BC,Band control" group.long 0xD38++0x3 line.long 0x0 "DSI_DPDL1SRCR,DSI D-PHY data lane 1 skew rate control register" hexmask.long.byte 0x0 0.--7. 1. "SRC,Slew rate control" tree.end tree "SEC_DSI" base ad:0x50016C00 rgroup.long 0x0++0x3 line.long 0x0 "DSI_VR,DSI Host version register" hexmask.long 0x0 0.--31. 1. "VERSION,Version of the DSI Host" group.long 0x4++0x17 line.long 0x0 "DSI_CR,DSI Host control register" bitfld.long 0x0 0. "EN,Enable" "0: DSI Host disabled (under reset),1: DSI Host enabled" line.long 0x4 "DSI_CCR,DSI Host clock control register" hexmask.long.byte 0x4 8.--15. 1. "TOCKDIV,Timeout clock division" hexmask.long.byte 0x4 0.--7. 1. "TXECKDIV,TX escape clock division" line.long 0x8 "DSI_LVCIDR,DSI Host LTDC VCID register" bitfld.long 0x8 0.--1. "VCID,Virtual channel ID" "0,1,2,3" line.long 0xC "DSI_LCOLCR,DSI Host LTDC color coding register" bitfld.long 0xC 8. "LPE,Loosely packet enable" "0: Loosely packet variant disabled,1: Loosely packet variant enabled" hexmask.long.byte 0xC 0.--3. 1. "COLC,Color coding" line.long 0x10 "DSI_LPCR,DSI Host LTDC polarity configuration register" bitfld.long 0x10 2. "HSP,HSYNC polarity" "0: HSYNC pin active high (default),1: VSYNC pin active low" bitfld.long 0x10 1. "VSP,VSYNC polarity" "0: Shutdown pin active high (default),1: Shutdown pin active low" newline bitfld.long 0x10 0. "DEP,Data enable polarity" "0: Data enable pin active high (default),1: Data enable pin active low" line.long 0x14 "DSI_LPMCR,DSI Host low-power mode configuration register" hexmask.long.byte 0x14 16.--23. 1. "LPSIZE,Largest packet size" hexmask.long.byte 0x14 0.--7. 1. "VLPSIZE,VACT largest packet size" group.long 0x2C++0x47 line.long 0x0 "DSI_PCR,DSI Host protocol configuration register" bitfld.long 0x0 5. "ETTXLPE,EoTp transmission in low-power enable" "0: EoTp transmission in low-power is disabled.,1: EoTp transmission in low-power is enabled." bitfld.long 0x0 4. "CRCRXE,CRC reception enable" "0: CRC reception is disabled.,1: CRC reception is enabled." newline bitfld.long 0x0 3. "ECCRXE,ECC reception enable" "0: ECC reception is disabled.,1: ECC reception is enabled." bitfld.long 0x0 2. "BTAE,Bus-turn-around enable" "0: Bus-turn-around request is disabled.,1: Bus-turn-around request is enabled." newline bitfld.long 0x0 1. "ETRXE,EoTp reception enable" "0: EoTp reception is disabled.,1: EoTp reception is enabled." bitfld.long 0x0 0. "ETTXE,EoTp transmission enable" "0: EoTp transmission is disabled.,1: EoTp transmission is enabled." line.long 0x4 "DSI_GVCIDR,DSI Host generic VCID register" bitfld.long 0x4 16.--17. "VCIDTX,Virtual channel ID for transmission" "0,1,2,3" bitfld.long 0x4 0.--1. "VCIDRX,Virtual channel ID for reception" "0,1,2,3" line.long 0x8 "DSI_MCR,DSI Host mode configuration register" bitfld.long 0x8 0. "CMDM,Command mode" "0: DSI Host is configured in video mode.,1: DSI Host is configured in command mode." line.long 0xC "DSI_VMCR,DSI Host video mode configuration register" bitfld.long 0xC 24. "PGO,Pattern generator orientation" "0: Vertical color bars.,1: Horizontal color bars." bitfld.long 0xC 20. "PGM,Pattern generator mode" "0: Color bars (horizontal or vertical).,1: BER pattern (vertical only)." newline bitfld.long 0xC 16. "PGE,Pattern generator enable" "0: Pattern generator is disabled.,1: Pattern generator is enabled." bitfld.long 0xC 15. "LPCE,Low-power command enable" "0: Command transmission in low-power mode is..,1: Command transmission in low-power mode is enabled." newline bitfld.long 0xC 14. "FBTAAE,Frame bus-turn-around acknowledge enable" "0: Acknowledge response at the end of a frame is..,1: Acknowledge response at the end of a frame is.." bitfld.long 0xC 13. "LPHFPE,Low-power horizontal front-porch enable" "0: Return to low-power inside the HFP period is..,1: Return to low-power inside the HFP period is.." newline bitfld.long 0xC 12. "LPHBPE,Low-power horizontal back-porch enable" "0: Return to low-power inside the HBP period is..,1: Return to low-power inside the HBP period is.." bitfld.long 0xC 11. "LPVAE,Low-power vertical active enable" "0: Return to low-power inside the VACT is disabled.,1: Return to low-power inside the VACT is enabled." newline bitfld.long 0xC 10. "LPVFPE,Low-power vertical front-porch enable" "0: Return to low-power inside the VFP is disabled.,1: Return to low-power inside the VFP is enabled." bitfld.long 0xC 9. "LPVBPE,Low-power vertical back-porch enable" "0: Return to low-power inside the VBP is disabled.,1: Return to low-power inside the VBP is enabled." newline bitfld.long 0xC 8. "LPVSAE,Low-power vertical sync active enable" "0: Return to low-power inside the VSA is disabled.,1: Return to low-power inside the VSA is enabled" bitfld.long 0xC 0.--1. "VMT,Video mode type" "0: Non-burst with sync pulses.,1: Non-burst with sync events.,?,?" line.long 0x10 "DSI_VPCR,DSI Host video packet configuration register" hexmask.long.word 0x10 0.--13. 1. "VPSIZE,Video packet size" line.long 0x14 "DSI_VCCR,DSI Host video chunks configuration register" hexmask.long.word 0x14 0.--12. 1. "NUMC,Number of chunks" line.long 0x18 "DSI_VNPCR,DSI Host video null packet configuration register" hexmask.long.word 0x18 0.--12. 1. "NPSIZE,Null packet size" line.long 0x1C "DSI_VHSACR,DSI Host video HSA configuration register" hexmask.long.word 0x1C 0.--11. 1. "HSA,Horizontal synchronism active duration" line.long 0x20 "DSI_VHBPCR,DSI Host video HBP configuration register" hexmask.long.word 0x20 0.--11. 1. "HBP,Horizontal back-porch duration" line.long 0x24 "DSI_VLCR,DSI Host video line configuration register" hexmask.long.word 0x24 0.--14. 1. "HLINE,Horizontal line duration" line.long 0x28 "DSI_VVSACR,DSI Host video VSA configuration register" hexmask.long.word 0x28 0.--9. 1. "VSA,Vertical synchronism active duration" line.long 0x2C "DSI_VVBPCR,DSI Host video VBP configuration register" hexmask.long.word 0x2C 0.--9. 1. "VBP,Vertical back-porch duration" line.long 0x30 "DSI_VVFPCR,DSI Host video VFP configuration register" hexmask.long.word 0x30 0.--9. 1. "VFP,Vertical front-porch duration" line.long 0x34 "DSI_VVACR,DSI Host video VA configuration register" hexmask.long.word 0x34 0.--13. 1. "VA,Vertical active duration" line.long 0x38 "DSI_LCCR,DSI Host LTDC command configuration register" hexmask.long.word 0x38 0.--15. 1. "CMDSIZE,Command size" line.long 0x3C "DSI_CMCR,DSI Host command mode configuration register" bitfld.long 0x3C 24. "MRDPS,Maximum read packet size" "0: High-speed,1: Low-power" bitfld.long 0x3C 19. "DLWTX,DCS long write transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 18. "DSR0TX,DCS short read zero parameter transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 17. "DSW1TX,DCS short read one parameter transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 16. "DSW0TX,DCS short write zero parameter transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 14. "GLWTX,Generic long write transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 13. "GSR2TX,Generic short read two parameters transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 12. "GSR1TX,Generic short read one parameters transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 11. "GSR0TX,Generic short read zero parameters transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 10. "GSW2TX,Generic short write two parameters transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 9. "GSW1TX,Generic short write one parameters transmission" "0: High-speed,1: Low-power" bitfld.long 0x3C 8. "GSW0TX,Generic short write zero parameters transmission" "0: High-speed,1: Low-power" newline bitfld.long 0x3C 1. "ARE,Acknowledge request enable" "0: Acknowledge request is disabled.,1: Acknowledge request is enabled." bitfld.long 0x3C 0. "TEARE,Tearing effect acknowledge request enable" "0: Tearing effect acknowledge request is disabled.,1: Tearing effect acknowledge request is enabled." line.long 0x40 "DSI_GHCR,DSI Host generic header configuration register" hexmask.long.byte 0x40 16.--23. 1. "WCMSB,WordCount MSB" hexmask.long.byte 0x40 8.--15. 1. "WCLSB,WordCount LSB" newline bitfld.long 0x40 6.--7. "VCID,Channel" "0,1,2,3" hexmask.long.byte 0x40 0.--5. 1. "DT,Type" line.long 0x44 "DSI_GPDR,DSI Host generic payload data register" hexmask.long.byte 0x44 24.--31. 1. "DATA4,Payload byte 4" hexmask.long.byte 0x44 16.--23. 1. "DATA3,Payload byte 3" newline hexmask.long.byte 0x44 8.--15. 1. "DATA2,Payload byte 2" hexmask.long.byte 0x44 0.--7. 1. "DATA1,Payload byte 1" rgroup.long 0x74++0x3 line.long 0x0 "DSI_GPSR,DSI Host generic packet status register" bitfld.long 0x0 19. "PBF,Payload buffer full" "0: Payload internal buffer not full,1: Payload internal buffer full" bitfld.long 0x0 18. "PBE,Payload buffer empty" "0: Payload internal buffer not empty,1: Payload internal buffer empty" newline bitfld.long 0x0 17. "CMDBF,Command buffer full" "0: Command internal buffer not full,1: Command internal buffer full" bitfld.long 0x0 16. "CMDBE,Command buffer empty" "0: Payload internal buffer not full,1: Payload internal buffer full" newline bitfld.long 0x0 6. "RCB,Read command busy" "0: No read command on going,1: Read command on going" bitfld.long 0x0 5. "PRDFF,Payload read FIFO full" "0: Read payload FIFO not full,1: Read payload FIFO ful." newline bitfld.long 0x0 4. "PRDFE,Payload read FIFO empty" "0: Read payload FIFO not empty,1: Read payload FIFO empty" bitfld.long 0x0 3. "PWRFF,Payload write FIFO full" "0: Write payload FIFO not full,1: Write payload FIFO full" newline bitfld.long 0x0 2. "PWRFE,Payload write FIFO empty" "0: Write payload FIFO not empty,1: Write payload FIFO empty" bitfld.long 0x0 1. "CMDFF,Command FIFO full" "0: Write payload FIFO not full,1: Write payload FIFO full" newline bitfld.long 0x0 0. "CMDFE,Command FIFO empty" "0: Write payload FIFO not empty,1: Write payload FIFO empty" group.long 0x78++0x17 line.long 0x0 "DSI_TCCR0,DSI Host timeout counter configuration register 0" hexmask.long.word 0x0 16.--31. 1. "HSTX_TOCNT,High-speed transmission timeout counter" hexmask.long.word 0x0 0.--15. 1. "LPRX_TOCNT,Low-power reception timeout counter" line.long 0x4 "DSI_TCCR1,DSI Host timeout counter configuration register 1" hexmask.long.word 0x4 0.--15. 1. "HSRD_TOCNT,High-speed read timeout counter" line.long 0x8 "DSI_TCCR2,DSI Host timeout counter configuration register 2" hexmask.long.word 0x8 0.--15. 1. "LPRD_TOCNT,Low-power read timeout counter" line.long 0xC "DSI_TCCR3,DSI Host timeout counter configuration register 3" bitfld.long 0xC 24. "PM,Presp mode" "0,1" hexmask.long.word 0xC 0.--15. 1. "HSWR_TOCNT,High-speed write timeout counter" line.long 0x10 "DSI_TCCR4,DSI Host timeout counter configuration register 4" hexmask.long.word 0x10 0.--15. 1. "LPWR_TOCNT,Low-power write timeout counter" line.long 0x14 "DSI_TCCR5,DSI Host timeout counter configuration register 5" hexmask.long.word 0x14 0.--15. 1. "BTA_TOCNT,Bus-turn-around timeout counter" group.long 0x94++0x1B line.long 0x0 "DSI_CLCR,DSI Host clock lane configuration register" bitfld.long 0x0 1. "ACR,Automatic clock lane control" "0: Automatic clock lane control disabled,1: Automatic clock lane control enabled" bitfld.long 0x0 0. "DPCC,D-PHY clock control" "0: Clock lane is in low-power mode.,1: Clock lane runs in high-speed mode." line.long 0x4 "DSI_CLTCR,DSI Host clock lane timer configuration register" hexmask.long.word 0x4 16.--25. 1. "HS2LP_TIME,High-speed to low-power time" hexmask.long.word 0x4 0.--9. 1. "LP2HS_TIME,Low-power to high-speed time" line.long 0x8 "DSI_DLTCR,DSI Host data lane timer configuration register" hexmask.long.word 0x8 16.--25. 1. "HS2LP_TIME,High-speed to low-power time" hexmask.long.word 0x8 0.--9. 1. "LP2HS_TIME,Low-power to high-speed time" line.long 0xC "DSI_PCTLR,DSI Host PHY control register" bitfld.long 0xC 2. "CKE,Clock enable" "0: D-PHY clock lane module is disabled.,1: D-PHY clock lane module is enabled." bitfld.long 0xC 1. "DEN,Digital enable" "0: The digital section of the D-PHY is in the reset..,1: The digital section of the D-PHY is enabled." line.long 0x10 "DSI_PCONFR,DSI Host PHY configuration register" hexmask.long.byte 0x10 8.--15. 1. "SW_TIME,Stop wait time" bitfld.long 0x10 0.--1. "NL,Number of lanes" "0: One data lane (lane 0),1: Two data lanes (lanes 0 and 1) - Reset value,?,?" line.long 0x14 "DSI_PUCR,DSI Host PHY ULPS control register" bitfld.long 0x14 3. "UEDL,ULPS exit on data lane" "0: No exit request,1: Exit ULPS mode on all active data lane URDL" bitfld.long 0x14 2. "URDL,ULPS request on data lane" "0: No ULPS request,1: Request ULPS mode on all active data lane UECL" newline bitfld.long 0x14 1. "UECL,ULPS exit on clock lane" "0: No exit request,1: Exit ULPS mode on clock lane" bitfld.long 0x14 0. "URCL,ULPS request on clock lane" "0: No ULPS request,1: Request ULPS mode on clock lane" line.long 0x18 "DSI_PTTCR,DSI Host PHY TX triggers configuration register" hexmask.long.byte 0x18 0.--3. 1. "TX_TRIG,Transmission trigger" rgroup.long 0xB0++0x3 line.long 0x0 "DSI_PSR,DSI Host PHY status register" bitfld.long 0x0 8. "UAN1,ULPS active not lane 1" "0,1" bitfld.long 0x0 7. "PSS1,PHY stop state lane 1" "0,1" newline bitfld.long 0x0 6. "RUE0,RX ULPS escape lane 0" "0,1" bitfld.long 0x0 5. "UAN0,ULPS active not lane 1" "0,1" newline bitfld.long 0x0 4. "PSS0,PHY stop state lane 0" "0,1" bitfld.long 0x0 3. "UANC,ULPS active not clock lane" "0,1" newline bitfld.long 0x0 2. "PSSC,PHY stop state clock lane" "0,1" bitfld.long 0x0 1. "PD,PHY direction" "0,1" rgroup.long 0xBC++0x7 line.long 0x0 "DSI_ISR0,DSI Host interrupt and status register 0" bitfld.long 0x0 20. "PE4,PHY error 4" "0,1" bitfld.long 0x0 19. "PE3,PHY error 3" "0,1" newline bitfld.long 0x0 18. "PE2,PHY error 2" "0,1" bitfld.long 0x0 17. "PE1,PHY error 1" "0,1" newline bitfld.long 0x0 16. "PE0,PHY error 0" "0,1" bitfld.long 0x0 15. "AE15,Acknowledge error 15" "0,1" newline bitfld.long 0x0 14. "AE14,Acknowledge error 14" "0,1" bitfld.long 0x0 13. "AE13,Acknowledge error 13" "0,1" newline bitfld.long 0x0 12. "AE12,Acknowledge error 12" "0,1" bitfld.long 0x0 11. "AE11,Acknowledge error 11" "0,1" newline bitfld.long 0x0 10. "AE10,Acknowledge error 10" "0,1" bitfld.long 0x0 9. "AE9,Acknowledge error 9" "0,1" newline bitfld.long 0x0 8. "AE8,Acknowledge error 8" "0,1" bitfld.long 0x0 7. "AE7,Acknowledge error 7" "0,1" newline bitfld.long 0x0 6. "AE6,Acknowledge error 6" "0,1" bitfld.long 0x0 5. "AE5,Acknowledge error 5" "0,1" newline bitfld.long 0x0 4. "AE4,Acknowledge error 4" "0,1" bitfld.long 0x0 3. "AE3,Acknowledge error 3" "0,1" newline bitfld.long 0x0 2. "AE2,Acknowledge error 2" "0,1" bitfld.long 0x0 1. "AE1,Acknowledge error 1" "0,1" newline bitfld.long 0x0 0. "AE0,Acknowledge error 0" "0,1" line.long 0x4 "DSI_ISR1,DSI Host interrupt and status register 1" bitfld.long 0x4 19. "PBUE,Payload buffer underflow error" "0,1" bitfld.long 0x4 12. "GPRXE,Generic payload receive error" "0,1" newline bitfld.long 0x4 11. "GPRDE,Generic payload read error" "0,1" bitfld.long 0x4 10. "GPTXE,Generic payload transmit error" "0,1" newline bitfld.long 0x4 9. "GPWRE,Generic payload write error" "0,1" bitfld.long 0x4 8. "GCWRE,Generic command write error" "0,1" newline bitfld.long 0x4 7. "LPWRE,LTDC payload write error" "0,1" bitfld.long 0x4 6. "EOTPE,EoTp error" "0,1" newline bitfld.long 0x4 5. "PSE,Packet size error" "0,1" bitfld.long 0x4 4. "CRCE,CRC error" "0,1" newline bitfld.long 0x4 3. "ECCME,ECC multi-bit error" "0,1" bitfld.long 0x4 2. "ECCSE,ECC single-bit error" "0,1" newline bitfld.long 0x4 1. "TOLPRX,Timeout low-power reception" "0,1" bitfld.long 0x4 0. "TOHSTX,Timeout high-speed transmission" "0,1" group.long 0xC4++0x7 line.long 0x0 "DSI_IER0,DSI Host interrupt enable register 0" bitfld.long 0x0 20. "PE4IE,PHY error 4 interrupt enable" "0: Interrupt on PHY error 4 disabled,1: Interrupt on PHY error 4 enabled" bitfld.long 0x0 19. "PE3IE,PHY error 3 interrupt enable" "0: Interrupt on PHY error 3 disabled,1: Interrupt on PHY error 3 enabled" newline bitfld.long 0x0 18. "PE2IE,PHY error 2 interrupt enable" "0: Interrupt on PHY error 2 disabled,1: Interrupt on PHY error 2 enabled" bitfld.long 0x0 17. "PE1IE,PHY error 1 interrupt enable" "0: Interrupt on PHY error 1 disabled,1: Interrupt on PHY error 1 enabled" newline bitfld.long 0x0 16. "PE0IE,PHY error 0 interrupt enable" "0: Interrupt on PHY error 0 disabled,1: Interrupt on PHY error 0 enabled" bitfld.long 0x0 15. "AE15IE,Acknowledge error 15 interrupt enable" "0: Interrupt on acknowledge error 15 disabled,1: Interrupt on acknowledge error 15 enabled" newline bitfld.long 0x0 14. "AE14IE,Acknowledge error 14 interrupt enable" "0: Interrupt on acknowledge error 14 disabled,1: Interrupt on acknowledge error 14 enabled" bitfld.long 0x0 13. "AE13IE,Acknowledge error 13 interrupt enable" "0: Interrupt on acknowledge error 13 disabled,1: Interrupt on acknowledge error 13 enabled" newline bitfld.long 0x0 12. "AE12IE,Acknowledge error 12 interrupt enable" "0: Interrupt on acknowledge error 12 disabled,1: Interrupt on acknowledge error 12 enabled" bitfld.long 0x0 11. "AE11IE,Acknowledge error 11 interrupt enable" "0: Interrupt on acknowledge error 11 disabled,1: Interrupt on acknowledge error 11 enabled" newline bitfld.long 0x0 10. "AE10IE,Acknowledge error 10 interrupt enable" "0: Interrupt on acknowledge error 10 disabled,1: Interrupt on acknowledge error 10 enable." bitfld.long 0x0 9. "AE9IE,Acknowledge error 9 interrupt enable" "0: Interrupt on acknowledge error 9 disabled,1: Interrupt on acknowledge error 9 enabled" newline bitfld.long 0x0 8. "AE8IE,Acknowledge error 8 interrupt enable" "0: Interrupt on acknowledge error 8 disabled,1: Interrupt on acknowledge error 8 enabled" bitfld.long 0x0 7. "AE7IE,Acknowledge error 7 interrupt enable" "0: Interrupt on acknowledge error 7 disabled,1: Interrupt on acknowledge error 7 enabled" newline bitfld.long 0x0 6. "AE6IE,Acknowledge error 6 interrupt enable" "0: Interrupt on acknowledge error 6 disabled,1: Interrupt on acknowledge error 6 enabled" bitfld.long 0x0 5. "AE5IE,Acknowledge error 5 interrupt enable" "0: Interrupt on acknowledge error 5 disabled,1: Interrupt on acknowledge error 5 enabled" newline bitfld.long 0x0 4. "AE4IE,Acknowledge error 4 interrupt enable" "0: Interrupt on acknowledge error 4 disabled,1: Interrupt on acknowledge error 4 enabled" bitfld.long 0x0 3. "AE3IE,Acknowledge error 3 interrupt enable" "0: Interrupt on acknowledge error 3 disabled,1: Interrupt on acknowledge error 3 enabled" newline bitfld.long 0x0 2. "AE2IE,Acknowledge error 2 interrupt enable" "0: Interrupt on acknowledge error 2 disabled,1: Interrupt on acknowledge error 2 enabled" bitfld.long 0x0 1. "AE1IE,Acknowledge error 1 interrupt enable" "0: Interrupt on acknowledge error 1 disabled,1: Interrupt on acknowledge error 1 enabled" newline bitfld.long 0x0 0. "AE0IE,Acknowledge error 0 interrupt enable" "0: Interrupt on acknowledge error 0 disabled,1: Interrupt on acknowledge error 0 enabled" line.long 0x4 "DSI_IER1,DSI Host interrupt enable register 1" bitfld.long 0x4 19. "PBUEIE,Payload buffer underflow error interrupt enable" "0: Interrupt on payload buffer underflow error..,1: Interrupt on payload buffer underflow error.." bitfld.long 0x4 12. "GPRXEIE,Generic payload receive error interrupt enable" "0: Interrupt on generic payload receive error..,1: Interrupt on generic payload receive error enabled" newline bitfld.long 0x4 11. "GPRDEIE,Generic payload read error interrupt enable" "0: Interrupt on generic payload read error disabled,1: Interrupt on generic payload read error enabled" bitfld.long 0x4 10. "GPTXEIE,Generic payload transmit error interrupt enable" "0: Interrupt on generic payload transmit error..,1: Interrupt on generic payload transmit error.." newline bitfld.long 0x4 9. "GPWREIE,Generic payload write error interrupt enable" "0: Interrupt on generic payload write error disabled,1: Interrupt on generic payload write error enabled" bitfld.long 0x4 8. "GCWREIE,Generic command write error interrupt enable" "0: Interrupt on generic command write error disabled,1: Interrupt on generic command write error enabled" newline bitfld.long 0x4 7. "LPWREIE,LTDC payload write error interrupt enable" "0: Interrupt on LTDC payload write error disabled,1: Interrupt on LTDC payload write error enabled" bitfld.long 0x4 6. "EOTPEIE,EoTp error interrupt enable" "0: Interrupt on EoTp error disabled,1: Interrupt on EoTp error enabled" newline bitfld.long 0x4 5. "PSEIE,Packet size error interrupt enable" "0: Interrupt on packet size error disabled,1: Interrupt on packet size error enabled" bitfld.long 0x4 4. "CRCEIE,CRC error interrupt enable" "0: Interrupt on CRC error disabled,1: Interrupt on CRC error enabled" newline bitfld.long 0x4 3. "ECCMEIE,ECC multi-bit error interrupt enable" "0: Interrupt on ECC multi-bit error disabled,1: Interrupt on ECC multi-bit error enabled" bitfld.long 0x4 2. "ECCSEIE,ECC single-bit error interrupt enable" "0: Interrupt on ECC single-bit error disabled,1: Interrupt on ECC single-bit error enabled" newline bitfld.long 0x4 1. "TOLPRXIE,Timeout low-power reception interrupt enable" "0: Interrupt on timeout low-power reception disabled,1: Interrupt on timeout low-power reception enabled" bitfld.long 0x4 0. "TOHSTXIE,Timeout high-speed transmission interrupt enable" "0: Interrupt on timeout high-speed transmission..,1: Interrupt on timeout high-speed transmission.." wgroup.long 0xD8++0x7 line.long 0x0 "DSI_FIR0,DSI Host force interrupt register 0" bitfld.long 0x0 20. "FPE4,Force PHY error 4" "0,1" bitfld.long 0x0 19. "FPE3,Force PHY error 3" "0,1" newline bitfld.long 0x0 18. "FPE2,Force PHY error 2" "0,1" bitfld.long 0x0 17. "FPE1,Force PHY error 1" "0,1" newline bitfld.long 0x0 16. "FPE0,Force PHY error 0" "0,1" bitfld.long 0x0 15. "FAE15,Force acknowledge error 15" "0,1" newline bitfld.long 0x0 14. "FAE14,Force acknowledge error 14" "0,1" bitfld.long 0x0 13. "FAE13,Force acknowledge error 13" "0,1" newline bitfld.long 0x0 12. "FAE12,Force acknowledge error 12" "0,1" bitfld.long 0x0 11. "FAE11,Force acknowledge error 11" "0,1" newline bitfld.long 0x0 10. "FAE10,Force acknowledge error 10" "0,1" bitfld.long 0x0 9. "FAE9,Force acknowledge error 9" "0,1" newline bitfld.long 0x0 8. "FAE8,Force acknowledge error 8" "0,1" bitfld.long 0x0 7. "FAE7,Force acknowledge error 7" "0,1" newline bitfld.long 0x0 6. "FAE6,Force acknowledge error 6" "0,1" bitfld.long 0x0 5. "FAE5,Force acknowledge error 5" "0,1" newline bitfld.long 0x0 4. "FAE4,Force acknowledge error 4" "0,1" bitfld.long 0x0 3. "FAE3,Force acknowledge error 3" "0,1" newline bitfld.long 0x0 2. "FAE2,Force acknowledge error 2" "0,1" bitfld.long 0x0 1. "FAE1,Force acknowledge error 1" "0,1" newline bitfld.long 0x0 0. "FAE0,Force acknowledge error 0" "0,1" line.long 0x4 "DSI_FIR1,DSI Host force interrupt register 1" bitfld.long 0x4 19. "FPBUE,Force payload buffer underflow error" "0,1" bitfld.long 0x4 12. "FGPRXE,Force generic payload receive error" "0,1" newline bitfld.long 0x4 11. "FGPRDE,Force generic payload read error" "0,1" bitfld.long 0x4 10. "FGPTXE,Force generic payload transmit error" "0,1" newline bitfld.long 0x4 9. "FGPWRE,Force generic payload write error" "0,1" bitfld.long 0x4 8. "FGCWRE,Force generic command write error" "0,1" newline bitfld.long 0x4 7. "FLPWRE,Force LTDC payload write error" "0,1" bitfld.long 0x4 6. "FEOTPE,Force EoTp error" "0,1" newline bitfld.long 0x4 5. "FPSE,Force packet size error" "0,1" bitfld.long 0x4 4. "FCRCE,Force CRC error" "0,1" newline bitfld.long 0x4 3. "FECCME,Force ECC multi-bit error" "0,1" bitfld.long 0x4 2. "FECCSE,Force ECC single-bit error" "0,1" newline bitfld.long 0x4 1. "FTOLPRX,Force timeout low-power reception" "0,1" bitfld.long 0x4 0. "FTOHSTX,Force timeout high-speed transmission" "0,1" group.long 0xF4++0x3 line.long 0x0 "DSI_DLTRCR,DSI Host data lane timer read configuration register" hexmask.long.word 0x0 0.--14. 1. "MRD_TIME,Maximum read time" group.long 0x100++0x3 line.long 0x0 "DSI_VSCR,DSI Host video shadow control register" bitfld.long 0x0 8. "UR,Update register" "0: No update requested,1: Register update requested" bitfld.long 0x0 0. "EN,Enable" "0: Register update is disabled.,1: Register update is enabled." group.long 0x10C++0x3 line.long 0x0 "DSI_LCVCIDR,DSI Host LTDC current VCID register" bitfld.long 0x0 0.--1. "VCID,Virtual channel ID" "0,1,2,3" rgroup.long 0x110++0x3 line.long 0x0 "DSI_LCCCR,DSI Host LTDC current color coding register" bitfld.long 0x0 8. "LPE,Loosely packed enable" "0: Loosely packed variant disabled,1: Loosely packed variant enabled" hexmask.long.byte 0x0 0.--3. 1. "COLC,Color coding" rgroup.long 0x118++0x3 line.long 0x0 "DSI_LPMCCR,DSI Host low-power mode current configuration register" hexmask.long.byte 0x0 16.--23. 1. "LPSIZE,Largest packet size" hexmask.long.byte 0x0 0.--7. 1. "VLPSIZE,VACT largest packet size" rgroup.long 0x138++0x2B line.long 0x0 "DSI_VMCCR,DSI Host video mode current configuration register" bitfld.long 0x0 9. "LPCE,Low-power command enable" "0: Command transmission in low-power mode is..,1: Command transmission in low-power mode is enabled." bitfld.long 0x0 8. "FBTAAE,Frame BTA acknowledge enable" "0: Acknowledge response at the end of a frame is..,1: Acknowledge response at the end of a frame is.." newline bitfld.long 0x0 7. "LPHFE,Low-power horizontal front-porch enable" "0: Return to low-power inside the HFP period is..,1: Return to low-power inside the HFP period is.." bitfld.long 0x0 6. "LPHBPE,Low-power horizontal back-porch enable" "0: Return to low-power inside the HBP period is..,1: Return to low-power inside the HBP period is.." newline bitfld.long 0x0 5. "LPVAE,Low-power vertical active enable" "0: Return to low-power inside the VACT is disabled.,1: Return to low-power inside the VACT is enabled." bitfld.long 0x0 4. "LPVFPE,Low-power vertical front-porch enable" "0: Return to low-power inside the VFP is disabled.,1: Return to low-power inside the VFP is enabled." newline bitfld.long 0x0 3. "LPVBPE,Low-power vertical back-porch enable" "0: Return to low-power inside the VBP is disabled.,1: Return to low-power inside the VBP is enabled." bitfld.long 0x0 2. "LPVSAE,Low-power vertical sync time enable" "0: Return to low-power inside the VSA is disabled.,1: Return to low-power inside the VSA is enabled" newline bitfld.long 0x0 0.--1. "VMT,Video mode type" "0: Non-burst with sync pulses,1: Non-burst with sync events,?,?" line.long 0x4 "DSI_VPCCR,DSI Host video packet current configuration register" hexmask.long.word 0x4 0.--13. 1. "VPSIZE,Video packet size" line.long 0x8 "DSI_VCCCR,DSI Host video chunks current configuration register" hexmask.long.word 0x8 0.--12. 1. "NUMC,Number of chunks" line.long 0xC "DSI_VNPCCR,DSI Host video null packet current configuration register" hexmask.long.word 0xC 0.--12. 1. "NPSIZE,Null packet size" line.long 0x10 "DSI_VHSACCR,DSI Host video HSA current configuration register" hexmask.long.word 0x10 0.--11. 1. "HSA,Horizontal synchronism active duration" line.long 0x14 "DSI_VHBPCCR,DSI Host video HBP current configuration register" hexmask.long.word 0x14 0.--11. 1. "HBP,Horizontal back-porch duration" line.long 0x18 "DSI_VLCCR,DSI Host video line current configuration register" hexmask.long.word 0x18 0.--14. 1. "HLINE,Horizontal line duration" line.long 0x1C "DSI_VVSACCR,DSI Host video VSA current configuration register" hexmask.long.word 0x1C 0.--9. 1. "VSA,Vertical synchronism active duration" line.long 0x20 "DSI_VVBPCCR,DSI Host video VBP current configuration register" hexmask.long.word 0x20 0.--9. 1. "VBP,Vertical back-porch duration" line.long 0x24 "DSI_VVFPCCR,DSI Host video VFP current configuration register" hexmask.long.word 0x24 0.--9. 1. "VFP,Vertical front-porch duration" line.long 0x28 "DSI_VVACCR,DSI Host video VA current configuration register" hexmask.long.word 0x28 0.--13. 1. "VA,Vertical active duration" rgroup.long 0x168++0x3 line.long 0x0 "DSI_FBSR,DSI Host FIFO and buffer status register" bitfld.long 0x0 23. "APBF,Adapted command mode payload buffer full" "0: Payload internal buffer not full,1: Payload internal buffer full" bitfld.long 0x0 22. "APBE,Adapted command mode payload buffer empty" "0: Payload internal buffer not empty,1: Payload internal buffer empty" newline bitfld.long 0x0 21. "ACBF,Adapted command mode command buffer full" "0: Command internal buffer not full,1: Command internal buffer full" bitfld.long 0x0 20. "ACBE,Adapted command mode command buffer empty" "0: Command internal buffer not empty,1: Command internal buffer empty" newline bitfld.long 0x0 17. "VPBF,Video mode payload buffer full" "0: Payload internal buffer not full,1: Payload internal buffer full" bitfld.long 0x0 16. "VPBE,Video mode payload buffer empty" "0: Payload internal buffer not empty,1: Payload internal buffer empty" newline bitfld.long 0x0 7. "APWFF,Adapted command mode payload write FIFO full" "0: Write payload FIFO not full,1: Write payload FIFO full" bitfld.long 0x0 6. "APWFE,Adapted command mode payload write FIFO empty" "0: Write payload FIFO not empty,1: Write payload FIFO empty" newline bitfld.long 0x0 5. "ACWFF,Adapted command mode command write FIFO full" "0: Write command FIFO not full,1: Write command FIFO full" bitfld.long 0x0 4. "ACWFE,Adapted command mode command write FIFO empty" "0: Write command FIFO not empty,1: Write command FIFO empty" newline bitfld.long 0x0 3. "VPWFF,Video mode payload write FIFO full" "0: Write payload FIFO not full,1: Write payload FIFO full" bitfld.long 0x0 2. "VPWFE,Video mode payload write FIFO empty" "0: Write payload FIFO not empty,1: Write payload FIFO empty" newline bitfld.long 0x0 1. "VCWFF,Video mode command write FIFO full" "0: Write command FIFO not full,1: Write command FIFO full" bitfld.long 0x0 0. "VCWFE,Video mode command write FIFO empty" "0: Write command FIFO not empty,1: Write command FIFO empty" group.long 0x400++0xB line.long 0x0 "DSI_WCFGR,DSI Wrapper configuration register" bitfld.long 0x0 7. "VSPOL,VSync polarity" "0: LTDC halted on a falling edge,1: LTDC halted on a rising edge" bitfld.long 0x0 6. "AR,Automatic refresh" "0: automatic refresh mode disabled,1: automatic refresh mode enabled" newline bitfld.long 0x0 5. "TEPOL,TE polarity" "0: rising edge.,1: falling edge." bitfld.long 0x0 4. "TESRC,TE source" "0: DSI Link,1: External pin" newline bitfld.long 0x0 1.--3. "COLMUX,Color multiplexing" "0: 16-bit configuration 1,1: 16-bit configuration 2,2: 16-bit configuration 3,3: 18-bit configuration 1,4: 18-bit configuration 2,5: 24-bit,?,?" bitfld.long 0x0 0. "DSIM,DSI mode" "0: Video mode,1: Adapted command mode" line.long 0x4 "DSI_WCR,DSI Wrapper control register" bitfld.long 0x4 3. "DSIEN,DSI enable" "0: DSI disabled,1: DSI enabled" bitfld.long 0x4 2. "LTDCEN,LTDC enable" "0: LTDC disabled,1: LTDC enabled" newline bitfld.long 0x4 1. "SHTDN,Shutdown" "0: display ON,1: display OFF" bitfld.long 0x4 0. "COLM,Color mode" "0: Full color mode,1: Eight color mode" line.long 0x8 "DSI_WIER,DSI Wrapper interrupt enable register" bitfld.long 0x8 10. "PLLUIE,PLL unlock interrupt enable" "0: PLL unlock interrupt disabled,1: PLL unlock interrupt enabled" bitfld.long 0x8 9. "PLLLIE,PLL lock interrupt enable" "0: PLL lock interrupt disabled,1: PLL lock interrupt enabled" newline bitfld.long 0x8 1. "ERIE,End of refresh interrupt enable" "0: End of refresh interrupt disabled,1: End of refresh interrupt enabled" bitfld.long 0x8 0. "TEIE,Tearing effect interrupt enable" "0: Tearing effect interrupt disabled,1: Tearing effect interrupt enabled" rgroup.long 0x40C++0x3 line.long 0x0 "DSI_WISR,DSI Wrapper interrupt and status register" bitfld.long 0x0 10. "PLLUIF,PLL unlock interrupt flag" "0: No PLL unlock event occurred,1: PLL unlock event occurred" bitfld.long 0x0 9. "PLLLIF,PLL lock interrupt flag" "0: No PLL lock event occurred,1: PLL lock event occurred" newline bitfld.long 0x0 8. "PLLLS,PLL lock status" "0: PLL is unlocked.,1: PLL is locked." bitfld.long 0x0 2. "BUSY,Busy flag" "0: No transfer on going,1: Transfer on going" newline bitfld.long 0x0 1. "ERIF,End of refresh interrupt flag" "0: No end of refresh event occurred,1: End of refresh event occurred" bitfld.long 0x0 0. "TEIF,Tearing effect interrupt flag" "0: No tearing effect event occurred,1: Tearing effect event occurred" wgroup.long 0x410++0x3 line.long 0x0 "DSI_WIFCR,DSI Wrapper interrupt flag clear register" bitfld.long 0x0 10. "CPLLUIF,Clear PLL unlock interrupt flag" "0,1" bitfld.long 0x0 9. "CPLLLIF,Clear PLL lock interrupt flag" "0,1" newline bitfld.long 0x0 1. "CERIF,Clear end of refresh interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear tearing effect interrupt flag" "0,1" group.long 0x418++0x3 line.long 0x0 "DSI_WPCR0,DSI Wrapper PHY configuration register 0" bitfld.long 0x0 13. "FTXSMDL,Force in TX Stop mode the data lanes" "0: No effect,1: Force the data lanes in TX Stop mode" bitfld.long 0x0 12. "FTXSMCL,Force in TX Stop mode the clock lane" "0: No effect,1: Force the clock lane in TX Stop mode" newline bitfld.long 0x0 8. "SWDL1,Swap data lane 1 pins" "0: Regular clock lane pin configuration,1: Swapped clock lane pin" bitfld.long 0x0 7. "SWDL0,Swap data lane 0 pins" "0: Regular clock lane pin configuration,1: Swapped clock lane pin" newline bitfld.long 0x0 6. "SWCL,Swap clock lane pins" "0: Regular clock lane pin configuration,1: Swapped clock lane pin" group.long 0x430++0x3 line.long 0x0 "DSI_WRPCR,DSI Wrapper regulator and PLL control register" hexmask.long.word 0x0 20.--28. 1. "ODF,PLL output division factor" hexmask.long.word 0x0 11.--19. 1. "IDF,PLL input division factor" newline hexmask.long.word 0x0 2.--10. 1. "NDIV,PLL loop division factor" bitfld.long 0x0 0. "PLLEN,PLL enable" "0: PLL disabled,1: PLL enabled" group.long 0x808++0x3 line.long 0x0 "DSI_BCFGR,DSI bias configuration register" bitfld.long 0x0 6. "PWRUP,Power-up" "0: Reference bias is powered down.,1: Reference bias is powered up." group.long 0xC04++0x3 line.long 0x0 "DSI_DPCBCR,DSI D-PHY clock band control register" hexmask.long.byte 0x0 3.--7. 1. "BC,Band control" group.long 0xC34++0x3 line.long 0x0 "DSI_DPCSRCR,DSI D-PHY clock skew rate control register" hexmask.long.byte 0x0 0.--7. 1. "SRC,Slew rate control" group.long 0xC70++0x3 line.long 0x0 "DSI_DPDL0BCR,DSI D-PHY data lane 0 band control register" hexmask.long.byte 0x0 0.--4. 1. "BC,Band control" group.long 0xCA0++0x3 line.long 0x0 "DSI_DPDL0SRCR,DSI D-PHY data lane 0 skew rate control register" hexmask.long.byte 0x0 0.--7. 1. "SRC,Slew rate control" group.long 0xD08++0x3 line.long 0x0 "DSI_DPDL1BCR,DSI D-PHY data lane 1 band control register" hexmask.long.byte 0x0 0.--4. 1. "BC,Band control" group.long 0xD38++0x3 line.long 0x0 "DSI_DPDL1SRCR,DSI D-PHY data lane 1 skew rate control register" hexmask.long.byte 0x0 0.--7. 1. "SRC,Slew rate control" tree.end tree.end endif tree "EXTI (Extended Interrupt/Event Controller)" base ad:0x0 tree "EXTI" base ad:0x46022000 group.long 0x0++0x1B line.long 0x0 "EXTI_RTSR1,EXTI rising trigger selection register" bitfld.long 0x0 25. "RT25,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 24. "RT24,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 23. "RT23,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 22. "RT22,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 21. "RT21,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 20. "RT20,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 19. "RT19,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 18. "RT18,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 17. "RT17,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 16. "RT16,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." line.long 0x4 "EXTI_FTSR1,EXTI falling trigger selection register" bitfld.long 0x4 25. "FT25,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 24. "FT24,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 23. "FT23,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 22. "FT22,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 21. "FT21,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 20. "FT20,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 19. "FT19,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 18. "FT18,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 17. "FT17,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 16. "FT16,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." line.long 0x8 "EXTI_SWIER1,EXTI software interrupt event register" bitfld.long 0x8 25. "SWI25,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 24. "SWI24,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 23. "SWI23,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 22. "SWI22,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 21. "SWI21,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 20. "SWI20,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 19. "SWI19,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 18. "SWI18,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 17. "SWI17,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 16. "SWI16,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 15. "SWI15,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 14. "SWI14,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 13. "SWI13,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 12. "SWI12,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 11. "SWI11,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 10. "SWI10,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 9. "SWI9,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 8. "SWI8,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 7. "SWI7,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 6. "SWI6,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 5. "SWI5,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 4. "SWI4,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 3. "SWI3,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 2. "SWI2,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 1. "SWI1,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 0. "SWI0,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." line.long 0xC "EXTI_RPR1,EXTI rising edge pending register" bitfld.long 0xC 25. "RPIF25,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 24. "RPIF24,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 23. "RPIF23,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 22. "RPIF22,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 21. "RPIF21,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 20. "RPIF20,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 19. "RPIF19,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 18. "RPIF18,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 17. "RPIF17,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 16. "RPIF16,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 15. "RPIF15,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 14. "RPIF14,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 13. "RPIF13,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 12. "RPIF12,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 11. "RPIF11,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 10. "RPIF10,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 9. "RPIF9,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 8. "RPIF8,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 7. "RPIF7,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 6. "RPIF6,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 5. "RPIF5,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 4. "RPIF4,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 3. "RPIF3,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 2. "RPIF2,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 1. "RPIF1,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 0. "RPIF0,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" line.long 0x10 "EXTI_FPR1,EXTI falling edge pending register" bitfld.long 0x10 25. "FPIF25,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 24. "FPIF24,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 23. "FPIF23,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 22. "FPIF22,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 21. "FPIF21,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 20. "FPIF20,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 19. "FPIF19,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 18. "FPIF18,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 17. "FPIF17,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 16. "FPIF16,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 15. "FPIF15,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 14. "FPIF14,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 13. "FPIF13,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 12. "FPIF12,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 11. "FPIF11,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 10. "FPIF10,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 9. "FPIF9,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 8. "FPIF8,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 7. "FPIF7,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 6. "FPIF6,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 5. "FPIF5,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 4. "FPIF4,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 3. "FPIF3,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 2. "FPIF2,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 1. "FPIF1,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 0. "FPIF0,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" line.long 0x14 "EXTI_SECCFGR1,EXTI security configuration register" bitfld.long 0x14 25. "SEC25,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 24. "SEC24,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 23. "SEC23,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 22. "SEC22,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 21. "SEC21,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 20. "SEC20,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 19. "SEC19,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 18. "SEC18,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 17. "SEC17,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 16. "SEC16,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 15. "SEC15,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 14. "SEC14,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 13. "SEC13,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 12. "SEC12,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 11. "SEC11,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 10. "SEC10,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 9. "SEC9,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 8. "SEC8,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 7. "SEC7,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 6. "SEC6,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 5. "SEC5,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 4. "SEC4,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 3. "SEC3,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 2. "SEC2,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 1. "SEC1,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 0. "SEC0,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" line.long 0x18 "EXTI_PRIVCFGR1,EXTI privilege configuration register" bitfld.long 0x18 25. "PRIV25,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 24. "PRIV24,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 23. "PRIV23,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 22. "PRIV22,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 21. "PRIV21,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 20. "PRIV20,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 19. "PRIV19,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 18. "PRIV18,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 17. "PRIV17,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 16. "PRIV16,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 15. "PRIV15,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 14. "PRIV14,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 13. "PRIV13,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 12. "PRIV12,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 11. "PRIV11,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 10. "PRIV10,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 9. "PRIV9,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 8. "PRIV8,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 7. "PRIV7,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 6. "PRIV6,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 5. "PRIV5,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 4. "PRIV4,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 3. "PRIV3,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 2. "PRIV2,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 1. "PRIV1,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 0. "PRIV0,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" group.long 0x60++0x13 line.long 0x0 "EXTI_EXTICR1,EXTI external interrupt selection register" hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTIm+3 GPIO port selection" hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTIm+2 GPIO port selection" newline hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTIm+1 GPIO port selection" hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTIm GPIO port selection" line.long 0x4 "EXTI_EXTICR2,EXTI external interrupt selection register" hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTIm+3 GPIO port selection" hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTIm+2 GPIO port selection" newline hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTIm+1 GPIO port selection" hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTIm GPIO port selection" line.long 0x8 "EXTI_EXTICR3,EXTI external interrupt selection register" hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTIm+3 GPIO port selection" hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTIm+2 GPIO port selection" newline hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTIm+1 GPIO port selection" hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTIm GPIO port selection" line.long 0xC "EXTI_EXTICR4,EXTI external interrupt selection register" hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTIm+3 GPIO port selection" hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTIm+2 GPIO port selection" newline hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTIm+1 GPIO port selection" hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTIm GPIO port selection" line.long 0x10 "EXTI_LOCKR,EXTI lock register" bitfld.long 0x10 0. "LOCK,Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock" "0: Security and privilege configuration open can be..,1: Security and privilege configuration locked can.." group.long 0x80++0x7 line.long 0x0 "EXTI_IMR1,EXTI CPU wake-up with interrupt mask register" bitfld.long 0x0 25. "IM25,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 24. "IM24,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 23. "IM23,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 22. "IM22,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 21. "IM21,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 20. "IM20,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 19. "IM19,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 18. "IM18,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 17. "IM17,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 16. "IM16,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 15. "IM15,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 14. "IM14,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 13. "IM13,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 12. "IM12,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 11. "IM11,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 10. "IM10,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 9. "IM9,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 8. "IM8,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 7. "IM7,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 6. "IM6,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 5. "IM5,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 4. "IM4,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 3. "IM3,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 2. "IM2,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 1. "IM1,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 0. "IM0,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." line.long 0x4 "EXTI_EMR1,EXTI CPU wake-up with event mask register" bitfld.long 0x4 25. "EM25,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 24. "EM24,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 23. "EM23,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 22. "EM22,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 21. "EM21,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 20. "EM20,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 19. "EM19,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 18. "EM18,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 17. "EM17,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 16. "EM16,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 15. "EM15,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 14. "EM14,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 13. "EM13,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 12. "EM12,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 11. "EM11,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 10. "EM10,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 9. "EM9,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 8. "EM8,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 7. "EM7,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 6. "EM6,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 5. "EM5,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 4. "EM4,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 3. "EM3,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 2. "EM2,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 1. "EM1,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 0. "EM0,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." tree.end tree "SEC_EXTI" base ad:0x56022000 group.long 0x0++0x1B line.long 0x0 "EXTI_RTSR1,EXTI rising trigger selection register" bitfld.long 0x0 25. "RT25,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 24. "RT24,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 23. "RT23,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 22. "RT22,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 21. "RT21,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 20. "RT20,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 19. "RT19,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 18. "RT18,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 17. "RT17,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 16. "RT16,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." line.long 0x4 "EXTI_FTSR1,EXTI falling trigger selection register" bitfld.long 0x4 25. "FT25,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 24. "FT24,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 23. "FT23,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 22. "FT22,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 21. "FT21,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 20. "FT20,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 19. "FT19,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 18. "FT18,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 17. "FT17,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 16. "FT16,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." line.long 0x8 "EXTI_SWIER1,EXTI software interrupt event register" bitfld.long 0x8 25. "SWI25,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 24. "SWI24,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 23. "SWI23,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 22. "SWI22,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 21. "SWI21,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 20. "SWI20,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 19. "SWI19,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 18. "SWI18,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 17. "SWI17,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 16. "SWI16,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 15. "SWI15,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 14. "SWI14,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 13. "SWI13,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 12. "SWI12,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 11. "SWI11,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 10. "SWI10,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 9. "SWI9,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 8. "SWI8,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 7. "SWI7,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 6. "SWI6,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 5. "SWI5,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 4. "SWI4,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 3. "SWI3,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 2. "SWI2,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." newline bitfld.long 0x8 1. "SWI1,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." bitfld.long 0x8 0. "SWI0,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 triggers a rising edge event on event.." line.long 0xC "EXTI_RPR1,EXTI rising edge pending register" bitfld.long 0xC 25. "RPIF25,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 24. "RPIF24,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 23. "RPIF23,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 22. "RPIF22,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 21. "RPIF21,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 20. "RPIF20,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 19. "RPIF19,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 18. "RPIF18,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 17. "RPIF17,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 16. "RPIF16,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 15. "RPIF15,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 14. "RPIF14,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 13. "RPIF13,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 12. "RPIF12,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 11. "RPIF11,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 10. "RPIF10,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 9. "RPIF9,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 8. "RPIF8,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 7. "RPIF7,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 6. "RPIF6,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 5. "RPIF5,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 4. "RPIF4,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 3. "RPIF3,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 2. "RPIF2,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 1. "RPIF1,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 0. "RPIF0,configurable event inputs x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" line.long 0x10 "EXTI_FPR1,EXTI falling edge pending register" bitfld.long 0x10 25. "FPIF25,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 24. "FPIF24,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 23. "FPIF23,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 22. "FPIF22,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 21. "FPIF21,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 20. "FPIF20,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 19. "FPIF19,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 18. "FPIF18,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 17. "FPIF17,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 16. "FPIF16,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 15. "FPIF15,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 14. "FPIF14,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 13. "FPIF13,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 12. "FPIF12,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 11. "FPIF11,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 10. "FPIF10,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 9. "FPIF9,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 8. "FPIF8,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 7. "FPIF7,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 6. "FPIF6,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 5. "FPIF5,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 4. "FPIF4,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 3. "FPIF3,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 2. "FPIF2,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 1. "FPIF1,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 0. "FPIF0,configurable event inputs x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" line.long 0x14 "EXTI_SECCFGR1,EXTI security configuration register" bitfld.long 0x14 25. "SEC25,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 24. "SEC24,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 23. "SEC23,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 22. "SEC22,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 21. "SEC21,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 20. "SEC20,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 19. "SEC19,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 18. "SEC18,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 17. "SEC17,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 16. "SEC16,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 15. "SEC15,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 14. "SEC14,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 13. "SEC13,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 12. "SEC12,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 11. "SEC11,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 10. "SEC10,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 9. "SEC9,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 8. "SEC8,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 7. "SEC7,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 6. "SEC6,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 5. "SEC5,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 4. "SEC4,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 3. "SEC3,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 2. "SEC2,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 1. "SEC1,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 0. "SEC0,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" line.long 0x18 "EXTI_PRIVCFGR1,EXTI privilege configuration register" bitfld.long 0x18 25. "PRIV25,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 24. "PRIV24,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 23. "PRIV23,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 22. "PRIV22,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 21. "PRIV21,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 20. "PRIV20,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 19. "PRIV19,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 18. "PRIV18,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 17. "PRIV17,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 16. "PRIV16,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 15. "PRIV15,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 14. "PRIV14,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 13. "PRIV13,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 12. "PRIV12,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 11. "PRIV11,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 10. "PRIV10,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 9. "PRIV9,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 8. "PRIV8,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 7. "PRIV7,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 6. "PRIV6,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 5. "PRIV5,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 4. "PRIV4,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 3. "PRIV3,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 2. "PRIV2,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 1. "PRIV1,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 0. "PRIV0,Security enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" group.long 0x60++0x13 line.long 0x0 "EXTI_EXTICR1,EXTI external interrupt selection register" hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTIm+3 GPIO port selection" hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTIm+2 GPIO port selection" newline hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTIm+1 GPIO port selection" hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTIm GPIO port selection" line.long 0x4 "EXTI_EXTICR2,EXTI external interrupt selection register" hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTIm+3 GPIO port selection" hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTIm+2 GPIO port selection" newline hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTIm+1 GPIO port selection" hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTIm GPIO port selection" line.long 0x8 "EXTI_EXTICR3,EXTI external interrupt selection register" hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTIm+3 GPIO port selection" hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTIm+2 GPIO port selection" newline hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTIm+1 GPIO port selection" hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTIm GPIO port selection" line.long 0xC "EXTI_EXTICR4,EXTI external interrupt selection register" hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTIm+3 GPIO port selection" hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTIm+2 GPIO port selection" newline hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTIm+1 GPIO port selection" hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTIm GPIO port selection" line.long 0x10 "EXTI_LOCKR,EXTI lock register" bitfld.long 0x10 0. "LOCK,Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock" "0: Security and privilege configuration open can be..,1: Security and privilege configuration locked can.." group.long 0x80++0x7 line.long 0x0 "EXTI_IMR1,EXTI CPU wake-up with interrupt mask register" bitfld.long 0x0 25. "IM25,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 24. "IM24,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 23. "IM23,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 22. "IM22,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 21. "IM21,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 20. "IM20,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 19. "IM19,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 18. "IM18,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 17. "IM17,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 16. "IM16,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 15. "IM15,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 14. "IM14,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 13. "IM13,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 12. "IM12,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 11. "IM11,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 10. "IM10,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 9. "IM9,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 8. "IM8,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 7. "IM7,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 6. "IM6,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 5. "IM5,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 4. "IM4,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 3. "IM3,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 2. "IM2,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." newline bitfld.long 0x0 1. "IM1,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." bitfld.long 0x0 0. "IM0,CPU wake-up with interrupt mask on event input x" "0: Wake-up with interrupt request from input event..,1: Wake-up with interrupt request from input event.." line.long 0x4 "EXTI_EMR1,EXTI CPU wake-up with event mask register" bitfld.long 0x4 25. "EM25,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 24. "EM24,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 23. "EM23,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 22. "EM22,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 21. "EM21,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 20. "EM20,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 19. "EM19,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 18. "EM18,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 17. "EM17,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 16. "EM16,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 15. "EM15,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 14. "EM14,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 13. "EM13,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 12. "EM12,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 11. "EM11,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 10. "EM10,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 9. "EM9,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 8. "EM8,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 7. "EM7,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 6. "EM6,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 5. "EM5,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 4. "EM4,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 3. "EM3,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 2. "EM2,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." newline bitfld.long 0x4 1. "EM1,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." bitfld.long 0x4 0. "EM0,CPU wake-up with event generation mask on event input x" "0: Wake-up with event generation from line x is..,1: Wake-up with event generation from line x is.." tree.end tree.end tree "FDCAN (Controller Area Network)" base ad:0x0 tree "FDCAN1" base ad:0x4000A400 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" group.long 0xC++0x23 line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" rbitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" line.long 0xC "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0xC 14. "TXP,TXP" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0xC 9. "BRSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0xC 1. "CCE,Configuration Change" "0,1" bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump" hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample" line.long 0x14 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" rbitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" rbitfld.long 0x4 6. "EW,Warning Status" "0,1" rbitfld.long 0x4 5. "EP,Error Passive" "0,1" newline rbitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" line.long 0x8 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 23. "ARA,ARA" "0,1" bitfld.long 0x0 22. "PED,PED" "0,1" bitfld.long 0x0 21. "PEA,PEA" "0,1" bitfld.long 0x0 20. "WDI,WDI" "0,1" bitfld.long 0x0 19. "BO,BO" "0,1" bitfld.long 0x0 18. "EW,EW" "0,1" bitfld.long 0x0 17. "EP,EP" "0,1" bitfld.long 0x0 16. "ELO,ELO" "0,1" bitfld.long 0x0 15. "TOO,TOO" "0,1" newline bitfld.long 0x0 14. "MRAF,MRAF" "0,1" bitfld.long 0x0 13. "TSW,TSW" "0,1" bitfld.long 0x0 12. "TEFL,TEFL" "0,1" bitfld.long 0x0 11. "TEFF,TEFF" "0,1" bitfld.long 0x0 10. "TEFN,TEFN" "0,1" bitfld.long 0x0 9. "TFE,TFE" "0,1" bitfld.long 0x0 8. "TCF,TCF" "0,1" bitfld.long 0x0 7. "TC,TC" "0,1" bitfld.long 0x0 6. "HPM,HPM" "0,1" newline bitfld.long 0x0 5. "RF1L,RF1L" "0,1" bitfld.long 0x0 4. "RF1F,RF1F" "0,1" bitfld.long 0x0 3. "RF1N,RF1N" "0,1" bitfld.long 0x0 2. "RF0L,RF0L" "0,1" bitfld.long 0x0 1. "RF0F,RF0F" "0,1" bitfld.long 0x0 0. "RF0N,RF0N" "0,1" line.long 0x4 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x4 23. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x4 22. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x4 21. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x4 20. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 19. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 18. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 17. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 16. "ELOE,Error Logging Overflow" "0,1" bitfld.long 0x4 15. "TOOE,Timeout Occurred Enable" "0,1" newline bitfld.long 0x4 14. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x4 13. "TSWE,TSWE" "0,1" bitfld.long 0x4 12. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x4 11. "TEFFE,Tx Event FIFO Full Enable" "0,1" bitfld.long 0x4 10. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x4 9. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 8. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x4 7. "TCE,Transmission Completed" "0,1" bitfld.long 0x4 6. "HPME,High Priority Message" "0,1" newline bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message" "0,1" line.long 0x8 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x8 6. "PERR,PERR" "0,1" bitfld.long 0x8 5. "BERR,BERR" "0,1" bitfld.long 0x8 4. "MISC,MISC" "0,1" bitfld.long 0x8 3. "TFERR,TFERR" "0,1" bitfld.long 0x8 2. "SMSG,SMSG" "0,1" bitfld.long 0x8 1. "RxFIFO1,RxFIFO1" "0,1" bitfld.long 0x8 0. "RxFIFO0,RxFIFO0" "0,1" line.long 0xC "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0x7 line.long 0x0 "FDCAN_RXGFC,FDCAN Global Filter Configuration" hexmask.long.byte 0x0 24.--27. 1. "LSE,LSE" hexmask.long.byte 0x0 16.--20. 1. "LSS,LSS" bitfld.long 0x0 9. "F0OM,F0OM" "0,1" bitfld.long 0x0 8. "F1OM,F1OM" "0,1" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x88++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" bitfld.long 0x0 0.--2. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7" rgroup.long 0x90++0x3 line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x94++0x3 line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 Acknowledge" "0,1,2,3,4,5,6,7" rgroup.long 0x98++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x9C++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 Acknowledge" "0,1,2,3,4,5,6,7" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 24. "TFQM,Tx FIFO/Queue Mode" "0,1" rgroup.long 0xC4++0x7 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "TFGI,TFGI" "0,1,2,3" bitfld.long 0x0 0.--2. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" bitfld.long 0x4 0.--2. "TRP,Transmission Request" "0,1,2,3,4,5,6,7" group.long 0xCC++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" bitfld.long 0x0 0.--2. "AR,Add Request" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" bitfld.long 0x4 0.--2. "CR,Cancellation Request" "0,1,2,3,4,5,6,7" rgroup.long 0xD4++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" bitfld.long 0x0 0.--2. "TO,Transmission Occurred." "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 0.--2. "CF,Cancellation Finished" "0,1,2,3,4,5,6,7" group.long 0xDC++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" bitfld.long 0x0 0.--2. "TIE,Transmission Interrupt" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 0.--2. "CFIE,Cancellation Finished Interrupt" "0,1,2,3,4,5,6,7" rgroup.long 0xE4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full." "0,1" bitfld.long 0x0 16.--17. "EFPI,Event FIFO Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "EFGI,Event FIFO Get Index." "0,1,2,3" bitfld.long 0x0 0.--2. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7" group.long 0xE8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" bitfld.long 0x0 0.--1. "EFAI,Event FIFO Acknowledge" "0,1,2,3" group.long 0x100++0x3 line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register" hexmask.long.byte 0x0 0.--3. 1. "PDIV,PDIV" tree.end tree "FDCAN1_RAM" base ad:0x4000AC00 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" group.long 0xC++0x23 line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" rbitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" line.long 0xC "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0xC 14. "TXP,TXP" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0xC 9. "BRSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0xC 1. "CCE,Configuration Change" "0,1" bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump" hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample" line.long 0x14 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" rbitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" rbitfld.long 0x4 6. "EW,Warning Status" "0,1" rbitfld.long 0x4 5. "EP,Error Passive" "0,1" newline rbitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" line.long 0x8 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 23. "ARA,ARA" "0,1" bitfld.long 0x0 22. "PED,PED" "0,1" bitfld.long 0x0 21. "PEA,PEA" "0,1" bitfld.long 0x0 20. "WDI,WDI" "0,1" bitfld.long 0x0 19. "BO,BO" "0,1" bitfld.long 0x0 18. "EW,EW" "0,1" bitfld.long 0x0 17. "EP,EP" "0,1" bitfld.long 0x0 16. "ELO,ELO" "0,1" bitfld.long 0x0 15. "TOO,TOO" "0,1" newline bitfld.long 0x0 14. "MRAF,MRAF" "0,1" bitfld.long 0x0 13. "TSW,TSW" "0,1" bitfld.long 0x0 12. "TEFL,TEFL" "0,1" bitfld.long 0x0 11. "TEFF,TEFF" "0,1" bitfld.long 0x0 10. "TEFN,TEFN" "0,1" bitfld.long 0x0 9. "TFE,TFE" "0,1" bitfld.long 0x0 8. "TCF,TCF" "0,1" bitfld.long 0x0 7. "TC,TC" "0,1" bitfld.long 0x0 6. "HPM,HPM" "0,1" newline bitfld.long 0x0 5. "RF1L,RF1L" "0,1" bitfld.long 0x0 4. "RF1F,RF1F" "0,1" bitfld.long 0x0 3. "RF1N,RF1N" "0,1" bitfld.long 0x0 2. "RF0L,RF0L" "0,1" bitfld.long 0x0 1. "RF0F,RF0F" "0,1" bitfld.long 0x0 0. "RF0N,RF0N" "0,1" line.long 0x4 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x4 23. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x4 22. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x4 21. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x4 20. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 19. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 18. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 17. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 16. "ELOE,Error Logging Overflow" "0,1" bitfld.long 0x4 15. "TOOE,Timeout Occurred Enable" "0,1" newline bitfld.long 0x4 14. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x4 13. "TSWE,TSWE" "0,1" bitfld.long 0x4 12. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x4 11. "TEFFE,Tx Event FIFO Full Enable" "0,1" bitfld.long 0x4 10. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x4 9. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 8. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x4 7. "TCE,Transmission Completed" "0,1" bitfld.long 0x4 6. "HPME,High Priority Message" "0,1" newline bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message" "0,1" line.long 0x8 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x8 6. "PERR,PERR" "0,1" bitfld.long 0x8 5. "BERR,BERR" "0,1" bitfld.long 0x8 4. "MISC,MISC" "0,1" bitfld.long 0x8 3. "TFERR,TFERR" "0,1" bitfld.long 0x8 2. "SMSG,SMSG" "0,1" bitfld.long 0x8 1. "RxFIFO1,RxFIFO1" "0,1" bitfld.long 0x8 0. "RxFIFO0,RxFIFO0" "0,1" line.long 0xC "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0x7 line.long 0x0 "FDCAN_RXGFC,FDCAN Global Filter Configuration" hexmask.long.byte 0x0 24.--27. 1. "LSE,LSE" hexmask.long.byte 0x0 16.--20. 1. "LSS,LSS" bitfld.long 0x0 9. "F0OM,F0OM" "0,1" bitfld.long 0x0 8. "F1OM,F1OM" "0,1" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x88++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" bitfld.long 0x0 0.--2. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7" rgroup.long 0x90++0x3 line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x94++0x3 line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 Acknowledge" "0,1,2,3,4,5,6,7" rgroup.long 0x98++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x9C++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 Acknowledge" "0,1,2,3,4,5,6,7" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 24. "TFQM,Tx FIFO/Queue Mode" "0,1" rgroup.long 0xC4++0x7 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "TFGI,TFGI" "0,1,2,3" bitfld.long 0x0 0.--2. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" bitfld.long 0x4 0.--2. "TRP,Transmission Request" "0,1,2,3,4,5,6,7" group.long 0xCC++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" bitfld.long 0x0 0.--2. "AR,Add Request" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" bitfld.long 0x4 0.--2. "CR,Cancellation Request" "0,1,2,3,4,5,6,7" rgroup.long 0xD4++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" bitfld.long 0x0 0.--2. "TO,Transmission Occurred." "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 0.--2. "CF,Cancellation Finished" "0,1,2,3,4,5,6,7" group.long 0xDC++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" bitfld.long 0x0 0.--2. "TIE,Transmission Interrupt" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 0.--2. "CFIE,Cancellation Finished Interrupt" "0,1,2,3,4,5,6,7" rgroup.long 0xE4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full." "0,1" bitfld.long 0x0 16.--17. "EFPI,Event FIFO Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "EFGI,Event FIFO Get Index." "0,1,2,3" bitfld.long 0x0 0.--2. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7" group.long 0xE8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" bitfld.long 0x0 0.--1. "EFAI,Event FIFO Acknowledge" "0,1,2,3" group.long 0x100++0x3 line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register" hexmask.long.byte 0x0 0.--3. 1. "PDIV,PDIV" tree.end tree "SEC_FDCAN1" base ad:0x5000A400 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" group.long 0xC++0x23 line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" rbitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" line.long 0xC "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0xC 14. "TXP,TXP" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0xC 9. "BRSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0xC 1. "CCE,Configuration Change" "0,1" bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump" hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample" line.long 0x14 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" rbitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" rbitfld.long 0x4 6. "EW,Warning Status" "0,1" rbitfld.long 0x4 5. "EP,Error Passive" "0,1" newline rbitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" line.long 0x8 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 23. "ARA,ARA" "0,1" bitfld.long 0x0 22. "PED,PED" "0,1" bitfld.long 0x0 21. "PEA,PEA" "0,1" bitfld.long 0x0 20. "WDI,WDI" "0,1" bitfld.long 0x0 19. "BO,BO" "0,1" bitfld.long 0x0 18. "EW,EW" "0,1" bitfld.long 0x0 17. "EP,EP" "0,1" bitfld.long 0x0 16. "ELO,ELO" "0,1" bitfld.long 0x0 15. "TOO,TOO" "0,1" newline bitfld.long 0x0 14. "MRAF,MRAF" "0,1" bitfld.long 0x0 13. "TSW,TSW" "0,1" bitfld.long 0x0 12. "TEFL,TEFL" "0,1" bitfld.long 0x0 11. "TEFF,TEFF" "0,1" bitfld.long 0x0 10. "TEFN,TEFN" "0,1" bitfld.long 0x0 9. "TFE,TFE" "0,1" bitfld.long 0x0 8. "TCF,TCF" "0,1" bitfld.long 0x0 7. "TC,TC" "0,1" bitfld.long 0x0 6. "HPM,HPM" "0,1" newline bitfld.long 0x0 5. "RF1L,RF1L" "0,1" bitfld.long 0x0 4. "RF1F,RF1F" "0,1" bitfld.long 0x0 3. "RF1N,RF1N" "0,1" bitfld.long 0x0 2. "RF0L,RF0L" "0,1" bitfld.long 0x0 1. "RF0F,RF0F" "0,1" bitfld.long 0x0 0. "RF0N,RF0N" "0,1" line.long 0x4 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x4 23. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x4 22. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x4 21. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x4 20. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 19. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 18. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 17. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 16. "ELOE,Error Logging Overflow" "0,1" bitfld.long 0x4 15. "TOOE,Timeout Occurred Enable" "0,1" newline bitfld.long 0x4 14. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x4 13. "TSWE,TSWE" "0,1" bitfld.long 0x4 12. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x4 11. "TEFFE,Tx Event FIFO Full Enable" "0,1" bitfld.long 0x4 10. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x4 9. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 8. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x4 7. "TCE,Transmission Completed" "0,1" bitfld.long 0x4 6. "HPME,High Priority Message" "0,1" newline bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message" "0,1" line.long 0x8 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x8 6. "PERR,PERR" "0,1" bitfld.long 0x8 5. "BERR,BERR" "0,1" bitfld.long 0x8 4. "MISC,MISC" "0,1" bitfld.long 0x8 3. "TFERR,TFERR" "0,1" bitfld.long 0x8 2. "SMSG,SMSG" "0,1" bitfld.long 0x8 1. "RxFIFO1,RxFIFO1" "0,1" bitfld.long 0x8 0. "RxFIFO0,RxFIFO0" "0,1" line.long 0xC "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0x7 line.long 0x0 "FDCAN_RXGFC,FDCAN Global Filter Configuration" hexmask.long.byte 0x0 24.--27. 1. "LSE,LSE" hexmask.long.byte 0x0 16.--20. 1. "LSS,LSS" bitfld.long 0x0 9. "F0OM,F0OM" "0,1" bitfld.long 0x0 8. "F1OM,F1OM" "0,1" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x88++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" bitfld.long 0x0 0.--2. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7" rgroup.long 0x90++0x3 line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x94++0x3 line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 Acknowledge" "0,1,2,3,4,5,6,7" rgroup.long 0x98++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x9C++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 Acknowledge" "0,1,2,3,4,5,6,7" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 24. "TFQM,Tx FIFO/Queue Mode" "0,1" rgroup.long 0xC4++0x7 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "TFGI,TFGI" "0,1,2,3" bitfld.long 0x0 0.--2. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" bitfld.long 0x4 0.--2. "TRP,Transmission Request" "0,1,2,3,4,5,6,7" group.long 0xCC++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" bitfld.long 0x0 0.--2. "AR,Add Request" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" bitfld.long 0x4 0.--2. "CR,Cancellation Request" "0,1,2,3,4,5,6,7" rgroup.long 0xD4++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" bitfld.long 0x0 0.--2. "TO,Transmission Occurred." "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 0.--2. "CF,Cancellation Finished" "0,1,2,3,4,5,6,7" group.long 0xDC++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" bitfld.long 0x0 0.--2. "TIE,Transmission Interrupt" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 0.--2. "CFIE,Cancellation Finished Interrupt" "0,1,2,3,4,5,6,7" rgroup.long 0xE4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full." "0,1" bitfld.long 0x0 16.--17. "EFPI,Event FIFO Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "EFGI,Event FIFO Get Index." "0,1,2,3" bitfld.long 0x0 0.--2. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7" group.long 0xE8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" bitfld.long 0x0 0.--1. "EFAI,Event FIFO Acknowledge" "0,1,2,3" group.long 0x100++0x3 line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register" hexmask.long.byte 0x0 0.--3. 1. "PDIV,PDIV" tree.end tree "SEC_FDCAN1_RAM" base ad:0x5000AC00 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" group.long 0xC++0x23 line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" rbitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" line.long 0xC "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0xC 14. "TXP,TXP" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0xC 9. "BRSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0xC 1. "CCE,Configuration Change" "0,1" bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump" hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample" line.long 0x14 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" rbitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" rbitfld.long 0x4 6. "EW,Warning Status" "0,1" rbitfld.long 0x4 5. "EP,Error Passive" "0,1" newline rbitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" line.long 0x8 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 23. "ARA,ARA" "0,1" bitfld.long 0x0 22. "PED,PED" "0,1" bitfld.long 0x0 21. "PEA,PEA" "0,1" bitfld.long 0x0 20. "WDI,WDI" "0,1" bitfld.long 0x0 19. "BO,BO" "0,1" bitfld.long 0x0 18. "EW,EW" "0,1" bitfld.long 0x0 17. "EP,EP" "0,1" bitfld.long 0x0 16. "ELO,ELO" "0,1" bitfld.long 0x0 15. "TOO,TOO" "0,1" newline bitfld.long 0x0 14. "MRAF,MRAF" "0,1" bitfld.long 0x0 13. "TSW,TSW" "0,1" bitfld.long 0x0 12. "TEFL,TEFL" "0,1" bitfld.long 0x0 11. "TEFF,TEFF" "0,1" bitfld.long 0x0 10. "TEFN,TEFN" "0,1" bitfld.long 0x0 9. "TFE,TFE" "0,1" bitfld.long 0x0 8. "TCF,TCF" "0,1" bitfld.long 0x0 7. "TC,TC" "0,1" bitfld.long 0x0 6. "HPM,HPM" "0,1" newline bitfld.long 0x0 5. "RF1L,RF1L" "0,1" bitfld.long 0x0 4. "RF1F,RF1F" "0,1" bitfld.long 0x0 3. "RF1N,RF1N" "0,1" bitfld.long 0x0 2. "RF0L,RF0L" "0,1" bitfld.long 0x0 1. "RF0F,RF0F" "0,1" bitfld.long 0x0 0. "RF0N,RF0N" "0,1" line.long 0x4 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x4 23. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x4 22. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x4 21. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x4 20. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 19. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 18. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 17. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 16. "ELOE,Error Logging Overflow" "0,1" bitfld.long 0x4 15. "TOOE,Timeout Occurred Enable" "0,1" newline bitfld.long 0x4 14. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x4 13. "TSWE,TSWE" "0,1" bitfld.long 0x4 12. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x4 11. "TEFFE,Tx Event FIFO Full Enable" "0,1" bitfld.long 0x4 10. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x4 9. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 8. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x4 7. "TCE,Transmission Completed" "0,1" bitfld.long 0x4 6. "HPME,High Priority Message" "0,1" newline bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message" "0,1" line.long 0x8 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x8 6. "PERR,PERR" "0,1" bitfld.long 0x8 5. "BERR,BERR" "0,1" bitfld.long 0x8 4. "MISC,MISC" "0,1" bitfld.long 0x8 3. "TFERR,TFERR" "0,1" bitfld.long 0x8 2. "SMSG,SMSG" "0,1" bitfld.long 0x8 1. "RxFIFO1,RxFIFO1" "0,1" bitfld.long 0x8 0. "RxFIFO0,RxFIFO0" "0,1" line.long 0xC "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0x7 line.long 0x0 "FDCAN_RXGFC,FDCAN Global Filter Configuration" hexmask.long.byte 0x0 24.--27. 1. "LSE,LSE" hexmask.long.byte 0x0 16.--20. 1. "LSS,LSS" bitfld.long 0x0 9. "F0OM,F0OM" "0,1" bitfld.long 0x0 8. "F1OM,F1OM" "0,1" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x88++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" bitfld.long 0x0 0.--2. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7" rgroup.long 0x90++0x3 line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x94++0x3 line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 Acknowledge" "0,1,2,3,4,5,6,7" rgroup.long 0x98++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x9C++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 Acknowledge" "0,1,2,3,4,5,6,7" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 24. "TFQM,Tx FIFO/Queue Mode" "0,1" rgroup.long 0xC4++0x7 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "TFGI,TFGI" "0,1,2,3" bitfld.long 0x0 0.--2. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" bitfld.long 0x4 0.--2. "TRP,Transmission Request" "0,1,2,3,4,5,6,7" group.long 0xCC++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" bitfld.long 0x0 0.--2. "AR,Add Request" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" bitfld.long 0x4 0.--2. "CR,Cancellation Request" "0,1,2,3,4,5,6,7" rgroup.long 0xD4++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" bitfld.long 0x0 0.--2. "TO,Transmission Occurred." "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 0.--2. "CF,Cancellation Finished" "0,1,2,3,4,5,6,7" group.long 0xDC++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" bitfld.long 0x0 0.--2. "TIE,Transmission Interrupt" "0,1,2,3,4,5,6,7" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 0.--2. "CFIE,Cancellation Finished Interrupt" "0,1,2,3,4,5,6,7" rgroup.long 0xE4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full." "0,1" bitfld.long 0x0 16.--17. "EFPI,Event FIFO Put Index" "0,1,2,3" bitfld.long 0x0 8.--9. "EFGI,Event FIFO Get Index." "0,1,2,3" bitfld.long 0x0 0.--2. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7" group.long 0xE8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" bitfld.long 0x0 0.--1. "EFAI,Event FIFO Acknowledge" "0,1,2,3" group.long 0x100++0x3 line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register" hexmask.long.byte 0x0 0.--3. 1. "PDIV,PDIV" tree.end tree.end tree "FLASH (Embedded Flash Memory)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "FLASH" base ad:0x40022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline endif bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x8 3.--9. 1. "PNB,Non-secure page number selection" newline endif bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline endif sif (cpuis("STM32U575*")) bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0,1" newline endif bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline sif (cpuis("STM32U575*")) hexmask.long.byte 0xC 3.--9. 1. "PNB,Secure page number selection" newline endif bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" newline endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x10 0.--19. 1. "ADDR_ECC,ECC fail address" endif rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" newline endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x0 0.--19. 1. "ADDR_OP,Interrupted operation address" endif group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline sif (cpuis("STM32U575*")) bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline endif bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM4 and SRAM5 erased when a system reset..,1: SRAM1 SRAM4 and SRAM5 not erased when a system.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x10 16.--22. 1. "SECWM1_PEND,End page of first secure area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x10 0.--6. 1. "SECWM1_PSTRT,Start page of first secure area" endif line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x14 16.--22. 1. "HDP1_PEND,End page of first hide protection area" endif line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x18 16.--22. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x18 0.--6. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" endif line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x1C 16.--22. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x1C 0.--6. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" endif line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x20 16.--22. 1. "SECWM2_PEND,End page of second secure area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x20 0.--6. 1. "SECWM2_PSTRT,Start page of second secure area" endif line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x24 16.--22. 1. "HDP2_PEND,End page of hide protection second area" endif line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x28 16.--22. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x28 0.--6. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" endif line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x2C 16.--22. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x2C 0.--6. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" endif wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0xF line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x90++0xF line.long 0x0 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x0 31. "SEC1BB31," "0,1" bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x4 31. "SEC1BB31," "0,1" bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x8 31. "SEC1BB31," "0,1" bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0xC 31. "SEC1BB31," "0,1" bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" bitfld.long 0xC 0. "SEC1BB0," "0,1" group.long 0xB0++0xF line.long 0x0 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x0 31. "SEC2BB31," "0,1" bitfld.long 0x0 30. "SEC2BB30," "0,1" newline bitfld.long 0x0 29. "SEC2BB29," "0,1" bitfld.long 0x0 28. "SEC2BB28," "0,1" newline bitfld.long 0x0 27. "SEC2BB27," "0,1" bitfld.long 0x0 26. "SEC2BB26," "0,1" newline bitfld.long 0x0 25. "SEC2BB25," "0,1" bitfld.long 0x0 24. "SEC2BB24," "0,1" newline bitfld.long 0x0 23. "SEC2BB23," "0,1" bitfld.long 0x0 22. "SEC2BB22," "0,1" newline bitfld.long 0x0 21. "SEC2BB21," "0,1" bitfld.long 0x0 20. "SEC2BB20," "0,1" newline bitfld.long 0x0 19. "SEC2BB19," "0,1" bitfld.long 0x0 18. "SEC2BB18," "0,1" newline bitfld.long 0x0 17. "SEC2BB17," "0,1" bitfld.long 0x0 16. "SEC2BB16," "0,1" newline bitfld.long 0x0 15. "SEC2BB15," "0,1" bitfld.long 0x0 14. "SEC2BB14," "0,1" newline bitfld.long 0x0 13. "SEC2BB13," "0,1" bitfld.long 0x0 12. "SEC2BB12," "0,1" newline bitfld.long 0x0 11. "SEC2BB11," "0,1" bitfld.long 0x0 10. "SEC2BB10," "0,1" newline bitfld.long 0x0 9. "SEC2BB9," "0,1" bitfld.long 0x0 8. "SEC2BB8," "0,1" newline bitfld.long 0x0 7. "SEC2BB7," "0,1" bitfld.long 0x0 6. "SEC2BB6," "0,1" newline bitfld.long 0x0 5. "SEC2BB5," "0,1" bitfld.long 0x0 4. "SEC2BB4," "0,1" newline bitfld.long 0x0 3. "SEC2BB3," "0,1" bitfld.long 0x0 2. "SEC2BB2," "0,1" newline bitfld.long 0x0 1. "SEC2BB1," "0,1" bitfld.long 0x0 0. "SEC2BB0," "0,1" line.long 0x4 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x4 31. "SEC2BB31," "0,1" bitfld.long 0x4 30. "SEC2BB30," "0,1" newline bitfld.long 0x4 29. "SEC2BB29," "0,1" bitfld.long 0x4 28. "SEC2BB28," "0,1" newline bitfld.long 0x4 27. "SEC2BB27," "0,1" bitfld.long 0x4 26. "SEC2BB26," "0,1" newline bitfld.long 0x4 25. "SEC2BB25," "0,1" bitfld.long 0x4 24. "SEC2BB24," "0,1" newline bitfld.long 0x4 23. "SEC2BB23," "0,1" bitfld.long 0x4 22. "SEC2BB22," "0,1" newline bitfld.long 0x4 21. "SEC2BB21," "0,1" bitfld.long 0x4 20. "SEC2BB20," "0,1" newline bitfld.long 0x4 19. "SEC2BB19," "0,1" bitfld.long 0x4 18. "SEC2BB18," "0,1" newline bitfld.long 0x4 17. "SEC2BB17," "0,1" bitfld.long 0x4 16. "SEC2BB16," "0,1" newline bitfld.long 0x4 15. "SEC2BB15," "0,1" bitfld.long 0x4 14. "SEC2BB14," "0,1" newline bitfld.long 0x4 13. "SEC2BB13," "0,1" bitfld.long 0x4 12. "SEC2BB12," "0,1" newline bitfld.long 0x4 11. "SEC2BB11," "0,1" bitfld.long 0x4 10. "SEC2BB10," "0,1" newline bitfld.long 0x4 9. "SEC2BB9," "0,1" bitfld.long 0x4 8. "SEC2BB8," "0,1" newline bitfld.long 0x4 7. "SEC2BB7," "0,1" bitfld.long 0x4 6. "SEC2BB6," "0,1" newline bitfld.long 0x4 5. "SEC2BB5," "0,1" bitfld.long 0x4 4. "SEC2BB4," "0,1" newline bitfld.long 0x4 3. "SEC2BB3," "0,1" bitfld.long 0x4 2. "SEC2BB2," "0,1" newline bitfld.long 0x4 1. "SEC2BB1," "0,1" bitfld.long 0x4 0. "SEC2BB0," "0,1" line.long 0x8 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x8 31. "SEC2BB31," "0,1" bitfld.long 0x8 30. "SEC2BB30," "0,1" newline bitfld.long 0x8 29. "SEC2BB29," "0,1" bitfld.long 0x8 28. "SEC2BB28," "0,1" newline bitfld.long 0x8 27. "SEC2BB27," "0,1" bitfld.long 0x8 26. "SEC2BB26," "0,1" newline bitfld.long 0x8 25. "SEC2BB25," "0,1" bitfld.long 0x8 24. "SEC2BB24," "0,1" newline bitfld.long 0x8 23. "SEC2BB23," "0,1" bitfld.long 0x8 22. "SEC2BB22," "0,1" newline bitfld.long 0x8 21. "SEC2BB21," "0,1" bitfld.long 0x8 20. "SEC2BB20," "0,1" newline bitfld.long 0x8 19. "SEC2BB19," "0,1" bitfld.long 0x8 18. "SEC2BB18," "0,1" newline bitfld.long 0x8 17. "SEC2BB17," "0,1" bitfld.long 0x8 16. "SEC2BB16," "0,1" newline bitfld.long 0x8 15. "SEC2BB15," "0,1" bitfld.long 0x8 14. "SEC2BB14," "0,1" newline bitfld.long 0x8 13. "SEC2BB13," "0,1" bitfld.long 0x8 12. "SEC2BB12," "0,1" newline bitfld.long 0x8 11. "SEC2BB11," "0,1" bitfld.long 0x8 10. "SEC2BB10," "0,1" newline bitfld.long 0x8 9. "SEC2BB9," "0,1" bitfld.long 0x8 8. "SEC2BB8," "0,1" newline bitfld.long 0x8 7. "SEC2BB7," "0,1" bitfld.long 0x8 6. "SEC2BB6," "0,1" newline bitfld.long 0x8 5. "SEC2BB5," "0,1" bitfld.long 0x8 4. "SEC2BB4," "0,1" newline bitfld.long 0x8 3. "SEC2BB3," "0,1" bitfld.long 0x8 2. "SEC2BB2," "0,1" newline bitfld.long 0x8 1. "SEC2BB1," "0,1" bitfld.long 0x8 0. "SEC2BB0," "0,1" line.long 0xC "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0xC 31. "SEC2BB31," "0,1" bitfld.long 0xC 30. "SEC2BB30," "0,1" newline bitfld.long 0xC 29. "SEC2BB29," "0,1" bitfld.long 0xC 28. "SEC2BB28," "0,1" newline bitfld.long 0xC 27. "SEC2BB27," "0,1" bitfld.long 0xC 26. "SEC2BB26," "0,1" newline bitfld.long 0xC 25. "SEC2BB25," "0,1" bitfld.long 0xC 24. "SEC2BB24," "0,1" newline bitfld.long 0xC 23. "SEC2BB23," "0,1" bitfld.long 0xC 22. "SEC2BB22," "0,1" newline bitfld.long 0xC 21. "SEC2BB21," "0,1" bitfld.long 0xC 20. "SEC2BB20," "0,1" newline bitfld.long 0xC 19. "SEC2BB19," "0,1" bitfld.long 0xC 18. "SEC2BB18," "0,1" newline bitfld.long 0xC 17. "SEC2BB17," "0,1" bitfld.long 0xC 16. "SEC2BB16," "0,1" newline bitfld.long 0xC 15. "SEC2BB15," "0,1" bitfld.long 0xC 14. "SEC2BB14," "0,1" newline bitfld.long 0xC 13. "SEC2BB13," "0,1" bitfld.long 0xC 12. "SEC2BB12," "0,1" newline bitfld.long 0xC 11. "SEC2BB11," "0,1" bitfld.long 0xC 10. "SEC2BB10," "0,1" newline bitfld.long 0xC 9. "SEC2BB9," "0,1" bitfld.long 0xC 8. "SEC2BB8," "0,1" newline bitfld.long 0xC 7. "SEC2BB7," "0,1" bitfld.long 0xC 6. "SEC2BB6," "0,1" newline bitfld.long 0xC 5. "SEC2BB5," "0,1" bitfld.long 0xC 4. "SEC2BB4," "0,1" newline bitfld.long 0xC 3. "SEC2BB3," "0,1" bitfld.long 0xC 2. "SEC2BB2," "0,1" newline bitfld.long 0xC 1. "SEC2BB1," "0,1" bitfld.long 0xC 0. "SEC2BB0," "0,1" group.long 0xE0++0xF line.long 0x0 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x0 31. "PRIV1BB31," "0,1" bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x4 31. "PRIV1BB31," "0,1" bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x8 31. "PRIV1BB31," "0,1" bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0xC 31. "PRIV1BB31," "0,1" bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" bitfld.long 0xC 0. "PRIV1BB0," "0,1" group.long 0x100++0xF line.long 0x0 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x0 31. "PRIV2BB31," "0,1" bitfld.long 0x0 30. "PRIV2BB30," "0,1" newline bitfld.long 0x0 29. "PRIV2BB29," "0,1" bitfld.long 0x0 28. "PRIV2BB28," "0,1" newline bitfld.long 0x0 27. "PRIV2BB27," "0,1" bitfld.long 0x0 26. "PRIV2BB26," "0,1" newline bitfld.long 0x0 25. "PRIV2BB25," "0,1" bitfld.long 0x0 24. "PRIV2BB24," "0,1" newline bitfld.long 0x0 23. "PRIV2BB23," "0,1" bitfld.long 0x0 22. "PRIV2BB22," "0,1" newline bitfld.long 0x0 21. "PRIV2BB21," "0,1" bitfld.long 0x0 20. "PRIV2BB20," "0,1" newline bitfld.long 0x0 19. "PRIV2BB19," "0,1" bitfld.long 0x0 18. "PRIV2BB18," "0,1" newline bitfld.long 0x0 17. "PRIV2BB17," "0,1" bitfld.long 0x0 16. "PRIV2BB16," "0,1" newline bitfld.long 0x0 15. "PRIV2BB15," "0,1" bitfld.long 0x0 14. "PRIV2BB14," "0,1" newline bitfld.long 0x0 13. "PRIV2BB13," "0,1" bitfld.long 0x0 12. "PRIV2BB12," "0,1" newline bitfld.long 0x0 11. "PRIV2BB11," "0,1" bitfld.long 0x0 10. "PRIV2BB10," "0,1" newline bitfld.long 0x0 9. "PRIV2BB9," "0,1" bitfld.long 0x0 8. "PRIV2BB8," "0,1" newline bitfld.long 0x0 7. "PRIV2BB7," "0,1" bitfld.long 0x0 6. "PRIV2BB6," "0,1" newline bitfld.long 0x0 5. "PRIV2BB5," "0,1" bitfld.long 0x0 4. "PRIV2BB4," "0,1" newline bitfld.long 0x0 3. "PRIV2BB3," "0,1" bitfld.long 0x0 2. "PRIV2BB2," "0,1" newline bitfld.long 0x0 1. "PRIV2BB1," "0,1" bitfld.long 0x0 0. "PRIV2BB0," "0,1" line.long 0x4 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x4 31. "PRIV2BB31," "0,1" bitfld.long 0x4 30. "PRIV2BB30," "0,1" newline bitfld.long 0x4 29. "PRIV2BB29," "0,1" bitfld.long 0x4 28. "PRIV2BB28," "0,1" newline bitfld.long 0x4 27. "PRIV2BB27," "0,1" bitfld.long 0x4 26. "PRIV2BB26," "0,1" newline bitfld.long 0x4 25. "PRIV2BB25," "0,1" bitfld.long 0x4 24. "PRIV2BB24," "0,1" newline bitfld.long 0x4 23. "PRIV2BB23," "0,1" bitfld.long 0x4 22. "PRIV2BB22," "0,1" newline bitfld.long 0x4 21. "PRIV2BB21," "0,1" bitfld.long 0x4 20. "PRIV2BB20," "0,1" newline bitfld.long 0x4 19. "PRIV2BB19," "0,1" bitfld.long 0x4 18. "PRIV2BB18," "0,1" newline bitfld.long 0x4 17. "PRIV2BB17," "0,1" bitfld.long 0x4 16. "PRIV2BB16," "0,1" newline bitfld.long 0x4 15. "PRIV2BB15," "0,1" bitfld.long 0x4 14. "PRIV2BB14," "0,1" newline bitfld.long 0x4 13. "PRIV2BB13," "0,1" bitfld.long 0x4 12. "PRIV2BB12," "0,1" newline bitfld.long 0x4 11. "PRIV2BB11," "0,1" bitfld.long 0x4 10. "PRIV2BB10," "0,1" newline bitfld.long 0x4 9. "PRIV2BB9," "0,1" bitfld.long 0x4 8. "PRIV2BB8," "0,1" newline bitfld.long 0x4 7. "PRIV2BB7," "0,1" bitfld.long 0x4 6. "PRIV2BB6," "0,1" newline bitfld.long 0x4 5. "PRIV2BB5," "0,1" bitfld.long 0x4 4. "PRIV2BB4," "0,1" newline bitfld.long 0x4 3. "PRIV2BB3," "0,1" bitfld.long 0x4 2. "PRIV2BB2," "0,1" newline bitfld.long 0x4 1. "PRIV2BB1," "0,1" bitfld.long 0x4 0. "PRIV2BB0," "0,1" line.long 0x8 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x8 31. "PRIV2BB31," "0,1" bitfld.long 0x8 30. "PRIV2BB30," "0,1" newline bitfld.long 0x8 29. "PRIV2BB29," "0,1" bitfld.long 0x8 28. "PRIV2BB28," "0,1" newline bitfld.long 0x8 27. "PRIV2BB27," "0,1" bitfld.long 0x8 26. "PRIV2BB26," "0,1" newline bitfld.long 0x8 25. "PRIV2BB25," "0,1" bitfld.long 0x8 24. "PRIV2BB24," "0,1" newline bitfld.long 0x8 23. "PRIV2BB23," "0,1" bitfld.long 0x8 22. "PRIV2BB22," "0,1" newline bitfld.long 0x8 21. "PRIV2BB21," "0,1" bitfld.long 0x8 20. "PRIV2BB20," "0,1" newline bitfld.long 0x8 19. "PRIV2BB19," "0,1" bitfld.long 0x8 18. "PRIV2BB18," "0,1" newline bitfld.long 0x8 17. "PRIV2BB17," "0,1" bitfld.long 0x8 16. "PRIV2BB16," "0,1" newline bitfld.long 0x8 15. "PRIV2BB15," "0,1" bitfld.long 0x8 14. "PRIV2BB14," "0,1" newline bitfld.long 0x8 13. "PRIV2BB13," "0,1" bitfld.long 0x8 12. "PRIV2BB12," "0,1" newline bitfld.long 0x8 11. "PRIV2BB11," "0,1" bitfld.long 0x8 10. "PRIV2BB10," "0,1" newline bitfld.long 0x8 9. "PRIV2BB9," "0,1" bitfld.long 0x8 8. "PRIV2BB8," "0,1" newline bitfld.long 0x8 7. "PRIV2BB7," "0,1" bitfld.long 0x8 6. "PRIV2BB6," "0,1" newline bitfld.long 0x8 5. "PRIV2BB5," "0,1" bitfld.long 0x8 4. "PRIV2BB4," "0,1" newline bitfld.long 0x8 3. "PRIV2BB3," "0,1" bitfld.long 0x8 2. "PRIV2BB2," "0,1" newline bitfld.long 0x8 1. "PRIV2BB1," "0,1" bitfld.long 0x8 0. "PRIV2BB0," "0,1" line.long 0xC "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0xC 31. "PRIV2BB31," "0,1" bitfld.long 0xC 30. "PRIV2BB30," "0,1" newline bitfld.long 0xC 29. "PRIV2BB29," "0,1" bitfld.long 0xC 28. "PRIV2BB28," "0,1" newline bitfld.long 0xC 27. "PRIV2BB27," "0,1" bitfld.long 0xC 26. "PRIV2BB26," "0,1" newline bitfld.long 0xC 25. "PRIV2BB25," "0,1" bitfld.long 0xC 24. "PRIV2BB24," "0,1" newline bitfld.long 0xC 23. "PRIV2BB23," "0,1" bitfld.long 0xC 22. "PRIV2BB22," "0,1" newline bitfld.long 0xC 21. "PRIV2BB21," "0,1" bitfld.long 0xC 20. "PRIV2BB20," "0,1" newline bitfld.long 0xC 19. "PRIV2BB19," "0,1" bitfld.long 0xC 18. "PRIV2BB18," "0,1" newline bitfld.long 0xC 17. "PRIV2BB17," "0,1" bitfld.long 0xC 16. "PRIV2BB16," "0,1" newline bitfld.long 0xC 15. "PRIV2BB15," "0,1" bitfld.long 0xC 14. "PRIV2BB14," "0,1" newline bitfld.long 0xC 13. "PRIV2BB13," "0,1" bitfld.long 0xC 12. "PRIV2BB12," "0,1" newline bitfld.long 0xC 11. "PRIV2BB11," "0,1" bitfld.long 0xC 10. "PRIV2BB10," "0,1" newline bitfld.long 0xC 9. "PRIV2BB9," "0,1" bitfld.long 0xC 8. "PRIV2BB8," "0,1" newline bitfld.long 0xC 7. "PRIV2BB7," "0,1" bitfld.long 0xC 6. "PRIV2BB6," "0,1" newline bitfld.long 0xC 5. "PRIV2BB5," "0,1" bitfld.long 0xC 4. "PRIV2BB4," "0,1" newline bitfld.long 0xC 3. "PRIV2BB3," "0,1" bitfld.long 0xC 2. "PRIV2BB2," "0,1" newline bitfld.long 0xC 1. "PRIV2BB1," "0,1" bitfld.long 0xC 0. "PRIV2BB0," "0,1" endif group.long 0xA0++0xF line.long 0x0 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x0 31. "SEC2BB31," "0,1" newline bitfld.long 0x0 30. "SEC2BB30," "0,1" newline bitfld.long 0x0 29. "SEC2BB29," "0,1" newline bitfld.long 0x0 28. "SEC2BB28," "0,1" newline bitfld.long 0x0 27. "SEC2BB27," "0,1" newline bitfld.long 0x0 26. "SEC2BB26," "0,1" newline bitfld.long 0x0 25. "SEC2BB25," "0,1" newline bitfld.long 0x0 24. "SEC2BB24," "0,1" newline bitfld.long 0x0 23. "SEC2BB23," "0,1" newline bitfld.long 0x0 22. "SEC2BB22," "0,1" newline bitfld.long 0x0 21. "SEC2BB21," "0,1" newline bitfld.long 0x0 20. "SEC2BB20," "0,1" newline bitfld.long 0x0 19. "SEC2BB19," "0,1" newline bitfld.long 0x0 18. "SEC2BB18," "0,1" newline bitfld.long 0x0 17. "SEC2BB17," "0,1" newline bitfld.long 0x0 16. "SEC2BB16," "0,1" newline bitfld.long 0x0 15. "SEC2BB15," "0,1" newline bitfld.long 0x0 14. "SEC2BB14," "0,1" newline bitfld.long 0x0 13. "SEC2BB13," "0,1" newline bitfld.long 0x0 12. "SEC2BB12," "0,1" newline bitfld.long 0x0 11. "SEC2BB11," "0,1" newline bitfld.long 0x0 10. "SEC2BB10," "0,1" newline bitfld.long 0x0 9. "SEC2BB9," "0,1" newline bitfld.long 0x0 8. "SEC2BB8," "0,1" newline bitfld.long 0x0 7. "SEC2BB7," "0,1" newline bitfld.long 0x0 6. "SEC2BB6," "0,1" newline bitfld.long 0x0 5. "SEC2BB5," "0,1" newline bitfld.long 0x0 4. "SEC2BB4," "0,1" newline bitfld.long 0x0 3. "SEC2BB3," "0,1" newline bitfld.long 0x0 2. "SEC2BB2," "0,1" newline bitfld.long 0x0 1. "SEC2BB1," "0,1" newline bitfld.long 0x0 0. "SEC2BB0," "0,1" line.long 0x4 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x4 31. "SEC2BB31," "0,1" newline bitfld.long 0x4 30. "SEC2BB30," "0,1" newline bitfld.long 0x4 29. "SEC2BB29," "0,1" newline bitfld.long 0x4 28. "SEC2BB28," "0,1" newline bitfld.long 0x4 27. "SEC2BB27," "0,1" newline bitfld.long 0x4 26. "SEC2BB26," "0,1" newline bitfld.long 0x4 25. "SEC2BB25," "0,1" newline bitfld.long 0x4 24. "SEC2BB24," "0,1" newline bitfld.long 0x4 23. "SEC2BB23," "0,1" newline bitfld.long 0x4 22. "SEC2BB22," "0,1" newline bitfld.long 0x4 21. "SEC2BB21," "0,1" newline bitfld.long 0x4 20. "SEC2BB20," "0,1" newline bitfld.long 0x4 19. "SEC2BB19," "0,1" newline bitfld.long 0x4 18. "SEC2BB18," "0,1" newline bitfld.long 0x4 17. "SEC2BB17," "0,1" newline bitfld.long 0x4 16. "SEC2BB16," "0,1" newline bitfld.long 0x4 15. "SEC2BB15," "0,1" newline bitfld.long 0x4 14. "SEC2BB14," "0,1" newline bitfld.long 0x4 13. "SEC2BB13," "0,1" newline bitfld.long 0x4 12. "SEC2BB12," "0,1" newline bitfld.long 0x4 11. "SEC2BB11," "0,1" newline bitfld.long 0x4 10. "SEC2BB10," "0,1" newline bitfld.long 0x4 9. "SEC2BB9," "0,1" newline bitfld.long 0x4 8. "SEC2BB8," "0,1" newline bitfld.long 0x4 7. "SEC2BB7," "0,1" newline bitfld.long 0x4 6. "SEC2BB6," "0,1" newline bitfld.long 0x4 5. "SEC2BB5," "0,1" newline bitfld.long 0x4 4. "SEC2BB4," "0,1" newline bitfld.long 0x4 3. "SEC2BB3," "0,1" newline bitfld.long 0x4 2. "SEC2BB2," "0,1" newline bitfld.long 0x4 1. "SEC2BB1," "0,1" newline bitfld.long 0x4 0. "SEC2BB0," "0,1" line.long 0x8 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x8 31. "SEC2BB31," "0,1" newline bitfld.long 0x8 30. "SEC2BB30," "0,1" newline bitfld.long 0x8 29. "SEC2BB29," "0,1" newline bitfld.long 0x8 28. "SEC2BB28," "0,1" newline bitfld.long 0x8 27. "SEC2BB27," "0,1" newline bitfld.long 0x8 26. "SEC2BB26," "0,1" newline bitfld.long 0x8 25. "SEC2BB25," "0,1" newline bitfld.long 0x8 24. "SEC2BB24," "0,1" newline bitfld.long 0x8 23. "SEC2BB23," "0,1" newline bitfld.long 0x8 22. "SEC2BB22," "0,1" newline bitfld.long 0x8 21. "SEC2BB21," "0,1" newline bitfld.long 0x8 20. "SEC2BB20," "0,1" newline bitfld.long 0x8 19. "SEC2BB19," "0,1" newline bitfld.long 0x8 18. "SEC2BB18," "0,1" newline bitfld.long 0x8 17. "SEC2BB17," "0,1" newline bitfld.long 0x8 16. "SEC2BB16," "0,1" newline bitfld.long 0x8 15. "SEC2BB15," "0,1" newline bitfld.long 0x8 14. "SEC2BB14," "0,1" newline bitfld.long 0x8 13. "SEC2BB13," "0,1" newline bitfld.long 0x8 12. "SEC2BB12," "0,1" newline bitfld.long 0x8 11. "SEC2BB11," "0,1" newline bitfld.long 0x8 10. "SEC2BB10," "0,1" newline bitfld.long 0x8 9. "SEC2BB9," "0,1" newline bitfld.long 0x8 8. "SEC2BB8," "0,1" newline bitfld.long 0x8 7. "SEC2BB7," "0,1" newline bitfld.long 0x8 6. "SEC2BB6," "0,1" newline bitfld.long 0x8 5. "SEC2BB5," "0,1" newline bitfld.long 0x8 4. "SEC2BB4," "0,1" newline bitfld.long 0x8 3. "SEC2BB3," "0,1" newline bitfld.long 0x8 2. "SEC2BB2," "0,1" newline bitfld.long 0x8 1. "SEC2BB1," "0,1" newline bitfld.long 0x8 0. "SEC2BB0," "0,1" line.long 0xC "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0xC 31. "SEC2BB31," "0,1" newline bitfld.long 0xC 30. "SEC2BB30," "0,1" newline bitfld.long 0xC 29. "SEC2BB29," "0,1" newline bitfld.long 0xC 28. "SEC2BB28," "0,1" newline bitfld.long 0xC 27. "SEC2BB27," "0,1" newline bitfld.long 0xC 26. "SEC2BB26," "0,1" newline bitfld.long 0xC 25. "SEC2BB25," "0,1" newline bitfld.long 0xC 24. "SEC2BB24," "0,1" newline bitfld.long 0xC 23. "SEC2BB23," "0,1" newline bitfld.long 0xC 22. "SEC2BB22," "0,1" newline bitfld.long 0xC 21. "SEC2BB21," "0,1" newline bitfld.long 0xC 20. "SEC2BB20," "0,1" newline bitfld.long 0xC 19. "SEC2BB19," "0,1" newline bitfld.long 0xC 18. "SEC2BB18," "0,1" newline bitfld.long 0xC 17. "SEC2BB17," "0,1" newline bitfld.long 0xC 16. "SEC2BB16," "0,1" newline bitfld.long 0xC 15. "SEC2BB15," "0,1" newline bitfld.long 0xC 14. "SEC2BB14," "0,1" newline bitfld.long 0xC 13. "SEC2BB13," "0,1" newline bitfld.long 0xC 12. "SEC2BB12," "0,1" newline bitfld.long 0xC 11. "SEC2BB11," "0,1" newline bitfld.long 0xC 10. "SEC2BB10," "0,1" newline bitfld.long 0xC 9. "SEC2BB9," "0,1" newline bitfld.long 0xC 8. "SEC2BB8," "0,1" newline bitfld.long 0xC 7. "SEC2BB7," "0,1" newline bitfld.long 0xC 6. "SEC2BB6," "0,1" newline bitfld.long 0xC 5. "SEC2BB5," "0,1" newline bitfld.long 0xC 4. "SEC2BB4," "0,1" newline bitfld.long 0xC 3. "SEC2BB3," "0,1" newline bitfld.long 0xC 2. "SEC2BB2," "0,1" newline bitfld.long 0xC 1. "SEC2BB1," "0,1" newline bitfld.long 0xC 0. "SEC2BB0," "0,1" group.long 0xC0++0x7 line.long 0x0 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x0 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x0 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x4 "FLASH_PRIVCFGR,FLASH privilege configuration register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x4 0. "SPRIV,Privileged protection for secure registers" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 1. "NSPRIV,Privileged protection for non-secure registers" "0: Non-secure Flash registers can be read and..,1: Non-secure Flash registers can be read and.." endif group.long 0xD0++0xF line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" group.long 0xF0++0xF line.long 0x0 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x0 31. "PRIV2BB31," "0,1" newline bitfld.long 0x0 30. "PRIV2BB30," "0,1" newline bitfld.long 0x0 29. "PRIV2BB29," "0,1" newline bitfld.long 0x0 28. "PRIV2BB28," "0,1" newline bitfld.long 0x0 27. "PRIV2BB27," "0,1" newline bitfld.long 0x0 26. "PRIV2BB26," "0,1" newline bitfld.long 0x0 25. "PRIV2BB25," "0,1" newline bitfld.long 0x0 24. "PRIV2BB24," "0,1" newline bitfld.long 0x0 23. "PRIV2BB23," "0,1" newline bitfld.long 0x0 22. "PRIV2BB22," "0,1" newline bitfld.long 0x0 21. "PRIV2BB21," "0,1" newline bitfld.long 0x0 20. "PRIV2BB20," "0,1" newline bitfld.long 0x0 19. "PRIV2BB19," "0,1" newline bitfld.long 0x0 18. "PRIV2BB18," "0,1" newline bitfld.long 0x0 17. "PRIV2BB17," "0,1" newline bitfld.long 0x0 16. "PRIV2BB16," "0,1" newline bitfld.long 0x0 15. "PRIV2BB15," "0,1" newline bitfld.long 0x0 14. "PRIV2BB14," "0,1" newline bitfld.long 0x0 13. "PRIV2BB13," "0,1" newline bitfld.long 0x0 12. "PRIV2BB12," "0,1" newline bitfld.long 0x0 11. "PRIV2BB11," "0,1" newline bitfld.long 0x0 10. "PRIV2BB10," "0,1" newline bitfld.long 0x0 9. "PRIV2BB9," "0,1" newline bitfld.long 0x0 8. "PRIV2BB8," "0,1" newline bitfld.long 0x0 7. "PRIV2BB7," "0,1" newline bitfld.long 0x0 6. "PRIV2BB6," "0,1" newline bitfld.long 0x0 5. "PRIV2BB5," "0,1" newline bitfld.long 0x0 4. "PRIV2BB4," "0,1" newline bitfld.long 0x0 3. "PRIV2BB3," "0,1" newline bitfld.long 0x0 2. "PRIV2BB2," "0,1" newline bitfld.long 0x0 1. "PRIV2BB1," "0,1" newline bitfld.long 0x0 0. "PRIV2BB0," "0,1" line.long 0x4 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x4 31. "PRIV2BB31," "0,1" newline bitfld.long 0x4 30. "PRIV2BB30," "0,1" newline bitfld.long 0x4 29. "PRIV2BB29," "0,1" newline bitfld.long 0x4 28. "PRIV2BB28," "0,1" newline bitfld.long 0x4 27. "PRIV2BB27," "0,1" newline bitfld.long 0x4 26. "PRIV2BB26," "0,1" newline bitfld.long 0x4 25. "PRIV2BB25," "0,1" newline bitfld.long 0x4 24. "PRIV2BB24," "0,1" newline bitfld.long 0x4 23. "PRIV2BB23," "0,1" newline bitfld.long 0x4 22. "PRIV2BB22," "0,1" newline bitfld.long 0x4 21. "PRIV2BB21," "0,1" newline bitfld.long 0x4 20. "PRIV2BB20," "0,1" newline bitfld.long 0x4 19. "PRIV2BB19," "0,1" newline bitfld.long 0x4 18. "PRIV2BB18," "0,1" newline bitfld.long 0x4 17. "PRIV2BB17," "0,1" newline bitfld.long 0x4 16. "PRIV2BB16," "0,1" newline bitfld.long 0x4 15. "PRIV2BB15," "0,1" newline bitfld.long 0x4 14. "PRIV2BB14," "0,1" newline bitfld.long 0x4 13. "PRIV2BB13," "0,1" newline bitfld.long 0x4 12. "PRIV2BB12," "0,1" newline bitfld.long 0x4 11. "PRIV2BB11," "0,1" newline bitfld.long 0x4 10. "PRIV2BB10," "0,1" newline bitfld.long 0x4 9. "PRIV2BB9," "0,1" newline bitfld.long 0x4 8. "PRIV2BB8," "0,1" newline bitfld.long 0x4 7. "PRIV2BB7," "0,1" newline bitfld.long 0x4 6. "PRIV2BB6," "0,1" newline bitfld.long 0x4 5. "PRIV2BB5," "0,1" newline bitfld.long 0x4 4. "PRIV2BB4," "0,1" newline bitfld.long 0x4 3. "PRIV2BB3," "0,1" newline bitfld.long 0x4 2. "PRIV2BB2," "0,1" newline bitfld.long 0x4 1. "PRIV2BB1," "0,1" newline bitfld.long 0x4 0. "PRIV2BB0," "0,1" line.long 0x8 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x8 31. "PRIV2BB31," "0,1" newline bitfld.long 0x8 30. "PRIV2BB30," "0,1" newline bitfld.long 0x8 29. "PRIV2BB29," "0,1" newline bitfld.long 0x8 28. "PRIV2BB28," "0,1" newline bitfld.long 0x8 27. "PRIV2BB27," "0,1" newline bitfld.long 0x8 26. "PRIV2BB26," "0,1" newline bitfld.long 0x8 25. "PRIV2BB25," "0,1" newline bitfld.long 0x8 24. "PRIV2BB24," "0,1" newline bitfld.long 0x8 23. "PRIV2BB23," "0,1" newline bitfld.long 0x8 22. "PRIV2BB22," "0,1" newline bitfld.long 0x8 21. "PRIV2BB21," "0,1" newline bitfld.long 0x8 20. "PRIV2BB20," "0,1" newline bitfld.long 0x8 19. "PRIV2BB19," "0,1" newline bitfld.long 0x8 18. "PRIV2BB18," "0,1" newline bitfld.long 0x8 17. "PRIV2BB17," "0,1" newline bitfld.long 0x8 16. "PRIV2BB16," "0,1" newline bitfld.long 0x8 15. "PRIV2BB15," "0,1" newline bitfld.long 0x8 14. "PRIV2BB14," "0,1" newline bitfld.long 0x8 13. "PRIV2BB13," "0,1" newline bitfld.long 0x8 12. "PRIV2BB12," "0,1" newline bitfld.long 0x8 11. "PRIV2BB11," "0,1" newline bitfld.long 0x8 10. "PRIV2BB10," "0,1" newline bitfld.long 0x8 9. "PRIV2BB9," "0,1" newline bitfld.long 0x8 8. "PRIV2BB8," "0,1" newline bitfld.long 0x8 7. "PRIV2BB7," "0,1" newline bitfld.long 0x8 6. "PRIV2BB6," "0,1" newline bitfld.long 0x8 5. "PRIV2BB5," "0,1" newline bitfld.long 0x8 4. "PRIV2BB4," "0,1" newline bitfld.long 0x8 3. "PRIV2BB3," "0,1" newline bitfld.long 0x8 2. "PRIV2BB2," "0,1" newline bitfld.long 0x8 1. "PRIV2BB1," "0,1" newline bitfld.long 0x8 0. "PRIV2BB0," "0,1" line.long 0xC "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0xC 31. "PRIV2BB31," "0,1" newline bitfld.long 0xC 30. "PRIV2BB30," "0,1" newline bitfld.long 0xC 29. "PRIV2BB29," "0,1" newline bitfld.long 0xC 28. "PRIV2BB28," "0,1" newline bitfld.long 0xC 27. "PRIV2BB27," "0,1" newline bitfld.long 0xC 26. "PRIV2BB26," "0,1" newline bitfld.long 0xC 25. "PRIV2BB25," "0,1" newline bitfld.long 0xC 24. "PRIV2BB24," "0,1" newline bitfld.long 0xC 23. "PRIV2BB23," "0,1" newline bitfld.long 0xC 22. "PRIV2BB22," "0,1" newline bitfld.long 0xC 21. "PRIV2BB21," "0,1" newline bitfld.long 0xC 20. "PRIV2BB20," "0,1" newline bitfld.long 0xC 19. "PRIV2BB19," "0,1" newline bitfld.long 0xC 18. "PRIV2BB18," "0,1" newline bitfld.long 0xC 17. "PRIV2BB17," "0,1" newline bitfld.long 0xC 16. "PRIV2BB16," "0,1" newline bitfld.long 0xC 15. "PRIV2BB15," "0,1" newline bitfld.long 0xC 14. "PRIV2BB14," "0,1" newline bitfld.long 0xC 13. "PRIV2BB13," "0,1" newline bitfld.long 0xC 12. "PRIV2BB12," "0,1" newline bitfld.long 0xC 11. "PRIV2BB11," "0,1" newline bitfld.long 0xC 10. "PRIV2BB10," "0,1" newline bitfld.long 0xC 9. "PRIV2BB9," "0,1" newline bitfld.long 0xC 8. "PRIV2BB8," "0,1" newline bitfld.long 0xC 7. "PRIV2BB7," "0,1" newline bitfld.long 0xC 6. "PRIV2BB6," "0,1" newline bitfld.long 0xC 5. "PRIV2BB5," "0,1" newline bitfld.long 0xC 4. "PRIV2BB4," "0,1" newline bitfld.long 0xC 3. "PRIV2BB3," "0,1" newline bitfld.long 0xC 2. "PRIV2BB2," "0,1" newline bitfld.long 0xC 1. "PRIV2BB1," "0,1" newline bitfld.long 0xC 0. "PRIV2BB0," "0,1" sif (cpuis("STM32U575*")) wgroup.long 0x8++0x3 line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" endif sif (cpuis("STM32U575*")) wgroup.long 0xC++0x3 line.long 0x0 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x0 0.--31. 1. "SECKEY,Flash memory secure key" endif sif (cpuis("STM32U575*")) wgroup.long 0x10++0x3 line.long 0x0 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEY,Option byte key" endif sif (cpuis("STM32U575*")) wgroup.long 0x18++0x3 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" endif sif (cpuis("STM32U575*")) wgroup.long 0x1C++0x3 line.long 0x0 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY2,Bank 2 power-down key" endif sif (cpuis("STM32U575*")) rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" endif sif (cpuis("STM32U575*")) wgroup.long 0x70++0x3 line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" endif sif (cpuis("STM32U575*")) wgroup.long 0x74++0x3 line.long 0x0 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" endif sif (cpuis("STM32U575*")) wgroup.long 0x78++0x3 line.long 0x0 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x0 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" endif sif (cpuis("STM32U575*")) wgroup.long 0x7C++0x3 line.long 0x0 "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0x0 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_FLASH" base ad:0x50022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline endif bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x8 3.--9. 1. "PNB,Non-secure page number selection" newline endif bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline endif sif (cpuis("STM32U575*")) bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0,1" newline endif bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline sif (cpuis("STM32U575*")) hexmask.long.byte 0xC 3.--9. 1. "PNB,Secure page number selection" newline endif bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" newline endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x10 0.--19. 1. "ADDR_ECC,ECC fail address" endif rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" newline endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x0 0.--19. 1. "ADDR_OP,Interrupted operation address" endif group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline sif (cpuis("STM32U575*")) bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline endif bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM4 and SRAM5 erased when a system reset..,1: SRAM1 SRAM4 and SRAM5 not erased when a system.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x10 16.--22. 1. "SECWM1_PEND,End page of first secure area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x10 0.--6. 1. "SECWM1_PSTRT,Start page of first secure area" endif line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x14 16.--22. 1. "HDP1_PEND,End page of first hide protection area" endif line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x18 16.--22. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x18 0.--6. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" endif line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x1C 16.--22. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x1C 0.--6. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" endif line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x20 16.--22. 1. "SECWM2_PEND,End page of second secure area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x20 0.--6. 1. "SECWM2_PSTRT,Start page of second secure area" endif line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x24 16.--22. 1. "HDP2_PEND,End page of hide protection second area" endif line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x28 16.--22. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x28 0.--6. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" endif line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x2C 16.--22. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x2C 0.--6. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" endif wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0xF line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x90++0xF line.long 0x0 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x0 31. "SEC1BB31," "0,1" bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x4 31. "SEC1BB31," "0,1" bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x8 31. "SEC1BB31," "0,1" bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0xC 31. "SEC1BB31," "0,1" bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" bitfld.long 0xC 0. "SEC1BB0," "0,1" group.long 0xB0++0xF line.long 0x0 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x0 31. "SEC2BB31," "0,1" bitfld.long 0x0 30. "SEC2BB30," "0,1" newline bitfld.long 0x0 29. "SEC2BB29," "0,1" bitfld.long 0x0 28. "SEC2BB28," "0,1" newline bitfld.long 0x0 27. "SEC2BB27," "0,1" bitfld.long 0x0 26. "SEC2BB26," "0,1" newline bitfld.long 0x0 25. "SEC2BB25," "0,1" bitfld.long 0x0 24. "SEC2BB24," "0,1" newline bitfld.long 0x0 23. "SEC2BB23," "0,1" bitfld.long 0x0 22. "SEC2BB22," "0,1" newline bitfld.long 0x0 21. "SEC2BB21," "0,1" bitfld.long 0x0 20. "SEC2BB20," "0,1" newline bitfld.long 0x0 19. "SEC2BB19," "0,1" bitfld.long 0x0 18. "SEC2BB18," "0,1" newline bitfld.long 0x0 17. "SEC2BB17," "0,1" bitfld.long 0x0 16. "SEC2BB16," "0,1" newline bitfld.long 0x0 15. "SEC2BB15," "0,1" bitfld.long 0x0 14. "SEC2BB14," "0,1" newline bitfld.long 0x0 13. "SEC2BB13," "0,1" bitfld.long 0x0 12. "SEC2BB12," "0,1" newline bitfld.long 0x0 11. "SEC2BB11," "0,1" bitfld.long 0x0 10. "SEC2BB10," "0,1" newline bitfld.long 0x0 9. "SEC2BB9," "0,1" bitfld.long 0x0 8. "SEC2BB8," "0,1" newline bitfld.long 0x0 7. "SEC2BB7," "0,1" bitfld.long 0x0 6. "SEC2BB6," "0,1" newline bitfld.long 0x0 5. "SEC2BB5," "0,1" bitfld.long 0x0 4. "SEC2BB4," "0,1" newline bitfld.long 0x0 3. "SEC2BB3," "0,1" bitfld.long 0x0 2. "SEC2BB2," "0,1" newline bitfld.long 0x0 1. "SEC2BB1," "0,1" bitfld.long 0x0 0. "SEC2BB0," "0,1" line.long 0x4 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x4 31. "SEC2BB31," "0,1" bitfld.long 0x4 30. "SEC2BB30," "0,1" newline bitfld.long 0x4 29. "SEC2BB29," "0,1" bitfld.long 0x4 28. "SEC2BB28," "0,1" newline bitfld.long 0x4 27. "SEC2BB27," "0,1" bitfld.long 0x4 26. "SEC2BB26," "0,1" newline bitfld.long 0x4 25. "SEC2BB25," "0,1" bitfld.long 0x4 24. "SEC2BB24," "0,1" newline bitfld.long 0x4 23. "SEC2BB23," "0,1" bitfld.long 0x4 22. "SEC2BB22," "0,1" newline bitfld.long 0x4 21. "SEC2BB21," "0,1" bitfld.long 0x4 20. "SEC2BB20," "0,1" newline bitfld.long 0x4 19. "SEC2BB19," "0,1" bitfld.long 0x4 18. "SEC2BB18," "0,1" newline bitfld.long 0x4 17. "SEC2BB17," "0,1" bitfld.long 0x4 16. "SEC2BB16," "0,1" newline bitfld.long 0x4 15. "SEC2BB15," "0,1" bitfld.long 0x4 14. "SEC2BB14," "0,1" newline bitfld.long 0x4 13. "SEC2BB13," "0,1" bitfld.long 0x4 12. "SEC2BB12," "0,1" newline bitfld.long 0x4 11. "SEC2BB11," "0,1" bitfld.long 0x4 10. "SEC2BB10," "0,1" newline bitfld.long 0x4 9. "SEC2BB9," "0,1" bitfld.long 0x4 8. "SEC2BB8," "0,1" newline bitfld.long 0x4 7. "SEC2BB7," "0,1" bitfld.long 0x4 6. "SEC2BB6," "0,1" newline bitfld.long 0x4 5. "SEC2BB5," "0,1" bitfld.long 0x4 4. "SEC2BB4," "0,1" newline bitfld.long 0x4 3. "SEC2BB3," "0,1" bitfld.long 0x4 2. "SEC2BB2," "0,1" newline bitfld.long 0x4 1. "SEC2BB1," "0,1" bitfld.long 0x4 0. "SEC2BB0," "0,1" line.long 0x8 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x8 31. "SEC2BB31," "0,1" bitfld.long 0x8 30. "SEC2BB30," "0,1" newline bitfld.long 0x8 29. "SEC2BB29," "0,1" bitfld.long 0x8 28. "SEC2BB28," "0,1" newline bitfld.long 0x8 27. "SEC2BB27," "0,1" bitfld.long 0x8 26. "SEC2BB26," "0,1" newline bitfld.long 0x8 25. "SEC2BB25," "0,1" bitfld.long 0x8 24. "SEC2BB24," "0,1" newline bitfld.long 0x8 23. "SEC2BB23," "0,1" bitfld.long 0x8 22. "SEC2BB22," "0,1" newline bitfld.long 0x8 21. "SEC2BB21," "0,1" bitfld.long 0x8 20. "SEC2BB20," "0,1" newline bitfld.long 0x8 19. "SEC2BB19," "0,1" bitfld.long 0x8 18. "SEC2BB18," "0,1" newline bitfld.long 0x8 17. "SEC2BB17," "0,1" bitfld.long 0x8 16. "SEC2BB16," "0,1" newline bitfld.long 0x8 15. "SEC2BB15," "0,1" bitfld.long 0x8 14. "SEC2BB14," "0,1" newline bitfld.long 0x8 13. "SEC2BB13," "0,1" bitfld.long 0x8 12. "SEC2BB12," "0,1" newline bitfld.long 0x8 11. "SEC2BB11," "0,1" bitfld.long 0x8 10. "SEC2BB10," "0,1" newline bitfld.long 0x8 9. "SEC2BB9," "0,1" bitfld.long 0x8 8. "SEC2BB8," "0,1" newline bitfld.long 0x8 7. "SEC2BB7," "0,1" bitfld.long 0x8 6. "SEC2BB6," "0,1" newline bitfld.long 0x8 5. "SEC2BB5," "0,1" bitfld.long 0x8 4. "SEC2BB4," "0,1" newline bitfld.long 0x8 3. "SEC2BB3," "0,1" bitfld.long 0x8 2. "SEC2BB2," "0,1" newline bitfld.long 0x8 1. "SEC2BB1," "0,1" bitfld.long 0x8 0. "SEC2BB0," "0,1" line.long 0xC "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0xC 31. "SEC2BB31," "0,1" bitfld.long 0xC 30. "SEC2BB30," "0,1" newline bitfld.long 0xC 29. "SEC2BB29," "0,1" bitfld.long 0xC 28. "SEC2BB28," "0,1" newline bitfld.long 0xC 27. "SEC2BB27," "0,1" bitfld.long 0xC 26. "SEC2BB26," "0,1" newline bitfld.long 0xC 25. "SEC2BB25," "0,1" bitfld.long 0xC 24. "SEC2BB24," "0,1" newline bitfld.long 0xC 23. "SEC2BB23," "0,1" bitfld.long 0xC 22. "SEC2BB22," "0,1" newline bitfld.long 0xC 21. "SEC2BB21," "0,1" bitfld.long 0xC 20. "SEC2BB20," "0,1" newline bitfld.long 0xC 19. "SEC2BB19," "0,1" bitfld.long 0xC 18. "SEC2BB18," "0,1" newline bitfld.long 0xC 17. "SEC2BB17," "0,1" bitfld.long 0xC 16. "SEC2BB16," "0,1" newline bitfld.long 0xC 15. "SEC2BB15," "0,1" bitfld.long 0xC 14. "SEC2BB14," "0,1" newline bitfld.long 0xC 13. "SEC2BB13," "0,1" bitfld.long 0xC 12. "SEC2BB12," "0,1" newline bitfld.long 0xC 11. "SEC2BB11," "0,1" bitfld.long 0xC 10. "SEC2BB10," "0,1" newline bitfld.long 0xC 9. "SEC2BB9," "0,1" bitfld.long 0xC 8. "SEC2BB8," "0,1" newline bitfld.long 0xC 7. "SEC2BB7," "0,1" bitfld.long 0xC 6. "SEC2BB6," "0,1" newline bitfld.long 0xC 5. "SEC2BB5," "0,1" bitfld.long 0xC 4. "SEC2BB4," "0,1" newline bitfld.long 0xC 3. "SEC2BB3," "0,1" bitfld.long 0xC 2. "SEC2BB2," "0,1" newline bitfld.long 0xC 1. "SEC2BB1," "0,1" bitfld.long 0xC 0. "SEC2BB0," "0,1" group.long 0xE0++0xF line.long 0x0 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x0 31. "PRIV1BB31," "0,1" bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x4 31. "PRIV1BB31," "0,1" bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x8 31. "PRIV1BB31," "0,1" bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0xC 31. "PRIV1BB31," "0,1" bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" bitfld.long 0xC 0. "PRIV1BB0," "0,1" group.long 0x100++0xF line.long 0x0 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x0 31. "PRIV2BB31," "0,1" bitfld.long 0x0 30. "PRIV2BB30," "0,1" newline bitfld.long 0x0 29. "PRIV2BB29," "0,1" bitfld.long 0x0 28. "PRIV2BB28," "0,1" newline bitfld.long 0x0 27. "PRIV2BB27," "0,1" bitfld.long 0x0 26. "PRIV2BB26," "0,1" newline bitfld.long 0x0 25. "PRIV2BB25," "0,1" bitfld.long 0x0 24. "PRIV2BB24," "0,1" newline bitfld.long 0x0 23. "PRIV2BB23," "0,1" bitfld.long 0x0 22. "PRIV2BB22," "0,1" newline bitfld.long 0x0 21. "PRIV2BB21," "0,1" bitfld.long 0x0 20. "PRIV2BB20," "0,1" newline bitfld.long 0x0 19. "PRIV2BB19," "0,1" bitfld.long 0x0 18. "PRIV2BB18," "0,1" newline bitfld.long 0x0 17. "PRIV2BB17," "0,1" bitfld.long 0x0 16. "PRIV2BB16," "0,1" newline bitfld.long 0x0 15. "PRIV2BB15," "0,1" bitfld.long 0x0 14. "PRIV2BB14," "0,1" newline bitfld.long 0x0 13. "PRIV2BB13," "0,1" bitfld.long 0x0 12. "PRIV2BB12," "0,1" newline bitfld.long 0x0 11. "PRIV2BB11," "0,1" bitfld.long 0x0 10. "PRIV2BB10," "0,1" newline bitfld.long 0x0 9. "PRIV2BB9," "0,1" bitfld.long 0x0 8. "PRIV2BB8," "0,1" newline bitfld.long 0x0 7. "PRIV2BB7," "0,1" bitfld.long 0x0 6. "PRIV2BB6," "0,1" newline bitfld.long 0x0 5. "PRIV2BB5," "0,1" bitfld.long 0x0 4. "PRIV2BB4," "0,1" newline bitfld.long 0x0 3. "PRIV2BB3," "0,1" bitfld.long 0x0 2. "PRIV2BB2," "0,1" newline bitfld.long 0x0 1. "PRIV2BB1," "0,1" bitfld.long 0x0 0. "PRIV2BB0," "0,1" line.long 0x4 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x4 31. "PRIV2BB31," "0,1" bitfld.long 0x4 30. "PRIV2BB30," "0,1" newline bitfld.long 0x4 29. "PRIV2BB29," "0,1" bitfld.long 0x4 28. "PRIV2BB28," "0,1" newline bitfld.long 0x4 27. "PRIV2BB27," "0,1" bitfld.long 0x4 26. "PRIV2BB26," "0,1" newline bitfld.long 0x4 25. "PRIV2BB25," "0,1" bitfld.long 0x4 24. "PRIV2BB24," "0,1" newline bitfld.long 0x4 23. "PRIV2BB23," "0,1" bitfld.long 0x4 22. "PRIV2BB22," "0,1" newline bitfld.long 0x4 21. "PRIV2BB21," "0,1" bitfld.long 0x4 20. "PRIV2BB20," "0,1" newline bitfld.long 0x4 19. "PRIV2BB19," "0,1" bitfld.long 0x4 18. "PRIV2BB18," "0,1" newline bitfld.long 0x4 17. "PRIV2BB17," "0,1" bitfld.long 0x4 16. "PRIV2BB16," "0,1" newline bitfld.long 0x4 15. "PRIV2BB15," "0,1" bitfld.long 0x4 14. "PRIV2BB14," "0,1" newline bitfld.long 0x4 13. "PRIV2BB13," "0,1" bitfld.long 0x4 12. "PRIV2BB12," "0,1" newline bitfld.long 0x4 11. "PRIV2BB11," "0,1" bitfld.long 0x4 10. "PRIV2BB10," "0,1" newline bitfld.long 0x4 9. "PRIV2BB9," "0,1" bitfld.long 0x4 8. "PRIV2BB8," "0,1" newline bitfld.long 0x4 7. "PRIV2BB7," "0,1" bitfld.long 0x4 6. "PRIV2BB6," "0,1" newline bitfld.long 0x4 5. "PRIV2BB5," "0,1" bitfld.long 0x4 4. "PRIV2BB4," "0,1" newline bitfld.long 0x4 3. "PRIV2BB3," "0,1" bitfld.long 0x4 2. "PRIV2BB2," "0,1" newline bitfld.long 0x4 1. "PRIV2BB1," "0,1" bitfld.long 0x4 0. "PRIV2BB0," "0,1" line.long 0x8 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x8 31. "PRIV2BB31," "0,1" bitfld.long 0x8 30. "PRIV2BB30," "0,1" newline bitfld.long 0x8 29. "PRIV2BB29," "0,1" bitfld.long 0x8 28. "PRIV2BB28," "0,1" newline bitfld.long 0x8 27. "PRIV2BB27," "0,1" bitfld.long 0x8 26. "PRIV2BB26," "0,1" newline bitfld.long 0x8 25. "PRIV2BB25," "0,1" bitfld.long 0x8 24. "PRIV2BB24," "0,1" newline bitfld.long 0x8 23. "PRIV2BB23," "0,1" bitfld.long 0x8 22. "PRIV2BB22," "0,1" newline bitfld.long 0x8 21. "PRIV2BB21," "0,1" bitfld.long 0x8 20. "PRIV2BB20," "0,1" newline bitfld.long 0x8 19. "PRIV2BB19," "0,1" bitfld.long 0x8 18. "PRIV2BB18," "0,1" newline bitfld.long 0x8 17. "PRIV2BB17," "0,1" bitfld.long 0x8 16. "PRIV2BB16," "0,1" newline bitfld.long 0x8 15. "PRIV2BB15," "0,1" bitfld.long 0x8 14. "PRIV2BB14," "0,1" newline bitfld.long 0x8 13. "PRIV2BB13," "0,1" bitfld.long 0x8 12. "PRIV2BB12," "0,1" newline bitfld.long 0x8 11. "PRIV2BB11," "0,1" bitfld.long 0x8 10. "PRIV2BB10," "0,1" newline bitfld.long 0x8 9. "PRIV2BB9," "0,1" bitfld.long 0x8 8. "PRIV2BB8," "0,1" newline bitfld.long 0x8 7. "PRIV2BB7," "0,1" bitfld.long 0x8 6. "PRIV2BB6," "0,1" newline bitfld.long 0x8 5. "PRIV2BB5," "0,1" bitfld.long 0x8 4. "PRIV2BB4," "0,1" newline bitfld.long 0x8 3. "PRIV2BB3," "0,1" bitfld.long 0x8 2. "PRIV2BB2," "0,1" newline bitfld.long 0x8 1. "PRIV2BB1," "0,1" bitfld.long 0x8 0. "PRIV2BB0," "0,1" line.long 0xC "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0xC 31. "PRIV2BB31," "0,1" bitfld.long 0xC 30. "PRIV2BB30," "0,1" newline bitfld.long 0xC 29. "PRIV2BB29," "0,1" bitfld.long 0xC 28. "PRIV2BB28," "0,1" newline bitfld.long 0xC 27. "PRIV2BB27," "0,1" bitfld.long 0xC 26. "PRIV2BB26," "0,1" newline bitfld.long 0xC 25. "PRIV2BB25," "0,1" bitfld.long 0xC 24. "PRIV2BB24," "0,1" newline bitfld.long 0xC 23. "PRIV2BB23," "0,1" bitfld.long 0xC 22. "PRIV2BB22," "0,1" newline bitfld.long 0xC 21. "PRIV2BB21," "0,1" bitfld.long 0xC 20. "PRIV2BB20," "0,1" newline bitfld.long 0xC 19. "PRIV2BB19," "0,1" bitfld.long 0xC 18. "PRIV2BB18," "0,1" newline bitfld.long 0xC 17. "PRIV2BB17," "0,1" bitfld.long 0xC 16. "PRIV2BB16," "0,1" newline bitfld.long 0xC 15. "PRIV2BB15," "0,1" bitfld.long 0xC 14. "PRIV2BB14," "0,1" newline bitfld.long 0xC 13. "PRIV2BB13," "0,1" bitfld.long 0xC 12. "PRIV2BB12," "0,1" newline bitfld.long 0xC 11. "PRIV2BB11," "0,1" bitfld.long 0xC 10. "PRIV2BB10," "0,1" newline bitfld.long 0xC 9. "PRIV2BB9," "0,1" bitfld.long 0xC 8. "PRIV2BB8," "0,1" newline bitfld.long 0xC 7. "PRIV2BB7," "0,1" bitfld.long 0xC 6. "PRIV2BB6," "0,1" newline bitfld.long 0xC 5. "PRIV2BB5," "0,1" bitfld.long 0xC 4. "PRIV2BB4," "0,1" newline bitfld.long 0xC 3. "PRIV2BB3," "0,1" bitfld.long 0xC 2. "PRIV2BB2," "0,1" newline bitfld.long 0xC 1. "PRIV2BB1," "0,1" bitfld.long 0xC 0. "PRIV2BB0," "0,1" endif group.long 0xA0++0xF line.long 0x0 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x0 31. "SEC2BB31," "0,1" newline bitfld.long 0x0 30. "SEC2BB30," "0,1" newline bitfld.long 0x0 29. "SEC2BB29," "0,1" newline bitfld.long 0x0 28. "SEC2BB28," "0,1" newline bitfld.long 0x0 27. "SEC2BB27," "0,1" newline bitfld.long 0x0 26. "SEC2BB26," "0,1" newline bitfld.long 0x0 25. "SEC2BB25," "0,1" newline bitfld.long 0x0 24. "SEC2BB24," "0,1" newline bitfld.long 0x0 23. "SEC2BB23," "0,1" newline bitfld.long 0x0 22. "SEC2BB22," "0,1" newline bitfld.long 0x0 21. "SEC2BB21," "0,1" newline bitfld.long 0x0 20. "SEC2BB20," "0,1" newline bitfld.long 0x0 19. "SEC2BB19," "0,1" newline bitfld.long 0x0 18. "SEC2BB18," "0,1" newline bitfld.long 0x0 17. "SEC2BB17," "0,1" newline bitfld.long 0x0 16. "SEC2BB16," "0,1" newline bitfld.long 0x0 15. "SEC2BB15," "0,1" newline bitfld.long 0x0 14. "SEC2BB14," "0,1" newline bitfld.long 0x0 13. "SEC2BB13," "0,1" newline bitfld.long 0x0 12. "SEC2BB12," "0,1" newline bitfld.long 0x0 11. "SEC2BB11," "0,1" newline bitfld.long 0x0 10. "SEC2BB10," "0,1" newline bitfld.long 0x0 9. "SEC2BB9," "0,1" newline bitfld.long 0x0 8. "SEC2BB8," "0,1" newline bitfld.long 0x0 7. "SEC2BB7," "0,1" newline bitfld.long 0x0 6. "SEC2BB6," "0,1" newline bitfld.long 0x0 5. "SEC2BB5," "0,1" newline bitfld.long 0x0 4. "SEC2BB4," "0,1" newline bitfld.long 0x0 3. "SEC2BB3," "0,1" newline bitfld.long 0x0 2. "SEC2BB2," "0,1" newline bitfld.long 0x0 1. "SEC2BB1," "0,1" newline bitfld.long 0x0 0. "SEC2BB0," "0,1" line.long 0x4 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x4 31. "SEC2BB31," "0,1" newline bitfld.long 0x4 30. "SEC2BB30," "0,1" newline bitfld.long 0x4 29. "SEC2BB29," "0,1" newline bitfld.long 0x4 28. "SEC2BB28," "0,1" newline bitfld.long 0x4 27. "SEC2BB27," "0,1" newline bitfld.long 0x4 26. "SEC2BB26," "0,1" newline bitfld.long 0x4 25. "SEC2BB25," "0,1" newline bitfld.long 0x4 24. "SEC2BB24," "0,1" newline bitfld.long 0x4 23. "SEC2BB23," "0,1" newline bitfld.long 0x4 22. "SEC2BB22," "0,1" newline bitfld.long 0x4 21. "SEC2BB21," "0,1" newline bitfld.long 0x4 20. "SEC2BB20," "0,1" newline bitfld.long 0x4 19. "SEC2BB19," "0,1" newline bitfld.long 0x4 18. "SEC2BB18," "0,1" newline bitfld.long 0x4 17. "SEC2BB17," "0,1" newline bitfld.long 0x4 16. "SEC2BB16," "0,1" newline bitfld.long 0x4 15. "SEC2BB15," "0,1" newline bitfld.long 0x4 14. "SEC2BB14," "0,1" newline bitfld.long 0x4 13. "SEC2BB13," "0,1" newline bitfld.long 0x4 12. "SEC2BB12," "0,1" newline bitfld.long 0x4 11. "SEC2BB11," "0,1" newline bitfld.long 0x4 10. "SEC2BB10," "0,1" newline bitfld.long 0x4 9. "SEC2BB9," "0,1" newline bitfld.long 0x4 8. "SEC2BB8," "0,1" newline bitfld.long 0x4 7. "SEC2BB7," "0,1" newline bitfld.long 0x4 6. "SEC2BB6," "0,1" newline bitfld.long 0x4 5. "SEC2BB5," "0,1" newline bitfld.long 0x4 4. "SEC2BB4," "0,1" newline bitfld.long 0x4 3. "SEC2BB3," "0,1" newline bitfld.long 0x4 2. "SEC2BB2," "0,1" newline bitfld.long 0x4 1. "SEC2BB1," "0,1" newline bitfld.long 0x4 0. "SEC2BB0," "0,1" line.long 0x8 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x8 31. "SEC2BB31," "0,1" newline bitfld.long 0x8 30. "SEC2BB30," "0,1" newline bitfld.long 0x8 29. "SEC2BB29," "0,1" newline bitfld.long 0x8 28. "SEC2BB28," "0,1" newline bitfld.long 0x8 27. "SEC2BB27," "0,1" newline bitfld.long 0x8 26. "SEC2BB26," "0,1" newline bitfld.long 0x8 25. "SEC2BB25," "0,1" newline bitfld.long 0x8 24. "SEC2BB24," "0,1" newline bitfld.long 0x8 23. "SEC2BB23," "0,1" newline bitfld.long 0x8 22. "SEC2BB22," "0,1" newline bitfld.long 0x8 21. "SEC2BB21," "0,1" newline bitfld.long 0x8 20. "SEC2BB20," "0,1" newline bitfld.long 0x8 19. "SEC2BB19," "0,1" newline bitfld.long 0x8 18. "SEC2BB18," "0,1" newline bitfld.long 0x8 17. "SEC2BB17," "0,1" newline bitfld.long 0x8 16. "SEC2BB16," "0,1" newline bitfld.long 0x8 15. "SEC2BB15," "0,1" newline bitfld.long 0x8 14. "SEC2BB14," "0,1" newline bitfld.long 0x8 13. "SEC2BB13," "0,1" newline bitfld.long 0x8 12. "SEC2BB12," "0,1" newline bitfld.long 0x8 11. "SEC2BB11," "0,1" newline bitfld.long 0x8 10. "SEC2BB10," "0,1" newline bitfld.long 0x8 9. "SEC2BB9," "0,1" newline bitfld.long 0x8 8. "SEC2BB8," "0,1" newline bitfld.long 0x8 7. "SEC2BB7," "0,1" newline bitfld.long 0x8 6. "SEC2BB6," "0,1" newline bitfld.long 0x8 5. "SEC2BB5," "0,1" newline bitfld.long 0x8 4. "SEC2BB4," "0,1" newline bitfld.long 0x8 3. "SEC2BB3," "0,1" newline bitfld.long 0x8 2. "SEC2BB2," "0,1" newline bitfld.long 0x8 1. "SEC2BB1," "0,1" newline bitfld.long 0x8 0. "SEC2BB0," "0,1" line.long 0xC "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0xC 31. "SEC2BB31," "0,1" newline bitfld.long 0xC 30. "SEC2BB30," "0,1" newline bitfld.long 0xC 29. "SEC2BB29," "0,1" newline bitfld.long 0xC 28. "SEC2BB28," "0,1" newline bitfld.long 0xC 27. "SEC2BB27," "0,1" newline bitfld.long 0xC 26. "SEC2BB26," "0,1" newline bitfld.long 0xC 25. "SEC2BB25," "0,1" newline bitfld.long 0xC 24. "SEC2BB24," "0,1" newline bitfld.long 0xC 23. "SEC2BB23," "0,1" newline bitfld.long 0xC 22. "SEC2BB22," "0,1" newline bitfld.long 0xC 21. "SEC2BB21," "0,1" newline bitfld.long 0xC 20. "SEC2BB20," "0,1" newline bitfld.long 0xC 19. "SEC2BB19," "0,1" newline bitfld.long 0xC 18. "SEC2BB18," "0,1" newline bitfld.long 0xC 17. "SEC2BB17," "0,1" newline bitfld.long 0xC 16. "SEC2BB16," "0,1" newline bitfld.long 0xC 15. "SEC2BB15," "0,1" newline bitfld.long 0xC 14. "SEC2BB14," "0,1" newline bitfld.long 0xC 13. "SEC2BB13," "0,1" newline bitfld.long 0xC 12. "SEC2BB12," "0,1" newline bitfld.long 0xC 11. "SEC2BB11," "0,1" newline bitfld.long 0xC 10. "SEC2BB10," "0,1" newline bitfld.long 0xC 9. "SEC2BB9," "0,1" newline bitfld.long 0xC 8. "SEC2BB8," "0,1" newline bitfld.long 0xC 7. "SEC2BB7," "0,1" newline bitfld.long 0xC 6. "SEC2BB6," "0,1" newline bitfld.long 0xC 5. "SEC2BB5," "0,1" newline bitfld.long 0xC 4. "SEC2BB4," "0,1" newline bitfld.long 0xC 3. "SEC2BB3," "0,1" newline bitfld.long 0xC 2. "SEC2BB2," "0,1" newline bitfld.long 0xC 1. "SEC2BB1," "0,1" newline bitfld.long 0xC 0. "SEC2BB0," "0,1" group.long 0xC0++0x7 line.long 0x0 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x0 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x0 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x4 "FLASH_PRIVCFGR,FLASH privilege configuration register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x4 0. "SPRIV,Privileged protection for secure registers" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 1. "NSPRIV,Privileged protection for non-secure registers" "0: Non-secure Flash registers can be read and..,1: Non-secure Flash registers can be read and.." endif group.long 0xD0++0xF line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" group.long 0xF0++0xF line.long 0x0 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x0 31. "PRIV2BB31," "0,1" newline bitfld.long 0x0 30. "PRIV2BB30," "0,1" newline bitfld.long 0x0 29. "PRIV2BB29," "0,1" newline bitfld.long 0x0 28. "PRIV2BB28," "0,1" newline bitfld.long 0x0 27. "PRIV2BB27," "0,1" newline bitfld.long 0x0 26. "PRIV2BB26," "0,1" newline bitfld.long 0x0 25. "PRIV2BB25," "0,1" newline bitfld.long 0x0 24. "PRIV2BB24," "0,1" newline bitfld.long 0x0 23. "PRIV2BB23," "0,1" newline bitfld.long 0x0 22. "PRIV2BB22," "0,1" newline bitfld.long 0x0 21. "PRIV2BB21," "0,1" newline bitfld.long 0x0 20. "PRIV2BB20," "0,1" newline bitfld.long 0x0 19. "PRIV2BB19," "0,1" newline bitfld.long 0x0 18. "PRIV2BB18," "0,1" newline bitfld.long 0x0 17. "PRIV2BB17," "0,1" newline bitfld.long 0x0 16. "PRIV2BB16," "0,1" newline bitfld.long 0x0 15. "PRIV2BB15," "0,1" newline bitfld.long 0x0 14. "PRIV2BB14," "0,1" newline bitfld.long 0x0 13. "PRIV2BB13," "0,1" newline bitfld.long 0x0 12. "PRIV2BB12," "0,1" newline bitfld.long 0x0 11. "PRIV2BB11," "0,1" newline bitfld.long 0x0 10. "PRIV2BB10," "0,1" newline bitfld.long 0x0 9. "PRIV2BB9," "0,1" newline bitfld.long 0x0 8. "PRIV2BB8," "0,1" newline bitfld.long 0x0 7. "PRIV2BB7," "0,1" newline bitfld.long 0x0 6. "PRIV2BB6," "0,1" newline bitfld.long 0x0 5. "PRIV2BB5," "0,1" newline bitfld.long 0x0 4. "PRIV2BB4," "0,1" newline bitfld.long 0x0 3. "PRIV2BB3," "0,1" newline bitfld.long 0x0 2. "PRIV2BB2," "0,1" newline bitfld.long 0x0 1. "PRIV2BB1," "0,1" newline bitfld.long 0x0 0. "PRIV2BB0," "0,1" line.long 0x4 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x4 31. "PRIV2BB31," "0,1" newline bitfld.long 0x4 30. "PRIV2BB30," "0,1" newline bitfld.long 0x4 29. "PRIV2BB29," "0,1" newline bitfld.long 0x4 28. "PRIV2BB28," "0,1" newline bitfld.long 0x4 27. "PRIV2BB27," "0,1" newline bitfld.long 0x4 26. "PRIV2BB26," "0,1" newline bitfld.long 0x4 25. "PRIV2BB25," "0,1" newline bitfld.long 0x4 24. "PRIV2BB24," "0,1" newline bitfld.long 0x4 23. "PRIV2BB23," "0,1" newline bitfld.long 0x4 22. "PRIV2BB22," "0,1" newline bitfld.long 0x4 21. "PRIV2BB21," "0,1" newline bitfld.long 0x4 20. "PRIV2BB20," "0,1" newline bitfld.long 0x4 19. "PRIV2BB19," "0,1" newline bitfld.long 0x4 18. "PRIV2BB18," "0,1" newline bitfld.long 0x4 17. "PRIV2BB17," "0,1" newline bitfld.long 0x4 16. "PRIV2BB16," "0,1" newline bitfld.long 0x4 15. "PRIV2BB15," "0,1" newline bitfld.long 0x4 14. "PRIV2BB14," "0,1" newline bitfld.long 0x4 13. "PRIV2BB13," "0,1" newline bitfld.long 0x4 12. "PRIV2BB12," "0,1" newline bitfld.long 0x4 11. "PRIV2BB11," "0,1" newline bitfld.long 0x4 10. "PRIV2BB10," "0,1" newline bitfld.long 0x4 9. "PRIV2BB9," "0,1" newline bitfld.long 0x4 8. "PRIV2BB8," "0,1" newline bitfld.long 0x4 7. "PRIV2BB7," "0,1" newline bitfld.long 0x4 6. "PRIV2BB6," "0,1" newline bitfld.long 0x4 5. "PRIV2BB5," "0,1" newline bitfld.long 0x4 4. "PRIV2BB4," "0,1" newline bitfld.long 0x4 3. "PRIV2BB3," "0,1" newline bitfld.long 0x4 2. "PRIV2BB2," "0,1" newline bitfld.long 0x4 1. "PRIV2BB1," "0,1" newline bitfld.long 0x4 0. "PRIV2BB0," "0,1" line.long 0x8 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x8 31. "PRIV2BB31," "0,1" newline bitfld.long 0x8 30. "PRIV2BB30," "0,1" newline bitfld.long 0x8 29. "PRIV2BB29," "0,1" newline bitfld.long 0x8 28. "PRIV2BB28," "0,1" newline bitfld.long 0x8 27. "PRIV2BB27," "0,1" newline bitfld.long 0x8 26. "PRIV2BB26," "0,1" newline bitfld.long 0x8 25. "PRIV2BB25," "0,1" newline bitfld.long 0x8 24. "PRIV2BB24," "0,1" newline bitfld.long 0x8 23. "PRIV2BB23," "0,1" newline bitfld.long 0x8 22. "PRIV2BB22," "0,1" newline bitfld.long 0x8 21. "PRIV2BB21," "0,1" newline bitfld.long 0x8 20. "PRIV2BB20," "0,1" newline bitfld.long 0x8 19. "PRIV2BB19," "0,1" newline bitfld.long 0x8 18. "PRIV2BB18," "0,1" newline bitfld.long 0x8 17. "PRIV2BB17," "0,1" newline bitfld.long 0x8 16. "PRIV2BB16," "0,1" newline bitfld.long 0x8 15. "PRIV2BB15," "0,1" newline bitfld.long 0x8 14. "PRIV2BB14," "0,1" newline bitfld.long 0x8 13. "PRIV2BB13," "0,1" newline bitfld.long 0x8 12. "PRIV2BB12," "0,1" newline bitfld.long 0x8 11. "PRIV2BB11," "0,1" newline bitfld.long 0x8 10. "PRIV2BB10," "0,1" newline bitfld.long 0x8 9. "PRIV2BB9," "0,1" newline bitfld.long 0x8 8. "PRIV2BB8," "0,1" newline bitfld.long 0x8 7. "PRIV2BB7," "0,1" newline bitfld.long 0x8 6. "PRIV2BB6," "0,1" newline bitfld.long 0x8 5. "PRIV2BB5," "0,1" newline bitfld.long 0x8 4. "PRIV2BB4," "0,1" newline bitfld.long 0x8 3. "PRIV2BB3," "0,1" newline bitfld.long 0x8 2. "PRIV2BB2," "0,1" newline bitfld.long 0x8 1. "PRIV2BB1," "0,1" newline bitfld.long 0x8 0. "PRIV2BB0," "0,1" line.long 0xC "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0xC 31. "PRIV2BB31," "0,1" newline bitfld.long 0xC 30. "PRIV2BB30," "0,1" newline bitfld.long 0xC 29. "PRIV2BB29," "0,1" newline bitfld.long 0xC 28. "PRIV2BB28," "0,1" newline bitfld.long 0xC 27. "PRIV2BB27," "0,1" newline bitfld.long 0xC 26. "PRIV2BB26," "0,1" newline bitfld.long 0xC 25. "PRIV2BB25," "0,1" newline bitfld.long 0xC 24. "PRIV2BB24," "0,1" newline bitfld.long 0xC 23. "PRIV2BB23," "0,1" newline bitfld.long 0xC 22. "PRIV2BB22," "0,1" newline bitfld.long 0xC 21. "PRIV2BB21," "0,1" newline bitfld.long 0xC 20. "PRIV2BB20," "0,1" newline bitfld.long 0xC 19. "PRIV2BB19," "0,1" newline bitfld.long 0xC 18. "PRIV2BB18," "0,1" newline bitfld.long 0xC 17. "PRIV2BB17," "0,1" newline bitfld.long 0xC 16. "PRIV2BB16," "0,1" newline bitfld.long 0xC 15. "PRIV2BB15," "0,1" newline bitfld.long 0xC 14. "PRIV2BB14," "0,1" newline bitfld.long 0xC 13. "PRIV2BB13," "0,1" newline bitfld.long 0xC 12. "PRIV2BB12," "0,1" newline bitfld.long 0xC 11. "PRIV2BB11," "0,1" newline bitfld.long 0xC 10. "PRIV2BB10," "0,1" newline bitfld.long 0xC 9. "PRIV2BB9," "0,1" newline bitfld.long 0xC 8. "PRIV2BB8," "0,1" newline bitfld.long 0xC 7. "PRIV2BB7," "0,1" newline bitfld.long 0xC 6. "PRIV2BB6," "0,1" newline bitfld.long 0xC 5. "PRIV2BB5," "0,1" newline bitfld.long 0xC 4. "PRIV2BB4," "0,1" newline bitfld.long 0xC 3. "PRIV2BB3," "0,1" newline bitfld.long 0xC 2. "PRIV2BB2," "0,1" newline bitfld.long 0xC 1. "PRIV2BB1," "0,1" newline bitfld.long 0xC 0. "PRIV2BB0," "0,1" sif (cpuis("STM32U575*")) wgroup.long 0x8++0x3 line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" endif sif (cpuis("STM32U575*")) wgroup.long 0xC++0x3 line.long 0x0 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x0 0.--31. 1. "SECKEY,Flash memory secure key" endif sif (cpuis("STM32U575*")) wgroup.long 0x10++0x3 line.long 0x0 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEY,Option byte key" endif sif (cpuis("STM32U575*")) wgroup.long 0x18++0x3 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" endif sif (cpuis("STM32U575*")) wgroup.long 0x1C++0x3 line.long 0x0 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY2,Bank 2 power-down key" endif sif (cpuis("STM32U575*")) rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" endif sif (cpuis("STM32U575*")) wgroup.long 0x70++0x3 line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" endif sif (cpuis("STM32U575*")) wgroup.long 0x74++0x3 line.long 0x0 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" endif sif (cpuis("STM32U575*")) wgroup.long 0x78++0x3 line.long 0x0 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x0 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" endif sif (cpuis("STM32U575*")) wgroup.long 0x7C++0x3 line.long 0x0 "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0x0 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" endif tree.end endif sif (cpuis("STM32U585*")) tree "FLASH" base ad:0x40022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--9. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0,1" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--9. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--19. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--19. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 and SRAM4 erase upon system reset" "0: SRAM1 SRAM3 and SRAM4 erased when a system reset..,1: SRAM1 SRAM3 and SRAM4 not erased when a system.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--22. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--6. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--22. 1. "HDP1_PEND,End page of first hide protection area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--22. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--6. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--22. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--6. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--22. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--6. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--22. 1. "HDP2_PEND,End page of hide protection second area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--22. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--6. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--22. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--6. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0xF line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 30. "SEC1BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 29. "SEC1BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 28. "SEC1BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 27. "SEC1BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 26. "SEC1BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 25. "SEC1BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 24. "SEC1BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 23. "SEC1BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 22. "SEC1BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 21. "SEC1BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 20. "SEC1BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 19. "SEC1BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 18. "SEC1BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 17. "SEC1BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 16. "SEC1BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 15. "SEC1BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 14. "SEC1BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 13. "SEC1BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 12. "SEC1BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 11. "SEC1BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 10. "SEC1BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 9. "SEC1BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 8. "SEC1BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 7. "SEC1BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 6. "SEC1BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 5. "SEC1BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 4. "SEC1BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 3. "SEC1BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 2. "SEC1BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 1. "SEC1BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 0. "SEC1BB0,page secure/non-secure attribution" "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 30. "SEC1BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 29. "SEC1BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 28. "SEC1BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 27. "SEC1BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 26. "SEC1BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 25. "SEC1BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 24. "SEC1BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 23. "SEC1BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 22. "SEC1BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 21. "SEC1BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 20. "SEC1BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 19. "SEC1BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 18. "SEC1BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 17. "SEC1BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 16. "SEC1BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 15. "SEC1BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 14. "SEC1BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 13. "SEC1BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 12. "SEC1BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 11. "SEC1BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 10. "SEC1BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 9. "SEC1BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 8. "SEC1BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 7. "SEC1BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 6. "SEC1BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 5. "SEC1BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 4. "SEC1BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 3. "SEC1BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 2. "SEC1BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 1. "SEC1BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 0. "SEC1BB0,page secure/non-secure attribution" "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 30. "SEC1BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 29. "SEC1BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 28. "SEC1BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 27. "SEC1BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 26. "SEC1BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 25. "SEC1BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 24. "SEC1BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 23. "SEC1BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 22. "SEC1BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 21. "SEC1BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 20. "SEC1BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 19. "SEC1BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 18. "SEC1BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 17. "SEC1BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 16. "SEC1BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 15. "SEC1BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 14. "SEC1BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 13. "SEC1BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 12. "SEC1BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 11. "SEC1BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 10. "SEC1BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 9. "SEC1BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 8. "SEC1BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 7. "SEC1BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 6. "SEC1BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 5. "SEC1BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 4. "SEC1BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 3. "SEC1BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 2. "SEC1BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 1. "SEC1BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 0. "SEC1BB0,page secure/non-secure attribution" "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 30. "SEC1BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 29. "SEC1BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 28. "SEC1BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 27. "SEC1BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 26. "SEC1BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 25. "SEC1BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 24. "SEC1BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 23. "SEC1BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 22. "SEC1BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 21. "SEC1BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 20. "SEC1BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 19. "SEC1BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 18. "SEC1BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 17. "SEC1BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 16. "SEC1BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 15. "SEC1BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 14. "SEC1BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 13. "SEC1BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 12. "SEC1BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 11. "SEC1BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 10. "SEC1BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 9. "SEC1BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 8. "SEC1BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 7. "SEC1BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 6. "SEC1BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 5. "SEC1BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 4. "SEC1BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 3. "SEC1BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 2. "SEC1BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 1. "SEC1BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 0. "SEC1BB0,page secure/non-secure attribution" "0,1" group.long 0xA0++0xF line.long 0x0 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x0 31. "SEC2BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 30. "SEC2BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 29. "SEC2BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 28. "SEC2BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 27. "SEC2BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 26. "SEC2BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 25. "SEC2BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 24. "SEC2BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 23. "SEC2BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 22. "SEC2BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 21. "SEC2BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 20. "SEC2BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 19. "SEC2BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 18. "SEC2BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 17. "SEC2BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 16. "SEC2BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 15. "SEC2BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 14. "SEC2BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 13. "SEC2BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 12. "SEC2BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 11. "SEC2BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 10. "SEC2BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 9. "SEC2BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 8. "SEC2BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 7. "SEC2BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 6. "SEC2BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 5. "SEC2BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 4. "SEC2BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 3. "SEC2BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 2. "SEC2BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 1. "SEC2BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 0. "SEC2BB0,page secure/non-secure attribution" "0,1" line.long 0x4 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x4 31. "SEC2BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 30. "SEC2BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 29. "SEC2BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 28. "SEC2BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 27. "SEC2BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 26. "SEC2BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 25. "SEC2BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 24. "SEC2BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 23. "SEC2BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 22. "SEC2BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 21. "SEC2BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 20. "SEC2BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 19. "SEC2BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 18. "SEC2BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 17. "SEC2BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 16. "SEC2BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 15. "SEC2BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 14. "SEC2BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 13. "SEC2BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 12. "SEC2BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 11. "SEC2BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 10. "SEC2BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 9. "SEC2BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 8. "SEC2BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 7. "SEC2BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 6. "SEC2BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 5. "SEC2BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 4. "SEC2BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 3. "SEC2BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 2. "SEC2BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 1. "SEC2BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 0. "SEC2BB0,page secure/non-secure attribution" "0,1" line.long 0x8 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x8 31. "SEC2BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 30. "SEC2BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 29. "SEC2BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 28. "SEC2BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 27. "SEC2BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 26. "SEC2BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 25. "SEC2BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 24. "SEC2BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 23. "SEC2BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 22. "SEC2BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 21. "SEC2BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 20. "SEC2BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 19. "SEC2BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 18. "SEC2BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 17. "SEC2BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 16. "SEC2BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 15. "SEC2BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 14. "SEC2BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 13. "SEC2BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 12. "SEC2BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 11. "SEC2BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 10. "SEC2BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 9. "SEC2BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 8. "SEC2BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 7. "SEC2BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 6. "SEC2BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 5. "SEC2BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 4. "SEC2BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 3. "SEC2BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 2. "SEC2BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 1. "SEC2BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 0. "SEC2BB0,page secure/non-secure attribution" "0,1" line.long 0xC "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0xC 31. "SEC2BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 30. "SEC2BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 29. "SEC2BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 28. "SEC2BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 27. "SEC2BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 26. "SEC2BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 25. "SEC2BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 24. "SEC2BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 23. "SEC2BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 22. "SEC2BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 21. "SEC2BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 20. "SEC2BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 19. "SEC2BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 18. "SEC2BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 17. "SEC2BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 16. "SEC2BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 15. "SEC2BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 14. "SEC2BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 13. "SEC2BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 12. "SEC2BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 11. "SEC2BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 10. "SEC2BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 9. "SEC2BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 8. "SEC2BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 7. "SEC2BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 6. "SEC2BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 5. "SEC2BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 4. "SEC2BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 3. "SEC2BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 2. "SEC2BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 1. "SEC2BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 0. "SEC2BB0,page secure/non-secure attribution" "0,1" group.long 0xC0++0x7 line.long 0x0 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x0 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x0 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x4 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x4 1. "NSPRIV,Privileged protection for non-secure registers" "0: Non-secure Flash registers can be read and..,1: Non-secure Flash registers can be read and.." newline bitfld.long 0x4 0. "SPRIV,Privileged protection for secure registers" "0: Secure Flash registers can be read and written..,1: Secure Flash registers can be read and written.." group.long 0xD0++0xF line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 30. "PRIV1BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 29. "PRIV1BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 28. "PRIV1BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 27. "PRIV1BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 26. "PRIV1BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 25. "PRIV1BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 24. "PRIV1BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 23. "PRIV1BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 22. "PRIV1BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 21. "PRIV1BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 20. "PRIV1BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 19. "PRIV1BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 18. "PRIV1BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 17. "PRIV1BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 16. "PRIV1BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 15. "PRIV1BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 14. "PRIV1BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 13. "PRIV1BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 12. "PRIV1BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 11. "PRIV1BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 10. "PRIV1BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 9. "PRIV1BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 8. "PRIV1BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 7. "PRIV1BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 6. "PRIV1BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 5. "PRIV1BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 4. "PRIV1BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 3. "PRIV1BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 2. "PRIV1BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 1. "PRIV1BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 0. "PRIV1BB0,page privileged/unprivileged attribution" "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 30. "PRIV1BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 29. "PRIV1BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 28. "PRIV1BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 27. "PRIV1BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 26. "PRIV1BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 25. "PRIV1BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 24. "PRIV1BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 23. "PRIV1BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 22. "PRIV1BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 21. "PRIV1BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 20. "PRIV1BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 19. "PRIV1BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 18. "PRIV1BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 17. "PRIV1BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 16. "PRIV1BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 15. "PRIV1BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 14. "PRIV1BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 13. "PRIV1BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 12. "PRIV1BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 11. "PRIV1BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 10. "PRIV1BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 9. "PRIV1BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 8. "PRIV1BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 7. "PRIV1BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 6. "PRIV1BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 5. "PRIV1BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 4. "PRIV1BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 3. "PRIV1BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 2. "PRIV1BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 1. "PRIV1BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 0. "PRIV1BB0,page privileged/unprivileged attribution" "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 30. "PRIV1BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 29. "PRIV1BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 28. "PRIV1BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 27. "PRIV1BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 26. "PRIV1BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 25. "PRIV1BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 24. "PRIV1BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 23. "PRIV1BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 22. "PRIV1BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 21. "PRIV1BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 20. "PRIV1BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 19. "PRIV1BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 18. "PRIV1BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 17. "PRIV1BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 16. "PRIV1BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 15. "PRIV1BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 14. "PRIV1BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 13. "PRIV1BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 12. "PRIV1BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 11. "PRIV1BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 10. "PRIV1BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 9. "PRIV1BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 8. "PRIV1BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 7. "PRIV1BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 6. "PRIV1BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 5. "PRIV1BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 4. "PRIV1BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 3. "PRIV1BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 2. "PRIV1BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 1. "PRIV1BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 0. "PRIV1BB0,page privileged/unprivileged attribution" "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 30. "PRIV1BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 29. "PRIV1BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 28. "PRIV1BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 27. "PRIV1BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 26. "PRIV1BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 25. "PRIV1BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 24. "PRIV1BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 23. "PRIV1BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 22. "PRIV1BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 21. "PRIV1BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 20. "PRIV1BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 19. "PRIV1BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 18. "PRIV1BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 17. "PRIV1BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 16. "PRIV1BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 15. "PRIV1BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 14. "PRIV1BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 13. "PRIV1BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 12. "PRIV1BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 11. "PRIV1BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 10. "PRIV1BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 9. "PRIV1BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 8. "PRIV1BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 7. "PRIV1BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 6. "PRIV1BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 5. "PRIV1BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 4. "PRIV1BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 3. "PRIV1BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 2. "PRIV1BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 1. "PRIV1BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 0. "PRIV1BB0,page privileged/unprivileged attribution" "0,1" group.long 0xF0++0xF line.long 0x0 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x0 31. "PRIV2BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 30. "PRIV2BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 29. "PRIV2BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 28. "PRIV2BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 27. "PRIV2BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 26. "PRIV2BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 25. "PRIV2BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 24. "PRIV2BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 23. "PRIV2BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 22. "PRIV2BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 21. "PRIV2BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 20. "PRIV2BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 19. "PRIV2BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 18. "PRIV2BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 17. "PRIV2BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 16. "PRIV2BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 15. "PRIV2BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 14. "PRIV2BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 13. "PRIV2BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 12. "PRIV2BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 11. "PRIV2BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 10. "PRIV2BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 9. "PRIV2BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 8. "PRIV2BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 7. "PRIV2BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 6. "PRIV2BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 5. "PRIV2BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 4. "PRIV2BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 3. "PRIV2BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 2. "PRIV2BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 1. "PRIV2BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 0. "PRIV2BB0,page privileged/unprivileged attribution" "0,1" line.long 0x4 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x4 31. "PRIV2BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 30. "PRIV2BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 29. "PRIV2BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 28. "PRIV2BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 27. "PRIV2BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 26. "PRIV2BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 25. "PRIV2BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 24. "PRIV2BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 23. "PRIV2BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 22. "PRIV2BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 21. "PRIV2BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 20. "PRIV2BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 19. "PRIV2BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 18. "PRIV2BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 17. "PRIV2BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 16. "PRIV2BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 15. "PRIV2BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 14. "PRIV2BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 13. "PRIV2BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 12. "PRIV2BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 11. "PRIV2BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 10. "PRIV2BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 9. "PRIV2BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 8. "PRIV2BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 7. "PRIV2BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 6. "PRIV2BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 5. "PRIV2BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 4. "PRIV2BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 3. "PRIV2BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 2. "PRIV2BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 1. "PRIV2BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 0. "PRIV2BB0,page privileged/unprivileged attribution" "0,1" line.long 0x8 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x8 31. "PRIV2BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 30. "PRIV2BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 29. "PRIV2BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 28. "PRIV2BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 27. "PRIV2BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 26. "PRIV2BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 25. "PRIV2BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 24. "PRIV2BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 23. "PRIV2BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 22. "PRIV2BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 21. "PRIV2BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 20. "PRIV2BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 19. "PRIV2BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 18. "PRIV2BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 17. "PRIV2BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 16. "PRIV2BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 15. "PRIV2BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 14. "PRIV2BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 13. "PRIV2BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 12. "PRIV2BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 11. "PRIV2BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 10. "PRIV2BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 9. "PRIV2BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 8. "PRIV2BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 7. "PRIV2BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 6. "PRIV2BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 5. "PRIV2BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 4. "PRIV2BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 3. "PRIV2BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 2. "PRIV2BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 1. "PRIV2BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 0. "PRIV2BB0,page privileged/unprivileged attribution" "0,1" line.long 0xC "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0xC 31. "PRIV2BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 30. "PRIV2BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 29. "PRIV2BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 28. "PRIV2BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 27. "PRIV2BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 26. "PRIV2BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 25. "PRIV2BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 24. "PRIV2BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 23. "PRIV2BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 22. "PRIV2BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 21. "PRIV2BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 20. "PRIV2BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 19. "PRIV2BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 18. "PRIV2BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 17. "PRIV2BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 16. "PRIV2BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 15. "PRIV2BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 14. "PRIV2BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 13. "PRIV2BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 12. "PRIV2BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 11. "PRIV2BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 10. "PRIV2BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 9. "PRIV2BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 8. "PRIV2BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 7. "PRIV2BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 6. "PRIV2BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 5. "PRIV2BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 4. "PRIV2BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 3. "PRIV2BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 2. "PRIV2BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 1. "PRIV2BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 0. "PRIV2BB0,page privileged/unprivileged attribution" "0,1" tree.end tree "SEC_FLASH" base ad:0x50022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--9. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0,1" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--9. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--19. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--19. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 and SRAM4 erase upon system reset" "0: SRAM1 SRAM3 and SRAM4 erased when a system reset..,1: SRAM1 SRAM3 and SRAM4 not erased when a system.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--22. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--6. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--22. 1. "HDP1_PEND,End page of first hide protection area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--22. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--6. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--22. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--6. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--22. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--6. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--22. 1. "HDP2_PEND,End page of hide protection second area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--22. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--6. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--22. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--6. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0xF line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 30. "SEC1BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 29. "SEC1BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 28. "SEC1BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 27. "SEC1BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 26. "SEC1BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 25. "SEC1BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 24. "SEC1BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 23. "SEC1BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 22. "SEC1BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 21. "SEC1BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 20. "SEC1BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 19. "SEC1BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 18. "SEC1BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 17. "SEC1BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 16. "SEC1BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 15. "SEC1BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 14. "SEC1BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 13. "SEC1BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 12. "SEC1BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 11. "SEC1BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 10. "SEC1BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 9. "SEC1BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 8. "SEC1BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 7. "SEC1BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 6. "SEC1BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 5. "SEC1BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 4. "SEC1BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 3. "SEC1BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 2. "SEC1BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 1. "SEC1BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 0. "SEC1BB0,page secure/non-secure attribution" "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 30. "SEC1BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 29. "SEC1BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 28. "SEC1BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 27. "SEC1BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 26. "SEC1BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 25. "SEC1BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 24. "SEC1BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 23. "SEC1BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 22. "SEC1BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 21. "SEC1BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 20. "SEC1BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 19. "SEC1BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 18. "SEC1BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 17. "SEC1BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 16. "SEC1BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 15. "SEC1BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 14. "SEC1BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 13. "SEC1BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 12. "SEC1BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 11. "SEC1BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 10. "SEC1BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 9. "SEC1BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 8. "SEC1BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 7. "SEC1BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 6. "SEC1BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 5. "SEC1BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 4. "SEC1BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 3. "SEC1BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 2. "SEC1BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 1. "SEC1BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 0. "SEC1BB0,page secure/non-secure attribution" "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 30. "SEC1BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 29. "SEC1BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 28. "SEC1BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 27. "SEC1BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 26. "SEC1BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 25. "SEC1BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 24. "SEC1BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 23. "SEC1BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 22. "SEC1BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 21. "SEC1BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 20. "SEC1BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 19. "SEC1BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 18. "SEC1BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 17. "SEC1BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 16. "SEC1BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 15. "SEC1BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 14. "SEC1BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 13. "SEC1BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 12. "SEC1BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 11. "SEC1BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 10. "SEC1BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 9. "SEC1BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 8. "SEC1BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 7. "SEC1BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 6. "SEC1BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 5. "SEC1BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 4. "SEC1BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 3. "SEC1BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 2. "SEC1BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 1. "SEC1BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 0. "SEC1BB0,page secure/non-secure attribution" "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 30. "SEC1BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 29. "SEC1BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 28. "SEC1BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 27. "SEC1BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 26. "SEC1BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 25. "SEC1BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 24. "SEC1BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 23. "SEC1BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 22. "SEC1BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 21. "SEC1BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 20. "SEC1BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 19. "SEC1BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 18. "SEC1BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 17. "SEC1BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 16. "SEC1BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 15. "SEC1BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 14. "SEC1BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 13. "SEC1BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 12. "SEC1BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 11. "SEC1BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 10. "SEC1BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 9. "SEC1BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 8. "SEC1BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 7. "SEC1BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 6. "SEC1BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 5. "SEC1BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 4. "SEC1BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 3. "SEC1BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 2. "SEC1BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 1. "SEC1BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 0. "SEC1BB0,page secure/non-secure attribution" "0,1" group.long 0xA0++0xF line.long 0x0 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x0 31. "SEC2BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 30. "SEC2BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 29. "SEC2BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 28. "SEC2BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 27. "SEC2BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 26. "SEC2BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 25. "SEC2BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 24. "SEC2BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 23. "SEC2BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 22. "SEC2BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 21. "SEC2BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 20. "SEC2BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 19. "SEC2BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 18. "SEC2BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 17. "SEC2BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 16. "SEC2BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 15. "SEC2BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 14. "SEC2BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 13. "SEC2BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 12. "SEC2BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 11. "SEC2BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 10. "SEC2BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 9. "SEC2BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 8. "SEC2BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 7. "SEC2BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 6. "SEC2BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 5. "SEC2BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 4. "SEC2BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 3. "SEC2BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 2. "SEC2BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 1. "SEC2BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x0 0. "SEC2BB0,page secure/non-secure attribution" "0,1" line.long 0x4 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x4 31. "SEC2BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 30. "SEC2BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 29. "SEC2BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 28. "SEC2BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 27. "SEC2BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 26. "SEC2BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 25. "SEC2BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 24. "SEC2BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 23. "SEC2BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 22. "SEC2BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 21. "SEC2BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 20. "SEC2BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 19. "SEC2BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 18. "SEC2BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 17. "SEC2BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 16. "SEC2BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 15. "SEC2BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 14. "SEC2BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 13. "SEC2BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 12. "SEC2BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 11. "SEC2BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 10. "SEC2BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 9. "SEC2BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 8. "SEC2BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 7. "SEC2BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 6. "SEC2BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 5. "SEC2BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 4. "SEC2BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 3. "SEC2BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 2. "SEC2BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 1. "SEC2BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x4 0. "SEC2BB0,page secure/non-secure attribution" "0,1" line.long 0x8 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x8 31. "SEC2BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 30. "SEC2BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 29. "SEC2BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 28. "SEC2BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 27. "SEC2BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 26. "SEC2BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 25. "SEC2BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 24. "SEC2BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 23. "SEC2BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 22. "SEC2BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 21. "SEC2BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 20. "SEC2BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 19. "SEC2BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 18. "SEC2BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 17. "SEC2BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 16. "SEC2BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 15. "SEC2BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 14. "SEC2BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 13. "SEC2BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 12. "SEC2BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 11. "SEC2BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 10. "SEC2BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 9. "SEC2BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 8. "SEC2BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 7. "SEC2BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 6. "SEC2BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 5. "SEC2BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 4. "SEC2BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 3. "SEC2BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 2. "SEC2BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 1. "SEC2BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0x8 0. "SEC2BB0,page secure/non-secure attribution" "0,1" line.long 0xC "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0xC 31. "SEC2BB31,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 30. "SEC2BB30,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 29. "SEC2BB29,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 28. "SEC2BB28,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 27. "SEC2BB27,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 26. "SEC2BB26,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 25. "SEC2BB25,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 24. "SEC2BB24,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 23. "SEC2BB23,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 22. "SEC2BB22,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 21. "SEC2BB21,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 20. "SEC2BB20,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 19. "SEC2BB19,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 18. "SEC2BB18,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 17. "SEC2BB17,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 16. "SEC2BB16,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 15. "SEC2BB15,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 14. "SEC2BB14,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 13. "SEC2BB13,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 12. "SEC2BB12,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 11. "SEC2BB11,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 10. "SEC2BB10,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 9. "SEC2BB9,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 8. "SEC2BB8,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 7. "SEC2BB7,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 6. "SEC2BB6,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 5. "SEC2BB5,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 4. "SEC2BB4,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 3. "SEC2BB3,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 2. "SEC2BB2,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 1. "SEC2BB1,page secure/non-secure attribution" "0,1" newline bitfld.long 0xC 0. "SEC2BB0,page secure/non-secure attribution" "0,1" group.long 0xC0++0x7 line.long 0x0 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x0 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x0 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x4 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x4 1. "NSPRIV,Privileged protection for non-secure registers" "0: Non-secure Flash registers can be read and..,1: Non-secure Flash registers can be read and.." newline bitfld.long 0x4 0. "SPRIV,Privileged protection for secure registers" "0: Secure Flash registers can be read and written..,1: Secure Flash registers can be read and written.." group.long 0xD0++0xF line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 30. "PRIV1BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 29. "PRIV1BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 28. "PRIV1BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 27. "PRIV1BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 26. "PRIV1BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 25. "PRIV1BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 24. "PRIV1BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 23. "PRIV1BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 22. "PRIV1BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 21. "PRIV1BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 20. "PRIV1BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 19. "PRIV1BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 18. "PRIV1BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 17. "PRIV1BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 16. "PRIV1BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 15. "PRIV1BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 14. "PRIV1BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 13. "PRIV1BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 12. "PRIV1BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 11. "PRIV1BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 10. "PRIV1BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 9. "PRIV1BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 8. "PRIV1BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 7. "PRIV1BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 6. "PRIV1BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 5. "PRIV1BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 4. "PRIV1BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 3. "PRIV1BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 2. "PRIV1BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 1. "PRIV1BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 0. "PRIV1BB0,page privileged/unprivileged attribution" "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 30. "PRIV1BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 29. "PRIV1BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 28. "PRIV1BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 27. "PRIV1BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 26. "PRIV1BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 25. "PRIV1BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 24. "PRIV1BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 23. "PRIV1BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 22. "PRIV1BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 21. "PRIV1BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 20. "PRIV1BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 19. "PRIV1BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 18. "PRIV1BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 17. "PRIV1BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 16. "PRIV1BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 15. "PRIV1BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 14. "PRIV1BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 13. "PRIV1BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 12. "PRIV1BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 11. "PRIV1BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 10. "PRIV1BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 9. "PRIV1BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 8. "PRIV1BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 7. "PRIV1BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 6. "PRIV1BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 5. "PRIV1BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 4. "PRIV1BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 3. "PRIV1BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 2. "PRIV1BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 1. "PRIV1BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 0. "PRIV1BB0,page privileged/unprivileged attribution" "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 30. "PRIV1BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 29. "PRIV1BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 28. "PRIV1BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 27. "PRIV1BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 26. "PRIV1BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 25. "PRIV1BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 24. "PRIV1BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 23. "PRIV1BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 22. "PRIV1BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 21. "PRIV1BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 20. "PRIV1BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 19. "PRIV1BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 18. "PRIV1BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 17. "PRIV1BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 16. "PRIV1BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 15. "PRIV1BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 14. "PRIV1BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 13. "PRIV1BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 12. "PRIV1BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 11. "PRIV1BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 10. "PRIV1BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 9. "PRIV1BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 8. "PRIV1BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 7. "PRIV1BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 6. "PRIV1BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 5. "PRIV1BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 4. "PRIV1BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 3. "PRIV1BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 2. "PRIV1BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 1. "PRIV1BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 0. "PRIV1BB0,page privileged/unprivileged attribution" "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 30. "PRIV1BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 29. "PRIV1BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 28. "PRIV1BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 27. "PRIV1BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 26. "PRIV1BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 25. "PRIV1BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 24. "PRIV1BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 23. "PRIV1BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 22. "PRIV1BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 21. "PRIV1BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 20. "PRIV1BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 19. "PRIV1BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 18. "PRIV1BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 17. "PRIV1BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 16. "PRIV1BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 15. "PRIV1BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 14. "PRIV1BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 13. "PRIV1BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 12. "PRIV1BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 11. "PRIV1BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 10. "PRIV1BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 9. "PRIV1BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 8. "PRIV1BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 7. "PRIV1BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 6. "PRIV1BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 5. "PRIV1BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 4. "PRIV1BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 3. "PRIV1BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 2. "PRIV1BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 1. "PRIV1BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 0. "PRIV1BB0,page privileged/unprivileged attribution" "0,1" group.long 0xF0++0xF line.long 0x0 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x0 31. "PRIV2BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 30. "PRIV2BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 29. "PRIV2BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 28. "PRIV2BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 27. "PRIV2BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 26. "PRIV2BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 25. "PRIV2BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 24. "PRIV2BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 23. "PRIV2BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 22. "PRIV2BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 21. "PRIV2BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 20. "PRIV2BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 19. "PRIV2BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 18. "PRIV2BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 17. "PRIV2BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 16. "PRIV2BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 15. "PRIV2BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 14. "PRIV2BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 13. "PRIV2BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 12. "PRIV2BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 11. "PRIV2BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 10. "PRIV2BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 9. "PRIV2BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 8. "PRIV2BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 7. "PRIV2BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 6. "PRIV2BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 5. "PRIV2BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 4. "PRIV2BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 3. "PRIV2BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 2. "PRIV2BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 1. "PRIV2BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x0 0. "PRIV2BB0,page privileged/unprivileged attribution" "0,1" line.long 0x4 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x4 31. "PRIV2BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 30. "PRIV2BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 29. "PRIV2BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 28. "PRIV2BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 27. "PRIV2BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 26. "PRIV2BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 25. "PRIV2BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 24. "PRIV2BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 23. "PRIV2BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 22. "PRIV2BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 21. "PRIV2BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 20. "PRIV2BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 19. "PRIV2BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 18. "PRIV2BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 17. "PRIV2BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 16. "PRIV2BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 15. "PRIV2BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 14. "PRIV2BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 13. "PRIV2BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 12. "PRIV2BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 11. "PRIV2BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 10. "PRIV2BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 9. "PRIV2BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 8. "PRIV2BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 7. "PRIV2BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 6. "PRIV2BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 5. "PRIV2BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 4. "PRIV2BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 3. "PRIV2BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 2. "PRIV2BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 1. "PRIV2BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x4 0. "PRIV2BB0,page privileged/unprivileged attribution" "0,1" line.long 0x8 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x8 31. "PRIV2BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 30. "PRIV2BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 29. "PRIV2BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 28. "PRIV2BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 27. "PRIV2BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 26. "PRIV2BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 25. "PRIV2BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 24. "PRIV2BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 23. "PRIV2BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 22. "PRIV2BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 21. "PRIV2BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 20. "PRIV2BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 19. "PRIV2BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 18. "PRIV2BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 17. "PRIV2BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 16. "PRIV2BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 15. "PRIV2BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 14. "PRIV2BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 13. "PRIV2BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 12. "PRIV2BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 11. "PRIV2BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 10. "PRIV2BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 9. "PRIV2BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 8. "PRIV2BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 7. "PRIV2BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 6. "PRIV2BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 5. "PRIV2BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 4. "PRIV2BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 3. "PRIV2BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 2. "PRIV2BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 1. "PRIV2BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0x8 0. "PRIV2BB0,page privileged/unprivileged attribution" "0,1" line.long 0xC "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0xC 31. "PRIV2BB31,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 30. "PRIV2BB30,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 29. "PRIV2BB29,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 28. "PRIV2BB28,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 27. "PRIV2BB27,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 26. "PRIV2BB26,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 25. "PRIV2BB25,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 24. "PRIV2BB24,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 23. "PRIV2BB23,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 22. "PRIV2BB22,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 21. "PRIV2BB21,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 20. "PRIV2BB20,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 19. "PRIV2BB19,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 18. "PRIV2BB18,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 17. "PRIV2BB17,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 16. "PRIV2BB16,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 15. "PRIV2BB15,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 14. "PRIV2BB14,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 13. "PRIV2BB13,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 12. "PRIV2BB12,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 11. "PRIV2BB11,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 10. "PRIV2BB10,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 9. "PRIV2BB9,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 8. "PRIV2BB8,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 7. "PRIV2BB7,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 6. "PRIV2BB6,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 5. "PRIV2BB5,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 4. "PRIV2BB4,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 3. "PRIV2BB3,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 2. "PRIV2BB2,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 1. "PRIV2BB1,page privileged/unprivileged attribution" "0,1" newline bitfld.long 0xC 0. "PRIV2BB0,page privileged/unprivileged attribution" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "FLASH" base ad:0x40022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end tree "SEC_FLASH" base ad:0x50022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "FLASH" base ad:0x40022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end tree "SEC_FLASH" base ad:0x50022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "FLASH" base ad:0x40022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end tree "SEC_FLASH" base ad:0x50022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "FLASH" base ad:0x40022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end tree "SEC_FLASH" base ad:0x50022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "FLASH" base ad:0x40022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end tree "SEC_FLASH" base ad:0x50022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "FLASH" base ad:0x40022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end tree "SEC_FLASH" base ad:0x50022000 group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,FLASH access control register" bitfld.long 0x0 14. "SLEEP_PD,Flash memory power-down mode during Sleep mode" "0: Flash in Idle mode during Sleep mode,1: Flash in power-down mode during Sleep mode" newline bitfld.long 0x0 13. "PDREQ2,Bank 2 power-down mode request" "0: No request for bank 2 to enter power-down mode,1: Bank 2 requested to enter power-down mode" newline bitfld.long 0x0 12. "PDREQ1,Bank 1 power-down mode request" "0: No request for bank 1 to enter power-down mode,1: Bank 1 requested to enter power-down mode" newline bitfld.long 0x0 11. "LPM,Low-power read mode" "0: Flash not in low-power read mode,1: Flash in low-power read mode" newline bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0: Prefetch disabled,1: Prefetch enabled" newline hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency" wgroup.long 0x8++0xB line.long 0x0 "FLASH_NSKEYR,FLASH non-secure key register" hexmask.long 0x0 0.--31. 1. "NSKEY,Flash memory non-secure key" line.long 0x4 "FLASH_SECKEYR,FLASH secure key register" hexmask.long 0x4 0.--31. 1. "SECKEY,Flash memory secure key" line.long 0x8 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x8 0.--31. 1. "OPTKEY,Option byte key" wgroup.long 0x18++0x7 line.long 0x0 "FLASH_PDKEY1R,FLASH bank 1 power-down key register" hexmask.long 0x0 0.--31. 1. "PDKEY1,Bank 1 power-down key" line.long 0x4 "FLASH_PDKEY2R,FLASH bank 2 power-down key register" hexmask.long 0x4 0.--31. 1. "PDKEY2,Bank 2 power-down key" group.long 0x20++0x13 line.long 0x0 "FLASH_NSSR,FLASH non-secure status register" rbitfld.long 0x0 21. "PD2,Bank 2 in power-down mode" "0,1" newline rbitfld.long 0x0 20. "PD1,Bank 1 in power-down mode" "0,1" newline rbitfld.long 0x0 19. "OEM2LOCK,OEM2 lock" "0,1" newline rbitfld.long 0x0 18. "OEM1LOCK,OEM1 lock" "0,1" newline rbitfld.long 0x0 17. "WDW,Non-secure wait data to write" "0,1" newline rbitfld.long 0x0 16. "BSY,Non-secure busy" "0,1" newline bitfld.long 0x0 13. "OPTWERR,Option write error" "0,1" newline bitfld.long 0x0 7. "PGSERR,Non-secure programming sequence error" "0,1" newline bitfld.long 0x0 6. "SIZERR,Non-secure size error" "0,1" newline bitfld.long 0x0 5. "PGAERR,Non-secure programming alignment error" "0,1" newline bitfld.long 0x0 4. "WRPERR,Non-secure write protection error" "0,1" newline bitfld.long 0x0 3. "PROGERR,Non-secure programming error" "0,1" newline bitfld.long 0x0 1. "OPERR,Non-secure operation error" "0,1" newline bitfld.long 0x0 0. "EOP,Non-secure end of operation" "0,1" line.long 0x4 "FLASH_SECSR,FLASH secure status register" rbitfld.long 0x4 17. "WDW,Secure wait data to write" "0,1" newline rbitfld.long 0x4 16. "BSY,Secure busy" "0,1" newline bitfld.long 0x4 14. "RDERR,Secure readout protection error" "0,1" newline bitfld.long 0x4 7. "PGSERR,Secure programming sequence error" "0,1" newline bitfld.long 0x4 6. "SIZERR,Secure size error" "0,1" newline bitfld.long 0x4 5. "PGAERR,Secure programming alignment error" "0,1" newline bitfld.long 0x4 4. "WRPERR,Secure write protection error" "0,1" newline bitfld.long 0x4 3. "PROGERR,Secure programming error" "0,1" newline bitfld.long 0x4 1. "OPERR,Secure operation error" "0,1" newline bitfld.long 0x4 0. "EOP,Secure end of operation" "0,1" line.long 0x8 "FLASH_NSCR,FLASH non-secure control register" bitfld.long 0x8 31. "LOCK,Non-secure lock" "0,1" newline bitfld.long 0x8 30. "OPTLOCK,Option lock" "0,1" newline bitfld.long 0x8 27. "OBL_LAUNCH,Force the option byte loading" "0: Option byte loading complete,1: Option byte loading requested" newline bitfld.long 0x8 25. "ERRIE,Non-secure error interrupt enable" "0: Non-secure OPERR error interrupt disabled,1: Non-secure OPERR error interrupt enabled" newline bitfld.long 0x8 24. "EOPIE,Non-secure end of operation interrupt enable" "0: Non-secure EOP Interrupt disabled,1: Non-secure EOP Interrupt enabled" newline bitfld.long 0x8 17. "OPTSTRT,Options modification start" "0,1" newline bitfld.long 0x8 16. "STRT,Non-secure start" "0,1" newline bitfld.long 0x8 15. "MER2,Non-secure bank 2 mass erase" "0,1" newline bitfld.long 0x8 14. "BWR,Non-secure burst write programming mode" "0,1" newline bitfld.long 0x8 11. "BKER,Non-secure bank selection for page erase" "0: Bank 1 selected for non-secure page erase,1: Bank 2 selected for non-secure page erase" newline hexmask.long.byte 0x8 3.--10. 1. "PNB,Non-secure page number selection" newline bitfld.long 0x8 2. "MER1,Non-secure bank 1 mass erase" "0,1" newline bitfld.long 0x8 1. "PER,Non-secure page erase" "0: Non-secure page erase disabled,1: Non-secure page erase enabled" newline bitfld.long 0x8 0. "PG,Non-secure programming" "0: Non-secure Flash programming disabled,1: Non-secure Flash programming enabled" line.long 0xC "FLASH_SECCR,FLASH secure control register" bitfld.long 0xC 31. "LOCK,Secure lock" "0,1" newline bitfld.long 0xC 29. "INV,Flash memory security state invert" "0,1" newline bitfld.long 0xC 26. "RDERRIE,Secure PCROP read error interrupt enable" "0: Secure PCROP read error interrupt disabled,1: Secure PCROP read error interrupt enabled" newline bitfld.long 0xC 25. "ERRIE,Secure error interrupt enable" "0: Secure OPERR error interrupt disabled,1: Secure OPERR error interrupt enabled" newline bitfld.long 0xC 24. "EOPIE,Secure End of operation interrupt enable" "0: Secure EOP Interrupt disabled,1: Secure EOP Interrupt enabled" newline bitfld.long 0xC 16. "STRT,Secure start" "0,1" newline bitfld.long 0xC 15. "MER2,Secure bank 2 mass erase" "0,1" newline bitfld.long 0xC 14. "BWR,Secure burst write programming mode" "0,1" newline bitfld.long 0xC 11. "BKER,Secure bank selection for page erase" "0: Bank 1 selected for secure page erase,1: Bank 2 selected for secure page erase" newline hexmask.long.byte 0xC 3.--10. 1. "PNB,Secure page number selection" newline bitfld.long 0xC 2. "MER1,Secure bank 1 mass erase" "0,1" newline bitfld.long 0xC 1. "PER,Secure page erase" "0: Secure page erase disabled,1: Secure page erase enabled" newline bitfld.long 0xC 0. "PG,Secure programming" "0: Secure Flash programming disabled,1: Secure Flash programming enabled" line.long 0x10 "FLASH_ECCR,FLASH ECC register" bitfld.long 0x10 31. "ECCD,ECC detection" "0,1" newline bitfld.long 0x10 30. "ECCC,ECC correction" "0,1" newline bitfld.long 0x10 24. "ECCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled." newline rbitfld.long 0x10 22. "SYSF_ECC,System Flash memory ECC fail" "0,1" newline rbitfld.long 0x10 21. "BK_ECC,ECC fail bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x10 0.--20. 1. "ADDR_ECC,ECC fail address" rgroup.long 0x34++0x3 line.long 0x0 "FLASH_OPSR,FLASH operation status register" bitfld.long 0x0 29.--31. "CODE_OP,Flash memory operation code" "0: No Flash operation interrupted by previous reset,1: Single write operation interrupted,2: Burst write operation interrupted,3: Page erase operation interrupted,4: Bank erase operation interrupted,5: Mass erase operation interrupted,6: Option change operation interrupted,?" newline bitfld.long 0x0 22. "SYSF_OP,Operation in system Flash memory interrupted" "0,1" newline bitfld.long 0x0 21. "BK_OP,Interrupted operation bank" "0: Bank 1,1: Bank 2" newline hexmask.long.tbyte 0x0 0.--20. 1. "ADDR_OP,Interrupted operation address" group.long 0x40++0x2F line.long 0x0 "FLASH_OPTR,FLASH option register" bitfld.long 0x0 31. "TZEN,Global TrustZone security enable" "0: Global TrustZone security disabled,1: Global TrustZone security enabled" newline bitfld.long 0x0 30. "IO_VDDIO2_HSLV,High-speed IO at low VDDIO2 voltage configuration bit" "0: High-speed IO at low VDDIO2 voltage feature..,1: High-speed IO at low VDDIO2 voltage feature.." newline bitfld.long 0x0 29. "IO_VDD_HSLV,High-speed IO at low VDD voltage configuration bit" "0: High-speed IO at low VDD voltage feature..,1: High-speed IO at low VDD voltage feature enabled.." newline bitfld.long 0x0 28. "PA15_PUPEN,PA15 pull-up enable" "0: USB power delivery dead-battery enabled/TDI..,1: USB power delivery dead-battery disabled/TDI.." newline bitfld.long 0x0 27. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1" newline bitfld.long 0x0 26. "nSWBOOT0,Software BOOT0" "0: BOOT0 taken from the option bit nBOOT0,1: BOOT0 taken from PH3/BOOT0 pin" newline bitfld.long 0x0 25. "SRAM2_RST,SRAM2 erase when system reset" "0: SRAM2 erased when a system reset occurs,1: SRAM2 not erased when a system reset occurs" newline bitfld.long 0x0 24. "SRAM2_ECC,SRAM2 ECC detection and correction enable" "0: SRAM2 ECC check enabled,1: SRAM2 ECC check disabled" newline bitfld.long 0x0 23. "SRAM3_ECC,SRAM3 ECC detection and correction enable" "0: SRAM3 ECC check enabled,1: SRAM3 ECC check disabled" newline bitfld.long 0x0 22. "BKPRAM_ECC,Backup RAM ECC detection and correction enable" "0: Backup RAM ECC check enabled,1: Backup RAM ECC check disabled" newline bitfld.long 0x0 21. "DUALBANK,Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices" "0: Single bank Flash with contiguous address in..,1: Dual-bank Flash with contiguous addresses" newline bitfld.long 0x0 20. "SWAP_BANK,Swap banks" "0: Bank 1 and bank 2 addresses not swapped,1: Bank 1 and bank 2 addresses swapped" newline bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog selected,1: Software window watchdog selected" newline bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter frozen in Standby..,1: Independent watchdog counter running in Standby.." newline bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter frozen in Stop mode,1: Independent watchdog counter running in Stop mode" newline bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog selected,1: Software independent watchdog selected" newline bitfld.long 0x0 15. "SRAM1345_RST,SRAM1 SRAM3 SRAM4 and SRAM5 erase upon system reset" "0: SRAM1 SRAM3 SRAM4 and SRAM5 erased when a system..,1: SRAM1 SRAM3 SRAM4 and SRAM5 not erased when a.." newline bitfld.long 0x0 14. "nRST_SHDW,Reset generation in Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode" newline bitfld.long 0x0 13. "nRST_STDBY,Reset generation in Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode" newline bitfld.long 0x0 12. "nRST_STOP,Reset generation in Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode" newline bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset level" "0: BOR level 0 (reset level threshold around 1.7 V),1: BOR level 1 (reset level threshold around 2.0 V),2: BOR level 2 (reset level threshold around 2.2 V),3: BOR level 3 (reset level threshold around 2.5 V),4: BOR level 4 (reset level threshold around 2.8 V),?,?,?" newline hexmask.long.byte 0x0 0.--7. 1. "RDP,Readout protection level" line.long 0x4 "FLASH_NSBOOTADD0R,FLASH non-secure boot address 0 register" hexmask.long 0x4 7.--31. 1. "NSBOOTADD0,Non-secure boot base address 0" line.long 0x8 "FLASH_NSBOOTADD1R,FLASH non-secure boot address 1 register" hexmask.long 0x8 7.--31. 1. "NSBOOTADD1,Non-secure boot address 1" line.long 0xC "FLASH_SECBOOTADD0R,FLASH secure boot address 0 register" hexmask.long 0xC 7.--31. 1. "SECBOOTADD0,Secure boot base address 0" newline bitfld.long 0xC 0. "BOOT_LOCK,Boot lock" "0,1" line.long 0x10 "FLASH_SECWM1R1,FLASH secure watermark1 register 1" hexmask.long.byte 0x10 16.--23. 1. "SECWM1_PEND,End page of first secure area" newline hexmask.long.byte 0x10 0.--7. 1. "SECWM1_PSTRT,Start page of first secure area" line.long 0x14 "FLASH_SECWM1R2,FLASH secure watermark1 register 2" bitfld.long 0x14 31. "HDP1EN,Hide protection first area enable" "0: No HDP area 1,1: HDP first area enabled" newline hexmask.long.byte 0x14 16.--23. 1. "HDP1_PEND,End page of first hide protection area" newline bitfld.long 0x14 15. "PCROP1EN,PCROP1 area enable" "0: PCROP1 area disabled,1: PCROP1 area enabled" newline hexmask.long.byte 0x14 0.--7. 1. "PCROP1_PSTRT,Start page of first PCROP area" line.long 0x18 "FLASH_WRP1AR,FLASH WRP1 area A address register" bitfld.long 0x18 31. "UNLOCK,Bank 1 WPR first area A unlock" "0: WRP1A start and end pages locked,1: WRP1A start and end pages unlocked" newline hexmask.long.byte 0x18 16.--23. 1. "WRP1A_PEND,Bank 1 WPR first area A end page" newline hexmask.long.byte 0x18 0.--7. 1. "WRP1A_PSTRT,bank 1 WPR first area A start page" line.long 0x1C "FLASH_WRP1BR,FLASH WRP1 area B address register" bitfld.long 0x1C 31. "UNLOCK,Bank 1 WPR second area B unlock" "0: WRP1B start and end pages locked,1: WRP1B start and end pages unlocked" newline hexmask.long.byte 0x1C 16.--23. 1. "WRP1B_PEND,Bank 1 WRP second area B end page" newline hexmask.long.byte 0x1C 0.--7. 1. "WRP1B_PSTRT,Bank 1 WRP second area B start page" line.long 0x20 "FLASH_SECWM2R1,FLASH secure watermark2 register 1" hexmask.long.byte 0x20 16.--23. 1. "SECWM2_PEND,End page of second secure area" newline hexmask.long.byte 0x20 0.--7. 1. "SECWM2_PSTRT,Start page of second secure area" line.long 0x24 "FLASH_SECWM2R2,FLASH secure watermark2 register 2" bitfld.long 0x24 31. "HDP2EN,Hide protection second area enable" "0: No HDP area 2,1: HDP second area is enabled." newline hexmask.long.byte 0x24 16.--23. 1. "HDP2_PEND,End page of hide protection second area" newline bitfld.long 0x24 15. "PCROP2EN,PCROP2 area enable" "0: PCROP2 area is disabled,1: PCROP2 area is enabled" newline hexmask.long.byte 0x24 0.--7. 1. "PCROP2_PSTRT,Start page of PCROP2 area" line.long 0x28 "FLASH_WRP2AR,FLASH WPR2 area A address register" bitfld.long 0x28 31. "UNLOCK,Bank 2 WPR first area A unlock" "0: WRP2A start and end pages locked,1: WRP2A start and end pages unlocked" newline hexmask.long.byte 0x28 16.--23. 1. "WRP2A_PEND,Bank 2 WPR first area A end page" newline hexmask.long.byte 0x28 0.--7. 1. "WRP2A_PSTRT,Bank 2 WPR first area A start page" line.long 0x2C "FLASH_WRP2BR,FLASH WPR2 area B address register" bitfld.long 0x2C 31. "UNLOCK,Bank 2 WPR second area B unlock" "0: WRP2B start and end pages locked,1: WRP2B start and end pages unlocked" newline hexmask.long.byte 0x2C 16.--23. 1. "WRP2B_PEND,Bank 2 WPR second area B end page" newline hexmask.long.byte 0x2C 0.--7. 1. "WRP2B_PSTRT,Bank 2 WPR second area B start page" wgroup.long 0x70++0xF line.long 0x0 "FLASH_OEM1KEYR1,FLASH OEM1 key register 1" hexmask.long 0x0 0.--31. 1. "OEM1KEY,OEM1 least significant bytes key" line.long 0x4 "FLASH_OEM1KEYR2,FLASH OEM1 key register 2" hexmask.long 0x4 0.--31. 1. "OEM1KEY,OEM1 most significant bytes key" line.long 0x8 "FLASH_OEM2KEYR1,FLASH OEM2 key register 1" hexmask.long 0x8 0.--31. 1. "OEM2KEY,OEM2 least significant bytes key" line.long 0xC "FLASH_OEM2KEYR2,FLASH OEM2 key register 2" hexmask.long 0xC 0.--31. 1. "OEM2KEY,OEM2 most significant bytes key" group.long 0x80++0x47 line.long 0x0 "FLASH_SEC1BBR1,FLASH secure block based bank 1 register 1" bitfld.long 0x0 31. "SEC1BB31," "0,1" newline bitfld.long 0x0 30. "SEC1BB30," "0,1" newline bitfld.long 0x0 29. "SEC1BB29," "0,1" newline bitfld.long 0x0 28. "SEC1BB28," "0,1" newline bitfld.long 0x0 27. "SEC1BB27," "0,1" newline bitfld.long 0x0 26. "SEC1BB26," "0,1" newline bitfld.long 0x0 25. "SEC1BB25," "0,1" newline bitfld.long 0x0 24. "SEC1BB24," "0,1" newline bitfld.long 0x0 23. "SEC1BB23," "0,1" newline bitfld.long 0x0 22. "SEC1BB22," "0,1" newline bitfld.long 0x0 21. "SEC1BB21," "0,1" newline bitfld.long 0x0 20. "SEC1BB20," "0,1" newline bitfld.long 0x0 19. "SEC1BB19," "0,1" newline bitfld.long 0x0 18. "SEC1BB18," "0,1" newline bitfld.long 0x0 17. "SEC1BB17," "0,1" newline bitfld.long 0x0 16. "SEC1BB16," "0,1" newline bitfld.long 0x0 15. "SEC1BB15," "0,1" newline bitfld.long 0x0 14. "SEC1BB14," "0,1" newline bitfld.long 0x0 13. "SEC1BB13," "0,1" newline bitfld.long 0x0 12. "SEC1BB12," "0,1" newline bitfld.long 0x0 11. "SEC1BB11," "0,1" newline bitfld.long 0x0 10. "SEC1BB10," "0,1" newline bitfld.long 0x0 9. "SEC1BB9," "0,1" newline bitfld.long 0x0 8. "SEC1BB8," "0,1" newline bitfld.long 0x0 7. "SEC1BB7," "0,1" newline bitfld.long 0x0 6. "SEC1BB6," "0,1" newline bitfld.long 0x0 5. "SEC1BB5," "0,1" newline bitfld.long 0x0 4. "SEC1BB4," "0,1" newline bitfld.long 0x0 3. "SEC1BB3," "0,1" newline bitfld.long 0x0 2. "SEC1BB2," "0,1" newline bitfld.long 0x0 1. "SEC1BB1," "0,1" newline bitfld.long 0x0 0. "SEC1BB0," "0,1" line.long 0x4 "FLASH_SEC1BBR2,FLASH secure block based bank 1 register 2" bitfld.long 0x4 31. "SEC1BB31," "0,1" newline bitfld.long 0x4 30. "SEC1BB30," "0,1" newline bitfld.long 0x4 29. "SEC1BB29," "0,1" newline bitfld.long 0x4 28. "SEC1BB28," "0,1" newline bitfld.long 0x4 27. "SEC1BB27," "0,1" newline bitfld.long 0x4 26. "SEC1BB26," "0,1" newline bitfld.long 0x4 25. "SEC1BB25," "0,1" newline bitfld.long 0x4 24. "SEC1BB24," "0,1" newline bitfld.long 0x4 23. "SEC1BB23," "0,1" newline bitfld.long 0x4 22. "SEC1BB22," "0,1" newline bitfld.long 0x4 21. "SEC1BB21," "0,1" newline bitfld.long 0x4 20. "SEC1BB20," "0,1" newline bitfld.long 0x4 19. "SEC1BB19," "0,1" newline bitfld.long 0x4 18. "SEC1BB18," "0,1" newline bitfld.long 0x4 17. "SEC1BB17," "0,1" newline bitfld.long 0x4 16. "SEC1BB16," "0,1" newline bitfld.long 0x4 15. "SEC1BB15," "0,1" newline bitfld.long 0x4 14. "SEC1BB14," "0,1" newline bitfld.long 0x4 13. "SEC1BB13," "0,1" newline bitfld.long 0x4 12. "SEC1BB12," "0,1" newline bitfld.long 0x4 11. "SEC1BB11," "0,1" newline bitfld.long 0x4 10. "SEC1BB10," "0,1" newline bitfld.long 0x4 9. "SEC1BB9," "0,1" newline bitfld.long 0x4 8. "SEC1BB8," "0,1" newline bitfld.long 0x4 7. "SEC1BB7," "0,1" newline bitfld.long 0x4 6. "SEC1BB6," "0,1" newline bitfld.long 0x4 5. "SEC1BB5," "0,1" newline bitfld.long 0x4 4. "SEC1BB4," "0,1" newline bitfld.long 0x4 3. "SEC1BB3," "0,1" newline bitfld.long 0x4 2. "SEC1BB2," "0,1" newline bitfld.long 0x4 1. "SEC1BB1," "0,1" newline bitfld.long 0x4 0. "SEC1BB0," "0,1" line.long 0x8 "FLASH_SEC1BBR3,FLASH secure block based bank 1 register 3" bitfld.long 0x8 31. "SEC1BB31," "0,1" newline bitfld.long 0x8 30. "SEC1BB30," "0,1" newline bitfld.long 0x8 29. "SEC1BB29," "0,1" newline bitfld.long 0x8 28. "SEC1BB28," "0,1" newline bitfld.long 0x8 27. "SEC1BB27," "0,1" newline bitfld.long 0x8 26. "SEC1BB26," "0,1" newline bitfld.long 0x8 25. "SEC1BB25," "0,1" newline bitfld.long 0x8 24. "SEC1BB24," "0,1" newline bitfld.long 0x8 23. "SEC1BB23," "0,1" newline bitfld.long 0x8 22. "SEC1BB22," "0,1" newline bitfld.long 0x8 21. "SEC1BB21," "0,1" newline bitfld.long 0x8 20. "SEC1BB20," "0,1" newline bitfld.long 0x8 19. "SEC1BB19," "0,1" newline bitfld.long 0x8 18. "SEC1BB18," "0,1" newline bitfld.long 0x8 17. "SEC1BB17," "0,1" newline bitfld.long 0x8 16. "SEC1BB16," "0,1" newline bitfld.long 0x8 15. "SEC1BB15," "0,1" newline bitfld.long 0x8 14. "SEC1BB14," "0,1" newline bitfld.long 0x8 13. "SEC1BB13," "0,1" newline bitfld.long 0x8 12. "SEC1BB12," "0,1" newline bitfld.long 0x8 11. "SEC1BB11," "0,1" newline bitfld.long 0x8 10. "SEC1BB10," "0,1" newline bitfld.long 0x8 9. "SEC1BB9," "0,1" newline bitfld.long 0x8 8. "SEC1BB8," "0,1" newline bitfld.long 0x8 7. "SEC1BB7," "0,1" newline bitfld.long 0x8 6. "SEC1BB6," "0,1" newline bitfld.long 0x8 5. "SEC1BB5," "0,1" newline bitfld.long 0x8 4. "SEC1BB4," "0,1" newline bitfld.long 0x8 3. "SEC1BB3," "0,1" newline bitfld.long 0x8 2. "SEC1BB2," "0,1" newline bitfld.long 0x8 1. "SEC1BB1," "0,1" newline bitfld.long 0x8 0. "SEC1BB0," "0,1" line.long 0xC "FLASH_SEC1BBR4,FLASH secure block based bank 1 register 4" bitfld.long 0xC 31. "SEC1BB31," "0,1" newline bitfld.long 0xC 30. "SEC1BB30," "0,1" newline bitfld.long 0xC 29. "SEC1BB29," "0,1" newline bitfld.long 0xC 28. "SEC1BB28," "0,1" newline bitfld.long 0xC 27. "SEC1BB27," "0,1" newline bitfld.long 0xC 26. "SEC1BB26," "0,1" newline bitfld.long 0xC 25. "SEC1BB25," "0,1" newline bitfld.long 0xC 24. "SEC1BB24," "0,1" newline bitfld.long 0xC 23. "SEC1BB23," "0,1" newline bitfld.long 0xC 22. "SEC1BB22," "0,1" newline bitfld.long 0xC 21. "SEC1BB21," "0,1" newline bitfld.long 0xC 20. "SEC1BB20," "0,1" newline bitfld.long 0xC 19. "SEC1BB19," "0,1" newline bitfld.long 0xC 18. "SEC1BB18," "0,1" newline bitfld.long 0xC 17. "SEC1BB17," "0,1" newline bitfld.long 0xC 16. "SEC1BB16," "0,1" newline bitfld.long 0xC 15. "SEC1BB15," "0,1" newline bitfld.long 0xC 14. "SEC1BB14," "0,1" newline bitfld.long 0xC 13. "SEC1BB13," "0,1" newline bitfld.long 0xC 12. "SEC1BB12," "0,1" newline bitfld.long 0xC 11. "SEC1BB11," "0,1" newline bitfld.long 0xC 10. "SEC1BB10," "0,1" newline bitfld.long 0xC 9. "SEC1BB9," "0,1" newline bitfld.long 0xC 8. "SEC1BB8," "0,1" newline bitfld.long 0xC 7. "SEC1BB7," "0,1" newline bitfld.long 0xC 6. "SEC1BB6," "0,1" newline bitfld.long 0xC 5. "SEC1BB5," "0,1" newline bitfld.long 0xC 4. "SEC1BB4," "0,1" newline bitfld.long 0xC 3. "SEC1BB3," "0,1" newline bitfld.long 0xC 2. "SEC1BB2," "0,1" newline bitfld.long 0xC 1. "SEC1BB1," "0,1" newline bitfld.long 0xC 0. "SEC1BB0," "0,1" line.long 0x10 "FLASH_SEC1BBR5,FLASH secure block based bank 1 register 5" bitfld.long 0x10 31. "SEC1BB31," "0,1" newline bitfld.long 0x10 30. "SEC1BB30," "0,1" newline bitfld.long 0x10 29. "SEC1BB29," "0,1" newline bitfld.long 0x10 28. "SEC1BB28," "0,1" newline bitfld.long 0x10 27. "SEC1BB27," "0,1" newline bitfld.long 0x10 26. "SEC1BB26," "0,1" newline bitfld.long 0x10 25. "SEC1BB25," "0,1" newline bitfld.long 0x10 24. "SEC1BB24," "0,1" newline bitfld.long 0x10 23. "SEC1BB23," "0,1" newline bitfld.long 0x10 22. "SEC1BB22," "0,1" newline bitfld.long 0x10 21. "SEC1BB21," "0,1" newline bitfld.long 0x10 20. "SEC1BB20," "0,1" newline bitfld.long 0x10 19. "SEC1BB19," "0,1" newline bitfld.long 0x10 18. "SEC1BB18," "0,1" newline bitfld.long 0x10 17. "SEC1BB17," "0,1" newline bitfld.long 0x10 16. "SEC1BB16," "0,1" newline bitfld.long 0x10 15. "SEC1BB15," "0,1" newline bitfld.long 0x10 14. "SEC1BB14," "0,1" newline bitfld.long 0x10 13. "SEC1BB13," "0,1" newline bitfld.long 0x10 12. "SEC1BB12," "0,1" newline bitfld.long 0x10 11. "SEC1BB11," "0,1" newline bitfld.long 0x10 10. "SEC1BB10," "0,1" newline bitfld.long 0x10 9. "SEC1BB9," "0,1" newline bitfld.long 0x10 8. "SEC1BB8," "0,1" newline bitfld.long 0x10 7. "SEC1BB7," "0,1" newline bitfld.long 0x10 6. "SEC1BB6," "0,1" newline bitfld.long 0x10 5. "SEC1BB5," "0,1" newline bitfld.long 0x10 4. "SEC1BB4," "0,1" newline bitfld.long 0x10 3. "SEC1BB3," "0,1" newline bitfld.long 0x10 2. "SEC1BB2," "0,1" newline bitfld.long 0x10 1. "SEC1BB1," "0,1" newline bitfld.long 0x10 0. "SEC1BB0," "0,1" line.long 0x14 "FLASH_SEC1BBR6,FLASH secure block based bank 1 register 6" bitfld.long 0x14 31. "SEC1BB31," "0,1" newline bitfld.long 0x14 30. "SEC1BB30," "0,1" newline bitfld.long 0x14 29. "SEC1BB29," "0,1" newline bitfld.long 0x14 28. "SEC1BB28," "0,1" newline bitfld.long 0x14 27. "SEC1BB27," "0,1" newline bitfld.long 0x14 26. "SEC1BB26," "0,1" newline bitfld.long 0x14 25. "SEC1BB25," "0,1" newline bitfld.long 0x14 24. "SEC1BB24," "0,1" newline bitfld.long 0x14 23. "SEC1BB23," "0,1" newline bitfld.long 0x14 22. "SEC1BB22," "0,1" newline bitfld.long 0x14 21. "SEC1BB21," "0,1" newline bitfld.long 0x14 20. "SEC1BB20," "0,1" newline bitfld.long 0x14 19. "SEC1BB19," "0,1" newline bitfld.long 0x14 18. "SEC1BB18," "0,1" newline bitfld.long 0x14 17. "SEC1BB17," "0,1" newline bitfld.long 0x14 16. "SEC1BB16," "0,1" newline bitfld.long 0x14 15. "SEC1BB15," "0,1" newline bitfld.long 0x14 14. "SEC1BB14," "0,1" newline bitfld.long 0x14 13. "SEC1BB13," "0,1" newline bitfld.long 0x14 12. "SEC1BB12," "0,1" newline bitfld.long 0x14 11. "SEC1BB11," "0,1" newline bitfld.long 0x14 10. "SEC1BB10," "0,1" newline bitfld.long 0x14 9. "SEC1BB9," "0,1" newline bitfld.long 0x14 8. "SEC1BB8," "0,1" newline bitfld.long 0x14 7. "SEC1BB7," "0,1" newline bitfld.long 0x14 6. "SEC1BB6," "0,1" newline bitfld.long 0x14 5. "SEC1BB5," "0,1" newline bitfld.long 0x14 4. "SEC1BB4," "0,1" newline bitfld.long 0x14 3. "SEC1BB3," "0,1" newline bitfld.long 0x14 2. "SEC1BB2," "0,1" newline bitfld.long 0x14 1. "SEC1BB1," "0,1" newline bitfld.long 0x14 0. "SEC1BB0," "0,1" line.long 0x18 "FLASH_SEC1BBR7,FLASH secure block based bank 1 register 7" bitfld.long 0x18 31. "SEC1BB31," "0,1" newline bitfld.long 0x18 30. "SEC1BB30," "0,1" newline bitfld.long 0x18 29. "SEC1BB29," "0,1" newline bitfld.long 0x18 28. "SEC1BB28," "0,1" newline bitfld.long 0x18 27. "SEC1BB27," "0,1" newline bitfld.long 0x18 26. "SEC1BB26," "0,1" newline bitfld.long 0x18 25. "SEC1BB25," "0,1" newline bitfld.long 0x18 24. "SEC1BB24," "0,1" newline bitfld.long 0x18 23. "SEC1BB23," "0,1" newline bitfld.long 0x18 22. "SEC1BB22," "0,1" newline bitfld.long 0x18 21. "SEC1BB21," "0,1" newline bitfld.long 0x18 20. "SEC1BB20," "0,1" newline bitfld.long 0x18 19. "SEC1BB19," "0,1" newline bitfld.long 0x18 18. "SEC1BB18," "0,1" newline bitfld.long 0x18 17. "SEC1BB17," "0,1" newline bitfld.long 0x18 16. "SEC1BB16," "0,1" newline bitfld.long 0x18 15. "SEC1BB15," "0,1" newline bitfld.long 0x18 14. "SEC1BB14," "0,1" newline bitfld.long 0x18 13. "SEC1BB13," "0,1" newline bitfld.long 0x18 12. "SEC1BB12," "0,1" newline bitfld.long 0x18 11. "SEC1BB11," "0,1" newline bitfld.long 0x18 10. "SEC1BB10," "0,1" newline bitfld.long 0x18 9. "SEC1BB9," "0,1" newline bitfld.long 0x18 8. "SEC1BB8," "0,1" newline bitfld.long 0x18 7. "SEC1BB7," "0,1" newline bitfld.long 0x18 6. "SEC1BB6," "0,1" newline bitfld.long 0x18 5. "SEC1BB5," "0,1" newline bitfld.long 0x18 4. "SEC1BB4," "0,1" newline bitfld.long 0x18 3. "SEC1BB3," "0,1" newline bitfld.long 0x18 2. "SEC1BB2," "0,1" newline bitfld.long 0x18 1. "SEC1BB1," "0,1" newline bitfld.long 0x18 0. "SEC1BB0," "0,1" line.long 0x1C "FLASH_SEC1BBR8,FLASH secure block based bank 1 register 8" bitfld.long 0x1C 31. "SEC1BB31," "0,1" newline bitfld.long 0x1C 30. "SEC1BB30," "0,1" newline bitfld.long 0x1C 29. "SEC1BB29," "0,1" newline bitfld.long 0x1C 28. "SEC1BB28," "0,1" newline bitfld.long 0x1C 27. "SEC1BB27," "0,1" newline bitfld.long 0x1C 26. "SEC1BB26," "0,1" newline bitfld.long 0x1C 25. "SEC1BB25," "0,1" newline bitfld.long 0x1C 24. "SEC1BB24," "0,1" newline bitfld.long 0x1C 23. "SEC1BB23," "0,1" newline bitfld.long 0x1C 22. "SEC1BB22," "0,1" newline bitfld.long 0x1C 21. "SEC1BB21," "0,1" newline bitfld.long 0x1C 20. "SEC1BB20," "0,1" newline bitfld.long 0x1C 19. "SEC1BB19," "0,1" newline bitfld.long 0x1C 18. "SEC1BB18," "0,1" newline bitfld.long 0x1C 17. "SEC1BB17," "0,1" newline bitfld.long 0x1C 16. "SEC1BB16," "0,1" newline bitfld.long 0x1C 15. "SEC1BB15," "0,1" newline bitfld.long 0x1C 14. "SEC1BB14," "0,1" newline bitfld.long 0x1C 13. "SEC1BB13," "0,1" newline bitfld.long 0x1C 12. "SEC1BB12," "0,1" newline bitfld.long 0x1C 11. "SEC1BB11," "0,1" newline bitfld.long 0x1C 10. "SEC1BB10," "0,1" newline bitfld.long 0x1C 9. "SEC1BB9," "0,1" newline bitfld.long 0x1C 8. "SEC1BB8," "0,1" newline bitfld.long 0x1C 7. "SEC1BB7," "0,1" newline bitfld.long 0x1C 6. "SEC1BB6," "0,1" newline bitfld.long 0x1C 5. "SEC1BB5," "0,1" newline bitfld.long 0x1C 4. "SEC1BB4," "0,1" newline bitfld.long 0x1C 3. "SEC1BB3," "0,1" newline bitfld.long 0x1C 2. "SEC1BB2," "0,1" newline bitfld.long 0x1C 1. "SEC1BB1," "0,1" newline bitfld.long 0x1C 0. "SEC1BB0," "0,1" line.long 0x20 "FLASH_SEC2BBR1,FLASH secure block based bank 2 register 1" bitfld.long 0x20 31. "SEC2BB31," "0,1" newline bitfld.long 0x20 30. "SEC2BB30," "0,1" newline bitfld.long 0x20 29. "SEC2BB29," "0,1" newline bitfld.long 0x20 28. "SEC2BB28," "0,1" newline bitfld.long 0x20 27. "SEC2BB27," "0,1" newline bitfld.long 0x20 26. "SEC2BB26," "0,1" newline bitfld.long 0x20 25. "SEC2BB25," "0,1" newline bitfld.long 0x20 24. "SEC2BB24," "0,1" newline bitfld.long 0x20 23. "SEC2BB23," "0,1" newline bitfld.long 0x20 22. "SEC2BB22," "0,1" newline bitfld.long 0x20 21. "SEC2BB21," "0,1" newline bitfld.long 0x20 20. "SEC2BB20," "0,1" newline bitfld.long 0x20 19. "SEC2BB19," "0,1" newline bitfld.long 0x20 18. "SEC2BB18," "0,1" newline bitfld.long 0x20 17. "SEC2BB17," "0,1" newline bitfld.long 0x20 16. "SEC2BB16," "0,1" newline bitfld.long 0x20 15. "SEC2BB15," "0,1" newline bitfld.long 0x20 14. "SEC2BB14," "0,1" newline bitfld.long 0x20 13. "SEC2BB13," "0,1" newline bitfld.long 0x20 12. "SEC2BB12," "0,1" newline bitfld.long 0x20 11. "SEC2BB11," "0,1" newline bitfld.long 0x20 10. "SEC2BB10," "0,1" newline bitfld.long 0x20 9. "SEC2BB9," "0,1" newline bitfld.long 0x20 8. "SEC2BB8," "0,1" newline bitfld.long 0x20 7. "SEC2BB7," "0,1" newline bitfld.long 0x20 6. "SEC2BB6," "0,1" newline bitfld.long 0x20 5. "SEC2BB5," "0,1" newline bitfld.long 0x20 4. "SEC2BB4," "0,1" newline bitfld.long 0x20 3. "SEC2BB3," "0,1" newline bitfld.long 0x20 2. "SEC2BB2," "0,1" newline bitfld.long 0x20 1. "SEC2BB1," "0,1" newline bitfld.long 0x20 0. "SEC2BB0," "0,1" line.long 0x24 "FLASH_SEC2BBR2,FLASH secure block based bank 2 register 2" bitfld.long 0x24 31. "SEC2BB31," "0,1" newline bitfld.long 0x24 30. "SEC2BB30," "0,1" newline bitfld.long 0x24 29. "SEC2BB29," "0,1" newline bitfld.long 0x24 28. "SEC2BB28," "0,1" newline bitfld.long 0x24 27. "SEC2BB27," "0,1" newline bitfld.long 0x24 26. "SEC2BB26," "0,1" newline bitfld.long 0x24 25. "SEC2BB25," "0,1" newline bitfld.long 0x24 24. "SEC2BB24," "0,1" newline bitfld.long 0x24 23. "SEC2BB23," "0,1" newline bitfld.long 0x24 22. "SEC2BB22," "0,1" newline bitfld.long 0x24 21. "SEC2BB21," "0,1" newline bitfld.long 0x24 20. "SEC2BB20," "0,1" newline bitfld.long 0x24 19. "SEC2BB19," "0,1" newline bitfld.long 0x24 18. "SEC2BB18," "0,1" newline bitfld.long 0x24 17. "SEC2BB17," "0,1" newline bitfld.long 0x24 16. "SEC2BB16," "0,1" newline bitfld.long 0x24 15. "SEC2BB15," "0,1" newline bitfld.long 0x24 14. "SEC2BB14," "0,1" newline bitfld.long 0x24 13. "SEC2BB13," "0,1" newline bitfld.long 0x24 12. "SEC2BB12," "0,1" newline bitfld.long 0x24 11. "SEC2BB11," "0,1" newline bitfld.long 0x24 10. "SEC2BB10," "0,1" newline bitfld.long 0x24 9. "SEC2BB9," "0,1" newline bitfld.long 0x24 8. "SEC2BB8," "0,1" newline bitfld.long 0x24 7. "SEC2BB7," "0,1" newline bitfld.long 0x24 6. "SEC2BB6," "0,1" newline bitfld.long 0x24 5. "SEC2BB5," "0,1" newline bitfld.long 0x24 4. "SEC2BB4," "0,1" newline bitfld.long 0x24 3. "SEC2BB3," "0,1" newline bitfld.long 0x24 2. "SEC2BB2," "0,1" newline bitfld.long 0x24 1. "SEC2BB1," "0,1" newline bitfld.long 0x24 0. "SEC2BB0," "0,1" line.long 0x28 "FLASH_SEC2BBR3,FLASH secure block based bank 2 register 3" bitfld.long 0x28 31. "SEC2BB31," "0,1" newline bitfld.long 0x28 30. "SEC2BB30," "0,1" newline bitfld.long 0x28 29. "SEC2BB29," "0,1" newline bitfld.long 0x28 28. "SEC2BB28," "0,1" newline bitfld.long 0x28 27. "SEC2BB27," "0,1" newline bitfld.long 0x28 26. "SEC2BB26," "0,1" newline bitfld.long 0x28 25. "SEC2BB25," "0,1" newline bitfld.long 0x28 24. "SEC2BB24," "0,1" newline bitfld.long 0x28 23. "SEC2BB23," "0,1" newline bitfld.long 0x28 22. "SEC2BB22," "0,1" newline bitfld.long 0x28 21. "SEC2BB21," "0,1" newline bitfld.long 0x28 20. "SEC2BB20," "0,1" newline bitfld.long 0x28 19. "SEC2BB19," "0,1" newline bitfld.long 0x28 18. "SEC2BB18," "0,1" newline bitfld.long 0x28 17. "SEC2BB17," "0,1" newline bitfld.long 0x28 16. "SEC2BB16," "0,1" newline bitfld.long 0x28 15. "SEC2BB15," "0,1" newline bitfld.long 0x28 14. "SEC2BB14," "0,1" newline bitfld.long 0x28 13. "SEC2BB13," "0,1" newline bitfld.long 0x28 12. "SEC2BB12," "0,1" newline bitfld.long 0x28 11. "SEC2BB11," "0,1" newline bitfld.long 0x28 10. "SEC2BB10," "0,1" newline bitfld.long 0x28 9. "SEC2BB9," "0,1" newline bitfld.long 0x28 8. "SEC2BB8," "0,1" newline bitfld.long 0x28 7. "SEC2BB7," "0,1" newline bitfld.long 0x28 6. "SEC2BB6," "0,1" newline bitfld.long 0x28 5. "SEC2BB5," "0,1" newline bitfld.long 0x28 4. "SEC2BB4," "0,1" newline bitfld.long 0x28 3. "SEC2BB3," "0,1" newline bitfld.long 0x28 2. "SEC2BB2," "0,1" newline bitfld.long 0x28 1. "SEC2BB1," "0,1" newline bitfld.long 0x28 0. "SEC2BB0," "0,1" line.long 0x2C "FLASH_SEC2BBR4,FLASH secure block based bank 2 register 4" bitfld.long 0x2C 31. "SEC2BB31," "0,1" newline bitfld.long 0x2C 30. "SEC2BB30," "0,1" newline bitfld.long 0x2C 29. "SEC2BB29," "0,1" newline bitfld.long 0x2C 28. "SEC2BB28," "0,1" newline bitfld.long 0x2C 27. "SEC2BB27," "0,1" newline bitfld.long 0x2C 26. "SEC2BB26," "0,1" newline bitfld.long 0x2C 25. "SEC2BB25," "0,1" newline bitfld.long 0x2C 24. "SEC2BB24," "0,1" newline bitfld.long 0x2C 23. "SEC2BB23," "0,1" newline bitfld.long 0x2C 22. "SEC2BB22," "0,1" newline bitfld.long 0x2C 21. "SEC2BB21," "0,1" newline bitfld.long 0x2C 20. "SEC2BB20," "0,1" newline bitfld.long 0x2C 19. "SEC2BB19," "0,1" newline bitfld.long 0x2C 18. "SEC2BB18," "0,1" newline bitfld.long 0x2C 17. "SEC2BB17," "0,1" newline bitfld.long 0x2C 16. "SEC2BB16," "0,1" newline bitfld.long 0x2C 15. "SEC2BB15," "0,1" newline bitfld.long 0x2C 14. "SEC2BB14," "0,1" newline bitfld.long 0x2C 13. "SEC2BB13," "0,1" newline bitfld.long 0x2C 12. "SEC2BB12," "0,1" newline bitfld.long 0x2C 11. "SEC2BB11," "0,1" newline bitfld.long 0x2C 10. "SEC2BB10," "0,1" newline bitfld.long 0x2C 9. "SEC2BB9," "0,1" newline bitfld.long 0x2C 8. "SEC2BB8," "0,1" newline bitfld.long 0x2C 7. "SEC2BB7," "0,1" newline bitfld.long 0x2C 6. "SEC2BB6," "0,1" newline bitfld.long 0x2C 5. "SEC2BB5," "0,1" newline bitfld.long 0x2C 4. "SEC2BB4," "0,1" newline bitfld.long 0x2C 3. "SEC2BB3," "0,1" newline bitfld.long 0x2C 2. "SEC2BB2," "0,1" newline bitfld.long 0x2C 1. "SEC2BB1," "0,1" newline bitfld.long 0x2C 0. "SEC2BB0," "0,1" line.long 0x30 "FLASH_SEC2BBR5,FLASH secure block based bank 2 register 5" bitfld.long 0x30 31. "SEC2BB31," "0,1" newline bitfld.long 0x30 30. "SEC2BB30," "0,1" newline bitfld.long 0x30 29. "SEC2BB29," "0,1" newline bitfld.long 0x30 28. "SEC2BB28," "0,1" newline bitfld.long 0x30 27. "SEC2BB27," "0,1" newline bitfld.long 0x30 26. "SEC2BB26," "0,1" newline bitfld.long 0x30 25. "SEC2BB25," "0,1" newline bitfld.long 0x30 24. "SEC2BB24," "0,1" newline bitfld.long 0x30 23. "SEC2BB23," "0,1" newline bitfld.long 0x30 22. "SEC2BB22," "0,1" newline bitfld.long 0x30 21. "SEC2BB21," "0,1" newline bitfld.long 0x30 20. "SEC2BB20," "0,1" newline bitfld.long 0x30 19. "SEC2BB19," "0,1" newline bitfld.long 0x30 18. "SEC2BB18," "0,1" newline bitfld.long 0x30 17. "SEC2BB17," "0,1" newline bitfld.long 0x30 16. "SEC2BB16," "0,1" newline bitfld.long 0x30 15. "SEC2BB15," "0,1" newline bitfld.long 0x30 14. "SEC2BB14," "0,1" newline bitfld.long 0x30 13. "SEC2BB13," "0,1" newline bitfld.long 0x30 12. "SEC2BB12," "0,1" newline bitfld.long 0x30 11. "SEC2BB11," "0,1" newline bitfld.long 0x30 10. "SEC2BB10," "0,1" newline bitfld.long 0x30 9. "SEC2BB9," "0,1" newline bitfld.long 0x30 8. "SEC2BB8," "0,1" newline bitfld.long 0x30 7. "SEC2BB7," "0,1" newline bitfld.long 0x30 6. "SEC2BB6," "0,1" newline bitfld.long 0x30 5. "SEC2BB5," "0,1" newline bitfld.long 0x30 4. "SEC2BB4," "0,1" newline bitfld.long 0x30 3. "SEC2BB3," "0,1" newline bitfld.long 0x30 2. "SEC2BB2," "0,1" newline bitfld.long 0x30 1. "SEC2BB1," "0,1" newline bitfld.long 0x30 0. "SEC2BB0," "0,1" line.long 0x34 "FLASH_SEC2BBR6,FLASH secure block based bank 2 register 6" bitfld.long 0x34 31. "SEC2BB31," "0,1" newline bitfld.long 0x34 30. "SEC2BB30," "0,1" newline bitfld.long 0x34 29. "SEC2BB29," "0,1" newline bitfld.long 0x34 28. "SEC2BB28," "0,1" newline bitfld.long 0x34 27. "SEC2BB27," "0,1" newline bitfld.long 0x34 26. "SEC2BB26," "0,1" newline bitfld.long 0x34 25. "SEC2BB25," "0,1" newline bitfld.long 0x34 24. "SEC2BB24," "0,1" newline bitfld.long 0x34 23. "SEC2BB23," "0,1" newline bitfld.long 0x34 22. "SEC2BB22," "0,1" newline bitfld.long 0x34 21. "SEC2BB21," "0,1" newline bitfld.long 0x34 20. "SEC2BB20," "0,1" newline bitfld.long 0x34 19. "SEC2BB19," "0,1" newline bitfld.long 0x34 18. "SEC2BB18," "0,1" newline bitfld.long 0x34 17. "SEC2BB17," "0,1" newline bitfld.long 0x34 16. "SEC2BB16," "0,1" newline bitfld.long 0x34 15. "SEC2BB15," "0,1" newline bitfld.long 0x34 14. "SEC2BB14," "0,1" newline bitfld.long 0x34 13. "SEC2BB13," "0,1" newline bitfld.long 0x34 12. "SEC2BB12," "0,1" newline bitfld.long 0x34 11. "SEC2BB11," "0,1" newline bitfld.long 0x34 10. "SEC2BB10," "0,1" newline bitfld.long 0x34 9. "SEC2BB9," "0,1" newline bitfld.long 0x34 8. "SEC2BB8," "0,1" newline bitfld.long 0x34 7. "SEC2BB7," "0,1" newline bitfld.long 0x34 6. "SEC2BB6," "0,1" newline bitfld.long 0x34 5. "SEC2BB5," "0,1" newline bitfld.long 0x34 4. "SEC2BB4," "0,1" newline bitfld.long 0x34 3. "SEC2BB3," "0,1" newline bitfld.long 0x34 2. "SEC2BB2," "0,1" newline bitfld.long 0x34 1. "SEC2BB1," "0,1" newline bitfld.long 0x34 0. "SEC2BB0," "0,1" line.long 0x38 "FLASH_SEC2BBR7,FLASH secure block based bank 2 register 7" bitfld.long 0x38 31. "SEC2BB31," "0,1" newline bitfld.long 0x38 30. "SEC2BB30," "0,1" newline bitfld.long 0x38 29. "SEC2BB29," "0,1" newline bitfld.long 0x38 28. "SEC2BB28," "0,1" newline bitfld.long 0x38 27. "SEC2BB27," "0,1" newline bitfld.long 0x38 26. "SEC2BB26," "0,1" newline bitfld.long 0x38 25. "SEC2BB25," "0,1" newline bitfld.long 0x38 24. "SEC2BB24," "0,1" newline bitfld.long 0x38 23. "SEC2BB23," "0,1" newline bitfld.long 0x38 22. "SEC2BB22," "0,1" newline bitfld.long 0x38 21. "SEC2BB21," "0,1" newline bitfld.long 0x38 20. "SEC2BB20," "0,1" newline bitfld.long 0x38 19. "SEC2BB19," "0,1" newline bitfld.long 0x38 18. "SEC2BB18," "0,1" newline bitfld.long 0x38 17. "SEC2BB17," "0,1" newline bitfld.long 0x38 16. "SEC2BB16," "0,1" newline bitfld.long 0x38 15. "SEC2BB15," "0,1" newline bitfld.long 0x38 14. "SEC2BB14," "0,1" newline bitfld.long 0x38 13. "SEC2BB13," "0,1" newline bitfld.long 0x38 12. "SEC2BB12," "0,1" newline bitfld.long 0x38 11. "SEC2BB11," "0,1" newline bitfld.long 0x38 10. "SEC2BB10," "0,1" newline bitfld.long 0x38 9. "SEC2BB9," "0,1" newline bitfld.long 0x38 8. "SEC2BB8," "0,1" newline bitfld.long 0x38 7. "SEC2BB7," "0,1" newline bitfld.long 0x38 6. "SEC2BB6," "0,1" newline bitfld.long 0x38 5. "SEC2BB5," "0,1" newline bitfld.long 0x38 4. "SEC2BB4," "0,1" newline bitfld.long 0x38 3. "SEC2BB3," "0,1" newline bitfld.long 0x38 2. "SEC2BB2," "0,1" newline bitfld.long 0x38 1. "SEC2BB1," "0,1" newline bitfld.long 0x38 0. "SEC2BB0," "0,1" line.long 0x3C "FLASH_SEC2BBR8,FLASH secure block based bank 2 register 8" bitfld.long 0x3C 31. "SEC2BB31," "0,1" newline bitfld.long 0x3C 30. "SEC2BB30," "0,1" newline bitfld.long 0x3C 29. "SEC2BB29," "0,1" newline bitfld.long 0x3C 28. "SEC2BB28," "0,1" newline bitfld.long 0x3C 27. "SEC2BB27," "0,1" newline bitfld.long 0x3C 26. "SEC2BB26," "0,1" newline bitfld.long 0x3C 25. "SEC2BB25," "0,1" newline bitfld.long 0x3C 24. "SEC2BB24," "0,1" newline bitfld.long 0x3C 23. "SEC2BB23," "0,1" newline bitfld.long 0x3C 22. "SEC2BB22," "0,1" newline bitfld.long 0x3C 21. "SEC2BB21," "0,1" newline bitfld.long 0x3C 20. "SEC2BB20," "0,1" newline bitfld.long 0x3C 19. "SEC2BB19," "0,1" newline bitfld.long 0x3C 18. "SEC2BB18," "0,1" newline bitfld.long 0x3C 17. "SEC2BB17," "0,1" newline bitfld.long 0x3C 16. "SEC2BB16," "0,1" newline bitfld.long 0x3C 15. "SEC2BB15," "0,1" newline bitfld.long 0x3C 14. "SEC2BB14," "0,1" newline bitfld.long 0x3C 13. "SEC2BB13," "0,1" newline bitfld.long 0x3C 12. "SEC2BB12," "0,1" newline bitfld.long 0x3C 11. "SEC2BB11," "0,1" newline bitfld.long 0x3C 10. "SEC2BB10," "0,1" newline bitfld.long 0x3C 9. "SEC2BB9," "0,1" newline bitfld.long 0x3C 8. "SEC2BB8," "0,1" newline bitfld.long 0x3C 7. "SEC2BB7," "0,1" newline bitfld.long 0x3C 6. "SEC2BB6," "0,1" newline bitfld.long 0x3C 5. "SEC2BB5," "0,1" newline bitfld.long 0x3C 4. "SEC2BB4," "0,1" newline bitfld.long 0x3C 3. "SEC2BB3," "0,1" newline bitfld.long 0x3C 2. "SEC2BB2," "0,1" newline bitfld.long 0x3C 1. "SEC2BB1," "0,1" newline bitfld.long 0x3C 0. "SEC2BB0," "0,1" line.long 0x40 "FLASH_SECHDPCR,FLASH secure HDP control register" bitfld.long 0x40 1. "HDP2_ACCDIS,HDP2 area access disable" "0: Access to HDP2 area granted,1: Access to HDP2 area denied (SECWM2Ry option.." newline bitfld.long 0x40 0. "HDP1_ACCDIS,HDP1 area access disable" "0: Access to HDP1 area granted,1: Access to HDP1 area denied (SECWM1Ry option.." line.long 0x44 "FLASH_PRIVCFGR,FLASH privilege configuration register" bitfld.long 0x44 1. "NSPRIV,Privileged protection for non-secure registers" "0,1" newline bitfld.long 0x44 0. "SPRIV,Privileged protection for secure registers" "0,1" group.long 0xD0++0x3F line.long 0x0 "FLASH_PRIV1BBR1,FLASH privilege block based bank 1 register 1" bitfld.long 0x0 31. "PRIV1BB31," "0,1" newline bitfld.long 0x0 30. "PRIV1BB30," "0,1" newline bitfld.long 0x0 29. "PRIV1BB29," "0,1" newline bitfld.long 0x0 28. "PRIV1BB28," "0,1" newline bitfld.long 0x0 27. "PRIV1BB27," "0,1" newline bitfld.long 0x0 26. "PRIV1BB26," "0,1" newline bitfld.long 0x0 25. "PRIV1BB25," "0,1" newline bitfld.long 0x0 24. "PRIV1BB24," "0,1" newline bitfld.long 0x0 23. "PRIV1BB23," "0,1" newline bitfld.long 0x0 22. "PRIV1BB22," "0,1" newline bitfld.long 0x0 21. "PRIV1BB21," "0,1" newline bitfld.long 0x0 20. "PRIV1BB20," "0,1" newline bitfld.long 0x0 19. "PRIV1BB19," "0,1" newline bitfld.long 0x0 18. "PRIV1BB18," "0,1" newline bitfld.long 0x0 17. "PRIV1BB17," "0,1" newline bitfld.long 0x0 16. "PRIV1BB16," "0,1" newline bitfld.long 0x0 15. "PRIV1BB15," "0,1" newline bitfld.long 0x0 14. "PRIV1BB14," "0,1" newline bitfld.long 0x0 13. "PRIV1BB13," "0,1" newline bitfld.long 0x0 12. "PRIV1BB12," "0,1" newline bitfld.long 0x0 11. "PRIV1BB11," "0,1" newline bitfld.long 0x0 10. "PRIV1BB10," "0,1" newline bitfld.long 0x0 9. "PRIV1BB9," "0,1" newline bitfld.long 0x0 8. "PRIV1BB8," "0,1" newline bitfld.long 0x0 7. "PRIV1BB7," "0,1" newline bitfld.long 0x0 6. "PRIV1BB6," "0,1" newline bitfld.long 0x0 5. "PRIV1BB5," "0,1" newline bitfld.long 0x0 4. "PRIV1BB4," "0,1" newline bitfld.long 0x0 3. "PRIV1BB3," "0,1" newline bitfld.long 0x0 2. "PRIV1BB2," "0,1" newline bitfld.long 0x0 1. "PRIV1BB1," "0,1" newline bitfld.long 0x0 0. "PRIV1BB0," "0,1" line.long 0x4 "FLASH_PRIV1BBR2,FLASH privilege block based bank 1 register 2" bitfld.long 0x4 31. "PRIV1BB31," "0,1" newline bitfld.long 0x4 30. "PRIV1BB30," "0,1" newline bitfld.long 0x4 29. "PRIV1BB29," "0,1" newline bitfld.long 0x4 28. "PRIV1BB28," "0,1" newline bitfld.long 0x4 27. "PRIV1BB27," "0,1" newline bitfld.long 0x4 26. "PRIV1BB26," "0,1" newline bitfld.long 0x4 25. "PRIV1BB25," "0,1" newline bitfld.long 0x4 24. "PRIV1BB24," "0,1" newline bitfld.long 0x4 23. "PRIV1BB23," "0,1" newline bitfld.long 0x4 22. "PRIV1BB22," "0,1" newline bitfld.long 0x4 21. "PRIV1BB21," "0,1" newline bitfld.long 0x4 20. "PRIV1BB20," "0,1" newline bitfld.long 0x4 19. "PRIV1BB19," "0,1" newline bitfld.long 0x4 18. "PRIV1BB18," "0,1" newline bitfld.long 0x4 17. "PRIV1BB17," "0,1" newline bitfld.long 0x4 16. "PRIV1BB16," "0,1" newline bitfld.long 0x4 15. "PRIV1BB15," "0,1" newline bitfld.long 0x4 14. "PRIV1BB14," "0,1" newline bitfld.long 0x4 13. "PRIV1BB13," "0,1" newline bitfld.long 0x4 12. "PRIV1BB12," "0,1" newline bitfld.long 0x4 11. "PRIV1BB11," "0,1" newline bitfld.long 0x4 10. "PRIV1BB10," "0,1" newline bitfld.long 0x4 9. "PRIV1BB9," "0,1" newline bitfld.long 0x4 8. "PRIV1BB8," "0,1" newline bitfld.long 0x4 7. "PRIV1BB7," "0,1" newline bitfld.long 0x4 6. "PRIV1BB6," "0,1" newline bitfld.long 0x4 5. "PRIV1BB5," "0,1" newline bitfld.long 0x4 4. "PRIV1BB4," "0,1" newline bitfld.long 0x4 3. "PRIV1BB3," "0,1" newline bitfld.long 0x4 2. "PRIV1BB2," "0,1" newline bitfld.long 0x4 1. "PRIV1BB1," "0,1" newline bitfld.long 0x4 0. "PRIV1BB0," "0,1" line.long 0x8 "FLASH_PRIV1BBR3,FLASH privilege block based bank 1 register 3" bitfld.long 0x8 31. "PRIV1BB31," "0,1" newline bitfld.long 0x8 30. "PRIV1BB30," "0,1" newline bitfld.long 0x8 29. "PRIV1BB29," "0,1" newline bitfld.long 0x8 28. "PRIV1BB28," "0,1" newline bitfld.long 0x8 27. "PRIV1BB27," "0,1" newline bitfld.long 0x8 26. "PRIV1BB26," "0,1" newline bitfld.long 0x8 25. "PRIV1BB25," "0,1" newline bitfld.long 0x8 24. "PRIV1BB24," "0,1" newline bitfld.long 0x8 23. "PRIV1BB23," "0,1" newline bitfld.long 0x8 22. "PRIV1BB22," "0,1" newline bitfld.long 0x8 21. "PRIV1BB21," "0,1" newline bitfld.long 0x8 20. "PRIV1BB20," "0,1" newline bitfld.long 0x8 19. "PRIV1BB19," "0,1" newline bitfld.long 0x8 18. "PRIV1BB18," "0,1" newline bitfld.long 0x8 17. "PRIV1BB17," "0,1" newline bitfld.long 0x8 16. "PRIV1BB16," "0,1" newline bitfld.long 0x8 15. "PRIV1BB15," "0,1" newline bitfld.long 0x8 14. "PRIV1BB14," "0,1" newline bitfld.long 0x8 13. "PRIV1BB13," "0,1" newline bitfld.long 0x8 12. "PRIV1BB12," "0,1" newline bitfld.long 0x8 11. "PRIV1BB11," "0,1" newline bitfld.long 0x8 10. "PRIV1BB10," "0,1" newline bitfld.long 0x8 9. "PRIV1BB9," "0,1" newline bitfld.long 0x8 8. "PRIV1BB8," "0,1" newline bitfld.long 0x8 7. "PRIV1BB7," "0,1" newline bitfld.long 0x8 6. "PRIV1BB6," "0,1" newline bitfld.long 0x8 5. "PRIV1BB5," "0,1" newline bitfld.long 0x8 4. "PRIV1BB4," "0,1" newline bitfld.long 0x8 3. "PRIV1BB3," "0,1" newline bitfld.long 0x8 2. "PRIV1BB2," "0,1" newline bitfld.long 0x8 1. "PRIV1BB1," "0,1" newline bitfld.long 0x8 0. "PRIV1BB0," "0,1" line.long 0xC "FLASH_PRIV1BBR4,FLASH privilege block based bank 1 register 4" bitfld.long 0xC 31. "PRIV1BB31," "0,1" newline bitfld.long 0xC 30. "PRIV1BB30," "0,1" newline bitfld.long 0xC 29. "PRIV1BB29," "0,1" newline bitfld.long 0xC 28. "PRIV1BB28," "0,1" newline bitfld.long 0xC 27. "PRIV1BB27," "0,1" newline bitfld.long 0xC 26. "PRIV1BB26," "0,1" newline bitfld.long 0xC 25. "PRIV1BB25," "0,1" newline bitfld.long 0xC 24. "PRIV1BB24," "0,1" newline bitfld.long 0xC 23. "PRIV1BB23," "0,1" newline bitfld.long 0xC 22. "PRIV1BB22," "0,1" newline bitfld.long 0xC 21. "PRIV1BB21," "0,1" newline bitfld.long 0xC 20. "PRIV1BB20," "0,1" newline bitfld.long 0xC 19. "PRIV1BB19," "0,1" newline bitfld.long 0xC 18. "PRIV1BB18," "0,1" newline bitfld.long 0xC 17. "PRIV1BB17," "0,1" newline bitfld.long 0xC 16. "PRIV1BB16," "0,1" newline bitfld.long 0xC 15. "PRIV1BB15," "0,1" newline bitfld.long 0xC 14. "PRIV1BB14," "0,1" newline bitfld.long 0xC 13. "PRIV1BB13," "0,1" newline bitfld.long 0xC 12. "PRIV1BB12," "0,1" newline bitfld.long 0xC 11. "PRIV1BB11," "0,1" newline bitfld.long 0xC 10. "PRIV1BB10," "0,1" newline bitfld.long 0xC 9. "PRIV1BB9," "0,1" newline bitfld.long 0xC 8. "PRIV1BB8," "0,1" newline bitfld.long 0xC 7. "PRIV1BB7," "0,1" newline bitfld.long 0xC 6. "PRIV1BB6," "0,1" newline bitfld.long 0xC 5. "PRIV1BB5," "0,1" newline bitfld.long 0xC 4. "PRIV1BB4," "0,1" newline bitfld.long 0xC 3. "PRIV1BB3," "0,1" newline bitfld.long 0xC 2. "PRIV1BB2," "0,1" newline bitfld.long 0xC 1. "PRIV1BB1," "0,1" newline bitfld.long 0xC 0. "PRIV1BB0," "0,1" line.long 0x10 "FLASH_PRIV1BBR5,FLASH privilege block based bank 1 register 5" bitfld.long 0x10 31. "PRIV1BB31," "0,1" newline bitfld.long 0x10 30. "PRIV1BB30," "0,1" newline bitfld.long 0x10 29. "PRIV1BB29," "0,1" newline bitfld.long 0x10 28. "PRIV1BB28," "0,1" newline bitfld.long 0x10 27. "PRIV1BB27," "0,1" newline bitfld.long 0x10 26. "PRIV1BB26," "0,1" newline bitfld.long 0x10 25. "PRIV1BB25," "0,1" newline bitfld.long 0x10 24. "PRIV1BB24," "0,1" newline bitfld.long 0x10 23. "PRIV1BB23," "0,1" newline bitfld.long 0x10 22. "PRIV1BB22," "0,1" newline bitfld.long 0x10 21. "PRIV1BB21," "0,1" newline bitfld.long 0x10 20. "PRIV1BB20," "0,1" newline bitfld.long 0x10 19. "PRIV1BB19," "0,1" newline bitfld.long 0x10 18. "PRIV1BB18," "0,1" newline bitfld.long 0x10 17. "PRIV1BB17," "0,1" newline bitfld.long 0x10 16. "PRIV1BB16," "0,1" newline bitfld.long 0x10 15. "PRIV1BB15," "0,1" newline bitfld.long 0x10 14. "PRIV1BB14," "0,1" newline bitfld.long 0x10 13. "PRIV1BB13," "0,1" newline bitfld.long 0x10 12. "PRIV1BB12," "0,1" newline bitfld.long 0x10 11. "PRIV1BB11," "0,1" newline bitfld.long 0x10 10. "PRIV1BB10," "0,1" newline bitfld.long 0x10 9. "PRIV1BB9," "0,1" newline bitfld.long 0x10 8. "PRIV1BB8," "0,1" newline bitfld.long 0x10 7. "PRIV1BB7," "0,1" newline bitfld.long 0x10 6. "PRIV1BB6," "0,1" newline bitfld.long 0x10 5. "PRIV1BB5," "0,1" newline bitfld.long 0x10 4. "PRIV1BB4," "0,1" newline bitfld.long 0x10 3. "PRIV1BB3," "0,1" newline bitfld.long 0x10 2. "PRIV1BB2," "0,1" newline bitfld.long 0x10 1. "PRIV1BB1," "0,1" newline bitfld.long 0x10 0. "PRIV1BB0," "0,1" line.long 0x14 "FLASH_PRIV1BBR6,FLASH privilege block based bank 1 register 6" bitfld.long 0x14 31. "PRIV1BB31," "0,1" newline bitfld.long 0x14 30. "PRIV1BB30," "0,1" newline bitfld.long 0x14 29. "PRIV1BB29," "0,1" newline bitfld.long 0x14 28. "PRIV1BB28," "0,1" newline bitfld.long 0x14 27. "PRIV1BB27," "0,1" newline bitfld.long 0x14 26. "PRIV1BB26," "0,1" newline bitfld.long 0x14 25. "PRIV1BB25," "0,1" newline bitfld.long 0x14 24. "PRIV1BB24," "0,1" newline bitfld.long 0x14 23. "PRIV1BB23," "0,1" newline bitfld.long 0x14 22. "PRIV1BB22," "0,1" newline bitfld.long 0x14 21. "PRIV1BB21," "0,1" newline bitfld.long 0x14 20. "PRIV1BB20," "0,1" newline bitfld.long 0x14 19. "PRIV1BB19," "0,1" newline bitfld.long 0x14 18. "PRIV1BB18," "0,1" newline bitfld.long 0x14 17. "PRIV1BB17," "0,1" newline bitfld.long 0x14 16. "PRIV1BB16," "0,1" newline bitfld.long 0x14 15. "PRIV1BB15," "0,1" newline bitfld.long 0x14 14. "PRIV1BB14," "0,1" newline bitfld.long 0x14 13. "PRIV1BB13," "0,1" newline bitfld.long 0x14 12. "PRIV1BB12," "0,1" newline bitfld.long 0x14 11. "PRIV1BB11," "0,1" newline bitfld.long 0x14 10. "PRIV1BB10," "0,1" newline bitfld.long 0x14 9. "PRIV1BB9," "0,1" newline bitfld.long 0x14 8. "PRIV1BB8," "0,1" newline bitfld.long 0x14 7. "PRIV1BB7," "0,1" newline bitfld.long 0x14 6. "PRIV1BB6," "0,1" newline bitfld.long 0x14 5. "PRIV1BB5," "0,1" newline bitfld.long 0x14 4. "PRIV1BB4," "0,1" newline bitfld.long 0x14 3. "PRIV1BB3," "0,1" newline bitfld.long 0x14 2. "PRIV1BB2," "0,1" newline bitfld.long 0x14 1. "PRIV1BB1," "0,1" newline bitfld.long 0x14 0. "PRIV1BB0," "0,1" line.long 0x18 "FLASH_PRIV1BBR7,FLASH privilege block based bank 1 register 7" bitfld.long 0x18 31. "PRIV1BB31," "0,1" newline bitfld.long 0x18 30. "PRIV1BB30," "0,1" newline bitfld.long 0x18 29. "PRIV1BB29," "0,1" newline bitfld.long 0x18 28. "PRIV1BB28," "0,1" newline bitfld.long 0x18 27. "PRIV1BB27," "0,1" newline bitfld.long 0x18 26. "PRIV1BB26," "0,1" newline bitfld.long 0x18 25. "PRIV1BB25," "0,1" newline bitfld.long 0x18 24. "PRIV1BB24," "0,1" newline bitfld.long 0x18 23. "PRIV1BB23," "0,1" newline bitfld.long 0x18 22. "PRIV1BB22," "0,1" newline bitfld.long 0x18 21. "PRIV1BB21," "0,1" newline bitfld.long 0x18 20. "PRIV1BB20," "0,1" newline bitfld.long 0x18 19. "PRIV1BB19," "0,1" newline bitfld.long 0x18 18. "PRIV1BB18," "0,1" newline bitfld.long 0x18 17. "PRIV1BB17," "0,1" newline bitfld.long 0x18 16. "PRIV1BB16," "0,1" newline bitfld.long 0x18 15. "PRIV1BB15," "0,1" newline bitfld.long 0x18 14. "PRIV1BB14," "0,1" newline bitfld.long 0x18 13. "PRIV1BB13," "0,1" newline bitfld.long 0x18 12. "PRIV1BB12," "0,1" newline bitfld.long 0x18 11. "PRIV1BB11," "0,1" newline bitfld.long 0x18 10. "PRIV1BB10," "0,1" newline bitfld.long 0x18 9. "PRIV1BB9," "0,1" newline bitfld.long 0x18 8. "PRIV1BB8," "0,1" newline bitfld.long 0x18 7. "PRIV1BB7," "0,1" newline bitfld.long 0x18 6. "PRIV1BB6," "0,1" newline bitfld.long 0x18 5. "PRIV1BB5," "0,1" newline bitfld.long 0x18 4. "PRIV1BB4," "0,1" newline bitfld.long 0x18 3. "PRIV1BB3," "0,1" newline bitfld.long 0x18 2. "PRIV1BB2," "0,1" newline bitfld.long 0x18 1. "PRIV1BB1," "0,1" newline bitfld.long 0x18 0. "PRIV1BB0," "0,1" line.long 0x1C "FLASH_PRIV1BBR8,FLASH privilege block based bank 1 register 8" bitfld.long 0x1C 31. "PRIV1BB31," "0,1" newline bitfld.long 0x1C 30. "PRIV1BB30," "0,1" newline bitfld.long 0x1C 29. "PRIV1BB29," "0,1" newline bitfld.long 0x1C 28. "PRIV1BB28," "0,1" newline bitfld.long 0x1C 27. "PRIV1BB27," "0,1" newline bitfld.long 0x1C 26. "PRIV1BB26," "0,1" newline bitfld.long 0x1C 25. "PRIV1BB25," "0,1" newline bitfld.long 0x1C 24. "PRIV1BB24," "0,1" newline bitfld.long 0x1C 23. "PRIV1BB23," "0,1" newline bitfld.long 0x1C 22. "PRIV1BB22," "0,1" newline bitfld.long 0x1C 21. "PRIV1BB21," "0,1" newline bitfld.long 0x1C 20. "PRIV1BB20," "0,1" newline bitfld.long 0x1C 19. "PRIV1BB19," "0,1" newline bitfld.long 0x1C 18. "PRIV1BB18," "0,1" newline bitfld.long 0x1C 17. "PRIV1BB17," "0,1" newline bitfld.long 0x1C 16. "PRIV1BB16," "0,1" newline bitfld.long 0x1C 15. "PRIV1BB15," "0,1" newline bitfld.long 0x1C 14. "PRIV1BB14," "0,1" newline bitfld.long 0x1C 13. "PRIV1BB13," "0,1" newline bitfld.long 0x1C 12. "PRIV1BB12," "0,1" newline bitfld.long 0x1C 11. "PRIV1BB11," "0,1" newline bitfld.long 0x1C 10. "PRIV1BB10," "0,1" newline bitfld.long 0x1C 9. "PRIV1BB9," "0,1" newline bitfld.long 0x1C 8. "PRIV1BB8," "0,1" newline bitfld.long 0x1C 7. "PRIV1BB7," "0,1" newline bitfld.long 0x1C 6. "PRIV1BB6," "0,1" newline bitfld.long 0x1C 5. "PRIV1BB5," "0,1" newline bitfld.long 0x1C 4. "PRIV1BB4," "0,1" newline bitfld.long 0x1C 3. "PRIV1BB3," "0,1" newline bitfld.long 0x1C 2. "PRIV1BB2," "0,1" newline bitfld.long 0x1C 1. "PRIV1BB1," "0,1" newline bitfld.long 0x1C 0. "PRIV1BB0," "0,1" line.long 0x20 "FLASH_PRIV2BBR1,FLASH privilege block based bank 2 register 1" bitfld.long 0x20 31. "PRIV2BB31," "0,1" newline bitfld.long 0x20 30. "PRIV2BB30," "0,1" newline bitfld.long 0x20 29. "PRIV2BB29," "0,1" newline bitfld.long 0x20 28. "PRIV2BB28," "0,1" newline bitfld.long 0x20 27. "PRIV2BB27," "0,1" newline bitfld.long 0x20 26. "PRIV2BB26," "0,1" newline bitfld.long 0x20 25. "PRIV2BB25," "0,1" newline bitfld.long 0x20 24. "PRIV2BB24," "0,1" newline bitfld.long 0x20 23. "PRIV2BB23," "0,1" newline bitfld.long 0x20 22. "PRIV2BB22," "0,1" newline bitfld.long 0x20 21. "PRIV2BB21," "0,1" newline bitfld.long 0x20 20. "PRIV2BB20," "0,1" newline bitfld.long 0x20 19. "PRIV2BB19," "0,1" newline bitfld.long 0x20 18. "PRIV2BB18," "0,1" newline bitfld.long 0x20 17. "PRIV2BB17," "0,1" newline bitfld.long 0x20 16. "PRIV2BB16," "0,1" newline bitfld.long 0x20 15. "PRIV2BB15," "0,1" newline bitfld.long 0x20 14. "PRIV2BB14," "0,1" newline bitfld.long 0x20 13. "PRIV2BB13," "0,1" newline bitfld.long 0x20 12. "PRIV2BB12," "0,1" newline bitfld.long 0x20 11. "PRIV2BB11," "0,1" newline bitfld.long 0x20 10. "PRIV2BB10," "0,1" newline bitfld.long 0x20 9. "PRIV2BB9," "0,1" newline bitfld.long 0x20 8. "PRIV2BB8," "0,1" newline bitfld.long 0x20 7. "PRIV2BB7," "0,1" newline bitfld.long 0x20 6. "PRIV2BB6," "0,1" newline bitfld.long 0x20 5. "PRIV2BB5," "0,1" newline bitfld.long 0x20 4. "PRIV2BB4," "0,1" newline bitfld.long 0x20 3. "PRIV2BB3," "0,1" newline bitfld.long 0x20 2. "PRIV2BB2," "0,1" newline bitfld.long 0x20 1. "PRIV2BB1," "0,1" newline bitfld.long 0x20 0. "PRIV2BB0," "0,1" line.long 0x24 "FLASH_PRIV2BBR2,FLASH privilege block based bank 2 register 2" bitfld.long 0x24 31. "PRIV2BB31," "0,1" newline bitfld.long 0x24 30. "PRIV2BB30," "0,1" newline bitfld.long 0x24 29. "PRIV2BB29," "0,1" newline bitfld.long 0x24 28. "PRIV2BB28," "0,1" newline bitfld.long 0x24 27. "PRIV2BB27," "0,1" newline bitfld.long 0x24 26. "PRIV2BB26," "0,1" newline bitfld.long 0x24 25. "PRIV2BB25," "0,1" newline bitfld.long 0x24 24. "PRIV2BB24," "0,1" newline bitfld.long 0x24 23. "PRIV2BB23," "0,1" newline bitfld.long 0x24 22. "PRIV2BB22," "0,1" newline bitfld.long 0x24 21. "PRIV2BB21," "0,1" newline bitfld.long 0x24 20. "PRIV2BB20," "0,1" newline bitfld.long 0x24 19. "PRIV2BB19," "0,1" newline bitfld.long 0x24 18. "PRIV2BB18," "0,1" newline bitfld.long 0x24 17. "PRIV2BB17," "0,1" newline bitfld.long 0x24 16. "PRIV2BB16," "0,1" newline bitfld.long 0x24 15. "PRIV2BB15," "0,1" newline bitfld.long 0x24 14. "PRIV2BB14," "0,1" newline bitfld.long 0x24 13. "PRIV2BB13," "0,1" newline bitfld.long 0x24 12. "PRIV2BB12," "0,1" newline bitfld.long 0x24 11. "PRIV2BB11," "0,1" newline bitfld.long 0x24 10. "PRIV2BB10," "0,1" newline bitfld.long 0x24 9. "PRIV2BB9," "0,1" newline bitfld.long 0x24 8. "PRIV2BB8," "0,1" newline bitfld.long 0x24 7. "PRIV2BB7," "0,1" newline bitfld.long 0x24 6. "PRIV2BB6," "0,1" newline bitfld.long 0x24 5. "PRIV2BB5," "0,1" newline bitfld.long 0x24 4. "PRIV2BB4," "0,1" newline bitfld.long 0x24 3. "PRIV2BB3," "0,1" newline bitfld.long 0x24 2. "PRIV2BB2," "0,1" newline bitfld.long 0x24 1. "PRIV2BB1," "0,1" newline bitfld.long 0x24 0. "PRIV2BB0," "0,1" line.long 0x28 "FLASH_PRIV2BBR3,FLASH privilege block based bank 2 register 3" bitfld.long 0x28 31. "PRIV2BB31," "0,1" newline bitfld.long 0x28 30. "PRIV2BB30," "0,1" newline bitfld.long 0x28 29. "PRIV2BB29," "0,1" newline bitfld.long 0x28 28. "PRIV2BB28," "0,1" newline bitfld.long 0x28 27. "PRIV2BB27," "0,1" newline bitfld.long 0x28 26. "PRIV2BB26," "0,1" newline bitfld.long 0x28 25. "PRIV2BB25," "0,1" newline bitfld.long 0x28 24. "PRIV2BB24," "0,1" newline bitfld.long 0x28 23. "PRIV2BB23," "0,1" newline bitfld.long 0x28 22. "PRIV2BB22," "0,1" newline bitfld.long 0x28 21. "PRIV2BB21," "0,1" newline bitfld.long 0x28 20. "PRIV2BB20," "0,1" newline bitfld.long 0x28 19. "PRIV2BB19," "0,1" newline bitfld.long 0x28 18. "PRIV2BB18," "0,1" newline bitfld.long 0x28 17. "PRIV2BB17," "0,1" newline bitfld.long 0x28 16. "PRIV2BB16," "0,1" newline bitfld.long 0x28 15. "PRIV2BB15," "0,1" newline bitfld.long 0x28 14. "PRIV2BB14," "0,1" newline bitfld.long 0x28 13. "PRIV2BB13," "0,1" newline bitfld.long 0x28 12. "PRIV2BB12," "0,1" newline bitfld.long 0x28 11. "PRIV2BB11," "0,1" newline bitfld.long 0x28 10. "PRIV2BB10," "0,1" newline bitfld.long 0x28 9. "PRIV2BB9," "0,1" newline bitfld.long 0x28 8. "PRIV2BB8," "0,1" newline bitfld.long 0x28 7. "PRIV2BB7," "0,1" newline bitfld.long 0x28 6. "PRIV2BB6," "0,1" newline bitfld.long 0x28 5. "PRIV2BB5," "0,1" newline bitfld.long 0x28 4. "PRIV2BB4," "0,1" newline bitfld.long 0x28 3. "PRIV2BB3," "0,1" newline bitfld.long 0x28 2. "PRIV2BB2," "0,1" newline bitfld.long 0x28 1. "PRIV2BB1," "0,1" newline bitfld.long 0x28 0. "PRIV2BB0," "0,1" line.long 0x2C "FLASH_PRIV2BBR4,FLASH privilege block based bank 2 register 4" bitfld.long 0x2C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x2C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x2C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x2C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x2C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x2C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x2C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x2C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x2C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x2C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x2C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x2C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x2C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x2C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x2C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x2C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x2C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x2C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x2C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x2C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x2C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x2C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x2C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x2C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x2C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x2C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x2C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x2C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x2C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x2C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x2C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x2C 0. "PRIV2BB0," "0,1" line.long 0x30 "FLASH_PRIV2BBR5,FLASH privilege block based bank 2 register 5" bitfld.long 0x30 31. "PRIV2BB31," "0,1" newline bitfld.long 0x30 30. "PRIV2BB30," "0,1" newline bitfld.long 0x30 29. "PRIV2BB29," "0,1" newline bitfld.long 0x30 28. "PRIV2BB28," "0,1" newline bitfld.long 0x30 27. "PRIV2BB27," "0,1" newline bitfld.long 0x30 26. "PRIV2BB26," "0,1" newline bitfld.long 0x30 25. "PRIV2BB25," "0,1" newline bitfld.long 0x30 24. "PRIV2BB24," "0,1" newline bitfld.long 0x30 23. "PRIV2BB23," "0,1" newline bitfld.long 0x30 22. "PRIV2BB22," "0,1" newline bitfld.long 0x30 21. "PRIV2BB21," "0,1" newline bitfld.long 0x30 20. "PRIV2BB20," "0,1" newline bitfld.long 0x30 19. "PRIV2BB19," "0,1" newline bitfld.long 0x30 18. "PRIV2BB18," "0,1" newline bitfld.long 0x30 17. "PRIV2BB17," "0,1" newline bitfld.long 0x30 16. "PRIV2BB16," "0,1" newline bitfld.long 0x30 15. "PRIV2BB15," "0,1" newline bitfld.long 0x30 14. "PRIV2BB14," "0,1" newline bitfld.long 0x30 13. "PRIV2BB13," "0,1" newline bitfld.long 0x30 12. "PRIV2BB12," "0,1" newline bitfld.long 0x30 11. "PRIV2BB11," "0,1" newline bitfld.long 0x30 10. "PRIV2BB10," "0,1" newline bitfld.long 0x30 9. "PRIV2BB9," "0,1" newline bitfld.long 0x30 8. "PRIV2BB8," "0,1" newline bitfld.long 0x30 7. "PRIV2BB7," "0,1" newline bitfld.long 0x30 6. "PRIV2BB6," "0,1" newline bitfld.long 0x30 5. "PRIV2BB5," "0,1" newline bitfld.long 0x30 4. "PRIV2BB4," "0,1" newline bitfld.long 0x30 3. "PRIV2BB3," "0,1" newline bitfld.long 0x30 2. "PRIV2BB2," "0,1" newline bitfld.long 0x30 1. "PRIV2BB1," "0,1" newline bitfld.long 0x30 0. "PRIV2BB0," "0,1" line.long 0x34 "FLASH_PRIV2BBR6,FLASH privilege block based bank 2 register 6" bitfld.long 0x34 31. "PRIV2BB31," "0,1" newline bitfld.long 0x34 30. "PRIV2BB30," "0,1" newline bitfld.long 0x34 29. "PRIV2BB29," "0,1" newline bitfld.long 0x34 28. "PRIV2BB28," "0,1" newline bitfld.long 0x34 27. "PRIV2BB27," "0,1" newline bitfld.long 0x34 26. "PRIV2BB26," "0,1" newline bitfld.long 0x34 25. "PRIV2BB25," "0,1" newline bitfld.long 0x34 24. "PRIV2BB24," "0,1" newline bitfld.long 0x34 23. "PRIV2BB23," "0,1" newline bitfld.long 0x34 22. "PRIV2BB22," "0,1" newline bitfld.long 0x34 21. "PRIV2BB21," "0,1" newline bitfld.long 0x34 20. "PRIV2BB20," "0,1" newline bitfld.long 0x34 19. "PRIV2BB19," "0,1" newline bitfld.long 0x34 18. "PRIV2BB18," "0,1" newline bitfld.long 0x34 17. "PRIV2BB17," "0,1" newline bitfld.long 0x34 16. "PRIV2BB16," "0,1" newline bitfld.long 0x34 15. "PRIV2BB15," "0,1" newline bitfld.long 0x34 14. "PRIV2BB14," "0,1" newline bitfld.long 0x34 13. "PRIV2BB13," "0,1" newline bitfld.long 0x34 12. "PRIV2BB12," "0,1" newline bitfld.long 0x34 11. "PRIV2BB11," "0,1" newline bitfld.long 0x34 10. "PRIV2BB10," "0,1" newline bitfld.long 0x34 9. "PRIV2BB9," "0,1" newline bitfld.long 0x34 8. "PRIV2BB8," "0,1" newline bitfld.long 0x34 7. "PRIV2BB7," "0,1" newline bitfld.long 0x34 6. "PRIV2BB6," "0,1" newline bitfld.long 0x34 5. "PRIV2BB5," "0,1" newline bitfld.long 0x34 4. "PRIV2BB4," "0,1" newline bitfld.long 0x34 3. "PRIV2BB3," "0,1" newline bitfld.long 0x34 2. "PRIV2BB2," "0,1" newline bitfld.long 0x34 1. "PRIV2BB1," "0,1" newline bitfld.long 0x34 0. "PRIV2BB0," "0,1" line.long 0x38 "FLASH_PRIV2BBR7,FLASH privilege block based bank 2 register 7" bitfld.long 0x38 31. "PRIV2BB31," "0,1" newline bitfld.long 0x38 30. "PRIV2BB30," "0,1" newline bitfld.long 0x38 29. "PRIV2BB29," "0,1" newline bitfld.long 0x38 28. "PRIV2BB28," "0,1" newline bitfld.long 0x38 27. "PRIV2BB27," "0,1" newline bitfld.long 0x38 26. "PRIV2BB26," "0,1" newline bitfld.long 0x38 25. "PRIV2BB25," "0,1" newline bitfld.long 0x38 24. "PRIV2BB24," "0,1" newline bitfld.long 0x38 23. "PRIV2BB23," "0,1" newline bitfld.long 0x38 22. "PRIV2BB22," "0,1" newline bitfld.long 0x38 21. "PRIV2BB21," "0,1" newline bitfld.long 0x38 20. "PRIV2BB20," "0,1" newline bitfld.long 0x38 19. "PRIV2BB19," "0,1" newline bitfld.long 0x38 18. "PRIV2BB18," "0,1" newline bitfld.long 0x38 17. "PRIV2BB17," "0,1" newline bitfld.long 0x38 16. "PRIV2BB16," "0,1" newline bitfld.long 0x38 15. "PRIV2BB15," "0,1" newline bitfld.long 0x38 14. "PRIV2BB14," "0,1" newline bitfld.long 0x38 13. "PRIV2BB13," "0,1" newline bitfld.long 0x38 12. "PRIV2BB12," "0,1" newline bitfld.long 0x38 11. "PRIV2BB11," "0,1" newline bitfld.long 0x38 10. "PRIV2BB10," "0,1" newline bitfld.long 0x38 9. "PRIV2BB9," "0,1" newline bitfld.long 0x38 8. "PRIV2BB8," "0,1" newline bitfld.long 0x38 7. "PRIV2BB7," "0,1" newline bitfld.long 0x38 6. "PRIV2BB6," "0,1" newline bitfld.long 0x38 5. "PRIV2BB5," "0,1" newline bitfld.long 0x38 4. "PRIV2BB4," "0,1" newline bitfld.long 0x38 3. "PRIV2BB3," "0,1" newline bitfld.long 0x38 2. "PRIV2BB2," "0,1" newline bitfld.long 0x38 1. "PRIV2BB1," "0,1" newline bitfld.long 0x38 0. "PRIV2BB0," "0,1" line.long 0x3C "FLASH_PRIV2BBR8,FLASH privilege block based bank 2 register 8" bitfld.long 0x3C 31. "PRIV2BB31," "0,1" newline bitfld.long 0x3C 30. "PRIV2BB30," "0,1" newline bitfld.long 0x3C 29. "PRIV2BB29," "0,1" newline bitfld.long 0x3C 28. "PRIV2BB28," "0,1" newline bitfld.long 0x3C 27. "PRIV2BB27," "0,1" newline bitfld.long 0x3C 26. "PRIV2BB26," "0,1" newline bitfld.long 0x3C 25. "PRIV2BB25," "0,1" newline bitfld.long 0x3C 24. "PRIV2BB24," "0,1" newline bitfld.long 0x3C 23. "PRIV2BB23," "0,1" newline bitfld.long 0x3C 22. "PRIV2BB22," "0,1" newline bitfld.long 0x3C 21. "PRIV2BB21," "0,1" newline bitfld.long 0x3C 20. "PRIV2BB20," "0,1" newline bitfld.long 0x3C 19. "PRIV2BB19," "0,1" newline bitfld.long 0x3C 18. "PRIV2BB18," "0,1" newline bitfld.long 0x3C 17. "PRIV2BB17," "0,1" newline bitfld.long 0x3C 16. "PRIV2BB16," "0,1" newline bitfld.long 0x3C 15. "PRIV2BB15," "0,1" newline bitfld.long 0x3C 14. "PRIV2BB14," "0,1" newline bitfld.long 0x3C 13. "PRIV2BB13," "0,1" newline bitfld.long 0x3C 12. "PRIV2BB12," "0,1" newline bitfld.long 0x3C 11. "PRIV2BB11," "0,1" newline bitfld.long 0x3C 10. "PRIV2BB10," "0,1" newline bitfld.long 0x3C 9. "PRIV2BB9," "0,1" newline bitfld.long 0x3C 8. "PRIV2BB8," "0,1" newline bitfld.long 0x3C 7. "PRIV2BB7," "0,1" newline bitfld.long 0x3C 6. "PRIV2BB6," "0,1" newline bitfld.long 0x3C 5. "PRIV2BB5," "0,1" newline bitfld.long 0x3C 4. "PRIV2BB4," "0,1" newline bitfld.long 0x3C 3. "PRIV2BB3," "0,1" newline bitfld.long 0x3C 2. "PRIV2BB2," "0,1" newline bitfld.long 0x3C 1. "PRIV2BB1," "0,1" newline bitfld.long 0x3C 0. "PRIV2BB0," "0,1" tree.end endif tree.end tree "FMAC (Filter Math Accelerator)" base ad:0x0 tree "FMAC" base ad:0x40021400 group.long 0x0++0x13 line.long 0x0 "X1BUFCFG,FMAC X1 Buffer Configuration register" bitfld.long 0x0 24.--25. "FULL_WM,Watermark for buffer full flag" "0,1,2,3" hexmask.long.byte 0x0 8.--15. 1. "X1_BUF_SIZE,Allocated size of X1 buffer in 16-bit words" hexmask.long.byte 0x0 0.--7. 1. "X1_BASE,Base address of X1 buffer" line.long 0x4 "X2BUFCFG,FMAC X2 Buffer Configuration register" hexmask.long.byte 0x4 8.--15. 1. "X2_BUF_SIZE,Size of X2 buffer in 16-bit words" hexmask.long.byte 0x4 0.--7. 1. "X2_BASE,Base address of X2 buffer" line.long 0x8 "YBUFCFG,FMAC Y Buffer Configuration register" bitfld.long 0x8 24.--25. "EMPTY_WM,Watermark for buffer empty flag" "0,1,2,3" hexmask.long.byte 0x8 8.--15. 1. "Y_BUF_SIZE,Size of Y buffer in 16-bit words" hexmask.long.byte 0x8 0.--7. 1. "Y_BASE,Base address of Y buffer" line.long 0xC "PARAM,FMAC Parameter register" bitfld.long 0xC 31. "START,Enable execution" "0,1" hexmask.long.byte 0xC 24.--30. 1. "FUNC,Function" hexmask.long.byte 0xC 16.--23. 1. "R,Input parameter R" hexmask.long.byte 0xC 8.--15. 1. "Q,Input parameter Q" hexmask.long.byte 0xC 0.--7. 1. "P,Input parameter P" line.long 0x10 "CR,FMAC Control register" bitfld.long 0x10 16. "RESET,Reset FMAC unit" "0,1" bitfld.long 0x10 15. "CLIPEN,Enable clipping" "0,1" bitfld.long 0x10 9. "DMAWEN,Enable DMA write channel requests" "0,1" bitfld.long 0x10 8. "DMAREN,Enable DMA read channel requests" "0,1" bitfld.long 0x10 4. "SATIEN,Enable saturation error interrupts" "0,1" bitfld.long 0x10 3. "UNFLIEN,Enable underflow error interrupts" "0,1" bitfld.long 0x10 2. "OVFLIEN,Enable overflow error interrupts" "0,1" bitfld.long 0x10 1. "WIEN,Enable write interrupt" "0,1" newline bitfld.long 0x10 0. "RIEN,Enable read interrupt" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,FMAC Status register" bitfld.long 0x0 10. "SAT,Saturation error flag" "0,1" bitfld.long 0x0 9. "UNFL,Underflow error flag" "0,1" bitfld.long 0x0 8. "OVFL,Overflow error flag" "0,1" bitfld.long 0x0 1. "X1FULL,X1 buffer full flag" "0,1" bitfld.long 0x0 0. "YEMPTY,Y buffer empty flag" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "WDATA,FMAC Write Data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Write data" rgroup.long 0x1C++0x3 line.long 0x0 "RDATA,FMAC Read Data register" hexmask.long.word 0x0 0.--15. 1. "RDATA,Read data" tree.end tree "SEC_FMAC" base ad:0x50021400 group.long 0x0++0x13 line.long 0x0 "X1BUFCFG,FMAC X1 Buffer Configuration register" bitfld.long 0x0 24.--25. "FULL_WM,Watermark for buffer full flag" "0,1,2,3" hexmask.long.byte 0x0 8.--15. 1. "X1_BUF_SIZE,Allocated size of X1 buffer in 16-bit words" hexmask.long.byte 0x0 0.--7. 1. "X1_BASE,Base address of X1 buffer" line.long 0x4 "X2BUFCFG,FMAC X2 Buffer Configuration register" hexmask.long.byte 0x4 8.--15. 1. "X2_BUF_SIZE,Size of X2 buffer in 16-bit words" hexmask.long.byte 0x4 0.--7. 1. "X2_BASE,Base address of X2 buffer" line.long 0x8 "YBUFCFG,FMAC Y Buffer Configuration register" bitfld.long 0x8 24.--25. "EMPTY_WM,Watermark for buffer empty flag" "0,1,2,3" hexmask.long.byte 0x8 8.--15. 1. "Y_BUF_SIZE,Size of Y buffer in 16-bit words" hexmask.long.byte 0x8 0.--7. 1. "Y_BASE,Base address of Y buffer" line.long 0xC "PARAM,FMAC Parameter register" bitfld.long 0xC 31. "START,Enable execution" "0,1" hexmask.long.byte 0xC 24.--30. 1. "FUNC,Function" hexmask.long.byte 0xC 16.--23. 1. "R,Input parameter R" hexmask.long.byte 0xC 8.--15. 1. "Q,Input parameter Q" hexmask.long.byte 0xC 0.--7. 1. "P,Input parameter P" line.long 0x10 "CR,FMAC Control register" bitfld.long 0x10 16. "RESET,Reset FMAC unit" "0,1" bitfld.long 0x10 15. "CLIPEN,Enable clipping" "0,1" bitfld.long 0x10 9. "DMAWEN,Enable DMA write channel requests" "0,1" bitfld.long 0x10 8. "DMAREN,Enable DMA read channel requests" "0,1" bitfld.long 0x10 4. "SATIEN,Enable saturation error interrupts" "0,1" bitfld.long 0x10 3. "UNFLIEN,Enable underflow error interrupts" "0,1" bitfld.long 0x10 2. "OVFLIEN,Enable overflow error interrupts" "0,1" bitfld.long 0x10 1. "WIEN,Enable write interrupt" "0,1" newline bitfld.long 0x10 0. "RIEN,Enable read interrupt" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,FMAC Status register" bitfld.long 0x0 10. "SAT,Saturation error flag" "0,1" bitfld.long 0x0 9. "UNFL,Underflow error flag" "0,1" bitfld.long 0x0 8. "OVFL,Overflow error flag" "0,1" bitfld.long 0x0 1. "X1FULL,X1 buffer full flag" "0,1" bitfld.long 0x0 0. "YEMPTY,Y buffer empty flag" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "WDATA,FMAC Write Data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Write data" rgroup.long 0x1C++0x3 line.long 0x0 "RDATA,FMAC Read Data register" hexmask.long.word 0x0 0.--15. 1. "RDATA,Read data" tree.end tree.end sif (cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U595*")||cpuis("STM32U599*")||cpuis("STM32U5A5*")||cpuis("STM32U5A9*")||cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "FMC (Flexible Memory Controller)" base ad:0x0 tree "FMC" base ad:0x420D0400 group.long 0x0++0x3 line.long 0x0 "BCR1,SRAM/NOR-Flash chip-select control register for bank 1" bitfld.long 0x0 31. "FMCEN,FMC controller enable" "0,1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0,1,2,3" bitfld.long 0x0 21. "WFDIS,Write FIFO disable" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous clock enable" "0,1" bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit" "0,1" bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0,1" bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable" "0,1" bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit" "0,1" group.long 0x8++0x3 line.long 0x0 "BCR2,SRAM/NOR-Flash chip-select control register for bank 2" bitfld.long 0x0 31. "FMCEN,FMC controller enable" "0,1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0,1,2,3" bitfld.long 0x0 21. "WFDIS,Write FIFO disable" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous clock enable" "0,1" bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit" "0,1" bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0,1" bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable" "0,1" bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit" "0,1" group.long 0x10++0x3 line.long 0x0 "BCR3,SRAM/NOR-Flash chip-select control register for bank 3" bitfld.long 0x0 31. "FMCEN,FMC controller enable" "0,1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0,1,2,3" bitfld.long 0x0 21. "WFDIS,Write FIFO disable" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous clock enable" "0,1" bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit" "0,1" bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0,1" bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable" "0,1" bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit" "0,1" group.long 0x18++0x3 line.long 0x0 "BCR4,SRAM/NOR-Flash chip-select control register for bank 4" bitfld.long 0x0 31. "FMCEN,FMC controller enable" "0,1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0,1,2,3" bitfld.long 0x0 21. "WFDIS,Write FIFO disable" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous clock enable" "0,1" bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit" "0,1" bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0,1" bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable" "0,1" bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit" "0,1" group.long 0x4++0x3 line.long 0x0 "BTR1,SRAM/NOR-Flash chip-select timing register for bank 1" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DATLAT,Data latency for synchronous memory" hexmask.long.byte 0x0 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0xC++0x3 line.long 0x0 "BTR2,SRAM/NOR-Flash chip-select timing register for bank 2" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DATLAT,Data latency for synchronous memory" hexmask.long.byte 0x0 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x14++0x3 line.long 0x0 "BTR3,SRAM/NOR-Flash chip-select timing register for bank 3" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DATLAT,Data latency for synchronous memory" hexmask.long.byte 0x0 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x1C++0x3 line.long 0x0 "BTR4,SRAM/NOR-Flash chip-select timing register for bank 4" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DATLAT,Data latency for synchronous memory" hexmask.long.byte 0x0 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x104++0x3 line.long 0x0 "BWTR1,SRAM/NOR-Flash write timing registers 1" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x10C++0x3 line.long 0x0 "BWTR2,SRAM/NOR-Flash write timing registers 2" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x114++0x3 line.long 0x0 "BWTR3,SRAM/NOR-Flash write timing registers 3" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x11C++0x3 line.long 0x0 "BWTR4,SRAM/NOR-Flash write timing registers 4" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x20++0x3 line.long 0x0 "PCSCNTR,PSRAM chip select counter register" bitfld.long 0x0 19. "CNTB4EN,Counter Bank 4 enable" "0,1" bitfld.long 0x0 18. "CNTB3EN,Counter Bank 3 enable" "0,1" bitfld.long 0x0 17. "CNTB2EN,Counter Bank 2 enable" "0,1" bitfld.long 0x0 16. "CNTB1EN,Counter Bank 1 enable" "0,1" hexmask.long.word 0x0 0.--15. 1. "CSCOUNT,Chip select counter" group.long 0x80++0xF line.long 0x0 "PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--15. "TAR,ALE to RE delay" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable bit" "0,1" bitfld.long 0x0 4.--5. "PWID,Data bus width" "0,1,2,3" bitfld.long 0x0 3. "PTYP,Memory type" "0,1" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit" "0,1" bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit" "0,1" line.long 0x4 "SR,status and interrupt register" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "PMEM,Common memory space timing register" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" tree.end tree "SEC_FMC" base ad:0x520D0400 group.long 0x0++0x3 line.long 0x0 "BCR1,SRAM/NOR-Flash chip-select control register for bank 1" bitfld.long 0x0 31. "FMCEN,FMC controller enable" "0,1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0,1,2,3" bitfld.long 0x0 21. "WFDIS,Write FIFO disable" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous clock enable" "0,1" bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit" "0,1" bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0,1" bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable" "0,1" bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit" "0,1" group.long 0x8++0x3 line.long 0x0 "BCR2,SRAM/NOR-Flash chip-select control register for bank 2" bitfld.long 0x0 31. "FMCEN,FMC controller enable" "0,1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0,1,2,3" bitfld.long 0x0 21. "WFDIS,Write FIFO disable" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous clock enable" "0,1" bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit" "0,1" bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0,1" bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable" "0,1" bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit" "0,1" group.long 0x10++0x3 line.long 0x0 "BCR3,SRAM/NOR-Flash chip-select control register for bank 3" bitfld.long 0x0 31. "FMCEN,FMC controller enable" "0,1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0,1,2,3" bitfld.long 0x0 21. "WFDIS,Write FIFO disable" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous clock enable" "0,1" bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit" "0,1" bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0,1" bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable" "0,1" bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit" "0,1" group.long 0x18++0x3 line.long 0x0 "BCR4,SRAM/NOR-Flash chip-select control register for bank 4" bitfld.long 0x0 31. "FMCEN,FMC controller enable" "0,1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0,1,2,3" bitfld.long 0x0 21. "WFDIS,Write FIFO disable" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous clock enable" "0,1" bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit" "0,1" bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0,1" bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable" "0,1" bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit" "0,1" group.long 0x4++0x3 line.long 0x0 "BTR1,SRAM/NOR-Flash chip-select timing register for bank 1" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DATLAT,Data latency for synchronous memory" hexmask.long.byte 0x0 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0xC++0x3 line.long 0x0 "BTR2,SRAM/NOR-Flash chip-select timing register for bank 2" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DATLAT,Data latency for synchronous memory" hexmask.long.byte 0x0 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x14++0x3 line.long 0x0 "BTR3,SRAM/NOR-Flash chip-select timing register for bank 3" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DATLAT,Data latency for synchronous memory" hexmask.long.byte 0x0 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x1C++0x3 line.long 0x0 "BTR4,SRAM/NOR-Flash chip-select timing register for bank 4" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DATLAT,Data latency for synchronous memory" hexmask.long.byte 0x0 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x104++0x3 line.long 0x0 "BWTR1,SRAM/NOR-Flash write timing registers 1" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x10C++0x3 line.long 0x0 "BWTR2,SRAM/NOR-Flash write timing registers 2" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x114++0x3 line.long 0x0 "BWTR3,SRAM/NOR-Flash write timing registers 3" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x11C++0x3 line.long 0x0 "BWTR4,SRAM/NOR-Flash write timing registers 4" bitfld.long 0x0 30.--31. "DATAHLD,Data hold phase duration" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,Access mode" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration" group.long 0x20++0x3 line.long 0x0 "PCSCNTR,PSRAM chip select counter register" bitfld.long 0x0 19. "CNTB4EN,Counter Bank 4 enable" "0,1" bitfld.long 0x0 18. "CNTB3EN,Counter Bank 3 enable" "0,1" bitfld.long 0x0 17. "CNTB2EN,Counter Bank 2 enable" "0,1" bitfld.long 0x0 16. "CNTB1EN,Counter Bank 1 enable" "0,1" hexmask.long.word 0x0 0.--15. 1. "CSCOUNT,Chip select counter" group.long 0x80++0xF line.long 0x0 "PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--15. "TAR,ALE to RE delay" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable bit" "0,1" bitfld.long 0x0 4.--5. "PWID,Data bus width" "0,1,2,3" bitfld.long 0x0 3. "PTYP,Memory type" "0,1" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit" "0,1" bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit" "0,1" line.long 0x4 "SR,status and interrupt register" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "PMEM,Common memory space timing register" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" tree.end tree.end endif sif (cpuis("STM32U599*")||cpuis("STM32U5A9*")||cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "GFXMMU (Chrom-GRC)" base ad:0x0 tree "GFXMMU" base ad:0x4002C000 group.long 0x0++0x3 line.long 0x0 "GFXMMU_CR,GFXMMU configuration register" bitfld.long 0x0 17. "OB,Outter bufferability" "0: No bufferable,1: Bufferable" bitfld.long 0x0 16. "OC,Outter cachability" "0: No cachable,1: Cachable" newline bitfld.long 0x0 12. "PD,Prefetch disable" "0: Prefetch enable,1: Prefetch disable" bitfld.long 0x0 11. "FC,Force caching" "0: Caching not forced,1: Caching forced" newline bitfld.long 0x0 9.--10. "CLB,Cache lock buffer" "0: Cache locked on buffer 0,1: Cache locked on buffer 1,2: Cache locked on buffer 2,3: Cache locked on buffer 3" bitfld.long 0x0 8. "CL,Cache lock" "0: Cache not locked,1: Cache locked to a buffer" newline bitfld.long 0x0 7. "CE,Cache enable" "0: Cache disable,1: Cache enable" bitfld.long 0x0 6. "BM192,192 Block mode" "0: 256 blocks per line,1: 192 blocks per line" newline bitfld.long 0x0 4. "AMEIE,AHB master error interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 3. "B3OIE,Buffer 3 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 2. "B2OIE,Buffer 2 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 1. "B1OIE,Buffer 1 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 0. "B0OIE,Buffer 0 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" rgroup.long 0x4++0x3 line.long 0x0 "GFXMMU_SR,GFXMMU status register" bitfld.long 0x0 4. "AMEF,AHB master error flag" "0,1" bitfld.long 0x0 3. "B3OF,Buffer 3 overflow flag" "0,1" newline bitfld.long 0x0 2. "B2OF,Buffer 2 overflow flag" "0,1" bitfld.long 0x0 1. "B1OF,Buffer 1 overflow flag" "0,1" newline bitfld.long 0x0 0. "B0OF,Buffer 0 overflow flag" "0,1" group.long 0x8++0xB line.long 0x0 "GFXMMU_FCR,GFXMMU flag clear register" bitfld.long 0x0 4. "CAMEF,Clear AHB master error flag" "0,1" bitfld.long 0x0 3. "CB3OF,Clear buffer 3 overflow flag" "0,1" newline bitfld.long 0x0 2. "CB2OF,Clear buffer 2 overflow flag" "0,1" bitfld.long 0x0 1. "CB1OF,Clear buffer 1 overflow flag" "0,1" newline bitfld.long 0x0 0. "CB0OF,Clear buffer 0 overflow flag" "0,1" line.long 0x4 "GFXMMU_CCR,GFXMMU cache control register" bitfld.long 0x4 1. "FI,Force invalidate" "0: Invalidation process complete,1: Force invalidation/invalidation process on going" bitfld.long 0x4 0. "FF,Force flush" "0: Flushing process complete,1: Force flush/flushing process on going" line.long 0x8 "GFXMMU_DVR,GFXMMU default value register" hexmask.long 0x8 0.--31. 1. "DV,Default value" group.long 0x20++0xF line.long 0x0 "GFXMMU_B0CR,GFXMMU buffer 0 configuration register" hexmask.long.word 0x0 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x0 4.--22. 1. "PBO,Physical buffer offset" line.long 0x4 "GFXMMU_B1CR,GFXMMU buffer 1 configuration register" hexmask.long.word 0x4 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x4 4.--22. 1. "PBO,Physical buffer offset" line.long 0x8 "GFXMMU_B2CR,GFXMMU buffer 2 configuration register" hexmask.long.word 0x8 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x8 4.--22. 1. "PBO,Physical buffer offset" line.long 0xC "GFXMMU_B3CR,GFXMMU buffer 3 configuration register" hexmask.long.word 0xC 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0xC 4.--22. 1. "PBO,Physical buffer offset" group.long 0x1000++0xFFF line.long 0x0 "GFXMMU_LUT0L,GFXMMU LUT entry 0 low" hexmask.long.byte 0x0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4 "GFXMMU_LUT0H,GFXMMU LUT entry 0 high" hexmask.long.tbyte 0x4 4.--21. 1. "LO,Line offset" line.long 0x8 "GFXMMU_LUT1L,GFXMMU LUT entry 1 low" hexmask.long.byte 0x8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC "GFXMMU_LUT1H,GFXMMU LUT entry 1 high" hexmask.long.tbyte 0xC 4.--21. 1. "LO,Line offset" line.long 0x10 "GFXMMU_LUT2L,GFXMMU LUT entry 2 low" hexmask.long.byte 0x10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14 "GFXMMU_LUT2H,GFXMMU LUT entry 2 high" hexmask.long.tbyte 0x14 4.--21. 1. "LO,Line offset" line.long 0x18 "GFXMMU_LUT3L,GFXMMU LUT entry 3 low" hexmask.long.byte 0x18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C "GFXMMU_LUT3H,GFXMMU LUT entry 3 high" hexmask.long.tbyte 0x1C 4.--21. 1. "LO,Line offset" line.long 0x20 "GFXMMU_LUT4L,GFXMMU LUT entry 4 low" hexmask.long.byte 0x20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24 "GFXMMU_LUT4H,GFXMMU LUT entry 4 high" hexmask.long.tbyte 0x24 4.--21. 1. "LO,Line offset" line.long 0x28 "GFXMMU_LUT5L,GFXMMU LUT entry 5 low" hexmask.long.byte 0x28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C "GFXMMU_LUT5H,GFXMMU LUT entry 5 high" hexmask.long.tbyte 0x2C 4.--21. 1. "LO,Line offset" line.long 0x30 "GFXMMU_LUT6L,GFXMMU LUT entry 6 low" hexmask.long.byte 0x30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34 "GFXMMU_LUT6H,GFXMMU LUT entry 6 high" hexmask.long.tbyte 0x34 4.--21. 1. "LO,Line offset" line.long 0x38 "GFXMMU_LUT7L,GFXMMU LUT entry 7 low" hexmask.long.byte 0x38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C "GFXMMU_LUT7H,GFXMMU LUT entry 7 high" hexmask.long.tbyte 0x3C 4.--21. 1. "LO,Line offset" line.long 0x40 "GFXMMU_LUT8L,GFXMMU LUT entry 8 low" hexmask.long.byte 0x40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44 "GFXMMU_LUT8H,GFXMMU LUT entry 8 high" hexmask.long.tbyte 0x44 4.--21. 1. "LO,Line offset" line.long 0x48 "GFXMMU_LUT9L,GFXMMU LUT entry 9 low" hexmask.long.byte 0x48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C "GFXMMU_LUT9H,GFXMMU LUT entry 9 high" hexmask.long.tbyte 0x4C 4.--21. 1. "LO,Line offset" line.long 0x50 "GFXMMU_LUT10L,GFXMMU LUT entry 10 low" hexmask.long.byte 0x50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54 "GFXMMU_LUT10H,GFXMMU LUT entry 10 high" hexmask.long.tbyte 0x54 4.--21. 1. "LO,Line offset" line.long 0x58 "GFXMMU_LUT11L,GFXMMU LUT entry 11 low" hexmask.long.byte 0x58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C "GFXMMU_LUT11H,GFXMMU LUT entry 11 high" hexmask.long.tbyte 0x5C 4.--21. 1. "LO,Line offset" line.long 0x60 "GFXMMU_LUT12L,GFXMMU LUT entry 12 low" hexmask.long.byte 0x60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64 "GFXMMU_LUT12H,GFXMMU LUT entry 12 high" hexmask.long.tbyte 0x64 4.--21. 1. "LO,Line offset" line.long 0x68 "GFXMMU_LUT13L,GFXMMU LUT entry 13 low" hexmask.long.byte 0x68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C "GFXMMU_LUT13H,GFXMMU LUT entry 13 high" hexmask.long.tbyte 0x6C 4.--21. 1. "LO,Line offset" line.long 0x70 "GFXMMU_LUT14L,GFXMMU LUT entry 14 low" hexmask.long.byte 0x70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74 "GFXMMU_LUT14H,GFXMMU LUT entry 14 high" hexmask.long.tbyte 0x74 4.--21. 1. "LO,Line offset" line.long 0x78 "GFXMMU_LUT15L,GFXMMU LUT entry 15 low" hexmask.long.byte 0x78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C "GFXMMU_LUT15H,GFXMMU LUT entry 15 high" hexmask.long.tbyte 0x7C 4.--21. 1. "LO,Line offset" line.long 0x80 "GFXMMU_LUT16L,GFXMMU LUT entry 16 low" hexmask.long.byte 0x80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84 "GFXMMU_LUT16H,GFXMMU LUT entry 16 high" hexmask.long.tbyte 0x84 4.--21. 1. "LO,Line offset" line.long 0x88 "GFXMMU_LUT17L,GFXMMU LUT entry 17 low" hexmask.long.byte 0x88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C "GFXMMU_LUT17H,GFXMMU LUT entry 17 high" hexmask.long.tbyte 0x8C 4.--21. 1. "LO,Line offset" line.long 0x90 "GFXMMU_LUT18L,GFXMMU LUT entry 18 low" hexmask.long.byte 0x90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94 "GFXMMU_LUT18H,GFXMMU LUT entry 18 high" hexmask.long.tbyte 0x94 4.--21. 1. "LO,Line offset" line.long 0x98 "GFXMMU_LUT19L,GFXMMU LUT entry 19 low" hexmask.long.byte 0x98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C "GFXMMU_LUT19H,GFXMMU LUT entry 19 high" hexmask.long.tbyte 0x9C 4.--21. 1. "LO,Line offset" line.long 0xA0 "GFXMMU_LUT20L,GFXMMU LUT entry 20 low" hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4 "GFXMMU_LUT20H,GFXMMU LUT entry 20 high" hexmask.long.tbyte 0xA4 4.--21. 1. "LO,Line offset" line.long 0xA8 "GFXMMU_LUT21L,GFXMMU LUT entry 21 low" hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC "GFXMMU_LUT21H,GFXMMU LUT entry 21 high" hexmask.long.tbyte 0xAC 4.--21. 1. "LO,Line offset" line.long 0xB0 "GFXMMU_LUT22L,GFXMMU LUT entry 22 low" hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4 "GFXMMU_LUT22H,GFXMMU LUT entry 22 high" hexmask.long.tbyte 0xB4 4.--21. 1. "LO,Line offset" line.long 0xB8 "GFXMMU_LUT23L,GFXMMU LUT entry 23 low" hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC "GFXMMU_LUT23H,GFXMMU LUT entry 23 high" hexmask.long.tbyte 0xBC 4.--21. 1. "LO,Line offset" line.long 0xC0 "GFXMMU_LUT24L,GFXMMU LUT entry 24 low" hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4 "GFXMMU_LUT24H,GFXMMU LUT entry 24 high" hexmask.long.tbyte 0xC4 4.--21. 1. "LO,Line offset" line.long 0xC8 "GFXMMU_LUT25L,GFXMMU LUT entry 25 low" hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC "GFXMMU_LUT25H,GFXMMU LUT entry 25 high" hexmask.long.tbyte 0xCC 4.--21. 1. "LO,Line offset" line.long 0xD0 "GFXMMU_LUT26L,GFXMMU LUT entry 26 low" hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4 "GFXMMU_LUT26H,GFXMMU LUT entry 26 high" hexmask.long.tbyte 0xD4 4.--21. 1. "LO,Line offset" line.long 0xD8 "GFXMMU_LUT27L,GFXMMU LUT entry 27 low" hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC "GFXMMU_LUT27H,GFXMMU LUT entry 27 high" hexmask.long.tbyte 0xDC 4.--21. 1. "LO,Line offset" line.long 0xE0 "GFXMMU_LUT28L,GFXMMU LUT entry 28 low" hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4 "GFXMMU_LUT28H,GFXMMU LUT entry 28 high" hexmask.long.tbyte 0xE4 4.--21. 1. "LO,Line offset" line.long 0xE8 "GFXMMU_LUT29L,GFXMMU LUT entry 29 low" hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC "GFXMMU_LUT29H,GFXMMU LUT entry 29 high" hexmask.long.tbyte 0xEC 4.--21. 1. "LO,Line offset" line.long 0xF0 "GFXMMU_LUT30L,GFXMMU LUT entry 30 low" hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4 "GFXMMU_LUT30H,GFXMMU LUT entry 30 high" hexmask.long.tbyte 0xF4 4.--21. 1. "LO,Line offset" line.long 0xF8 "GFXMMU_LUT31L,GFXMMU LUT entry 31 low" hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC "GFXMMU_LUT31H,GFXMMU LUT entry 31 high" hexmask.long.tbyte 0xFC 4.--21. 1. "LO,Line offset" line.long 0x100 "GFXMMU_LUT32L,GFXMMU LUT entry 32 low" hexmask.long.byte 0x100 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x100 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x104 "GFXMMU_LUT32H,GFXMMU LUT entry 32 high" hexmask.long.tbyte 0x104 4.--21. 1. "LO,Line offset" line.long 0x108 "GFXMMU_LUT33L,GFXMMU LUT entry 33 low" hexmask.long.byte 0x108 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x108 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x10C "GFXMMU_LUT33H,GFXMMU LUT entry 33 high" hexmask.long.tbyte 0x10C 4.--21. 1. "LO,Line offset" line.long 0x110 "GFXMMU_LUT34L,GFXMMU LUT entry 34 low" hexmask.long.byte 0x110 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x110 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x114 "GFXMMU_LUT34H,GFXMMU LUT entry 34 high" hexmask.long.tbyte 0x114 4.--21. 1. "LO,Line offset" line.long 0x118 "GFXMMU_LUT35L,GFXMMU LUT entry 35 low" hexmask.long.byte 0x118 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x118 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x11C "GFXMMU_LUT35H,GFXMMU LUT entry 35 high" hexmask.long.tbyte 0x11C 4.--21. 1. "LO,Line offset" line.long 0x120 "GFXMMU_LUT36L,GFXMMU LUT entry 36 low" hexmask.long.byte 0x120 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x120 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x124 "GFXMMU_LUT36H,GFXMMU LUT entry 36 high" hexmask.long.tbyte 0x124 4.--21. 1. "LO,Line offset" line.long 0x128 "GFXMMU_LUT37L,GFXMMU LUT entry 37 low" hexmask.long.byte 0x128 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x128 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x12C "GFXMMU_LUT37H,GFXMMU LUT entry 37 high" hexmask.long.tbyte 0x12C 4.--21. 1. "LO,Line offset" line.long 0x130 "GFXMMU_LUT38L,GFXMMU LUT entry 38 low" hexmask.long.byte 0x130 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x130 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x134 "GFXMMU_LUT38H,GFXMMU LUT entry 38 high" hexmask.long.tbyte 0x134 4.--21. 1. "LO,Line offset" line.long 0x138 "GFXMMU_LUT39L,GFXMMU LUT entry 39 low" hexmask.long.byte 0x138 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x138 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x13C "GFXMMU_LUT39H,GFXMMU LUT entry 39 high" hexmask.long.tbyte 0x13C 4.--21. 1. "LO,Line offset" line.long 0x140 "GFXMMU_LUT40L,GFXMMU LUT entry 40 low" hexmask.long.byte 0x140 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x140 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x144 "GFXMMU_LUT40H,GFXMMU LUT entry 40 high" hexmask.long.tbyte 0x144 4.--21. 1. "LO,Line offset" line.long 0x148 "GFXMMU_LUT41L,GFXMMU LUT entry 41 low" hexmask.long.byte 0x148 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x148 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14C "GFXMMU_LUT41H,GFXMMU LUT entry 41 high" hexmask.long.tbyte 0x14C 4.--21. 1. "LO,Line offset" line.long 0x150 "GFXMMU_LUT42L,GFXMMU LUT entry 42 low" hexmask.long.byte 0x150 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x150 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x154 "GFXMMU_LUT42H,GFXMMU LUT entry 42 high" hexmask.long.tbyte 0x154 4.--21. 1. "LO,Line offset" line.long 0x158 "GFXMMU_LUT43L,GFXMMU LUT entry 43 low" hexmask.long.byte 0x158 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x158 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x15C "GFXMMU_LUT43H,GFXMMU LUT entry 43 high" hexmask.long.tbyte 0x15C 4.--21. 1. "LO,Line offset" line.long 0x160 "GFXMMU_LUT44L,GFXMMU LUT entry 44 low" hexmask.long.byte 0x160 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x160 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x164 "GFXMMU_LUT44H,GFXMMU LUT entry 44 high" hexmask.long.tbyte 0x164 4.--21. 1. "LO,Line offset" line.long 0x168 "GFXMMU_LUT45L,GFXMMU LUT entry 45 low" hexmask.long.byte 0x168 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x168 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x16C "GFXMMU_LUT45H,GFXMMU LUT entry 45 high" hexmask.long.tbyte 0x16C 4.--21. 1. "LO,Line offset" line.long 0x170 "GFXMMU_LUT46L,GFXMMU LUT entry 46 low" hexmask.long.byte 0x170 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x170 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x174 "GFXMMU_LUT46H,GFXMMU LUT entry 46 high" hexmask.long.tbyte 0x174 4.--21. 1. "LO,Line offset" line.long 0x178 "GFXMMU_LUT47L,GFXMMU LUT entry 47 low" hexmask.long.byte 0x178 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x178 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x17C "GFXMMU_LUT47H,GFXMMU LUT entry 47 high" hexmask.long.tbyte 0x17C 4.--21. 1. "LO,Line offset" line.long 0x180 "GFXMMU_LUT48L,GFXMMU LUT entry 48 low" hexmask.long.byte 0x180 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x180 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x184 "GFXMMU_LUT48H,GFXMMU LUT entry 48 high" hexmask.long.tbyte 0x184 4.--21. 1. "LO,Line offset" line.long 0x188 "GFXMMU_LUT49L,GFXMMU LUT entry 49 low" hexmask.long.byte 0x188 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x188 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x18C "GFXMMU_LUT49H,GFXMMU LUT entry 49 high" hexmask.long.tbyte 0x18C 4.--21. 1. "LO,Line offset" line.long 0x190 "GFXMMU_LUT50L,GFXMMU LUT entry 50 low" hexmask.long.byte 0x190 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x190 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x194 "GFXMMU_LUT50H,GFXMMU LUT entry 50 high" hexmask.long.tbyte 0x194 4.--21. 1. "LO,Line offset" line.long 0x198 "GFXMMU_LUT51L,GFXMMU LUT entry 51 low" hexmask.long.byte 0x198 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x198 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x19C "GFXMMU_LUT51H,GFXMMU LUT entry 51 high" hexmask.long.tbyte 0x19C 4.--21. 1. "LO,Line offset" line.long 0x1A0 "GFXMMU_LUT52L,GFXMMU LUT entry 52 low" hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1A4 "GFXMMU_LUT52H,GFXMMU LUT entry 52 high" hexmask.long.tbyte 0x1A4 4.--21. 1. "LO,Line offset" line.long 0x1A8 "GFXMMU_LUT53L,GFXMMU LUT entry 53 low" hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1AC "GFXMMU_LUT53H,GFXMMU LUT entry 53 high" hexmask.long.tbyte 0x1AC 4.--21. 1. "LO,Line offset" line.long 0x1B0 "GFXMMU_LUT54L,GFXMMU LUT entry 54 low" hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1B4 "GFXMMU_LUT54H,GFXMMU LUT entry 54 high" hexmask.long.tbyte 0x1B4 4.--21. 1. "LO,Line offset" line.long 0x1B8 "GFXMMU_LUT55L,GFXMMU LUT entry 55 low" hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1BC "GFXMMU_LUT55H,GFXMMU LUT entry 55 high" hexmask.long.tbyte 0x1BC 4.--21. 1. "LO,Line offset" line.long 0x1C0 "GFXMMU_LUT56L,GFXMMU LUT entry 56 low" hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C4 "GFXMMU_LUT56H,GFXMMU LUT entry 56 high" hexmask.long.tbyte 0x1C4 4.--21. 1. "LO,Line offset" line.long 0x1C8 "GFXMMU_LUT57L,GFXMMU LUT entry 57 low" hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1CC "GFXMMU_LUT57H,GFXMMU LUT entry 57 high" hexmask.long.tbyte 0x1CC 4.--21. 1. "LO,Line offset" line.long 0x1D0 "GFXMMU_LUT58L,GFXMMU LUT entry 58 low" hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1D4 "GFXMMU_LUT58H,GFXMMU LUT entry 58 high" hexmask.long.tbyte 0x1D4 4.--21. 1. "LO,Line offset" line.long 0x1D8 "GFXMMU_LUT59L,GFXMMU LUT entry 59 low" hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1DC "GFXMMU_LUT59H,GFXMMU LUT entry 59 high" hexmask.long.tbyte 0x1DC 4.--21. 1. "LO,Line offset" line.long 0x1E0 "GFXMMU_LUT60L,GFXMMU LUT entry 60 low" hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1E4 "GFXMMU_LUT60H,GFXMMU LUT entry 60 high" hexmask.long.tbyte 0x1E4 4.--21. 1. "LO,Line offset" line.long 0x1E8 "GFXMMU_LUT61L,GFXMMU LUT entry 61 low" hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1EC "GFXMMU_LUT61H,GFXMMU LUT entry 61 high" hexmask.long.tbyte 0x1EC 4.--21. 1. "LO,Line offset" line.long 0x1F0 "GFXMMU_LUT62L,GFXMMU LUT entry 62 low" hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1F4 "GFXMMU_LUT62H,GFXMMU LUT entry 62 high" hexmask.long.tbyte 0x1F4 4.--21. 1. "LO,Line offset" line.long 0x1F8 "GFXMMU_LUT63L,GFXMMU LUT entry 63 low" hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1FC "GFXMMU_LUT63H,GFXMMU LUT entry 63 high" hexmask.long.tbyte 0x1FC 4.--21. 1. "LO,Line offset" line.long 0x200 "GFXMMU_LUT64L,GFXMMU LUT entry 64 low" hexmask.long.byte 0x200 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x200 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x204 "GFXMMU_LUT64H,GFXMMU LUT entry 64 high" hexmask.long.tbyte 0x204 4.--21. 1. "LO,Line offset" line.long 0x208 "GFXMMU_LUT65L,GFXMMU LUT entry 65 low" hexmask.long.byte 0x208 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x208 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x20C "GFXMMU_LUT65H,GFXMMU LUT entry 65 high" hexmask.long.tbyte 0x20C 4.--21. 1. "LO,Line offset" line.long 0x210 "GFXMMU_LUT66L,GFXMMU LUT entry 66 low" hexmask.long.byte 0x210 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x210 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x214 "GFXMMU_LUT66H,GFXMMU LUT entry 66 high" hexmask.long.tbyte 0x214 4.--21. 1. "LO,Line offset" line.long 0x218 "GFXMMU_LUT67L,GFXMMU LUT entry 67 low" hexmask.long.byte 0x218 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x218 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x21C "GFXMMU_LUT67H,GFXMMU LUT entry 67 high" hexmask.long.tbyte 0x21C 4.--21. 1. "LO,Line offset" line.long 0x220 "GFXMMU_LUT68L,GFXMMU LUT entry 68 low" hexmask.long.byte 0x220 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x220 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x224 "GFXMMU_LUT68H,GFXMMU LUT entry 68 high" hexmask.long.tbyte 0x224 4.--21. 1. "LO,Line offset" line.long 0x228 "GFXMMU_LUT69L,GFXMMU LUT entry 69 low" hexmask.long.byte 0x228 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x228 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x22C "GFXMMU_LUT69H,GFXMMU LUT entry 69 high" hexmask.long.tbyte 0x22C 4.--21. 1. "LO,Line offset" line.long 0x230 "GFXMMU_LUT70L,GFXMMU LUT entry 70 low" hexmask.long.byte 0x230 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x230 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x234 "GFXMMU_LUT70H,GFXMMU LUT entry 70 high" hexmask.long.tbyte 0x234 4.--21. 1. "LO,Line offset" line.long 0x238 "GFXMMU_LUT71L,GFXMMU LUT entry 71 low" hexmask.long.byte 0x238 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x238 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x23C "GFXMMU_LUT71H,GFXMMU LUT entry 71 high" hexmask.long.tbyte 0x23C 4.--21. 1. "LO,Line offset" line.long 0x240 "GFXMMU_LUT72L,GFXMMU LUT entry 72 low" hexmask.long.byte 0x240 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x240 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x244 "GFXMMU_LUT72H,GFXMMU LUT entry 72 high" hexmask.long.tbyte 0x244 4.--21. 1. "LO,Line offset" line.long 0x248 "GFXMMU_LUT73L,GFXMMU LUT entry 73 low" hexmask.long.byte 0x248 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x248 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24C "GFXMMU_LUT73H,GFXMMU LUT entry 73 high" hexmask.long.tbyte 0x24C 4.--21. 1. "LO,Line offset" line.long 0x250 "GFXMMU_LUT74L,GFXMMU LUT entry 74 low" hexmask.long.byte 0x250 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x250 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x254 "GFXMMU_LUT74H,GFXMMU LUT entry 74 high" hexmask.long.tbyte 0x254 4.--21. 1. "LO,Line offset" line.long 0x258 "GFXMMU_LUT75L,GFXMMU LUT entry 75 low" hexmask.long.byte 0x258 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x258 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x25C "GFXMMU_LUT75H,GFXMMU LUT entry 75 high" hexmask.long.tbyte 0x25C 4.--21. 1. "LO,Line offset" line.long 0x260 "GFXMMU_LUT76L,GFXMMU LUT entry 76 low" hexmask.long.byte 0x260 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x260 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x264 "GFXMMU_LUT76H,GFXMMU LUT entry 76 high" hexmask.long.tbyte 0x264 4.--21. 1. "LO,Line offset" line.long 0x268 "GFXMMU_LUT77L,GFXMMU LUT entry 77 low" hexmask.long.byte 0x268 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x268 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x26C "GFXMMU_LUT77H,GFXMMU LUT entry 77 high" hexmask.long.tbyte 0x26C 4.--21. 1. "LO,Line offset" line.long 0x270 "GFXMMU_LUT78L,GFXMMU LUT entry 78 low" hexmask.long.byte 0x270 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x270 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x274 "GFXMMU_LUT78H,GFXMMU LUT entry 78 high" hexmask.long.tbyte 0x274 4.--21. 1. "LO,Line offset" line.long 0x278 "GFXMMU_LUT79L,GFXMMU LUT entry 79 low" hexmask.long.byte 0x278 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x278 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x27C "GFXMMU_LUT79H,GFXMMU LUT entry 79 high" hexmask.long.tbyte 0x27C 4.--21. 1. "LO,Line offset" line.long 0x280 "GFXMMU_LUT80L,GFXMMU LUT entry 80 low" hexmask.long.byte 0x280 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x280 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x284 "GFXMMU_LUT80H,GFXMMU LUT entry 80 high" hexmask.long.tbyte 0x284 4.--21. 1. "LO,Line offset" line.long 0x288 "GFXMMU_LUT81L,GFXMMU LUT entry 81 low" hexmask.long.byte 0x288 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x288 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x28C "GFXMMU_LUT81H,GFXMMU LUT entry 81 high" hexmask.long.tbyte 0x28C 4.--21. 1. "LO,Line offset" line.long 0x290 "GFXMMU_LUT82L,GFXMMU LUT entry 82 low" hexmask.long.byte 0x290 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x290 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x294 "GFXMMU_LUT82H,GFXMMU LUT entry 82 high" hexmask.long.tbyte 0x294 4.--21. 1. "LO,Line offset" line.long 0x298 "GFXMMU_LUT83L,GFXMMU LUT entry 83 low" hexmask.long.byte 0x298 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x298 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x29C "GFXMMU_LUT83H,GFXMMU LUT entry 83 high" hexmask.long.tbyte 0x29C 4.--21. 1. "LO,Line offset" line.long 0x2A0 "GFXMMU_LUT84L,GFXMMU LUT entry 84 low" hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2A4 "GFXMMU_LUT84H,GFXMMU LUT entry 84 high" hexmask.long.tbyte 0x2A4 4.--21. 1. "LO,Line offset" line.long 0x2A8 "GFXMMU_LUT85L,GFXMMU LUT entry 85 low" hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2AC "GFXMMU_LUT85H,GFXMMU LUT entry 85 high" hexmask.long.tbyte 0x2AC 4.--21. 1. "LO,Line offset" line.long 0x2B0 "GFXMMU_LUT86L,GFXMMU LUT entry 86 low" hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2B4 "GFXMMU_LUT86H,GFXMMU LUT entry 86 high" hexmask.long.tbyte 0x2B4 4.--21. 1. "LO,Line offset" line.long 0x2B8 "GFXMMU_LUT87L,GFXMMU LUT entry 87 low" hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2BC "GFXMMU_LUT87H,GFXMMU LUT entry 87 high" hexmask.long.tbyte 0x2BC 4.--21. 1. "LO,Line offset" line.long 0x2C0 "GFXMMU_LUT88L,GFXMMU LUT entry 88 low" hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C4 "GFXMMU_LUT88H,GFXMMU LUT entry 88 high" hexmask.long.tbyte 0x2C4 4.--21. 1. "LO,Line offset" line.long 0x2C8 "GFXMMU_LUT89L,GFXMMU LUT entry 89 low" hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2CC "GFXMMU_LUT89H,GFXMMU LUT entry 89 high" hexmask.long.tbyte 0x2CC 4.--21. 1. "LO,Line offset" line.long 0x2D0 "GFXMMU_LUT90L,GFXMMU LUT entry 90 low" hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2D4 "GFXMMU_LUT90H,GFXMMU LUT entry 90 high" hexmask.long.tbyte 0x2D4 4.--21. 1. "LO,Line offset" line.long 0x2D8 "GFXMMU_LUT91L,GFXMMU LUT entry 91 low" hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2DC "GFXMMU_LUT91H,GFXMMU LUT entry 91 high" hexmask.long.tbyte 0x2DC 4.--21. 1. "LO,Line offset" line.long 0x2E0 "GFXMMU_LUT92L,GFXMMU LUT entry 92 low" hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2E4 "GFXMMU_LUT92H,GFXMMU LUT entry 92 high" hexmask.long.tbyte 0x2E4 4.--21. 1. "LO,Line offset" line.long 0x2E8 "GFXMMU_LUT93L,GFXMMU LUT entry 93 low" hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2EC "GFXMMU_LUT93H,GFXMMU LUT entry 93 high" hexmask.long.tbyte 0x2EC 4.--21. 1. "LO,Line offset" line.long 0x2F0 "GFXMMU_LUT94L,GFXMMU LUT entry 94 low" hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2F4 "GFXMMU_LUT94H,GFXMMU LUT entry 94 high" hexmask.long.tbyte 0x2F4 4.--21. 1. "LO,Line offset" line.long 0x2F8 "GFXMMU_LUT95L,GFXMMU LUT entry 95 low" hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2FC "GFXMMU_LUT95H,GFXMMU LUT entry 95 high" hexmask.long.tbyte 0x2FC 4.--21. 1. "LO,Line offset" line.long 0x300 "GFXMMU_LUT96L,GFXMMU LUT entry 96 low" hexmask.long.byte 0x300 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x300 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x304 "GFXMMU_LUT96H,GFXMMU LUT entry 96 high" hexmask.long.tbyte 0x304 4.--21. 1. "LO,Line offset" line.long 0x308 "GFXMMU_LUT97L,GFXMMU LUT entry 97 low" hexmask.long.byte 0x308 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x308 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x30C "GFXMMU_LUT97H,GFXMMU LUT entry 97 high" hexmask.long.tbyte 0x30C 4.--21. 1. "LO,Line offset" line.long 0x310 "GFXMMU_LUT98L,GFXMMU LUT entry 98 low" hexmask.long.byte 0x310 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x310 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x314 "GFXMMU_LUT98H,GFXMMU LUT entry 98 high" hexmask.long.tbyte 0x314 4.--21. 1. "LO,Line offset" line.long 0x318 "GFXMMU_LUT99L,GFXMMU LUT entry 99 low" hexmask.long.byte 0x318 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x318 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x31C "GFXMMU_LUT99H,GFXMMU LUT entry 99 high" hexmask.long.tbyte 0x31C 4.--21. 1. "LO,Line offset" line.long 0x320 "GFXMMU_LUT100L,GFXMMU LUT entry 100 low" hexmask.long.byte 0x320 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x320 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x324 "GFXMMU_LUT100H,GFXMMU LUT entry 100 high" hexmask.long.tbyte 0x324 4.--21. 1. "LO,Line offset" line.long 0x328 "GFXMMU_LUT101L,GFXMMU LUT entry 101 low" hexmask.long.byte 0x328 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x328 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x32C "GFXMMU_LUT101H,GFXMMU LUT entry 101 high" hexmask.long.tbyte 0x32C 4.--21. 1. "LO,Line offset" line.long 0x330 "GFXMMU_LUT102L,GFXMMU LUT entry 102 low" hexmask.long.byte 0x330 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x330 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x334 "GFXMMU_LUT102H,GFXMMU LUT entry 102 high" hexmask.long.tbyte 0x334 4.--21. 1. "LO,Line offset" line.long 0x338 "GFXMMU_LUT103L,GFXMMU LUT entry 103 low" hexmask.long.byte 0x338 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x338 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x33C "GFXMMU_LUT103H,GFXMMU LUT entry 103 high" hexmask.long.tbyte 0x33C 4.--21. 1. "LO,Line offset" line.long 0x340 "GFXMMU_LUT104L,GFXMMU LUT entry 104 low" hexmask.long.byte 0x340 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x340 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x344 "GFXMMU_LUT104H,GFXMMU LUT entry 104 high" hexmask.long.tbyte 0x344 4.--21. 1. "LO,Line offset" line.long 0x348 "GFXMMU_LUT105L,GFXMMU LUT entry 105 low" hexmask.long.byte 0x348 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x348 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34C "GFXMMU_LUT105H,GFXMMU LUT entry 105 high" hexmask.long.tbyte 0x34C 4.--21. 1. "LO,Line offset" line.long 0x350 "GFXMMU_LUT106L,GFXMMU LUT entry 106 low" hexmask.long.byte 0x350 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x350 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x354 "GFXMMU_LUT106H,GFXMMU LUT entry 106 high" hexmask.long.tbyte 0x354 4.--21. 1. "LO,Line offset" line.long 0x358 "GFXMMU_LUT107L,GFXMMU LUT entry 107 low" hexmask.long.byte 0x358 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x358 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x35C "GFXMMU_LUT107H,GFXMMU LUT entry 107 high" hexmask.long.tbyte 0x35C 4.--21. 1. "LO,Line offset" line.long 0x360 "GFXMMU_LUT108L,GFXMMU LUT entry 108 low" hexmask.long.byte 0x360 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x360 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x364 "GFXMMU_LUT108H,GFXMMU LUT entry 108 high" hexmask.long.tbyte 0x364 4.--21. 1. "LO,Line offset" line.long 0x368 "GFXMMU_LUT109L,GFXMMU LUT entry 109 low" hexmask.long.byte 0x368 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x368 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x36C "GFXMMU_LUT109H,GFXMMU LUT entry 109 high" hexmask.long.tbyte 0x36C 4.--21. 1. "LO,Line offset" line.long 0x370 "GFXMMU_LUT110L,GFXMMU LUT entry 110 low" hexmask.long.byte 0x370 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x370 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x374 "GFXMMU_LUT110H,GFXMMU LUT entry 110 high" hexmask.long.tbyte 0x374 4.--21. 1. "LO,Line offset" line.long 0x378 "GFXMMU_LUT111L,GFXMMU LUT entry 111 low" hexmask.long.byte 0x378 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x378 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x37C "GFXMMU_LUT111H,GFXMMU LUT entry 111 high" hexmask.long.tbyte 0x37C 4.--21. 1. "LO,Line offset" line.long 0x380 "GFXMMU_LUT112L,GFXMMU LUT entry 112 low" hexmask.long.byte 0x380 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x380 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x384 "GFXMMU_LUT112H,GFXMMU LUT entry 112 high" hexmask.long.tbyte 0x384 4.--21. 1. "LO,Line offset" line.long 0x388 "GFXMMU_LUT113L,GFXMMU LUT entry 113 low" hexmask.long.byte 0x388 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x388 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x38C "GFXMMU_LUT113H,GFXMMU LUT entry 113 high" hexmask.long.tbyte 0x38C 4.--21. 1. "LO,Line offset" line.long 0x390 "GFXMMU_LUT114L,GFXMMU LUT entry 114 low" hexmask.long.byte 0x390 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x390 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x394 "GFXMMU_LUT114H,GFXMMU LUT entry 114 high" hexmask.long.tbyte 0x394 4.--21. 1. "LO,Line offset" line.long 0x398 "GFXMMU_LUT115L,GFXMMU LUT entry 115 low" hexmask.long.byte 0x398 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x398 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x39C "GFXMMU_LUT115H,GFXMMU LUT entry 115 high" hexmask.long.tbyte 0x39C 4.--21. 1. "LO,Line offset" line.long 0x3A0 "GFXMMU_LUT116L,GFXMMU LUT entry 116 low" hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3A4 "GFXMMU_LUT116H,GFXMMU LUT entry 116 high" hexmask.long.tbyte 0x3A4 4.--21. 1. "LO,Line offset" line.long 0x3A8 "GFXMMU_LUT117L,GFXMMU LUT entry 117 low" hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3AC "GFXMMU_LUT117H,GFXMMU LUT entry 117 high" hexmask.long.tbyte 0x3AC 4.--21. 1. "LO,Line offset" line.long 0x3B0 "GFXMMU_LUT118L,GFXMMU LUT entry 118 low" hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3B4 "GFXMMU_LUT118H,GFXMMU LUT entry 118 high" hexmask.long.tbyte 0x3B4 4.--21. 1. "LO,Line offset" line.long 0x3B8 "GFXMMU_LUT119L,GFXMMU LUT entry 119 low" hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3BC "GFXMMU_LUT119H,GFXMMU LUT entry 119 high" hexmask.long.tbyte 0x3BC 4.--21. 1. "LO,Line offset" line.long 0x3C0 "GFXMMU_LUT120L,GFXMMU LUT entry 120 low" hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C4 "GFXMMU_LUT120H,GFXMMU LUT entry 120 high" hexmask.long.tbyte 0x3C4 4.--21. 1. "LO,Line offset" line.long 0x3C8 "GFXMMU_LUT121L,GFXMMU LUT entry 121 low" hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3CC "GFXMMU_LUT121H,GFXMMU LUT entry 121 high" hexmask.long.tbyte 0x3CC 4.--21. 1. "LO,Line offset" line.long 0x3D0 "GFXMMU_LUT122L,GFXMMU LUT entry 122 low" hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3D4 "GFXMMU_LUT122H,GFXMMU LUT entry 122 high" hexmask.long.tbyte 0x3D4 4.--21. 1. "LO,Line offset" line.long 0x3D8 "GFXMMU_LUT123L,GFXMMU LUT entry 123 low" hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3DC "GFXMMU_LUT123H,GFXMMU LUT entry 123 high" hexmask.long.tbyte 0x3DC 4.--21. 1. "LO,Line offset" line.long 0x3E0 "GFXMMU_LUT124L,GFXMMU LUT entry 124 low" hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3E4 "GFXMMU_LUT124H,GFXMMU LUT entry 124 high" hexmask.long.tbyte 0x3E4 4.--21. 1. "LO,Line offset" line.long 0x3E8 "GFXMMU_LUT125L,GFXMMU LUT entry 125 low" hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3EC "GFXMMU_LUT125H,GFXMMU LUT entry 125 high" hexmask.long.tbyte 0x3EC 4.--21. 1. "LO,Line offset" line.long 0x3F0 "GFXMMU_LUT126L,GFXMMU LUT entry 126 low" hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3F4 "GFXMMU_LUT126H,GFXMMU LUT entry 126 high" hexmask.long.tbyte 0x3F4 4.--21. 1. "LO,Line offset" line.long 0x3F8 "GFXMMU_LUT127L,GFXMMU LUT entry 127 low" hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3FC "GFXMMU_LUT127H,GFXMMU LUT entry 127 high" hexmask.long.tbyte 0x3FC 4.--21. 1. "LO,Line offset" line.long 0x400 "GFXMMU_LUT128L,GFXMMU LUT entry 128 low" hexmask.long.byte 0x400 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x400 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x404 "GFXMMU_LUT128H,GFXMMU LUT entry 128 high" hexmask.long.tbyte 0x404 4.--21. 1. "LO,Line offset" line.long 0x408 "GFXMMU_LUT129L,GFXMMU LUT entry 129 low" hexmask.long.byte 0x408 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x408 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x40C "GFXMMU_LUT129H,GFXMMU LUT entry 129 high" hexmask.long.tbyte 0x40C 4.--21. 1. "LO,Line offset" line.long 0x410 "GFXMMU_LUT130L,GFXMMU LUT entry 130 low" hexmask.long.byte 0x410 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x410 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x414 "GFXMMU_LUT130H,GFXMMU LUT entry 130 high" hexmask.long.tbyte 0x414 4.--21. 1. "LO,Line offset" line.long 0x418 "GFXMMU_LUT131L,GFXMMU LUT entry 131 low" hexmask.long.byte 0x418 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x418 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x41C "GFXMMU_LUT131H,GFXMMU LUT entry 131 high" hexmask.long.tbyte 0x41C 4.--21. 1. "LO,Line offset" line.long 0x420 "GFXMMU_LUT132L,GFXMMU LUT entry 132 low" hexmask.long.byte 0x420 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x420 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x424 "GFXMMU_LUT132H,GFXMMU LUT entry 132 high" hexmask.long.tbyte 0x424 4.--21. 1. "LO,Line offset" line.long 0x428 "GFXMMU_LUT133L,GFXMMU LUT entry 133 low" hexmask.long.byte 0x428 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x428 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x42C "GFXMMU_LUT133H,GFXMMU LUT entry 133 high" hexmask.long.tbyte 0x42C 4.--21. 1. "LO,Line offset" line.long 0x430 "GFXMMU_LUT134L,GFXMMU LUT entry 134 low" hexmask.long.byte 0x430 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x430 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x434 "GFXMMU_LUT134H,GFXMMU LUT entry 134 high" hexmask.long.tbyte 0x434 4.--21. 1. "LO,Line offset" line.long 0x438 "GFXMMU_LUT135L,GFXMMU LUT entry 135 low" hexmask.long.byte 0x438 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x438 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x43C "GFXMMU_LUT135H,GFXMMU LUT entry 135 high" hexmask.long.tbyte 0x43C 4.--21. 1. "LO,Line offset" line.long 0x440 "GFXMMU_LUT136L,GFXMMU LUT entry 136 low" hexmask.long.byte 0x440 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x440 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x444 "GFXMMU_LUT136H,GFXMMU LUT entry 136 high" hexmask.long.tbyte 0x444 4.--21. 1. "LO,Line offset" line.long 0x448 "GFXMMU_LUT137L,GFXMMU LUT entry 137 low" hexmask.long.byte 0x448 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x448 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44C "GFXMMU_LUT137H,GFXMMU LUT entry 137 high" hexmask.long.tbyte 0x44C 4.--21. 1. "LO,Line offset" line.long 0x450 "GFXMMU_LUT138L,GFXMMU LUT entry 138 low" hexmask.long.byte 0x450 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x450 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x454 "GFXMMU_LUT138H,GFXMMU LUT entry 138 high" hexmask.long.tbyte 0x454 4.--21. 1. "LO,Line offset" line.long 0x458 "GFXMMU_LUT139L,GFXMMU LUT entry 139 low" hexmask.long.byte 0x458 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x458 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x45C "GFXMMU_LUT139H,GFXMMU LUT entry 139 high" hexmask.long.tbyte 0x45C 4.--21. 1. "LO,Line offset" line.long 0x460 "GFXMMU_LUT140L,GFXMMU LUT entry 140 low" hexmask.long.byte 0x460 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x460 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x464 "GFXMMU_LUT140H,GFXMMU LUT entry 140 high" hexmask.long.tbyte 0x464 4.--21. 1. "LO,Line offset" line.long 0x468 "GFXMMU_LUT141L,GFXMMU LUT entry 141 low" hexmask.long.byte 0x468 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x468 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x46C "GFXMMU_LUT141H,GFXMMU LUT entry 141 high" hexmask.long.tbyte 0x46C 4.--21. 1. "LO,Line offset" line.long 0x470 "GFXMMU_LUT142L,GFXMMU LUT entry 142 low" hexmask.long.byte 0x470 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x470 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x474 "GFXMMU_LUT142H,GFXMMU LUT entry 142 high" hexmask.long.tbyte 0x474 4.--21. 1. "LO,Line offset" line.long 0x478 "GFXMMU_LUT143L,GFXMMU LUT entry 143 low" hexmask.long.byte 0x478 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x478 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x47C "GFXMMU_LUT143H,GFXMMU LUT entry 143 high" hexmask.long.tbyte 0x47C 4.--21. 1. "LO,Line offset" line.long 0x480 "GFXMMU_LUT144L,GFXMMU LUT entry 144 low" hexmask.long.byte 0x480 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x480 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x484 "GFXMMU_LUT144H,GFXMMU LUT entry 144 high" hexmask.long.tbyte 0x484 4.--21. 1. "LO,Line offset" line.long 0x488 "GFXMMU_LUT145L,GFXMMU LUT entry 145 low" hexmask.long.byte 0x488 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x488 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x48C "GFXMMU_LUT145H,GFXMMU LUT entry 145 high" hexmask.long.tbyte 0x48C 4.--21. 1. "LO,Line offset" line.long 0x490 "GFXMMU_LUT146L,GFXMMU LUT entry 146 low" hexmask.long.byte 0x490 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x490 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x494 "GFXMMU_LUT146H,GFXMMU LUT entry 146 high" hexmask.long.tbyte 0x494 4.--21. 1. "LO,Line offset" line.long 0x498 "GFXMMU_LUT147L,GFXMMU LUT entry 147 low" hexmask.long.byte 0x498 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x498 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x49C "GFXMMU_LUT147H,GFXMMU LUT entry 147 high" hexmask.long.tbyte 0x49C 4.--21. 1. "LO,Line offset" line.long 0x4A0 "GFXMMU_LUT148L,GFXMMU LUT entry 148 low" hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4A4 "GFXMMU_LUT148H,GFXMMU LUT entry 148 high" hexmask.long.tbyte 0x4A4 4.--21. 1. "LO,Line offset" line.long 0x4A8 "GFXMMU_LUT149L,GFXMMU LUT entry 149 low" hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4AC "GFXMMU_LUT149H,GFXMMU LUT entry 149 high" hexmask.long.tbyte 0x4AC 4.--21. 1. "LO,Line offset" line.long 0x4B0 "GFXMMU_LUT150L,GFXMMU LUT entry 150 low" hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4B4 "GFXMMU_LUT150H,GFXMMU LUT entry 150 high" hexmask.long.tbyte 0x4B4 4.--21. 1. "LO,Line offset" line.long 0x4B8 "GFXMMU_LUT151L,GFXMMU LUT entry 151 low" hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4BC "GFXMMU_LUT151H,GFXMMU LUT entry 151 high" hexmask.long.tbyte 0x4BC 4.--21. 1. "LO,Line offset" line.long 0x4C0 "GFXMMU_LUT152L,GFXMMU LUT entry 152 low" hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C4 "GFXMMU_LUT152H,GFXMMU LUT entry 152 high" hexmask.long.tbyte 0x4C4 4.--21. 1. "LO,Line offset" line.long 0x4C8 "GFXMMU_LUT153L,GFXMMU LUT entry 153 low" hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4CC "GFXMMU_LUT153H,GFXMMU LUT entry 153 high" hexmask.long.tbyte 0x4CC 4.--21. 1. "LO,Line offset" line.long 0x4D0 "GFXMMU_LUT154L,GFXMMU LUT entry 154 low" hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4D4 "GFXMMU_LUT154H,GFXMMU LUT entry 154 high" hexmask.long.tbyte 0x4D4 4.--21. 1. "LO,Line offset" line.long 0x4D8 "GFXMMU_LUT155L,GFXMMU LUT entry 155 low" hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4DC "GFXMMU_LUT155H,GFXMMU LUT entry 155 high" hexmask.long.tbyte 0x4DC 4.--21. 1. "LO,Line offset" line.long 0x4E0 "GFXMMU_LUT156L,GFXMMU LUT entry 156 low" hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4E4 "GFXMMU_LUT156H,GFXMMU LUT entry 156 high" hexmask.long.tbyte 0x4E4 4.--21. 1. "LO,Line offset" line.long 0x4E8 "GFXMMU_LUT157L,GFXMMU LUT entry 157 low" hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4EC "GFXMMU_LUT157H,GFXMMU LUT entry 157 high" hexmask.long.tbyte 0x4EC 4.--21. 1. "LO,Line offset" line.long 0x4F0 "GFXMMU_LUT158L,GFXMMU LUT entry 158 low" hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4F4 "GFXMMU_LUT158H,GFXMMU LUT entry 158 high" hexmask.long.tbyte 0x4F4 4.--21. 1. "LO,Line offset" line.long 0x4F8 "GFXMMU_LUT159L,GFXMMU LUT entry 159 low" hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4FC "GFXMMU_LUT159H,GFXMMU LUT entry 159 high" hexmask.long.tbyte 0x4FC 4.--21. 1. "LO,Line offset" line.long 0x500 "GFXMMU_LUT160L,GFXMMU LUT entry 160 low" hexmask.long.byte 0x500 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x500 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x504 "GFXMMU_LUT160H,GFXMMU LUT entry 160 high" hexmask.long.tbyte 0x504 4.--21. 1. "LO,Line offset" line.long 0x508 "GFXMMU_LUT161L,GFXMMU LUT entry 161 low" hexmask.long.byte 0x508 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x508 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x50C "GFXMMU_LUT161H,GFXMMU LUT entry 161 high" hexmask.long.tbyte 0x50C 4.--21. 1. "LO,Line offset" line.long 0x510 "GFXMMU_LUT162L,GFXMMU LUT entry 162 low" hexmask.long.byte 0x510 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x510 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x514 "GFXMMU_LUT162H,GFXMMU LUT entry 162 high" hexmask.long.tbyte 0x514 4.--21. 1. "LO,Line offset" line.long 0x518 "GFXMMU_LUT163L,GFXMMU LUT entry 163 low" hexmask.long.byte 0x518 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x518 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x51C "GFXMMU_LUT163H,GFXMMU LUT entry 163 high" hexmask.long.tbyte 0x51C 4.--21. 1. "LO,Line offset" line.long 0x520 "GFXMMU_LUT164L,GFXMMU LUT entry 164 low" hexmask.long.byte 0x520 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x520 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x524 "GFXMMU_LUT164H,GFXMMU LUT entry 164 high" hexmask.long.tbyte 0x524 4.--21. 1. "LO,Line offset" line.long 0x528 "GFXMMU_LUT165L,GFXMMU LUT entry 165 low" hexmask.long.byte 0x528 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x528 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x52C "GFXMMU_LUT165H,GFXMMU LUT entry 165 high" hexmask.long.tbyte 0x52C 4.--21. 1. "LO,Line offset" line.long 0x530 "GFXMMU_LUT166L,GFXMMU LUT entry 166 low" hexmask.long.byte 0x530 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x530 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x534 "GFXMMU_LUT166H,GFXMMU LUT entry 166 high" hexmask.long.tbyte 0x534 4.--21. 1. "LO,Line offset" line.long 0x538 "GFXMMU_LUT167L,GFXMMU LUT entry 167 low" hexmask.long.byte 0x538 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x538 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x53C "GFXMMU_LUT167H,GFXMMU LUT entry 167 high" hexmask.long.tbyte 0x53C 4.--21. 1. "LO,Line offset" line.long 0x540 "GFXMMU_LUT168L,GFXMMU LUT entry 168 low" hexmask.long.byte 0x540 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x540 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x544 "GFXMMU_LUT168H,GFXMMU LUT entry 168 high" hexmask.long.tbyte 0x544 4.--21. 1. "LO,Line offset" line.long 0x548 "GFXMMU_LUT169L,GFXMMU LUT entry 169 low" hexmask.long.byte 0x548 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x548 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54C "GFXMMU_LUT169H,GFXMMU LUT entry 169 high" hexmask.long.tbyte 0x54C 4.--21. 1. "LO,Line offset" line.long 0x550 "GFXMMU_LUT170L,GFXMMU LUT entry 170 low" hexmask.long.byte 0x550 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x550 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x554 "GFXMMU_LUT170H,GFXMMU LUT entry 170 high" hexmask.long.tbyte 0x554 4.--21. 1. "LO,Line offset" line.long 0x558 "GFXMMU_LUT171L,GFXMMU LUT entry 171 low" hexmask.long.byte 0x558 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x558 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x55C "GFXMMU_LUT171H,GFXMMU LUT entry 171 high" hexmask.long.tbyte 0x55C 4.--21. 1. "LO,Line offset" line.long 0x560 "GFXMMU_LUT172L,GFXMMU LUT entry 172 low" hexmask.long.byte 0x560 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x560 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x564 "GFXMMU_LUT172H,GFXMMU LUT entry 172 high" hexmask.long.tbyte 0x564 4.--21. 1. "LO,Line offset" line.long 0x568 "GFXMMU_LUT173L,GFXMMU LUT entry 173 low" hexmask.long.byte 0x568 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x568 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x56C "GFXMMU_LUT173H,GFXMMU LUT entry 173 high" hexmask.long.tbyte 0x56C 4.--21. 1. "LO,Line offset" line.long 0x570 "GFXMMU_LUT174L,GFXMMU LUT entry 174 low" hexmask.long.byte 0x570 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x570 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x574 "GFXMMU_LUT174H,GFXMMU LUT entry 174 high" hexmask.long.tbyte 0x574 4.--21. 1. "LO,Line offset" line.long 0x578 "GFXMMU_LUT175L,GFXMMU LUT entry 175 low" hexmask.long.byte 0x578 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x578 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x57C "GFXMMU_LUT175H,GFXMMU LUT entry 175 high" hexmask.long.tbyte 0x57C 4.--21. 1. "LO,Line offset" line.long 0x580 "GFXMMU_LUT176L,GFXMMU LUT entry 176 low" hexmask.long.byte 0x580 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x580 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x584 "GFXMMU_LUT176H,GFXMMU LUT entry 176 high" hexmask.long.tbyte 0x584 4.--21. 1. "LO,Line offset" line.long 0x588 "GFXMMU_LUT177L,GFXMMU LUT entry 177 low" hexmask.long.byte 0x588 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x588 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x58C "GFXMMU_LUT177H,GFXMMU LUT entry 177 high" hexmask.long.tbyte 0x58C 4.--21. 1. "LO,Line offset" line.long 0x590 "GFXMMU_LUT178L,GFXMMU LUT entry 178 low" hexmask.long.byte 0x590 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x590 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x594 "GFXMMU_LUT178H,GFXMMU LUT entry 178 high" hexmask.long.tbyte 0x594 4.--21. 1. "LO,Line offset" line.long 0x598 "GFXMMU_LUT179L,GFXMMU LUT entry 179 low" hexmask.long.byte 0x598 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x598 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x59C "GFXMMU_LUT179H,GFXMMU LUT entry 179 high" hexmask.long.tbyte 0x59C 4.--21. 1. "LO,Line offset" line.long 0x5A0 "GFXMMU_LUT180L,GFXMMU LUT entry 180 low" hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5A4 "GFXMMU_LUT180H,GFXMMU LUT entry 180 high" hexmask.long.tbyte 0x5A4 4.--21. 1. "LO,Line offset" line.long 0x5A8 "GFXMMU_LUT181L,GFXMMU LUT entry 181 low" hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5AC "GFXMMU_LUT181H,GFXMMU LUT entry 181 high" hexmask.long.tbyte 0x5AC 4.--21. 1. "LO,Line offset" line.long 0x5B0 "GFXMMU_LUT182L,GFXMMU LUT entry 182 low" hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5B4 "GFXMMU_LUT182H,GFXMMU LUT entry 182 high" hexmask.long.tbyte 0x5B4 4.--21. 1. "LO,Line offset" line.long 0x5B8 "GFXMMU_LUT183L,GFXMMU LUT entry 183 low" hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5BC "GFXMMU_LUT183H,GFXMMU LUT entry 183 high" hexmask.long.tbyte 0x5BC 4.--21. 1. "LO,Line offset" line.long 0x5C0 "GFXMMU_LUT184L,GFXMMU LUT entry 184 low" hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C4 "GFXMMU_LUT184H,GFXMMU LUT entry 184 high" hexmask.long.tbyte 0x5C4 4.--21. 1. "LO,Line offset" line.long 0x5C8 "GFXMMU_LUT185L,GFXMMU LUT entry 185 low" hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5CC "GFXMMU_LUT185H,GFXMMU LUT entry 185 high" hexmask.long.tbyte 0x5CC 4.--21. 1. "LO,Line offset" line.long 0x5D0 "GFXMMU_LUT186L,GFXMMU LUT entry 186 low" hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5D4 "GFXMMU_LUT186H,GFXMMU LUT entry 186 high" hexmask.long.tbyte 0x5D4 4.--21. 1. "LO,Line offset" line.long 0x5D8 "GFXMMU_LUT187L,GFXMMU LUT entry 187 low" hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5DC "GFXMMU_LUT187H,GFXMMU LUT entry 187 high" hexmask.long.tbyte 0x5DC 4.--21. 1. "LO,Line offset" line.long 0x5E0 "GFXMMU_LUT188L,GFXMMU LUT entry 188 low" hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5E4 "GFXMMU_LUT188H,GFXMMU LUT entry 188 high" hexmask.long.tbyte 0x5E4 4.--21. 1. "LO,Line offset" line.long 0x5E8 "GFXMMU_LUT189L,GFXMMU LUT entry 189 low" hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5EC "GFXMMU_LUT189H,GFXMMU LUT entry 189 high" hexmask.long.tbyte 0x5EC 4.--21. 1. "LO,Line offset" line.long 0x5F0 "GFXMMU_LUT190L,GFXMMU LUT entry 190 low" hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5F4 "GFXMMU_LUT190H,GFXMMU LUT entry 190 high" hexmask.long.tbyte 0x5F4 4.--21. 1. "LO,Line offset" line.long 0x5F8 "GFXMMU_LUT191L,GFXMMU LUT entry 191 low" hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5FC "GFXMMU_LUT191H,GFXMMU LUT entry 191 high" hexmask.long.tbyte 0x5FC 4.--21. 1. "LO,Line offset" line.long 0x600 "GFXMMU_LUT192L,GFXMMU LUT entry 192 low" hexmask.long.byte 0x600 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x600 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x604 "GFXMMU_LUT192H,GFXMMU LUT entry 192 high" hexmask.long.tbyte 0x604 4.--21. 1. "LO,Line offset" line.long 0x608 "GFXMMU_LUT193L,GFXMMU LUT entry 193 low" hexmask.long.byte 0x608 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x608 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x60C "GFXMMU_LUT193H,GFXMMU LUT entry 193 high" hexmask.long.tbyte 0x60C 4.--21. 1. "LO,Line offset" line.long 0x610 "GFXMMU_LUT194L,GFXMMU LUT entry 194 low" hexmask.long.byte 0x610 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x610 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x614 "GFXMMU_LUT194H,GFXMMU LUT entry 194 high" hexmask.long.tbyte 0x614 4.--21. 1. "LO,Line offset" line.long 0x618 "GFXMMU_LUT195L,GFXMMU LUT entry 195 low" hexmask.long.byte 0x618 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x618 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x61C "GFXMMU_LUT195H,GFXMMU LUT entry 195 high" hexmask.long.tbyte 0x61C 4.--21. 1. "LO,Line offset" line.long 0x620 "GFXMMU_LUT196L,GFXMMU LUT entry 196 low" hexmask.long.byte 0x620 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x620 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x624 "GFXMMU_LUT196H,GFXMMU LUT entry 196 high" hexmask.long.tbyte 0x624 4.--21. 1. "LO,Line offset" line.long 0x628 "GFXMMU_LUT197L,GFXMMU LUT entry 197 low" hexmask.long.byte 0x628 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x628 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x62C "GFXMMU_LUT197H,GFXMMU LUT entry 197 high" hexmask.long.tbyte 0x62C 4.--21. 1. "LO,Line offset" line.long 0x630 "GFXMMU_LUT198L,GFXMMU LUT entry 198 low" hexmask.long.byte 0x630 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x630 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x634 "GFXMMU_LUT198H,GFXMMU LUT entry 198 high" hexmask.long.tbyte 0x634 4.--21. 1. "LO,Line offset" line.long 0x638 "GFXMMU_LUT199L,GFXMMU LUT entry 199 low" hexmask.long.byte 0x638 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x638 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x63C "GFXMMU_LUT199H,GFXMMU LUT entry 199 high" hexmask.long.tbyte 0x63C 4.--21. 1. "LO,Line offset" line.long 0x640 "GFXMMU_LUT200L,GFXMMU LUT entry 200 low" hexmask.long.byte 0x640 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x640 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x644 "GFXMMU_LUT200H,GFXMMU LUT entry 200 high" hexmask.long.tbyte 0x644 4.--21. 1. "LO,Line offset" line.long 0x648 "GFXMMU_LUT201L,GFXMMU LUT entry 201 low" hexmask.long.byte 0x648 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x648 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64C "GFXMMU_LUT201H,GFXMMU LUT entry 201 high" hexmask.long.tbyte 0x64C 4.--21. 1. "LO,Line offset" line.long 0x650 "GFXMMU_LUT202L,GFXMMU LUT entry 202 low" hexmask.long.byte 0x650 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x650 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x654 "GFXMMU_LUT202H,GFXMMU LUT entry 202 high" hexmask.long.tbyte 0x654 4.--21. 1. "LO,Line offset" line.long 0x658 "GFXMMU_LUT203L,GFXMMU LUT entry 203 low" hexmask.long.byte 0x658 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x658 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x65C "GFXMMU_LUT203H,GFXMMU LUT entry 203 high" hexmask.long.tbyte 0x65C 4.--21. 1. "LO,Line offset" line.long 0x660 "GFXMMU_LUT204L,GFXMMU LUT entry 204 low" hexmask.long.byte 0x660 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x660 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x664 "GFXMMU_LUT204H,GFXMMU LUT entry 204 high" hexmask.long.tbyte 0x664 4.--21. 1. "LO,Line offset" line.long 0x668 "GFXMMU_LUT205L,GFXMMU LUT entry 205 low" hexmask.long.byte 0x668 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x668 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x66C "GFXMMU_LUT205H,GFXMMU LUT entry 205 high" hexmask.long.tbyte 0x66C 4.--21. 1. "LO,Line offset" line.long 0x670 "GFXMMU_LUT206L,GFXMMU LUT entry 206 low" hexmask.long.byte 0x670 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x670 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x674 "GFXMMU_LUT206H,GFXMMU LUT entry 206 high" hexmask.long.tbyte 0x674 4.--21. 1. "LO,Line offset" line.long 0x678 "GFXMMU_LUT207L,GFXMMU LUT entry 207 low" hexmask.long.byte 0x678 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x678 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x67C "GFXMMU_LUT207H,GFXMMU LUT entry 207 high" hexmask.long.tbyte 0x67C 4.--21. 1. "LO,Line offset" line.long 0x680 "GFXMMU_LUT208L,GFXMMU LUT entry 208 low" hexmask.long.byte 0x680 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x680 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x684 "GFXMMU_LUT208H,GFXMMU LUT entry 208 high" hexmask.long.tbyte 0x684 4.--21. 1. "LO,Line offset" line.long 0x688 "GFXMMU_LUT209L,GFXMMU LUT entry 209 low" hexmask.long.byte 0x688 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x688 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x68C "GFXMMU_LUT209H,GFXMMU LUT entry 209 high" hexmask.long.tbyte 0x68C 4.--21. 1. "LO,Line offset" line.long 0x690 "GFXMMU_LUT210L,GFXMMU LUT entry 210 low" hexmask.long.byte 0x690 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x690 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x694 "GFXMMU_LUT210H,GFXMMU LUT entry 210 high" hexmask.long.tbyte 0x694 4.--21. 1. "LO,Line offset" line.long 0x698 "GFXMMU_LUT211L,GFXMMU LUT entry 211 low" hexmask.long.byte 0x698 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x698 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x69C "GFXMMU_LUT211H,GFXMMU LUT entry 211 high" hexmask.long.tbyte 0x69C 4.--21. 1. "LO,Line offset" line.long 0x6A0 "GFXMMU_LUT212L,GFXMMU LUT entry 212 low" hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6A4 "GFXMMU_LUT212H,GFXMMU LUT entry 212 high" hexmask.long.tbyte 0x6A4 4.--21. 1. "LO,Line offset" line.long 0x6A8 "GFXMMU_LUT213L,GFXMMU LUT entry 213 low" hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6AC "GFXMMU_LUT213H,GFXMMU LUT entry 213 high" hexmask.long.tbyte 0x6AC 4.--21. 1. "LO,Line offset" line.long 0x6B0 "GFXMMU_LUT214L,GFXMMU LUT entry 214 low" hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6B4 "GFXMMU_LUT214H,GFXMMU LUT entry 214 high" hexmask.long.tbyte 0x6B4 4.--21. 1. "LO,Line offset" line.long 0x6B8 "GFXMMU_LUT215L,GFXMMU LUT entry 215 low" hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6BC "GFXMMU_LUT215H,GFXMMU LUT entry 215 high" hexmask.long.tbyte 0x6BC 4.--21. 1. "LO,Line offset" line.long 0x6C0 "GFXMMU_LUT216L,GFXMMU LUT entry 216 low" hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C4 "GFXMMU_LUT216H,GFXMMU LUT entry 216 high" hexmask.long.tbyte 0x6C4 4.--21. 1. "LO,Line offset" line.long 0x6C8 "GFXMMU_LUT217L,GFXMMU LUT entry 217 low" hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6CC "GFXMMU_LUT217H,GFXMMU LUT entry 217 high" hexmask.long.tbyte 0x6CC 4.--21. 1. "LO,Line offset" line.long 0x6D0 "GFXMMU_LUT218L,GFXMMU LUT entry 218 low" hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6D4 "GFXMMU_LUT218H,GFXMMU LUT entry 218 high" hexmask.long.tbyte 0x6D4 4.--21. 1. "LO,Line offset" line.long 0x6D8 "GFXMMU_LUT219L,GFXMMU LUT entry 219 low" hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6DC "GFXMMU_LUT219H,GFXMMU LUT entry 219 high" hexmask.long.tbyte 0x6DC 4.--21. 1. "LO,Line offset" line.long 0x6E0 "GFXMMU_LUT220L,GFXMMU LUT entry 220 low" hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6E4 "GFXMMU_LUT220H,GFXMMU LUT entry 220 high" hexmask.long.tbyte 0x6E4 4.--21. 1. "LO,Line offset" line.long 0x6E8 "GFXMMU_LUT221L,GFXMMU LUT entry 221 low" hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6EC "GFXMMU_LUT221H,GFXMMU LUT entry 221 high" hexmask.long.tbyte 0x6EC 4.--21. 1. "LO,Line offset" line.long 0x6F0 "GFXMMU_LUT222L,GFXMMU LUT entry 222 low" hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6F4 "GFXMMU_LUT222H,GFXMMU LUT entry 222 high" hexmask.long.tbyte 0x6F4 4.--21. 1. "LO,Line offset" line.long 0x6F8 "GFXMMU_LUT223L,GFXMMU LUT entry 223 low" hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6FC "GFXMMU_LUT223H,GFXMMU LUT entry 223 high" hexmask.long.tbyte 0x6FC 4.--21. 1. "LO,Line offset" line.long 0x700 "GFXMMU_LUT224L,GFXMMU LUT entry 224 low" hexmask.long.byte 0x700 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x700 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x704 "GFXMMU_LUT224H,GFXMMU LUT entry 224 high" hexmask.long.tbyte 0x704 4.--21. 1. "LO,Line offset" line.long 0x708 "GFXMMU_LUT225L,GFXMMU LUT entry 225 low" hexmask.long.byte 0x708 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x708 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x70C "GFXMMU_LUT225H,GFXMMU LUT entry 225 high" hexmask.long.tbyte 0x70C 4.--21. 1. "LO,Line offset" line.long 0x710 "GFXMMU_LUT226L,GFXMMU LUT entry 226 low" hexmask.long.byte 0x710 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x710 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x714 "GFXMMU_LUT226H,GFXMMU LUT entry 226 high" hexmask.long.tbyte 0x714 4.--21. 1. "LO,Line offset" line.long 0x718 "GFXMMU_LUT227L,GFXMMU LUT entry 227 low" hexmask.long.byte 0x718 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x718 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x71C "GFXMMU_LUT227H,GFXMMU LUT entry 227 high" hexmask.long.tbyte 0x71C 4.--21. 1. "LO,Line offset" line.long 0x720 "GFXMMU_LUT228L,GFXMMU LUT entry 228 low" hexmask.long.byte 0x720 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x720 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x724 "GFXMMU_LUT228H,GFXMMU LUT entry 228 high" hexmask.long.tbyte 0x724 4.--21. 1. "LO,Line offset" line.long 0x728 "GFXMMU_LUT229L,GFXMMU LUT entry 229 low" hexmask.long.byte 0x728 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x728 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x72C "GFXMMU_LUT229H,GFXMMU LUT entry 229 high" hexmask.long.tbyte 0x72C 4.--21. 1. "LO,Line offset" line.long 0x730 "GFXMMU_LUT230L,GFXMMU LUT entry 230 low" hexmask.long.byte 0x730 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x730 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x734 "GFXMMU_LUT230H,GFXMMU LUT entry 230 high" hexmask.long.tbyte 0x734 4.--21. 1. "LO,Line offset" line.long 0x738 "GFXMMU_LUT231L,GFXMMU LUT entry 231 low" hexmask.long.byte 0x738 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x738 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x73C "GFXMMU_LUT231H,GFXMMU LUT entry 231 high" hexmask.long.tbyte 0x73C 4.--21. 1. "LO,Line offset" line.long 0x740 "GFXMMU_LUT232L,GFXMMU LUT entry 232 low" hexmask.long.byte 0x740 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x740 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x744 "GFXMMU_LUT232H,GFXMMU LUT entry 232 high" hexmask.long.tbyte 0x744 4.--21. 1. "LO,Line offset" line.long 0x748 "GFXMMU_LUT233L,GFXMMU LUT entry 233 low" hexmask.long.byte 0x748 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x748 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74C "GFXMMU_LUT233H,GFXMMU LUT entry 233 high" hexmask.long.tbyte 0x74C 4.--21. 1. "LO,Line offset" line.long 0x750 "GFXMMU_LUT234L,GFXMMU LUT entry 234 low" hexmask.long.byte 0x750 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x750 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x754 "GFXMMU_LUT234H,GFXMMU LUT entry 234 high" hexmask.long.tbyte 0x754 4.--21. 1. "LO,Line offset" line.long 0x758 "GFXMMU_LUT235L,GFXMMU LUT entry 235 low" hexmask.long.byte 0x758 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x758 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x75C "GFXMMU_LUT235H,GFXMMU LUT entry 235 high" hexmask.long.tbyte 0x75C 4.--21. 1. "LO,Line offset" line.long 0x760 "GFXMMU_LUT236L,GFXMMU LUT entry 236 low" hexmask.long.byte 0x760 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x760 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x764 "GFXMMU_LUT236H,GFXMMU LUT entry 236 high" hexmask.long.tbyte 0x764 4.--21. 1. "LO,Line offset" line.long 0x768 "GFXMMU_LUT237L,GFXMMU LUT entry 237 low" hexmask.long.byte 0x768 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x768 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x76C "GFXMMU_LUT237H,GFXMMU LUT entry 237 high" hexmask.long.tbyte 0x76C 4.--21. 1. "LO,Line offset" line.long 0x770 "GFXMMU_LUT238L,GFXMMU LUT entry 238 low" hexmask.long.byte 0x770 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x770 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x774 "GFXMMU_LUT238H,GFXMMU LUT entry 238 high" hexmask.long.tbyte 0x774 4.--21. 1. "LO,Line offset" line.long 0x778 "GFXMMU_LUT239L,GFXMMU LUT entry 239 low" hexmask.long.byte 0x778 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x778 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x77C "GFXMMU_LUT239H,GFXMMU LUT entry 239 high" hexmask.long.tbyte 0x77C 4.--21. 1. "LO,Line offset" line.long 0x780 "GFXMMU_LUT240L,GFXMMU LUT entry 240 low" hexmask.long.byte 0x780 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x780 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x784 "GFXMMU_LUT240H,GFXMMU LUT entry 240 high" hexmask.long.tbyte 0x784 4.--21. 1. "LO,Line offset" line.long 0x788 "GFXMMU_LUT241L,GFXMMU LUT entry 241 low" hexmask.long.byte 0x788 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x788 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x78C "GFXMMU_LUT241H,GFXMMU LUT entry 241 high" hexmask.long.tbyte 0x78C 4.--21. 1. "LO,Line offset" line.long 0x790 "GFXMMU_LUT242L,GFXMMU LUT entry 242 low" hexmask.long.byte 0x790 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x790 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x794 "GFXMMU_LUT242H,GFXMMU LUT entry 242 high" hexmask.long.tbyte 0x794 4.--21. 1. "LO,Line offset" line.long 0x798 "GFXMMU_LUT243L,GFXMMU LUT entry 243 low" hexmask.long.byte 0x798 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x798 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x79C "GFXMMU_LUT243H,GFXMMU LUT entry 243 high" hexmask.long.tbyte 0x79C 4.--21. 1. "LO,Line offset" line.long 0x7A0 "GFXMMU_LUT244L,GFXMMU LUT entry 244 low" hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7A4 "GFXMMU_LUT244H,GFXMMU LUT entry 244 high" hexmask.long.tbyte 0x7A4 4.--21. 1. "LO,Line offset" line.long 0x7A8 "GFXMMU_LUT245L,GFXMMU LUT entry 245 low" hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7AC "GFXMMU_LUT245H,GFXMMU LUT entry 245 high" hexmask.long.tbyte 0x7AC 4.--21. 1. "LO,Line offset" line.long 0x7B0 "GFXMMU_LUT246L,GFXMMU LUT entry 246 low" hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7B4 "GFXMMU_LUT246H,GFXMMU LUT entry 246 high" hexmask.long.tbyte 0x7B4 4.--21. 1. "LO,Line offset" line.long 0x7B8 "GFXMMU_LUT247L,GFXMMU LUT entry 247 low" hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7BC "GFXMMU_LUT247H,GFXMMU LUT entry 247 high" hexmask.long.tbyte 0x7BC 4.--21. 1. "LO,Line offset" line.long 0x7C0 "GFXMMU_LUT248L,GFXMMU LUT entry 248 low" hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C4 "GFXMMU_LUT248H,GFXMMU LUT entry 248 high" hexmask.long.tbyte 0x7C4 4.--21. 1. "LO,Line offset" line.long 0x7C8 "GFXMMU_LUT249L,GFXMMU LUT entry 249 low" hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7CC "GFXMMU_LUT249H,GFXMMU LUT entry 249 high" hexmask.long.tbyte 0x7CC 4.--21. 1. "LO,Line offset" line.long 0x7D0 "GFXMMU_LUT250L,GFXMMU LUT entry 250 low" hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7D4 "GFXMMU_LUT250H,GFXMMU LUT entry 250 high" hexmask.long.tbyte 0x7D4 4.--21. 1. "LO,Line offset" line.long 0x7D8 "GFXMMU_LUT251L,GFXMMU LUT entry 251 low" hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7DC "GFXMMU_LUT251H,GFXMMU LUT entry 251 high" hexmask.long.tbyte 0x7DC 4.--21. 1. "LO,Line offset" line.long 0x7E0 "GFXMMU_LUT252L,GFXMMU LUT entry 252 low" hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7E4 "GFXMMU_LUT252H,GFXMMU LUT entry 252 high" hexmask.long.tbyte 0x7E4 4.--21. 1. "LO,Line offset" line.long 0x7E8 "GFXMMU_LUT253L,GFXMMU LUT entry 253 low" hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7EC "GFXMMU_LUT253H,GFXMMU LUT entry 253 high" hexmask.long.tbyte 0x7EC 4.--21. 1. "LO,Line offset" line.long 0x7F0 "GFXMMU_LUT254L,GFXMMU LUT entry 254 low" hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7F4 "GFXMMU_LUT254H,GFXMMU LUT entry 254 high" hexmask.long.tbyte 0x7F4 4.--21. 1. "LO,Line offset" line.long 0x7F8 "GFXMMU_LUT255L,GFXMMU LUT entry 255 low" hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7FC "GFXMMU_LUT255H,GFXMMU LUT entry 255 high" hexmask.long.tbyte 0x7FC 4.--21. 1. "LO,Line offset" line.long 0x800 "GFXMMU_LUT256L,GFXMMU LUT entry 256 low" hexmask.long.byte 0x800 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x800 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x804 "GFXMMU_LUT256H,GFXMMU LUT entry 256 high" hexmask.long.tbyte 0x804 4.--21. 1. "LO,Line offset" line.long 0x808 "GFXMMU_LUT257L,GFXMMU LUT entry 257 low" hexmask.long.byte 0x808 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x808 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x80C "GFXMMU_LUT257H,GFXMMU LUT entry 257 high" hexmask.long.tbyte 0x80C 4.--21. 1. "LO,Line offset" line.long 0x810 "GFXMMU_LUT258L,GFXMMU LUT entry 258 low" hexmask.long.byte 0x810 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x810 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x814 "GFXMMU_LUT258H,GFXMMU LUT entry 258 high" hexmask.long.tbyte 0x814 4.--21. 1. "LO,Line offset" line.long 0x818 "GFXMMU_LUT259L,GFXMMU LUT entry 259 low" hexmask.long.byte 0x818 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x818 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x81C "GFXMMU_LUT259H,GFXMMU LUT entry 259 high" hexmask.long.tbyte 0x81C 4.--21. 1. "LO,Line offset" line.long 0x820 "GFXMMU_LUT260L,GFXMMU LUT entry 260 low" hexmask.long.byte 0x820 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x820 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x824 "GFXMMU_LUT260H,GFXMMU LUT entry 260 high" hexmask.long.tbyte 0x824 4.--21. 1. "LO,Line offset" line.long 0x828 "GFXMMU_LUT261L,GFXMMU LUT entry 261 low" hexmask.long.byte 0x828 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x828 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x82C "GFXMMU_LUT261H,GFXMMU LUT entry 261 high" hexmask.long.tbyte 0x82C 4.--21. 1. "LO,Line offset" line.long 0x830 "GFXMMU_LUT262L,GFXMMU LUT entry 262 low" hexmask.long.byte 0x830 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x830 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x834 "GFXMMU_LUT262H,GFXMMU LUT entry 262 high" hexmask.long.tbyte 0x834 4.--21. 1. "LO,Line offset" line.long 0x838 "GFXMMU_LUT263L,GFXMMU LUT entry 263 low" hexmask.long.byte 0x838 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x838 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x83C "GFXMMU_LUT263H,GFXMMU LUT entry 263 high" hexmask.long.tbyte 0x83C 4.--21. 1. "LO,Line offset" line.long 0x840 "GFXMMU_LUT264L,GFXMMU LUT entry 264 low" hexmask.long.byte 0x840 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x840 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x844 "GFXMMU_LUT264H,GFXMMU LUT entry 264 high" hexmask.long.tbyte 0x844 4.--21. 1. "LO,Line offset" line.long 0x848 "GFXMMU_LUT265L,GFXMMU LUT entry 265 low" hexmask.long.byte 0x848 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x848 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84C "GFXMMU_LUT265H,GFXMMU LUT entry 265 high" hexmask.long.tbyte 0x84C 4.--21. 1. "LO,Line offset" line.long 0x850 "GFXMMU_LUT266L,GFXMMU LUT entry 266 low" hexmask.long.byte 0x850 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x850 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x854 "GFXMMU_LUT266H,GFXMMU LUT entry 266 high" hexmask.long.tbyte 0x854 4.--21. 1. "LO,Line offset" line.long 0x858 "GFXMMU_LUT267L,GFXMMU LUT entry 267 low" hexmask.long.byte 0x858 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x858 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x85C "GFXMMU_LUT267H,GFXMMU LUT entry 267 high" hexmask.long.tbyte 0x85C 4.--21. 1. "LO,Line offset" line.long 0x860 "GFXMMU_LUT268L,GFXMMU LUT entry 268 low" hexmask.long.byte 0x860 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x860 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x864 "GFXMMU_LUT268H,GFXMMU LUT entry 268 high" hexmask.long.tbyte 0x864 4.--21. 1. "LO,Line offset" line.long 0x868 "GFXMMU_LUT269L,GFXMMU LUT entry 269 low" hexmask.long.byte 0x868 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x868 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x86C "GFXMMU_LUT269H,GFXMMU LUT entry 269 high" hexmask.long.tbyte 0x86C 4.--21. 1. "LO,Line offset" line.long 0x870 "GFXMMU_LUT270L,GFXMMU LUT entry 270 low" hexmask.long.byte 0x870 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x870 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x874 "GFXMMU_LUT270H,GFXMMU LUT entry 270 high" hexmask.long.tbyte 0x874 4.--21. 1. "LO,Line offset" line.long 0x878 "GFXMMU_LUT271L,GFXMMU LUT entry 271 low" hexmask.long.byte 0x878 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x878 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x87C "GFXMMU_LUT271H,GFXMMU LUT entry 271 high" hexmask.long.tbyte 0x87C 4.--21. 1. "LO,Line offset" line.long 0x880 "GFXMMU_LUT272L,GFXMMU LUT entry 272 low" hexmask.long.byte 0x880 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x880 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x884 "GFXMMU_LUT272H,GFXMMU LUT entry 272 high" hexmask.long.tbyte 0x884 4.--21. 1. "LO,Line offset" line.long 0x888 "GFXMMU_LUT273L,GFXMMU LUT entry 273 low" hexmask.long.byte 0x888 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x888 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x88C "GFXMMU_LUT273H,GFXMMU LUT entry 273 high" hexmask.long.tbyte 0x88C 4.--21. 1. "LO,Line offset" line.long 0x890 "GFXMMU_LUT274L,GFXMMU LUT entry 274 low" hexmask.long.byte 0x890 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x890 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x894 "GFXMMU_LUT274H,GFXMMU LUT entry 274 high" hexmask.long.tbyte 0x894 4.--21. 1. "LO,Line offset" line.long 0x898 "GFXMMU_LUT275L,GFXMMU LUT entry 275 low" hexmask.long.byte 0x898 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x898 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x89C "GFXMMU_LUT275H,GFXMMU LUT entry 275 high" hexmask.long.tbyte 0x89C 4.--21. 1. "LO,Line offset" line.long 0x8A0 "GFXMMU_LUT276L,GFXMMU LUT entry 276 low" hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8A4 "GFXMMU_LUT276H,GFXMMU LUT entry 276 high" hexmask.long.tbyte 0x8A4 4.--21. 1. "LO,Line offset" line.long 0x8A8 "GFXMMU_LUT277L,GFXMMU LUT entry 277 low" hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8AC "GFXMMU_LUT277H,GFXMMU LUT entry 277 high" hexmask.long.tbyte 0x8AC 4.--21. 1. "LO,Line offset" line.long 0x8B0 "GFXMMU_LUT278L,GFXMMU LUT entry 278 low" hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8B4 "GFXMMU_LUT278H,GFXMMU LUT entry 278 high" hexmask.long.tbyte 0x8B4 4.--21. 1. "LO,Line offset" line.long 0x8B8 "GFXMMU_LUT279L,GFXMMU LUT entry 279 low" hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8BC "GFXMMU_LUT279H,GFXMMU LUT entry 279 high" hexmask.long.tbyte 0x8BC 4.--21. 1. "LO,Line offset" line.long 0x8C0 "GFXMMU_LUT280L,GFXMMU LUT entry 280 low" hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C4 "GFXMMU_LUT280H,GFXMMU LUT entry 280 high" hexmask.long.tbyte 0x8C4 4.--21. 1. "LO,Line offset" line.long 0x8C8 "GFXMMU_LUT281L,GFXMMU LUT entry 281 low" hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8CC "GFXMMU_LUT281H,GFXMMU LUT entry 281 high" hexmask.long.tbyte 0x8CC 4.--21. 1. "LO,Line offset" line.long 0x8D0 "GFXMMU_LUT282L,GFXMMU LUT entry 282 low" hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8D4 "GFXMMU_LUT282H,GFXMMU LUT entry 282 high" hexmask.long.tbyte 0x8D4 4.--21. 1. "LO,Line offset" line.long 0x8D8 "GFXMMU_LUT283L,GFXMMU LUT entry 283 low" hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8DC "GFXMMU_LUT283H,GFXMMU LUT entry 283 high" hexmask.long.tbyte 0x8DC 4.--21. 1. "LO,Line offset" line.long 0x8E0 "GFXMMU_LUT284L,GFXMMU LUT entry 284 low" hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8E4 "GFXMMU_LUT284H,GFXMMU LUT entry 284 high" hexmask.long.tbyte 0x8E4 4.--21. 1. "LO,Line offset" line.long 0x8E8 "GFXMMU_LUT285L,GFXMMU LUT entry 285 low" hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8EC "GFXMMU_LUT285H,GFXMMU LUT entry 285 high" hexmask.long.tbyte 0x8EC 4.--21. 1. "LO,Line offset" line.long 0x8F0 "GFXMMU_LUT286L,GFXMMU LUT entry 286 low" hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8F4 "GFXMMU_LUT286H,GFXMMU LUT entry 286 high" hexmask.long.tbyte 0x8F4 4.--21. 1. "LO,Line offset" line.long 0x8F8 "GFXMMU_LUT287L,GFXMMU LUT entry 287 low" hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8FC "GFXMMU_LUT287H,GFXMMU LUT entry 287 high" hexmask.long.tbyte 0x8FC 4.--21. 1. "LO,Line offset" line.long 0x900 "GFXMMU_LUT288L,GFXMMU LUT entry 288 low" hexmask.long.byte 0x900 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x900 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x904 "GFXMMU_LUT288H,GFXMMU LUT entry 288 high" hexmask.long.tbyte 0x904 4.--21. 1. "LO,Line offset" line.long 0x908 "GFXMMU_LUT289L,GFXMMU LUT entry 289 low" hexmask.long.byte 0x908 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x908 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x90C "GFXMMU_LUT289H,GFXMMU LUT entry 289 high" hexmask.long.tbyte 0x90C 4.--21. 1. "LO,Line offset" line.long 0x910 "GFXMMU_LUT290L,GFXMMU LUT entry 290 low" hexmask.long.byte 0x910 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x910 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x914 "GFXMMU_LUT290H,GFXMMU LUT entry 290 high" hexmask.long.tbyte 0x914 4.--21. 1. "LO,Line offset" line.long 0x918 "GFXMMU_LUT291L,GFXMMU LUT entry 291 low" hexmask.long.byte 0x918 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x918 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x91C "GFXMMU_LUT291H,GFXMMU LUT entry 291 high" hexmask.long.tbyte 0x91C 4.--21. 1. "LO,Line offset" line.long 0x920 "GFXMMU_LUT292L,GFXMMU LUT entry 292 low" hexmask.long.byte 0x920 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x920 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x924 "GFXMMU_LUT292H,GFXMMU LUT entry 292 high" hexmask.long.tbyte 0x924 4.--21. 1. "LO,Line offset" line.long 0x928 "GFXMMU_LUT293L,GFXMMU LUT entry 293 low" hexmask.long.byte 0x928 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x928 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x92C "GFXMMU_LUT293H,GFXMMU LUT entry 293 high" hexmask.long.tbyte 0x92C 4.--21. 1. "LO,Line offset" line.long 0x930 "GFXMMU_LUT294L,GFXMMU LUT entry 294 low" hexmask.long.byte 0x930 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x930 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x934 "GFXMMU_LUT294H,GFXMMU LUT entry 294 high" hexmask.long.tbyte 0x934 4.--21. 1. "LO,Line offset" line.long 0x938 "GFXMMU_LUT295L,GFXMMU LUT entry 295 low" hexmask.long.byte 0x938 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x938 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x93C "GFXMMU_LUT295H,GFXMMU LUT entry 295 high" hexmask.long.tbyte 0x93C 4.--21. 1. "LO,Line offset" line.long 0x940 "GFXMMU_LUT296L,GFXMMU LUT entry 296 low" hexmask.long.byte 0x940 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x940 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x944 "GFXMMU_LUT296H,GFXMMU LUT entry 296 high" hexmask.long.tbyte 0x944 4.--21. 1. "LO,Line offset" line.long 0x948 "GFXMMU_LUT297L,GFXMMU LUT entry 297 low" hexmask.long.byte 0x948 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x948 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94C "GFXMMU_LUT297H,GFXMMU LUT entry 297 high" hexmask.long.tbyte 0x94C 4.--21. 1. "LO,Line offset" line.long 0x950 "GFXMMU_LUT298L,GFXMMU LUT entry 298 low" hexmask.long.byte 0x950 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x950 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x954 "GFXMMU_LUT298H,GFXMMU LUT entry 298 high" hexmask.long.tbyte 0x954 4.--21. 1. "LO,Line offset" line.long 0x958 "GFXMMU_LUT299L,GFXMMU LUT entry 299 low" hexmask.long.byte 0x958 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x958 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x95C "GFXMMU_LUT299H,GFXMMU LUT entry 299 high" hexmask.long.tbyte 0x95C 4.--21. 1. "LO,Line offset" line.long 0x960 "GFXMMU_LUT300L,GFXMMU LUT entry 300 low" hexmask.long.byte 0x960 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x960 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x964 "GFXMMU_LUT300H,GFXMMU LUT entry 300 high" hexmask.long.tbyte 0x964 4.--21. 1. "LO,Line offset" line.long 0x968 "GFXMMU_LUT301L,GFXMMU LUT entry 301 low" hexmask.long.byte 0x968 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x968 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x96C "GFXMMU_LUT301H,GFXMMU LUT entry 301 high" hexmask.long.tbyte 0x96C 4.--21. 1. "LO,Line offset" line.long 0x970 "GFXMMU_LUT302L,GFXMMU LUT entry 302 low" hexmask.long.byte 0x970 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x970 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x974 "GFXMMU_LUT302H,GFXMMU LUT entry 302 high" hexmask.long.tbyte 0x974 4.--21. 1. "LO,Line offset" line.long 0x978 "GFXMMU_LUT303L,GFXMMU LUT entry 303 low" hexmask.long.byte 0x978 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x978 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x97C "GFXMMU_LUT303H,GFXMMU LUT entry 303 high" hexmask.long.tbyte 0x97C 4.--21. 1. "LO,Line offset" line.long 0x980 "GFXMMU_LUT304L,GFXMMU LUT entry 304 low" hexmask.long.byte 0x980 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x980 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x984 "GFXMMU_LUT304H,GFXMMU LUT entry 304 high" hexmask.long.tbyte 0x984 4.--21. 1. "LO,Line offset" line.long 0x988 "GFXMMU_LUT305L,GFXMMU LUT entry 305 low" hexmask.long.byte 0x988 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x988 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x98C "GFXMMU_LUT305H,GFXMMU LUT entry 305 high" hexmask.long.tbyte 0x98C 4.--21. 1. "LO,Line offset" line.long 0x990 "GFXMMU_LUT306L,GFXMMU LUT entry 306 low" hexmask.long.byte 0x990 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x990 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x994 "GFXMMU_LUT306H,GFXMMU LUT entry 306 high" hexmask.long.tbyte 0x994 4.--21. 1. "LO,Line offset" line.long 0x998 "GFXMMU_LUT307L,GFXMMU LUT entry 307 low" hexmask.long.byte 0x998 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x998 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x99C "GFXMMU_LUT307H,GFXMMU LUT entry 307 high" hexmask.long.tbyte 0x99C 4.--21. 1. "LO,Line offset" line.long 0x9A0 "GFXMMU_LUT308L,GFXMMU LUT entry 308 low" hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9A4 "GFXMMU_LUT308H,GFXMMU LUT entry 308 high" hexmask.long.tbyte 0x9A4 4.--21. 1. "LO,Line offset" line.long 0x9A8 "GFXMMU_LUT309L,GFXMMU LUT entry 309 low" hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9AC "GFXMMU_LUT309H,GFXMMU LUT entry 309 high" hexmask.long.tbyte 0x9AC 4.--21. 1. "LO,Line offset" line.long 0x9B0 "GFXMMU_LUT310L,GFXMMU LUT entry 310 low" hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9B4 "GFXMMU_LUT310H,GFXMMU LUT entry 310 high" hexmask.long.tbyte 0x9B4 4.--21. 1. "LO,Line offset" line.long 0x9B8 "GFXMMU_LUT311L,GFXMMU LUT entry 311 low" hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9BC "GFXMMU_LUT311H,GFXMMU LUT entry 311 high" hexmask.long.tbyte 0x9BC 4.--21. 1. "LO,Line offset" line.long 0x9C0 "GFXMMU_LUT312L,GFXMMU LUT entry 312 low" hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C4 "GFXMMU_LUT312H,GFXMMU LUT entry 312 high" hexmask.long.tbyte 0x9C4 4.--21. 1. "LO,Line offset" line.long 0x9C8 "GFXMMU_LUT313L,GFXMMU LUT entry 313 low" hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9CC "GFXMMU_LUT313H,GFXMMU LUT entry 313 high" hexmask.long.tbyte 0x9CC 4.--21. 1. "LO,Line offset" line.long 0x9D0 "GFXMMU_LUT314L,GFXMMU LUT entry 314 low" hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9D4 "GFXMMU_LUT314H,GFXMMU LUT entry 314 high" hexmask.long.tbyte 0x9D4 4.--21. 1. "LO,Line offset" line.long 0x9D8 "GFXMMU_LUT315L,GFXMMU LUT entry 315 low" hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9DC "GFXMMU_LUT315H,GFXMMU LUT entry 315 high" hexmask.long.tbyte 0x9DC 4.--21. 1. "LO,Line offset" line.long 0x9E0 "GFXMMU_LUT316L,GFXMMU LUT entry 316 low" hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9E4 "GFXMMU_LUT316H,GFXMMU LUT entry 316 high" hexmask.long.tbyte 0x9E4 4.--21. 1. "LO,Line offset" line.long 0x9E8 "GFXMMU_LUT317L,GFXMMU LUT entry 317 low" hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9EC "GFXMMU_LUT317H,GFXMMU LUT entry 317 high" hexmask.long.tbyte 0x9EC 4.--21. 1. "LO,Line offset" line.long 0x9F0 "GFXMMU_LUT318L,GFXMMU LUT entry 318 low" hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9F4 "GFXMMU_LUT318H,GFXMMU LUT entry 318 high" hexmask.long.tbyte 0x9F4 4.--21. 1. "LO,Line offset" line.long 0x9F8 "GFXMMU_LUT319L,GFXMMU LUT entry 319 low" hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9FC "GFXMMU_LUT319H,GFXMMU LUT entry 319 high" hexmask.long.tbyte 0x9FC 4.--21. 1. "LO,Line offset" line.long 0xA00 "GFXMMU_LUT320L,GFXMMU LUT entry 320 low" hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA04 "GFXMMU_LUT320H,GFXMMU LUT entry 320 high" hexmask.long.tbyte 0xA04 4.--21. 1. "LO,Line offset" line.long 0xA08 "GFXMMU_LUT321L,GFXMMU LUT entry 321 low" hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA0C "GFXMMU_LUT321H,GFXMMU LUT entry 321 high" hexmask.long.tbyte 0xA0C 4.--21. 1. "LO,Line offset" line.long 0xA10 "GFXMMU_LUT322L,GFXMMU LUT entry 322 low" hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA14 "GFXMMU_LUT322H,GFXMMU LUT entry 322 high" hexmask.long.tbyte 0xA14 4.--21. 1. "LO,Line offset" line.long 0xA18 "GFXMMU_LUT323L,GFXMMU LUT entry 323 low" hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA1C "GFXMMU_LUT323H,GFXMMU LUT entry 323 high" hexmask.long.tbyte 0xA1C 4.--21. 1. "LO,Line offset" line.long 0xA20 "GFXMMU_LUT324L,GFXMMU LUT entry 324 low" hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA24 "GFXMMU_LUT324H,GFXMMU LUT entry 324 high" hexmask.long.tbyte 0xA24 4.--21. 1. "LO,Line offset" line.long 0xA28 "GFXMMU_LUT325L,GFXMMU LUT entry 325 low" hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA2C "GFXMMU_LUT325H,GFXMMU LUT entry 325 high" hexmask.long.tbyte 0xA2C 4.--21. 1. "LO,Line offset" line.long 0xA30 "GFXMMU_LUT326L,GFXMMU LUT entry 326 low" hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA34 "GFXMMU_LUT326H,GFXMMU LUT entry 326 high" hexmask.long.tbyte 0xA34 4.--21. 1. "LO,Line offset" line.long 0xA38 "GFXMMU_LUT327L,GFXMMU LUT entry 327 low" hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA3C "GFXMMU_LUT327H,GFXMMU LUT entry 327 high" hexmask.long.tbyte 0xA3C 4.--21. 1. "LO,Line offset" line.long 0xA40 "GFXMMU_LUT328L,GFXMMU LUT entry 328 low" hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA44 "GFXMMU_LUT328H,GFXMMU LUT entry 328 high" hexmask.long.tbyte 0xA44 4.--21. 1. "LO,Line offset" line.long 0xA48 "GFXMMU_LUT329L,GFXMMU LUT entry 329 low" hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4C "GFXMMU_LUT329H,GFXMMU LUT entry 329 high" hexmask.long.tbyte 0xA4C 4.--21. 1. "LO,Line offset" line.long 0xA50 "GFXMMU_LUT330L,GFXMMU LUT entry 330 low" hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA54 "GFXMMU_LUT330H,GFXMMU LUT entry 330 high" hexmask.long.tbyte 0xA54 4.--21. 1. "LO,Line offset" line.long 0xA58 "GFXMMU_LUT331L,GFXMMU LUT entry 331 low" hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA5C "GFXMMU_LUT331H,GFXMMU LUT entry 331 high" hexmask.long.tbyte 0xA5C 4.--21. 1. "LO,Line offset" line.long 0xA60 "GFXMMU_LUT332L,GFXMMU LUT entry 332 low" hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA64 "GFXMMU_LUT332H,GFXMMU LUT entry 332 high" hexmask.long.tbyte 0xA64 4.--21. 1. "LO,Line offset" line.long 0xA68 "GFXMMU_LUT333L,GFXMMU LUT entry 333 low" hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA6C "GFXMMU_LUT333H,GFXMMU LUT entry 333 high" hexmask.long.tbyte 0xA6C 4.--21. 1. "LO,Line offset" line.long 0xA70 "GFXMMU_LUT334L,GFXMMU LUT entry 334 low" hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA74 "GFXMMU_LUT334H,GFXMMU LUT entry 334 high" hexmask.long.tbyte 0xA74 4.--21. 1. "LO,Line offset" line.long 0xA78 "GFXMMU_LUT335L,GFXMMU LUT entry 335 low" hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA7C "GFXMMU_LUT335H,GFXMMU LUT entry 335 high" hexmask.long.tbyte 0xA7C 4.--21. 1. "LO,Line offset" line.long 0xA80 "GFXMMU_LUT336L,GFXMMU LUT entry 336 low" hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA84 "GFXMMU_LUT336H,GFXMMU LUT entry 336 high" hexmask.long.tbyte 0xA84 4.--21. 1. "LO,Line offset" line.long 0xA88 "GFXMMU_LUT337L,GFXMMU LUT entry 337 low" hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA8C "GFXMMU_LUT337H,GFXMMU LUT entry 337 high" hexmask.long.tbyte 0xA8C 4.--21. 1. "LO,Line offset" line.long 0xA90 "GFXMMU_LUT338L,GFXMMU LUT entry 338 low" hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA94 "GFXMMU_LUT338H,GFXMMU LUT entry 338 high" hexmask.long.tbyte 0xA94 4.--21. 1. "LO,Line offset" line.long 0xA98 "GFXMMU_LUT339L,GFXMMU LUT entry 339 low" hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA9C "GFXMMU_LUT339H,GFXMMU LUT entry 339 high" hexmask.long.tbyte 0xA9C 4.--21. 1. "LO,Line offset" line.long 0xAA0 "GFXMMU_LUT340L,GFXMMU LUT entry 340 low" hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAA4 "GFXMMU_LUT340H,GFXMMU LUT entry 340 high" hexmask.long.tbyte 0xAA4 4.--21. 1. "LO,Line offset" line.long 0xAA8 "GFXMMU_LUT341L,GFXMMU LUT entry 341 low" hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAAC "GFXMMU_LUT341H,GFXMMU LUT entry 341 high" hexmask.long.tbyte 0xAAC 4.--21. 1. "LO,Line offset" line.long 0xAB0 "GFXMMU_LUT342L,GFXMMU LUT entry 342 low" hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAB4 "GFXMMU_LUT342H,GFXMMU LUT entry 342 high" hexmask.long.tbyte 0xAB4 4.--21. 1. "LO,Line offset" line.long 0xAB8 "GFXMMU_LUT343L,GFXMMU LUT entry 343 low" hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xABC "GFXMMU_LUT343H,GFXMMU LUT entry 343 high" hexmask.long.tbyte 0xABC 4.--21. 1. "LO,Line offset" line.long 0xAC0 "GFXMMU_LUT344L,GFXMMU LUT entry 344 low" hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC4 "GFXMMU_LUT344H,GFXMMU LUT entry 344 high" hexmask.long.tbyte 0xAC4 4.--21. 1. "LO,Line offset" line.long 0xAC8 "GFXMMU_LUT345L,GFXMMU LUT entry 345 low" hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xACC "GFXMMU_LUT345H,GFXMMU LUT entry 345 high" hexmask.long.tbyte 0xACC 4.--21. 1. "LO,Line offset" line.long 0xAD0 "GFXMMU_LUT346L,GFXMMU LUT entry 346 low" hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAD4 "GFXMMU_LUT346H,GFXMMU LUT entry 346 high" hexmask.long.tbyte 0xAD4 4.--21. 1. "LO,Line offset" line.long 0xAD8 "GFXMMU_LUT347L,GFXMMU LUT entry 347 low" hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xADC "GFXMMU_LUT347H,GFXMMU LUT entry 347 high" hexmask.long.tbyte 0xADC 4.--21. 1. "LO,Line offset" line.long 0xAE0 "GFXMMU_LUT348L,GFXMMU LUT entry 348 low" hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAE4 "GFXMMU_LUT348H,GFXMMU LUT entry 348 high" hexmask.long.tbyte 0xAE4 4.--21. 1. "LO,Line offset" line.long 0xAE8 "GFXMMU_LUT349L,GFXMMU LUT entry 349 low" hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAEC "GFXMMU_LUT349H,GFXMMU LUT entry 349 high" hexmask.long.tbyte 0xAEC 4.--21. 1. "LO,Line offset" line.long 0xAF0 "GFXMMU_LUT350L,GFXMMU LUT entry 350 low" hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAF4 "GFXMMU_LUT350H,GFXMMU LUT entry 350 high" hexmask.long.tbyte 0xAF4 4.--21. 1. "LO,Line offset" line.long 0xAF8 "GFXMMU_LUT351L,GFXMMU LUT entry 351 low" hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAFC "GFXMMU_LUT351H,GFXMMU LUT entry 351 high" hexmask.long.tbyte 0xAFC 4.--21. 1. "LO,Line offset" line.long 0xB00 "GFXMMU_LUT352L,GFXMMU LUT entry 352 low" hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB04 "GFXMMU_LUT352H,GFXMMU LUT entry 352 high" hexmask.long.tbyte 0xB04 4.--21. 1. "LO,Line offset" line.long 0xB08 "GFXMMU_LUT353L,GFXMMU LUT entry 353 low" hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB0C "GFXMMU_LUT353H,GFXMMU LUT entry 353 high" hexmask.long.tbyte 0xB0C 4.--21. 1. "LO,Line offset" line.long 0xB10 "GFXMMU_LUT354L,GFXMMU LUT entry 354 low" hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB14 "GFXMMU_LUT354H,GFXMMU LUT entry 354 high" hexmask.long.tbyte 0xB14 4.--21. 1. "LO,Line offset" line.long 0xB18 "GFXMMU_LUT355L,GFXMMU LUT entry 355 low" hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB1C "GFXMMU_LUT355H,GFXMMU LUT entry 355 high" hexmask.long.tbyte 0xB1C 4.--21. 1. "LO,Line offset" line.long 0xB20 "GFXMMU_LUT356L,GFXMMU LUT entry 356 low" hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB24 "GFXMMU_LUT356H,GFXMMU LUT entry 356 high" hexmask.long.tbyte 0xB24 4.--21. 1. "LO,Line offset" line.long 0xB28 "GFXMMU_LUT357L,GFXMMU LUT entry 357 low" hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB2C "GFXMMU_LUT357H,GFXMMU LUT entry 357 high" hexmask.long.tbyte 0xB2C 4.--21. 1. "LO,Line offset" line.long 0xB30 "GFXMMU_LUT358L,GFXMMU LUT entry 358 low" hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB34 "GFXMMU_LUT358H,GFXMMU LUT entry 358 high" hexmask.long.tbyte 0xB34 4.--21. 1. "LO,Line offset" line.long 0xB38 "GFXMMU_LUT359L,GFXMMU LUT entry 359 low" hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB3C "GFXMMU_LUT359H,GFXMMU LUT entry 359 high" hexmask.long.tbyte 0xB3C 4.--21. 1. "LO,Line offset" line.long 0xB40 "GFXMMU_LUT360L,GFXMMU LUT entry 360 low" hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB44 "GFXMMU_LUT360H,GFXMMU LUT entry 360 high" hexmask.long.tbyte 0xB44 4.--21. 1. "LO,Line offset" line.long 0xB48 "GFXMMU_LUT361L,GFXMMU LUT entry 361 low" hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4C "GFXMMU_LUT361H,GFXMMU LUT entry 361 high" hexmask.long.tbyte 0xB4C 4.--21. 1. "LO,Line offset" line.long 0xB50 "GFXMMU_LUT362L,GFXMMU LUT entry 362 low" hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB54 "GFXMMU_LUT362H,GFXMMU LUT entry 362 high" hexmask.long.tbyte 0xB54 4.--21. 1. "LO,Line offset" line.long 0xB58 "GFXMMU_LUT363L,GFXMMU LUT entry 363 low" hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB5C "GFXMMU_LUT363H,GFXMMU LUT entry 363 high" hexmask.long.tbyte 0xB5C 4.--21. 1. "LO,Line offset" line.long 0xB60 "GFXMMU_LUT364L,GFXMMU LUT entry 364 low" hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB64 "GFXMMU_LUT364H,GFXMMU LUT entry 364 high" hexmask.long.tbyte 0xB64 4.--21. 1. "LO,Line offset" line.long 0xB68 "GFXMMU_LUT365L,GFXMMU LUT entry 365 low" hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB6C "GFXMMU_LUT365H,GFXMMU LUT entry 365 high" hexmask.long.tbyte 0xB6C 4.--21. 1. "LO,Line offset" line.long 0xB70 "GFXMMU_LUT366L,GFXMMU LUT entry 366 low" hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB74 "GFXMMU_LUT366H,GFXMMU LUT entry 366 high" hexmask.long.tbyte 0xB74 4.--21. 1. "LO,Line offset" line.long 0xB78 "GFXMMU_LUT367L,GFXMMU LUT entry 367 low" hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB7C "GFXMMU_LUT367H,GFXMMU LUT entry 367 high" hexmask.long.tbyte 0xB7C 4.--21. 1. "LO,Line offset" line.long 0xB80 "GFXMMU_LUT368L,GFXMMU LUT entry 368 low" hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB84 "GFXMMU_LUT368H,GFXMMU LUT entry 368 high" hexmask.long.tbyte 0xB84 4.--21. 1. "LO,Line offset" line.long 0xB88 "GFXMMU_LUT369L,GFXMMU LUT entry 369 low" hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB8C "GFXMMU_LUT369H,GFXMMU LUT entry 369 high" hexmask.long.tbyte 0xB8C 4.--21. 1. "LO,Line offset" line.long 0xB90 "GFXMMU_LUT370L,GFXMMU LUT entry 370 low" hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB94 "GFXMMU_LUT370H,GFXMMU LUT entry 370 high" hexmask.long.tbyte 0xB94 4.--21. 1. "LO,Line offset" line.long 0xB98 "GFXMMU_LUT371L,GFXMMU LUT entry 371 low" hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB9C "GFXMMU_LUT371H,GFXMMU LUT entry 371 high" hexmask.long.tbyte 0xB9C 4.--21. 1. "LO,Line offset" line.long 0xBA0 "GFXMMU_LUT372L,GFXMMU LUT entry 372 low" hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBA4 "GFXMMU_LUT372H,GFXMMU LUT entry 372 high" hexmask.long.tbyte 0xBA4 4.--21. 1. "LO,Line offset" line.long 0xBA8 "GFXMMU_LUT373L,GFXMMU LUT entry 373 low" hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBAC "GFXMMU_LUT373H,GFXMMU LUT entry 373 high" hexmask.long.tbyte 0xBAC 4.--21. 1. "LO,Line offset" line.long 0xBB0 "GFXMMU_LUT374L,GFXMMU LUT entry 374 low" hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBB4 "GFXMMU_LUT374H,GFXMMU LUT entry 374 high" hexmask.long.tbyte 0xBB4 4.--21. 1. "LO,Line offset" line.long 0xBB8 "GFXMMU_LUT375L,GFXMMU LUT entry 375 low" hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBBC "GFXMMU_LUT375H,GFXMMU LUT entry 375 high" hexmask.long.tbyte 0xBBC 4.--21. 1. "LO,Line offset" line.long 0xBC0 "GFXMMU_LUT376L,GFXMMU LUT entry 376 low" hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC4 "GFXMMU_LUT376H,GFXMMU LUT entry 376 high" hexmask.long.tbyte 0xBC4 4.--21. 1. "LO,Line offset" line.long 0xBC8 "GFXMMU_LUT377L,GFXMMU LUT entry 377 low" hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBCC "GFXMMU_LUT377H,GFXMMU LUT entry 377 high" hexmask.long.tbyte 0xBCC 4.--21. 1. "LO,Line offset" line.long 0xBD0 "GFXMMU_LUT378L,GFXMMU LUT entry 378 low" hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBD4 "GFXMMU_LUT378H,GFXMMU LUT entry 378 high" hexmask.long.tbyte 0xBD4 4.--21. 1. "LO,Line offset" line.long 0xBD8 "GFXMMU_LUT379L,GFXMMU LUT entry 379 low" hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBDC "GFXMMU_LUT379H,GFXMMU LUT entry 379 high" hexmask.long.tbyte 0xBDC 4.--21. 1. "LO,Line offset" line.long 0xBE0 "GFXMMU_LUT380L,GFXMMU LUT entry 380 low" hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBE4 "GFXMMU_LUT380H,GFXMMU LUT entry 380 high" hexmask.long.tbyte 0xBE4 4.--21. 1. "LO,Line offset" line.long 0xBE8 "GFXMMU_LUT381L,GFXMMU LUT entry 381 low" hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBEC "GFXMMU_LUT381H,GFXMMU LUT entry 381 high" hexmask.long.tbyte 0xBEC 4.--21. 1. "LO,Line offset" line.long 0xBF0 "GFXMMU_LUT382L,GFXMMU LUT entry 382 low" hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBF4 "GFXMMU_LUT382H,GFXMMU LUT entry 382 high" hexmask.long.tbyte 0xBF4 4.--21. 1. "LO,Line offset" line.long 0xBF8 "GFXMMU_LUT383L,GFXMMU LUT entry 383 low" hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBFC "GFXMMU_LUT383H,GFXMMU LUT entry 383 high" hexmask.long.tbyte 0xBFC 4.--21. 1. "LO,Line offset" line.long 0xC00 "GFXMMU_LUT384L,GFXMMU LUT entry 384 low" hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC04 "GFXMMU_LUT384H,GFXMMU LUT entry 384 high" hexmask.long.tbyte 0xC04 4.--21. 1. "LO,Line offset" line.long 0xC08 "GFXMMU_LUT385L,GFXMMU LUT entry 385 low" hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC0C "GFXMMU_LUT385H,GFXMMU LUT entry 385 high" hexmask.long.tbyte 0xC0C 4.--21. 1. "LO,Line offset" line.long 0xC10 "GFXMMU_LUT386L,GFXMMU LUT entry 386 low" hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC14 "GFXMMU_LUT386H,GFXMMU LUT entry 386 high" hexmask.long.tbyte 0xC14 4.--21. 1. "LO,Line offset" line.long 0xC18 "GFXMMU_LUT387L,GFXMMU LUT entry 387 low" hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC1C "GFXMMU_LUT387H,GFXMMU LUT entry 387 high" hexmask.long.tbyte 0xC1C 4.--21. 1. "LO,Line offset" line.long 0xC20 "GFXMMU_LUT388L,GFXMMU LUT entry 388 low" hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC24 "GFXMMU_LUT388H,GFXMMU LUT entry 388 high" hexmask.long.tbyte 0xC24 4.--21. 1. "LO,Line offset" line.long 0xC28 "GFXMMU_LUT389L,GFXMMU LUT entry 389 low" hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC2C "GFXMMU_LUT389H,GFXMMU LUT entry 389 high" hexmask.long.tbyte 0xC2C 4.--21. 1. "LO,Line offset" line.long 0xC30 "GFXMMU_LUT390L,GFXMMU LUT entry 390 low" hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC34 "GFXMMU_LUT390H,GFXMMU LUT entry 390 high" hexmask.long.tbyte 0xC34 4.--21. 1. "LO,Line offset" line.long 0xC38 "GFXMMU_LUT391L,GFXMMU LUT entry 391 low" hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC3C "GFXMMU_LUT391H,GFXMMU LUT entry 391 high" hexmask.long.tbyte 0xC3C 4.--21. 1. "LO,Line offset" line.long 0xC40 "GFXMMU_LUT392L,GFXMMU LUT entry 392 low" hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC44 "GFXMMU_LUT392H,GFXMMU LUT entry 392 high" hexmask.long.tbyte 0xC44 4.--21. 1. "LO,Line offset" line.long 0xC48 "GFXMMU_LUT393L,GFXMMU LUT entry 393 low" hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4C "GFXMMU_LUT393H,GFXMMU LUT entry 393 high" hexmask.long.tbyte 0xC4C 4.--21. 1. "LO,Line offset" line.long 0xC50 "GFXMMU_LUT394L,GFXMMU LUT entry 394 low" hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC54 "GFXMMU_LUT394H,GFXMMU LUT entry 394 high" hexmask.long.tbyte 0xC54 4.--21. 1. "LO,Line offset" line.long 0xC58 "GFXMMU_LUT395L,GFXMMU LUT entry 395 low" hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC5C "GFXMMU_LUT395H,GFXMMU LUT entry 395 high" hexmask.long.tbyte 0xC5C 4.--21. 1. "LO,Line offset" line.long 0xC60 "GFXMMU_LUT396L,GFXMMU LUT entry 396 low" hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC64 "GFXMMU_LUT396H,GFXMMU LUT entry 396 high" hexmask.long.tbyte 0xC64 4.--21. 1. "LO,Line offset" line.long 0xC68 "GFXMMU_LUT397L,GFXMMU LUT entry 397 low" hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC6C "GFXMMU_LUT397H,GFXMMU LUT entry 397 high" hexmask.long.tbyte 0xC6C 4.--21. 1. "LO,Line offset" line.long 0xC70 "GFXMMU_LUT398L,GFXMMU LUT entry 398 low" hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC74 "GFXMMU_LUT398H,GFXMMU LUT entry 398 high" hexmask.long.tbyte 0xC74 4.--21. 1. "LO,Line offset" line.long 0xC78 "GFXMMU_LUT399L,GFXMMU LUT entry 399 low" hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC7C "GFXMMU_LUT399H,GFXMMU LUT entry 399 high" hexmask.long.tbyte 0xC7C 4.--21. 1. "LO,Line offset" line.long 0xC80 "GFXMMU_LUT400L,GFXMMU LUT entry 400 low" hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC84 "GFXMMU_LUT400H,GFXMMU LUT entry 400 high" hexmask.long.tbyte 0xC84 4.--21. 1. "LO,Line offset" line.long 0xC88 "GFXMMU_LUT401L,GFXMMU LUT entry 401 low" hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC8C "GFXMMU_LUT401H,GFXMMU LUT entry 401 high" hexmask.long.tbyte 0xC8C 4.--21. 1. "LO,Line offset" line.long 0xC90 "GFXMMU_LUT402L,GFXMMU LUT entry 402 low" hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC94 "GFXMMU_LUT402H,GFXMMU LUT entry 402 high" hexmask.long.tbyte 0xC94 4.--21. 1. "LO,Line offset" line.long 0xC98 "GFXMMU_LUT403L,GFXMMU LUT entry 403 low" hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC9C "GFXMMU_LUT403H,GFXMMU LUT entry 403 high" hexmask.long.tbyte 0xC9C 4.--21. 1. "LO,Line offset" line.long 0xCA0 "GFXMMU_LUT404L,GFXMMU LUT entry 404 low" hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCA4 "GFXMMU_LUT404H,GFXMMU LUT entry 404 high" hexmask.long.tbyte 0xCA4 4.--21. 1. "LO,Line offset" line.long 0xCA8 "GFXMMU_LUT405L,GFXMMU LUT entry 405 low" hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCAC "GFXMMU_LUT405H,GFXMMU LUT entry 405 high" hexmask.long.tbyte 0xCAC 4.--21. 1. "LO,Line offset" line.long 0xCB0 "GFXMMU_LUT406L,GFXMMU LUT entry 406 low" hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCB4 "GFXMMU_LUT406H,GFXMMU LUT entry 406 high" hexmask.long.tbyte 0xCB4 4.--21. 1. "LO,Line offset" line.long 0xCB8 "GFXMMU_LUT407L,GFXMMU LUT entry 407 low" hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCBC "GFXMMU_LUT407H,GFXMMU LUT entry 407 high" hexmask.long.tbyte 0xCBC 4.--21. 1. "LO,Line offset" line.long 0xCC0 "GFXMMU_LUT408L,GFXMMU LUT entry 408 low" hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC4 "GFXMMU_LUT408H,GFXMMU LUT entry 408 high" hexmask.long.tbyte 0xCC4 4.--21. 1. "LO,Line offset" line.long 0xCC8 "GFXMMU_LUT409L,GFXMMU LUT entry 409 low" hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCCC "GFXMMU_LUT409H,GFXMMU LUT entry 409 high" hexmask.long.tbyte 0xCCC 4.--21. 1. "LO,Line offset" line.long 0xCD0 "GFXMMU_LUT410L,GFXMMU LUT entry 410 low" hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCD4 "GFXMMU_LUT410H,GFXMMU LUT entry 410 high" hexmask.long.tbyte 0xCD4 4.--21. 1. "LO,Line offset" line.long 0xCD8 "GFXMMU_LUT411L,GFXMMU LUT entry 411 low" hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCDC "GFXMMU_LUT411H,GFXMMU LUT entry 411 high" hexmask.long.tbyte 0xCDC 4.--21. 1. "LO,Line offset" line.long 0xCE0 "GFXMMU_LUT412L,GFXMMU LUT entry 412 low" hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCE4 "GFXMMU_LUT412H,GFXMMU LUT entry 412 high" hexmask.long.tbyte 0xCE4 4.--21. 1. "LO,Line offset" line.long 0xCE8 "GFXMMU_LUT413L,GFXMMU LUT entry 413 low" hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCEC "GFXMMU_LUT413H,GFXMMU LUT entry 413 high" hexmask.long.tbyte 0xCEC 4.--21. 1. "LO,Line offset" line.long 0xCF0 "GFXMMU_LUT414L,GFXMMU LUT entry 414 low" hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCF4 "GFXMMU_LUT414H,GFXMMU LUT entry 414 high" hexmask.long.tbyte 0xCF4 4.--21. 1. "LO,Line offset" line.long 0xCF8 "GFXMMU_LUT415L,GFXMMU LUT entry 415 low" hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCFC "GFXMMU_LUT415H,GFXMMU LUT entry 415 high" hexmask.long.tbyte 0xCFC 4.--21. 1. "LO,Line offset" line.long 0xD00 "GFXMMU_LUT416L,GFXMMU LUT entry 416 low" hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD04 "GFXMMU_LUT416H,GFXMMU LUT entry 416 high" hexmask.long.tbyte 0xD04 4.--21. 1. "LO,Line offset" line.long 0xD08 "GFXMMU_LUT417L,GFXMMU LUT entry 417 low" hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD0C "GFXMMU_LUT417H,GFXMMU LUT entry 417 high" hexmask.long.tbyte 0xD0C 4.--21. 1. "LO,Line offset" line.long 0xD10 "GFXMMU_LUT418L,GFXMMU LUT entry 418 low" hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD14 "GFXMMU_LUT418H,GFXMMU LUT entry 418 high" hexmask.long.tbyte 0xD14 4.--21. 1. "LO,Line offset" line.long 0xD18 "GFXMMU_LUT419L,GFXMMU LUT entry 419 low" hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD1C "GFXMMU_LUT419H,GFXMMU LUT entry 419 high" hexmask.long.tbyte 0xD1C 4.--21. 1. "LO,Line offset" line.long 0xD20 "GFXMMU_LUT420L,GFXMMU LUT entry 420 low" hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD24 "GFXMMU_LUT420H,GFXMMU LUT entry 420 high" hexmask.long.tbyte 0xD24 4.--21. 1. "LO,Line offset" line.long 0xD28 "GFXMMU_LUT421L,GFXMMU LUT entry 421 low" hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD2C "GFXMMU_LUT421H,GFXMMU LUT entry 421 high" hexmask.long.tbyte 0xD2C 4.--21. 1. "LO,Line offset" line.long 0xD30 "GFXMMU_LUT422L,GFXMMU LUT entry 422 low" hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD34 "GFXMMU_LUT422H,GFXMMU LUT entry 422 high" hexmask.long.tbyte 0xD34 4.--21. 1. "LO,Line offset" line.long 0xD38 "GFXMMU_LUT423L,GFXMMU LUT entry 423 low" hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD3C "GFXMMU_LUT423H,GFXMMU LUT entry 423 high" hexmask.long.tbyte 0xD3C 4.--21. 1. "LO,Line offset" line.long 0xD40 "GFXMMU_LUT424L,GFXMMU LUT entry 424 low" hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD44 "GFXMMU_LUT424H,GFXMMU LUT entry 424 high" hexmask.long.tbyte 0xD44 4.--21. 1. "LO,Line offset" line.long 0xD48 "GFXMMU_LUT425L,GFXMMU LUT entry 425 low" hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4C "GFXMMU_LUT425H,GFXMMU LUT entry 425 high" hexmask.long.tbyte 0xD4C 4.--21. 1. "LO,Line offset" line.long 0xD50 "GFXMMU_LUT426L,GFXMMU LUT entry 426 low" hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD54 "GFXMMU_LUT426H,GFXMMU LUT entry 426 high" hexmask.long.tbyte 0xD54 4.--21. 1. "LO,Line offset" line.long 0xD58 "GFXMMU_LUT427L,GFXMMU LUT entry 427 low" hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD5C "GFXMMU_LUT427H,GFXMMU LUT entry 427 high" hexmask.long.tbyte 0xD5C 4.--21. 1. "LO,Line offset" line.long 0xD60 "GFXMMU_LUT428L,GFXMMU LUT entry 428 low" hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD64 "GFXMMU_LUT428H,GFXMMU LUT entry 428 high" hexmask.long.tbyte 0xD64 4.--21. 1. "LO,Line offset" line.long 0xD68 "GFXMMU_LUT429L,GFXMMU LUT entry 429 low" hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD6C "GFXMMU_LUT429H,GFXMMU LUT entry 429 high" hexmask.long.tbyte 0xD6C 4.--21. 1. "LO,Line offset" line.long 0xD70 "GFXMMU_LUT430L,GFXMMU LUT entry 430 low" hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD74 "GFXMMU_LUT430H,GFXMMU LUT entry 430 high" hexmask.long.tbyte 0xD74 4.--21. 1. "LO,Line offset" line.long 0xD78 "GFXMMU_LUT431L,GFXMMU LUT entry 431 low" hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD7C "GFXMMU_LUT431H,GFXMMU LUT entry 431 high" hexmask.long.tbyte 0xD7C 4.--21. 1. "LO,Line offset" line.long 0xD80 "GFXMMU_LUT432L,GFXMMU LUT entry 432 low" hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD84 "GFXMMU_LUT432H,GFXMMU LUT entry 432 high" hexmask.long.tbyte 0xD84 4.--21. 1. "LO,Line offset" line.long 0xD88 "GFXMMU_LUT433L,GFXMMU LUT entry 433 low" hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD8C "GFXMMU_LUT433H,GFXMMU LUT entry 433 high" hexmask.long.tbyte 0xD8C 4.--21. 1. "LO,Line offset" line.long 0xD90 "GFXMMU_LUT434L,GFXMMU LUT entry 434 low" hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD94 "GFXMMU_LUT434H,GFXMMU LUT entry 434 high" hexmask.long.tbyte 0xD94 4.--21. 1. "LO,Line offset" line.long 0xD98 "GFXMMU_LUT435L,GFXMMU LUT entry 435 low" hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD9C "GFXMMU_LUT435H,GFXMMU LUT entry 435 high" hexmask.long.tbyte 0xD9C 4.--21. 1. "LO,Line offset" line.long 0xDA0 "GFXMMU_LUT436L,GFXMMU LUT entry 436 low" hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDA4 "GFXMMU_LUT436H,GFXMMU LUT entry 436 high" hexmask.long.tbyte 0xDA4 4.--21. 1. "LO,Line offset" line.long 0xDA8 "GFXMMU_LUT437L,GFXMMU LUT entry 437 low" hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDAC "GFXMMU_LUT437H,GFXMMU LUT entry 437 high" hexmask.long.tbyte 0xDAC 4.--21. 1. "LO,Line offset" line.long 0xDB0 "GFXMMU_LUT438L,GFXMMU LUT entry 438 low" hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDB4 "GFXMMU_LUT438H,GFXMMU LUT entry 438 high" hexmask.long.tbyte 0xDB4 4.--21. 1. "LO,Line offset" line.long 0xDB8 "GFXMMU_LUT439L,GFXMMU LUT entry 439 low" hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDBC "GFXMMU_LUT439H,GFXMMU LUT entry 439 high" hexmask.long.tbyte 0xDBC 4.--21. 1. "LO,Line offset" line.long 0xDC0 "GFXMMU_LUT440L,GFXMMU LUT entry 440 low" hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC4 "GFXMMU_LUT440H,GFXMMU LUT entry 440 high" hexmask.long.tbyte 0xDC4 4.--21. 1. "LO,Line offset" line.long 0xDC8 "GFXMMU_LUT441L,GFXMMU LUT entry 441 low" hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDCC "GFXMMU_LUT441H,GFXMMU LUT entry 441 high" hexmask.long.tbyte 0xDCC 4.--21. 1. "LO,Line offset" line.long 0xDD0 "GFXMMU_LUT442L,GFXMMU LUT entry 442 low" hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDD4 "GFXMMU_LUT442H,GFXMMU LUT entry 442 high" hexmask.long.tbyte 0xDD4 4.--21. 1. "LO,Line offset" line.long 0xDD8 "GFXMMU_LUT443L,GFXMMU LUT entry 443 low" hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDDC "GFXMMU_LUT443H,GFXMMU LUT entry 443 high" hexmask.long.tbyte 0xDDC 4.--21. 1. "LO,Line offset" line.long 0xDE0 "GFXMMU_LUT444L,GFXMMU LUT entry 444 low" hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDE4 "GFXMMU_LUT444H,GFXMMU LUT entry 444 high" hexmask.long.tbyte 0xDE4 4.--21. 1. "LO,Line offset" line.long 0xDE8 "GFXMMU_LUT445L,GFXMMU LUT entry 445 low" hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDEC "GFXMMU_LUT445H,GFXMMU LUT entry 445 high" hexmask.long.tbyte 0xDEC 4.--21. 1. "LO,Line offset" line.long 0xDF0 "GFXMMU_LUT446L,GFXMMU LUT entry 446 low" hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDF4 "GFXMMU_LUT446H,GFXMMU LUT entry 446 high" hexmask.long.tbyte 0xDF4 4.--21. 1. "LO,Line offset" line.long 0xDF8 "GFXMMU_LUT447L,GFXMMU LUT entry 447 low" hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDFC "GFXMMU_LUT447H,GFXMMU LUT entry 447 high" hexmask.long.tbyte 0xDFC 4.--21. 1. "LO,Line offset" line.long 0xE00 "GFXMMU_LUT448L,GFXMMU LUT entry 448 low" hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE04 "GFXMMU_LUT448H,GFXMMU LUT entry 448 high" hexmask.long.tbyte 0xE04 4.--21. 1. "LO,Line offset" line.long 0xE08 "GFXMMU_LUT449L,GFXMMU LUT entry 449 low" hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE0C "GFXMMU_LUT449H,GFXMMU LUT entry 449 high" hexmask.long.tbyte 0xE0C 4.--21. 1. "LO,Line offset" line.long 0xE10 "GFXMMU_LUT450L,GFXMMU LUT entry 450 low" hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE14 "GFXMMU_LUT450H,GFXMMU LUT entry 450 high" hexmask.long.tbyte 0xE14 4.--21. 1. "LO,Line offset" line.long 0xE18 "GFXMMU_LUT451L,GFXMMU LUT entry 451 low" hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE1C "GFXMMU_LUT451H,GFXMMU LUT entry 451 high" hexmask.long.tbyte 0xE1C 4.--21. 1. "LO,Line offset" line.long 0xE20 "GFXMMU_LUT452L,GFXMMU LUT entry 452 low" hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE24 "GFXMMU_LUT452H,GFXMMU LUT entry 452 high" hexmask.long.tbyte 0xE24 4.--21. 1. "LO,Line offset" line.long 0xE28 "GFXMMU_LUT453L,GFXMMU LUT entry 453 low" hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE2C "GFXMMU_LUT453H,GFXMMU LUT entry 453 high" hexmask.long.tbyte 0xE2C 4.--21. 1. "LO,Line offset" line.long 0xE30 "GFXMMU_LUT454L,GFXMMU LUT entry 454 low" hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE34 "GFXMMU_LUT454H,GFXMMU LUT entry 454 high" hexmask.long.tbyte 0xE34 4.--21. 1. "LO,Line offset" line.long 0xE38 "GFXMMU_LUT455L,GFXMMU LUT entry 455 low" hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE3C "GFXMMU_LUT455H,GFXMMU LUT entry 455 high" hexmask.long.tbyte 0xE3C 4.--21. 1. "LO,Line offset" line.long 0xE40 "GFXMMU_LUT456L,GFXMMU LUT entry 456 low" hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE44 "GFXMMU_LUT456H,GFXMMU LUT entry 456 high" hexmask.long.tbyte 0xE44 4.--21. 1. "LO,Line offset" line.long 0xE48 "GFXMMU_LUT457L,GFXMMU LUT entry 457 low" hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4C "GFXMMU_LUT457H,GFXMMU LUT entry 457 high" hexmask.long.tbyte 0xE4C 4.--21. 1. "LO,Line offset" line.long 0xE50 "GFXMMU_LUT458L,GFXMMU LUT entry 458 low" hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE54 "GFXMMU_LUT458H,GFXMMU LUT entry 458 high" hexmask.long.tbyte 0xE54 4.--21. 1. "LO,Line offset" line.long 0xE58 "GFXMMU_LUT459L,GFXMMU LUT entry 459 low" hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE5C "GFXMMU_LUT459H,GFXMMU LUT entry 459 high" hexmask.long.tbyte 0xE5C 4.--21. 1. "LO,Line offset" line.long 0xE60 "GFXMMU_LUT460L,GFXMMU LUT entry 460 low" hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE64 "GFXMMU_LUT460H,GFXMMU LUT entry 460 high" hexmask.long.tbyte 0xE64 4.--21. 1. "LO,Line offset" line.long 0xE68 "GFXMMU_LUT461L,GFXMMU LUT entry 461 low" hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE6C "GFXMMU_LUT461H,GFXMMU LUT entry 461 high" hexmask.long.tbyte 0xE6C 4.--21. 1. "LO,Line offset" line.long 0xE70 "GFXMMU_LUT462L,GFXMMU LUT entry 462 low" hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE74 "GFXMMU_LUT462H,GFXMMU LUT entry 462 high" hexmask.long.tbyte 0xE74 4.--21. 1. "LO,Line offset" line.long 0xE78 "GFXMMU_LUT463L,GFXMMU LUT entry 463 low" hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE7C "GFXMMU_LUT463H,GFXMMU LUT entry 463 high" hexmask.long.tbyte 0xE7C 4.--21. 1. "LO,Line offset" line.long 0xE80 "GFXMMU_LUT464L,GFXMMU LUT entry 464 low" hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE84 "GFXMMU_LUT464H,GFXMMU LUT entry 464 high" hexmask.long.tbyte 0xE84 4.--21. 1. "LO,Line offset" line.long 0xE88 "GFXMMU_LUT465L,GFXMMU LUT entry 465 low" hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE8C "GFXMMU_LUT465H,GFXMMU LUT entry 465 high" hexmask.long.tbyte 0xE8C 4.--21. 1. "LO,Line offset" line.long 0xE90 "GFXMMU_LUT466L,GFXMMU LUT entry 466 low" hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE94 "GFXMMU_LUT466H,GFXMMU LUT entry 466 high" hexmask.long.tbyte 0xE94 4.--21. 1. "LO,Line offset" line.long 0xE98 "GFXMMU_LUT467L,GFXMMU LUT entry 467 low" hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE9C "GFXMMU_LUT467H,GFXMMU LUT entry 467 high" hexmask.long.tbyte 0xE9C 4.--21. 1. "LO,Line offset" line.long 0xEA0 "GFXMMU_LUT468L,GFXMMU LUT entry 468 low" hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEA4 "GFXMMU_LUT468H,GFXMMU LUT entry 468 high" hexmask.long.tbyte 0xEA4 4.--21. 1. "LO,Line offset" line.long 0xEA8 "GFXMMU_LUT469L,GFXMMU LUT entry 469 low" hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEAC "GFXMMU_LUT469H,GFXMMU LUT entry 469 high" hexmask.long.tbyte 0xEAC 4.--21. 1. "LO,Line offset" line.long 0xEB0 "GFXMMU_LUT470L,GFXMMU LUT entry 470 low" hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEB4 "GFXMMU_LUT470H,GFXMMU LUT entry 470 high" hexmask.long.tbyte 0xEB4 4.--21. 1. "LO,Line offset" line.long 0xEB8 "GFXMMU_LUT471L,GFXMMU LUT entry 471 low" hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEBC "GFXMMU_LUT471H,GFXMMU LUT entry 471 high" hexmask.long.tbyte 0xEBC 4.--21. 1. "LO,Line offset" line.long 0xEC0 "GFXMMU_LUT472L,GFXMMU LUT entry 472 low" hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC4 "GFXMMU_LUT472H,GFXMMU LUT entry 472 high" hexmask.long.tbyte 0xEC4 4.--21. 1. "LO,Line offset" line.long 0xEC8 "GFXMMU_LUT473L,GFXMMU LUT entry 473 low" hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xECC "GFXMMU_LUT473H,GFXMMU LUT entry 473 high" hexmask.long.tbyte 0xECC 4.--21. 1. "LO,Line offset" line.long 0xED0 "GFXMMU_LUT474L,GFXMMU LUT entry 474 low" hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xED0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xED4 "GFXMMU_LUT474H,GFXMMU LUT entry 474 high" hexmask.long.tbyte 0xED4 4.--21. 1. "LO,Line offset" line.long 0xED8 "GFXMMU_LUT475L,GFXMMU LUT entry 475 low" hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xED8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEDC "GFXMMU_LUT475H,GFXMMU LUT entry 475 high" hexmask.long.tbyte 0xEDC 4.--21. 1. "LO,Line offset" line.long 0xEE0 "GFXMMU_LUT476L,GFXMMU LUT entry 476 low" hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEE4 "GFXMMU_LUT476H,GFXMMU LUT entry 476 high" hexmask.long.tbyte 0xEE4 4.--21. 1. "LO,Line offset" line.long 0xEE8 "GFXMMU_LUT477L,GFXMMU LUT entry 477 low" hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEEC "GFXMMU_LUT477H,GFXMMU LUT entry 477 high" hexmask.long.tbyte 0xEEC 4.--21. 1. "LO,Line offset" line.long 0xEF0 "GFXMMU_LUT478L,GFXMMU LUT entry 478 low" hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEF4 "GFXMMU_LUT478H,GFXMMU LUT entry 478 high" hexmask.long.tbyte 0xEF4 4.--21. 1. "LO,Line offset" line.long 0xEF8 "GFXMMU_LUT479L,GFXMMU LUT entry 479 low" hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEFC "GFXMMU_LUT479H,GFXMMU LUT entry 479 high" hexmask.long.tbyte 0xEFC 4.--21. 1. "LO,Line offset" line.long 0xF00 "GFXMMU_LUT480L,GFXMMU LUT entry 480 low" hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF04 "GFXMMU_LUT480H,GFXMMU LUT entry 480 high" hexmask.long.tbyte 0xF04 4.--21. 1. "LO,Line offset" line.long 0xF08 "GFXMMU_LUT481L,GFXMMU LUT entry 481 low" hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF0C "GFXMMU_LUT481H,GFXMMU LUT entry 481 high" hexmask.long.tbyte 0xF0C 4.--21. 1. "LO,Line offset" line.long 0xF10 "GFXMMU_LUT482L,GFXMMU LUT entry 482 low" hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF14 "GFXMMU_LUT482H,GFXMMU LUT entry 482 high" hexmask.long.tbyte 0xF14 4.--21. 1. "LO,Line offset" line.long 0xF18 "GFXMMU_LUT483L,GFXMMU LUT entry 483 low" hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF1C "GFXMMU_LUT483H,GFXMMU LUT entry 483 high" hexmask.long.tbyte 0xF1C 4.--21. 1. "LO,Line offset" line.long 0xF20 "GFXMMU_LUT484L,GFXMMU LUT entry 484 low" hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF24 "GFXMMU_LUT484H,GFXMMU LUT entry 484 high" hexmask.long.tbyte 0xF24 4.--21. 1. "LO,Line offset" line.long 0xF28 "GFXMMU_LUT485L,GFXMMU LUT entry 485 low" hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF2C "GFXMMU_LUT485H,GFXMMU LUT entry 485 high" hexmask.long.tbyte 0xF2C 4.--21. 1. "LO,Line offset" line.long 0xF30 "GFXMMU_LUT486L,GFXMMU LUT entry 486 low" hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF34 "GFXMMU_LUT486H,GFXMMU LUT entry 486 high" hexmask.long.tbyte 0xF34 4.--21. 1. "LO,Line offset" line.long 0xF38 "GFXMMU_LUT487L,GFXMMU LUT entry 487 low" hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF3C "GFXMMU_LUT487H,GFXMMU LUT entry 487 high" hexmask.long.tbyte 0xF3C 4.--21. 1. "LO,Line offset" line.long 0xF40 "GFXMMU_LUT488L,GFXMMU LUT entry 488 low" hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF44 "GFXMMU_LUT488H,GFXMMU LUT entry 488 high" hexmask.long.tbyte 0xF44 4.--21. 1. "LO,Line offset" line.long 0xF48 "GFXMMU_LUT489L,GFXMMU LUT entry 489 low" hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4C "GFXMMU_LUT489H,GFXMMU LUT entry 489 high" hexmask.long.tbyte 0xF4C 4.--21. 1. "LO,Line offset" line.long 0xF50 "GFXMMU_LUT490L,GFXMMU LUT entry 490 low" hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF54 "GFXMMU_LUT490H,GFXMMU LUT entry 490 high" hexmask.long.tbyte 0xF54 4.--21. 1. "LO,Line offset" line.long 0xF58 "GFXMMU_LUT491L,GFXMMU LUT entry 491 low" hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF5C "GFXMMU_LUT491H,GFXMMU LUT entry 491 high" hexmask.long.tbyte 0xF5C 4.--21. 1. "LO,Line offset" line.long 0xF60 "GFXMMU_LUT492L,GFXMMU LUT entry 492 low" hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF64 "GFXMMU_LUT492H,GFXMMU LUT entry 492 high" hexmask.long.tbyte 0xF64 4.--21. 1. "LO,Line offset" line.long 0xF68 "GFXMMU_LUT493L,GFXMMU LUT entry 493 low" hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF6C "GFXMMU_LUT493H,GFXMMU LUT entry 493 high" hexmask.long.tbyte 0xF6C 4.--21. 1. "LO,Line offset" line.long 0xF70 "GFXMMU_LUT494L,GFXMMU LUT entry 494 low" hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF74 "GFXMMU_LUT494H,GFXMMU LUT entry 494 high" hexmask.long.tbyte 0xF74 4.--21. 1. "LO,Line offset" line.long 0xF78 "GFXMMU_LUT495L,GFXMMU LUT entry 495 low" hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF7C "GFXMMU_LUT495H,GFXMMU LUT entry 495 high" hexmask.long.tbyte 0xF7C 4.--21. 1. "LO,Line offset" line.long 0xF80 "GFXMMU_LUT496L,GFXMMU LUT entry 496 low" hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF84 "GFXMMU_LUT496H,GFXMMU LUT entry 496 high" hexmask.long.tbyte 0xF84 4.--21. 1. "LO,Line offset" line.long 0xF88 "GFXMMU_LUT497L,GFXMMU LUT entry 497 low" hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF8C "GFXMMU_LUT497H,GFXMMU LUT entry 497 high" hexmask.long.tbyte 0xF8C 4.--21. 1. "LO,Line offset" line.long 0xF90 "GFXMMU_LUT498L,GFXMMU LUT entry 498 low" hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF94 "GFXMMU_LUT498H,GFXMMU LUT entry 498 high" hexmask.long.tbyte 0xF94 4.--21. 1. "LO,Line offset" line.long 0xF98 "GFXMMU_LUT499L,GFXMMU LUT entry 499 low" hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF9C "GFXMMU_LUT499H,GFXMMU LUT entry 499 high" hexmask.long.tbyte 0xF9C 4.--21. 1. "LO,Line offset" line.long 0xFA0 "GFXMMU_LUT500L,GFXMMU LUT entry 500 low" hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFA4 "GFXMMU_LUT500H,GFXMMU LUT entry 500 high" hexmask.long.tbyte 0xFA4 4.--21. 1. "LO,Line offset" line.long 0xFA8 "GFXMMU_LUT501L,GFXMMU LUT entry 501 low" hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFAC "GFXMMU_LUT501H,GFXMMU LUT entry 501 high" hexmask.long.tbyte 0xFAC 4.--21. 1. "LO,Line offset" line.long 0xFB0 "GFXMMU_LUT502L,GFXMMU LUT entry 502 low" hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFB4 "GFXMMU_LUT502H,GFXMMU LUT entry 502 high" hexmask.long.tbyte 0xFB4 4.--21. 1. "LO,Line offset" line.long 0xFB8 "GFXMMU_LUT503L,GFXMMU LUT entry 503 low" hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFBC "GFXMMU_LUT503H,GFXMMU LUT entry 503 high" hexmask.long.tbyte 0xFBC 4.--21. 1. "LO,Line offset" line.long 0xFC0 "GFXMMU_LUT504L,GFXMMU LUT entry 504 low" hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC4 "GFXMMU_LUT504H,GFXMMU LUT entry 504 high" hexmask.long.tbyte 0xFC4 4.--21. 1. "LO,Line offset" line.long 0xFC8 "GFXMMU_LUT505L,GFXMMU LUT entry 505 low" hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFCC "GFXMMU_LUT505H,GFXMMU LUT entry 505 high" hexmask.long.tbyte 0xFCC 4.--21. 1. "LO,Line offset" line.long 0xFD0 "GFXMMU_LUT506L,GFXMMU LUT entry 506 low" hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFD4 "GFXMMU_LUT506H,GFXMMU LUT entry 506 high" hexmask.long.tbyte 0xFD4 4.--21. 1. "LO,Line offset" line.long 0xFD8 "GFXMMU_LUT507L,GFXMMU LUT entry 507 low" hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFDC "GFXMMU_LUT507H,GFXMMU LUT entry 507 high" hexmask.long.tbyte 0xFDC 4.--21. 1. "LO,Line offset" line.long 0xFE0 "GFXMMU_LUT508L,GFXMMU LUT entry 508 low" hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFE4 "GFXMMU_LUT508H,GFXMMU LUT entry 508 high" hexmask.long.tbyte 0xFE4 4.--21. 1. "LO,Line offset" line.long 0xFE8 "GFXMMU_LUT509L,GFXMMU LUT entry 509 low" hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFEC "GFXMMU_LUT509H,GFXMMU LUT entry 509 high" hexmask.long.tbyte 0xFEC 4.--21. 1. "LO,Line offset" line.long 0xFF0 "GFXMMU_LUT510L,GFXMMU LUT entry 510 low" hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFF4 "GFXMMU_LUT510H,GFXMMU LUT entry 510 high" hexmask.long.tbyte 0xFF4 4.--21. 1. "LO,Line offset" line.long 0xFF8 "GFXMMU_LUT511L,GFXMMU LUT entry 511 low" hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFFC "GFXMMU_LUT511H,GFXMMU LUT entry 511 high" hexmask.long.tbyte 0xFFC 4.--21. 1. "LO,Line offset" group.long 0x2000++0xFFF line.long 0x0 "GFXMMU_LUT512L,GFXMMU LUT entry 512 low" hexmask.long.byte 0x0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4 "GFXMMU_LUT512H,GFXMMU LUT entry 512 high" hexmask.long.tbyte 0x4 4.--21. 1. "LO,Line offset" line.long 0x8 "GFXMMU_LUT513L,GFXMMU LUT entry 513 low" hexmask.long.byte 0x8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC "GFXMMU_LUT513H,GFXMMU LUT entry 513 high" hexmask.long.tbyte 0xC 4.--21. 1. "LO,Line offset" line.long 0x10 "GFXMMU_LUT514L,GFXMMU LUT entry 514 low" hexmask.long.byte 0x10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14 "GFXMMU_LUT514H,GFXMMU LUT entry 514 high" hexmask.long.tbyte 0x14 4.--21. 1. "LO,Line offset" line.long 0x18 "GFXMMU_LUT515L,GFXMMU LUT entry 515 low" hexmask.long.byte 0x18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C "GFXMMU_LUT515H,GFXMMU LUT entry 515 high" hexmask.long.tbyte 0x1C 4.--21. 1. "LO,Line offset" line.long 0x20 "GFXMMU_LUT516L,GFXMMU LUT entry 516 low" hexmask.long.byte 0x20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24 "GFXMMU_LUT516H,GFXMMU LUT entry 516 high" hexmask.long.tbyte 0x24 4.--21. 1. "LO,Line offset" line.long 0x28 "GFXMMU_LUT517L,GFXMMU LUT entry 517 low" hexmask.long.byte 0x28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C "GFXMMU_LUT517H,GFXMMU LUT entry 517 high" hexmask.long.tbyte 0x2C 4.--21. 1. "LO,Line offset" line.long 0x30 "GFXMMU_LUT518L,GFXMMU LUT entry 518 low" hexmask.long.byte 0x30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34 "GFXMMU_LUT518H,GFXMMU LUT entry 518 high" hexmask.long.tbyte 0x34 4.--21. 1. "LO,Line offset" line.long 0x38 "GFXMMU_LUT519L,GFXMMU LUT entry 519 low" hexmask.long.byte 0x38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C "GFXMMU_LUT519H,GFXMMU LUT entry 519 high" hexmask.long.tbyte 0x3C 4.--21. 1. "LO,Line offset" line.long 0x40 "GFXMMU_LUT520L,GFXMMU LUT entry 520 low" hexmask.long.byte 0x40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44 "GFXMMU_LUT520H,GFXMMU LUT entry 520 high" hexmask.long.tbyte 0x44 4.--21. 1. "LO,Line offset" line.long 0x48 "GFXMMU_LUT521L,GFXMMU LUT entry 521 low" hexmask.long.byte 0x48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C "GFXMMU_LUT521H,GFXMMU LUT entry 521 high" hexmask.long.tbyte 0x4C 4.--21. 1. "LO,Line offset" line.long 0x50 "GFXMMU_LUT522L,GFXMMU LUT entry 522 low" hexmask.long.byte 0x50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54 "GFXMMU_LUT522H,GFXMMU LUT entry 522 high" hexmask.long.tbyte 0x54 4.--21. 1. "LO,Line offset" line.long 0x58 "GFXMMU_LUT523L,GFXMMU LUT entry 523 low" hexmask.long.byte 0x58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C "GFXMMU_LUT523H,GFXMMU LUT entry 523 high" hexmask.long.tbyte 0x5C 4.--21. 1. "LO,Line offset" line.long 0x60 "GFXMMU_LUT524L,GFXMMU LUT entry 524 low" hexmask.long.byte 0x60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64 "GFXMMU_LUT524H,GFXMMU LUT entry 524 high" hexmask.long.tbyte 0x64 4.--21. 1. "LO,Line offset" line.long 0x68 "GFXMMU_LUT525L,GFXMMU LUT entry 525 low" hexmask.long.byte 0x68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C "GFXMMU_LUT525H,GFXMMU LUT entry 525 high" hexmask.long.tbyte 0x6C 4.--21. 1. "LO,Line offset" line.long 0x70 "GFXMMU_LUT526L,GFXMMU LUT entry 526 low" hexmask.long.byte 0x70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74 "GFXMMU_LUT526H,GFXMMU LUT entry 526 high" hexmask.long.tbyte 0x74 4.--21. 1. "LO,Line offset" line.long 0x78 "GFXMMU_LUT527L,GFXMMU LUT entry 527 low" hexmask.long.byte 0x78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C "GFXMMU_LUT527H,GFXMMU LUT entry 527 high" hexmask.long.tbyte 0x7C 4.--21. 1. "LO,Line offset" line.long 0x80 "GFXMMU_LUT528L,GFXMMU LUT entry 528 low" hexmask.long.byte 0x80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84 "GFXMMU_LUT528H,GFXMMU LUT entry 528 high" hexmask.long.tbyte 0x84 4.--21. 1. "LO,Line offset" line.long 0x88 "GFXMMU_LUT529L,GFXMMU LUT entry 529 low" hexmask.long.byte 0x88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C "GFXMMU_LUT529H,GFXMMU LUT entry 529 high" hexmask.long.tbyte 0x8C 4.--21. 1. "LO,Line offset" line.long 0x90 "GFXMMU_LUT530L,GFXMMU LUT entry 530 low" hexmask.long.byte 0x90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94 "GFXMMU_LUT530H,GFXMMU LUT entry 530 high" hexmask.long.tbyte 0x94 4.--21. 1. "LO,Line offset" line.long 0x98 "GFXMMU_LUT531L,GFXMMU LUT entry 531 low" hexmask.long.byte 0x98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C "GFXMMU_LUT531H,GFXMMU LUT entry 531 high" hexmask.long.tbyte 0x9C 4.--21. 1. "LO,Line offset" line.long 0xA0 "GFXMMU_LUT532L,GFXMMU LUT entry 532 low" hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4 "GFXMMU_LUT532H,GFXMMU LUT entry 532 high" hexmask.long.tbyte 0xA4 4.--21. 1. "LO,Line offset" line.long 0xA8 "GFXMMU_LUT533L,GFXMMU LUT entry 533 low" hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC "GFXMMU_LUT533H,GFXMMU LUT entry 533 high" hexmask.long.tbyte 0xAC 4.--21. 1. "LO,Line offset" line.long 0xB0 "GFXMMU_LUT534L,GFXMMU LUT entry 534 low" hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4 "GFXMMU_LUT534H,GFXMMU LUT entry 534 high" hexmask.long.tbyte 0xB4 4.--21. 1. "LO,Line offset" line.long 0xB8 "GFXMMU_LUT535L,GFXMMU LUT entry 535 low" hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC "GFXMMU_LUT535H,GFXMMU LUT entry 535 high" hexmask.long.tbyte 0xBC 4.--21. 1. "LO,Line offset" line.long 0xC0 "GFXMMU_LUT536L,GFXMMU LUT entry 536 low" hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4 "GFXMMU_LUT536H,GFXMMU LUT entry 536 high" hexmask.long.tbyte 0xC4 4.--21. 1. "LO,Line offset" line.long 0xC8 "GFXMMU_LUT537L,GFXMMU LUT entry 537 low" hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC "GFXMMU_LUT537H,GFXMMU LUT entry 537 high" hexmask.long.tbyte 0xCC 4.--21. 1. "LO,Line offset" line.long 0xD0 "GFXMMU_LUT538L,GFXMMU LUT entry 538 low" hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4 "GFXMMU_LUT538H,GFXMMU LUT entry 538 high" hexmask.long.tbyte 0xD4 4.--21. 1. "LO,Line offset" line.long 0xD8 "GFXMMU_LUT539L,GFXMMU LUT entry 539 low" hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC "GFXMMU_LUT539H,GFXMMU LUT entry 539 high" hexmask.long.tbyte 0xDC 4.--21. 1. "LO,Line offset" line.long 0xE0 "GFXMMU_LUT540L,GFXMMU LUT entry 540 low" hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4 "GFXMMU_LUT540H,GFXMMU LUT entry 540 high" hexmask.long.tbyte 0xE4 4.--21. 1. "LO,Line offset" line.long 0xE8 "GFXMMU_LUT541L,GFXMMU LUT entry 541 low" hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC "GFXMMU_LUT541H,GFXMMU LUT entry 541 high" hexmask.long.tbyte 0xEC 4.--21. 1. "LO,Line offset" line.long 0xF0 "GFXMMU_LUT542L,GFXMMU LUT entry 542 low" hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4 "GFXMMU_LUT542H,GFXMMU LUT entry 542 high" hexmask.long.tbyte 0xF4 4.--21. 1. "LO,Line offset" line.long 0xF8 "GFXMMU_LUT543L,GFXMMU LUT entry 543 low" hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC "GFXMMU_LUT543H,GFXMMU LUT entry 543 high" hexmask.long.tbyte 0xFC 4.--21. 1. "LO,Line offset" line.long 0x100 "GFXMMU_LUT544L,GFXMMU LUT entry 544 low" hexmask.long.byte 0x100 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x100 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x104 "GFXMMU_LUT544H,GFXMMU LUT entry 544 high" hexmask.long.tbyte 0x104 4.--21. 1. "LO,Line offset" line.long 0x108 "GFXMMU_LUT545L,GFXMMU LUT entry 545 low" hexmask.long.byte 0x108 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x108 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x10C "GFXMMU_LUT545H,GFXMMU LUT entry 545 high" hexmask.long.tbyte 0x10C 4.--21. 1. "LO,Line offset" line.long 0x110 "GFXMMU_LUT546L,GFXMMU LUT entry 546 low" hexmask.long.byte 0x110 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x110 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x114 "GFXMMU_LUT546H,GFXMMU LUT entry 546 high" hexmask.long.tbyte 0x114 4.--21. 1. "LO,Line offset" line.long 0x118 "GFXMMU_LUT547L,GFXMMU LUT entry 547 low" hexmask.long.byte 0x118 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x118 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x11C "GFXMMU_LUT547H,GFXMMU LUT entry 547 high" hexmask.long.tbyte 0x11C 4.--21. 1. "LO,Line offset" line.long 0x120 "GFXMMU_LUT548L,GFXMMU LUT entry 548 low" hexmask.long.byte 0x120 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x120 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x124 "GFXMMU_LUT548H,GFXMMU LUT entry 548 high" hexmask.long.tbyte 0x124 4.--21. 1. "LO,Line offset" line.long 0x128 "GFXMMU_LUT549L,GFXMMU LUT entry 549 low" hexmask.long.byte 0x128 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x128 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x12C "GFXMMU_LUT549H,GFXMMU LUT entry 549 high" hexmask.long.tbyte 0x12C 4.--21. 1. "LO,Line offset" line.long 0x130 "GFXMMU_LUT550L,GFXMMU LUT entry 550 low" hexmask.long.byte 0x130 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x130 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x134 "GFXMMU_LUT550H,GFXMMU LUT entry 550 high" hexmask.long.tbyte 0x134 4.--21. 1. "LO,Line offset" line.long 0x138 "GFXMMU_LUT551L,GFXMMU LUT entry 551 low" hexmask.long.byte 0x138 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x138 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x13C "GFXMMU_LUT551H,GFXMMU LUT entry 551 high" hexmask.long.tbyte 0x13C 4.--21. 1. "LO,Line offset" line.long 0x140 "GFXMMU_LUT552L,GFXMMU LUT entry 552 low" hexmask.long.byte 0x140 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x140 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x144 "GFXMMU_LUT552H,GFXMMU LUT entry 552 high" hexmask.long.tbyte 0x144 4.--21. 1. "LO,Line offset" line.long 0x148 "GFXMMU_LUT553L,GFXMMU LUT entry 553 low" hexmask.long.byte 0x148 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x148 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14C "GFXMMU_LUT553H,GFXMMU LUT entry 553 high" hexmask.long.tbyte 0x14C 4.--21. 1. "LO,Line offset" line.long 0x150 "GFXMMU_LUT554L,GFXMMU LUT entry 554 low" hexmask.long.byte 0x150 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x150 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x154 "GFXMMU_LUT554H,GFXMMU LUT entry 554 high" hexmask.long.tbyte 0x154 4.--21. 1. "LO,Line offset" line.long 0x158 "GFXMMU_LUT555L,GFXMMU LUT entry 555 low" hexmask.long.byte 0x158 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x158 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x15C "GFXMMU_LUT555H,GFXMMU LUT entry 555 high" hexmask.long.tbyte 0x15C 4.--21. 1. "LO,Line offset" line.long 0x160 "GFXMMU_LUT556L,GFXMMU LUT entry 556 low" hexmask.long.byte 0x160 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x160 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x164 "GFXMMU_LUT556H,GFXMMU LUT entry 556 high" hexmask.long.tbyte 0x164 4.--21. 1. "LO,Line offset" line.long 0x168 "GFXMMU_LUT557L,GFXMMU LUT entry 557 low" hexmask.long.byte 0x168 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x168 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x16C "GFXMMU_LUT557H,GFXMMU LUT entry 557 high" hexmask.long.tbyte 0x16C 4.--21. 1. "LO,Line offset" line.long 0x170 "GFXMMU_LUT558L,GFXMMU LUT entry 558 low" hexmask.long.byte 0x170 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x170 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x174 "GFXMMU_LUT558H,GFXMMU LUT entry 558 high" hexmask.long.tbyte 0x174 4.--21. 1. "LO,Line offset" line.long 0x178 "GFXMMU_LUT559L,GFXMMU LUT entry 559 low" hexmask.long.byte 0x178 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x178 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x17C "GFXMMU_LUT559H,GFXMMU LUT entry 559 high" hexmask.long.tbyte 0x17C 4.--21. 1. "LO,Line offset" line.long 0x180 "GFXMMU_LUT560L,GFXMMU LUT entry 560 low" hexmask.long.byte 0x180 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x180 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x184 "GFXMMU_LUT560H,GFXMMU LUT entry 560 high" hexmask.long.tbyte 0x184 4.--21. 1. "LO,Line offset" line.long 0x188 "GFXMMU_LUT561L,GFXMMU LUT entry 561 low" hexmask.long.byte 0x188 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x188 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x18C "GFXMMU_LUT561H,GFXMMU LUT entry 561 high" hexmask.long.tbyte 0x18C 4.--21. 1. "LO,Line offset" line.long 0x190 "GFXMMU_LUT562L,GFXMMU LUT entry 562 low" hexmask.long.byte 0x190 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x190 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x194 "GFXMMU_LUT562H,GFXMMU LUT entry 562 high" hexmask.long.tbyte 0x194 4.--21. 1. "LO,Line offset" line.long 0x198 "GFXMMU_LUT563L,GFXMMU LUT entry 563 low" hexmask.long.byte 0x198 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x198 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x19C "GFXMMU_LUT563H,GFXMMU LUT entry 563 high" hexmask.long.tbyte 0x19C 4.--21. 1. "LO,Line offset" line.long 0x1A0 "GFXMMU_LUT564L,GFXMMU LUT entry 564 low" hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1A4 "GFXMMU_LUT564H,GFXMMU LUT entry 564 high" hexmask.long.tbyte 0x1A4 4.--21. 1. "LO,Line offset" line.long 0x1A8 "GFXMMU_LUT565L,GFXMMU LUT entry 565 low" hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1AC "GFXMMU_LUT565H,GFXMMU LUT entry 565 high" hexmask.long.tbyte 0x1AC 4.--21. 1. "LO,Line offset" line.long 0x1B0 "GFXMMU_LUT566L,GFXMMU LUT entry 566 low" hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1B4 "GFXMMU_LUT566H,GFXMMU LUT entry 566 high" hexmask.long.tbyte 0x1B4 4.--21. 1. "LO,Line offset" line.long 0x1B8 "GFXMMU_LUT567L,GFXMMU LUT entry 567 low" hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1BC "GFXMMU_LUT567H,GFXMMU LUT entry 567 high" hexmask.long.tbyte 0x1BC 4.--21. 1. "LO,Line offset" line.long 0x1C0 "GFXMMU_LUT568L,GFXMMU LUT entry 568 low" hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C4 "GFXMMU_LUT568H,GFXMMU LUT entry 568 high" hexmask.long.tbyte 0x1C4 4.--21. 1. "LO,Line offset" line.long 0x1C8 "GFXMMU_LUT569L,GFXMMU LUT entry 569 low" hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1CC "GFXMMU_LUT569H,GFXMMU LUT entry 569 high" hexmask.long.tbyte 0x1CC 4.--21. 1. "LO,Line offset" line.long 0x1D0 "GFXMMU_LUT570L,GFXMMU LUT entry 570 low" hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1D4 "GFXMMU_LUT570H,GFXMMU LUT entry 570 high" hexmask.long.tbyte 0x1D4 4.--21. 1. "LO,Line offset" line.long 0x1D8 "GFXMMU_LUT571L,GFXMMU LUT entry 571 low" hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1DC "GFXMMU_LUT571H,GFXMMU LUT entry 571 high" hexmask.long.tbyte 0x1DC 4.--21. 1. "LO,Line offset" line.long 0x1E0 "GFXMMU_LUT572L,GFXMMU LUT entry 572 low" hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1E4 "GFXMMU_LUT572H,GFXMMU LUT entry 572 high" hexmask.long.tbyte 0x1E4 4.--21. 1. "LO,Line offset" line.long 0x1E8 "GFXMMU_LUT573L,GFXMMU LUT entry 573 low" hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1EC "GFXMMU_LUT573H,GFXMMU LUT entry 573 high" hexmask.long.tbyte 0x1EC 4.--21. 1. "LO,Line offset" line.long 0x1F0 "GFXMMU_LUT574L,GFXMMU LUT entry 574 low" hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1F4 "GFXMMU_LUT574H,GFXMMU LUT entry 574 high" hexmask.long.tbyte 0x1F4 4.--21. 1. "LO,Line offset" line.long 0x1F8 "GFXMMU_LUT575L,GFXMMU LUT entry 575 low" hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1FC "GFXMMU_LUT575H,GFXMMU LUT entry 575 high" hexmask.long.tbyte 0x1FC 4.--21. 1. "LO,Line offset" line.long 0x200 "GFXMMU_LUT576L,GFXMMU LUT entry 576 low" hexmask.long.byte 0x200 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x200 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x204 "GFXMMU_LUT576H,GFXMMU LUT entry 576 high" hexmask.long.tbyte 0x204 4.--21. 1. "LO,Line offset" line.long 0x208 "GFXMMU_LUT577L,GFXMMU LUT entry 577 low" hexmask.long.byte 0x208 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x208 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x20C "GFXMMU_LUT577H,GFXMMU LUT entry 577 high" hexmask.long.tbyte 0x20C 4.--21. 1. "LO,Line offset" line.long 0x210 "GFXMMU_LUT578L,GFXMMU LUT entry 578 low" hexmask.long.byte 0x210 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x210 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x214 "GFXMMU_LUT578H,GFXMMU LUT entry 578 high" hexmask.long.tbyte 0x214 4.--21. 1. "LO,Line offset" line.long 0x218 "GFXMMU_LUT579L,GFXMMU LUT entry 579 low" hexmask.long.byte 0x218 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x218 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x21C "GFXMMU_LUT579H,GFXMMU LUT entry 579 high" hexmask.long.tbyte 0x21C 4.--21. 1. "LO,Line offset" line.long 0x220 "GFXMMU_LUT580L,GFXMMU LUT entry 580 low" hexmask.long.byte 0x220 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x220 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x224 "GFXMMU_LUT580H,GFXMMU LUT entry 580 high" hexmask.long.tbyte 0x224 4.--21. 1. "LO,Line offset" line.long 0x228 "GFXMMU_LUT581L,GFXMMU LUT entry 581 low" hexmask.long.byte 0x228 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x228 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x22C "GFXMMU_LUT581H,GFXMMU LUT entry 581 high" hexmask.long.tbyte 0x22C 4.--21. 1. "LO,Line offset" line.long 0x230 "GFXMMU_LUT582L,GFXMMU LUT entry 582 low" hexmask.long.byte 0x230 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x230 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x234 "GFXMMU_LUT582H,GFXMMU LUT entry 582 high" hexmask.long.tbyte 0x234 4.--21. 1. "LO,Line offset" line.long 0x238 "GFXMMU_LUT583L,GFXMMU LUT entry 583 low" hexmask.long.byte 0x238 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x238 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x23C "GFXMMU_LUT583H,GFXMMU LUT entry 583 high" hexmask.long.tbyte 0x23C 4.--21. 1. "LO,Line offset" line.long 0x240 "GFXMMU_LUT584L,GFXMMU LUT entry 584 low" hexmask.long.byte 0x240 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x240 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x244 "GFXMMU_LUT584H,GFXMMU LUT entry 584 high" hexmask.long.tbyte 0x244 4.--21. 1. "LO,Line offset" line.long 0x248 "GFXMMU_LUT585L,GFXMMU LUT entry 585 low" hexmask.long.byte 0x248 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x248 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24C "GFXMMU_LUT585H,GFXMMU LUT entry 585 high" hexmask.long.tbyte 0x24C 4.--21. 1. "LO,Line offset" line.long 0x250 "GFXMMU_LUT586L,GFXMMU LUT entry 586 low" hexmask.long.byte 0x250 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x250 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x254 "GFXMMU_LUT586H,GFXMMU LUT entry 586 high" hexmask.long.tbyte 0x254 4.--21. 1. "LO,Line offset" line.long 0x258 "GFXMMU_LUT587L,GFXMMU LUT entry 587 low" hexmask.long.byte 0x258 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x258 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x25C "GFXMMU_LUT587H,GFXMMU LUT entry 587 high" hexmask.long.tbyte 0x25C 4.--21. 1. "LO,Line offset" line.long 0x260 "GFXMMU_LUT588L,GFXMMU LUT entry 588 low" hexmask.long.byte 0x260 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x260 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x264 "GFXMMU_LUT588H,GFXMMU LUT entry 588 high" hexmask.long.tbyte 0x264 4.--21. 1. "LO,Line offset" line.long 0x268 "GFXMMU_LUT589L,GFXMMU LUT entry 589 low" hexmask.long.byte 0x268 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x268 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x26C "GFXMMU_LUT589H,GFXMMU LUT entry 589 high" hexmask.long.tbyte 0x26C 4.--21. 1. "LO,Line offset" line.long 0x270 "GFXMMU_LUT590L,GFXMMU LUT entry 590 low" hexmask.long.byte 0x270 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x270 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x274 "GFXMMU_LUT590H,GFXMMU LUT entry 590 high" hexmask.long.tbyte 0x274 4.--21. 1. "LO,Line offset" line.long 0x278 "GFXMMU_LUT591L,GFXMMU LUT entry 591 low" hexmask.long.byte 0x278 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x278 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x27C "GFXMMU_LUT591H,GFXMMU LUT entry 591 high" hexmask.long.tbyte 0x27C 4.--21. 1. "LO,Line offset" line.long 0x280 "GFXMMU_LUT592L,GFXMMU LUT entry 592 low" hexmask.long.byte 0x280 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x280 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x284 "GFXMMU_LUT592H,GFXMMU LUT entry 592 high" hexmask.long.tbyte 0x284 4.--21. 1. "LO,Line offset" line.long 0x288 "GFXMMU_LUT593L,GFXMMU LUT entry 593 low" hexmask.long.byte 0x288 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x288 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x28C "GFXMMU_LUT593H,GFXMMU LUT entry 593 high" hexmask.long.tbyte 0x28C 4.--21. 1. "LO,Line offset" line.long 0x290 "GFXMMU_LUT594L,GFXMMU LUT entry 594 low" hexmask.long.byte 0x290 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x290 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x294 "GFXMMU_LUT594H,GFXMMU LUT entry 594 high" hexmask.long.tbyte 0x294 4.--21. 1. "LO,Line offset" line.long 0x298 "GFXMMU_LUT595L,GFXMMU LUT entry 595 low" hexmask.long.byte 0x298 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x298 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x29C "GFXMMU_LUT595H,GFXMMU LUT entry 595 high" hexmask.long.tbyte 0x29C 4.--21. 1. "LO,Line offset" line.long 0x2A0 "GFXMMU_LUT596L,GFXMMU LUT entry 596 low" hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2A4 "GFXMMU_LUT596H,GFXMMU LUT entry 596 high" hexmask.long.tbyte 0x2A4 4.--21. 1. "LO,Line offset" line.long 0x2A8 "GFXMMU_LUT597L,GFXMMU LUT entry 597 low" hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2AC "GFXMMU_LUT597H,GFXMMU LUT entry 597 high" hexmask.long.tbyte 0x2AC 4.--21. 1. "LO,Line offset" line.long 0x2B0 "GFXMMU_LUT598L,GFXMMU LUT entry 598 low" hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2B4 "GFXMMU_LUT598H,GFXMMU LUT entry 598 high" hexmask.long.tbyte 0x2B4 4.--21. 1. "LO,Line offset" line.long 0x2B8 "GFXMMU_LUT599L,GFXMMU LUT entry 599 low" hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2BC "GFXMMU_LUT599H,GFXMMU LUT entry 599 high" hexmask.long.tbyte 0x2BC 4.--21. 1. "LO,Line offset" line.long 0x2C0 "GFXMMU_LUT600L,GFXMMU LUT entry 600 low" hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C4 "GFXMMU_LUT600H,GFXMMU LUT entry 600 high" hexmask.long.tbyte 0x2C4 4.--21. 1. "LO,Line offset" line.long 0x2C8 "GFXMMU_LUT601L,GFXMMU LUT entry 601 low" hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2CC "GFXMMU_LUT601H,GFXMMU LUT entry 601 high" hexmask.long.tbyte 0x2CC 4.--21. 1. "LO,Line offset" line.long 0x2D0 "GFXMMU_LUT602L,GFXMMU LUT entry 602 low" hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2D4 "GFXMMU_LUT602H,GFXMMU LUT entry 602 high" hexmask.long.tbyte 0x2D4 4.--21. 1. "LO,Line offset" line.long 0x2D8 "GFXMMU_LUT603L,GFXMMU LUT entry 603 low" hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2DC "GFXMMU_LUT603H,GFXMMU LUT entry 603 high" hexmask.long.tbyte 0x2DC 4.--21. 1. "LO,Line offset" line.long 0x2E0 "GFXMMU_LUT604L,GFXMMU LUT entry 604 low" hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2E4 "GFXMMU_LUT604H,GFXMMU LUT entry 604 high" hexmask.long.tbyte 0x2E4 4.--21. 1. "LO,Line offset" line.long 0x2E8 "GFXMMU_LUT605L,GFXMMU LUT entry 605 low" hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2EC "GFXMMU_LUT605H,GFXMMU LUT entry 605 high" hexmask.long.tbyte 0x2EC 4.--21. 1. "LO,Line offset" line.long 0x2F0 "GFXMMU_LUT606L,GFXMMU LUT entry 606 low" hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2F4 "GFXMMU_LUT606H,GFXMMU LUT entry 606 high" hexmask.long.tbyte 0x2F4 4.--21. 1. "LO,Line offset" line.long 0x2F8 "GFXMMU_LUT607L,GFXMMU LUT entry 607 low" hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2FC "GFXMMU_LUT607H,GFXMMU LUT entry 607 high" hexmask.long.tbyte 0x2FC 4.--21. 1. "LO,Line offset" line.long 0x300 "GFXMMU_LUT608L,GFXMMU LUT entry 608 low" hexmask.long.byte 0x300 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x300 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x304 "GFXMMU_LUT608H,GFXMMU LUT entry 608 high" hexmask.long.tbyte 0x304 4.--21. 1. "LO,Line offset" line.long 0x308 "GFXMMU_LUT609L,GFXMMU LUT entry 609 low" hexmask.long.byte 0x308 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x308 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x30C "GFXMMU_LUT609H,GFXMMU LUT entry 609 high" hexmask.long.tbyte 0x30C 4.--21. 1. "LO,Line offset" line.long 0x310 "GFXMMU_LUT610L,GFXMMU LUT entry 610 low" hexmask.long.byte 0x310 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x310 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x314 "GFXMMU_LUT610H,GFXMMU LUT entry 610 high" hexmask.long.tbyte 0x314 4.--21. 1. "LO,Line offset" line.long 0x318 "GFXMMU_LUT611L,GFXMMU LUT entry 611 low" hexmask.long.byte 0x318 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x318 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x31C "GFXMMU_LUT611H,GFXMMU LUT entry 611 high" hexmask.long.tbyte 0x31C 4.--21. 1. "LO,Line offset" line.long 0x320 "GFXMMU_LUT612L,GFXMMU LUT entry 612 low" hexmask.long.byte 0x320 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x320 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x324 "GFXMMU_LUT612H,GFXMMU LUT entry 612 high" hexmask.long.tbyte 0x324 4.--21. 1. "LO,Line offset" line.long 0x328 "GFXMMU_LUT613L,GFXMMU LUT entry 613 low" hexmask.long.byte 0x328 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x328 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x32C "GFXMMU_LUT613H,GFXMMU LUT entry 613 high" hexmask.long.tbyte 0x32C 4.--21. 1. "LO,Line offset" line.long 0x330 "GFXMMU_LUT614L,GFXMMU LUT entry 614 low" hexmask.long.byte 0x330 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x330 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x334 "GFXMMU_LUT614H,GFXMMU LUT entry 614 high" hexmask.long.tbyte 0x334 4.--21. 1. "LO,Line offset" line.long 0x338 "GFXMMU_LUT615L,GFXMMU LUT entry 615 low" hexmask.long.byte 0x338 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x338 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x33C "GFXMMU_LUT615H,GFXMMU LUT entry 615 high" hexmask.long.tbyte 0x33C 4.--21. 1. "LO,Line offset" line.long 0x340 "GFXMMU_LUT616L,GFXMMU LUT entry 616 low" hexmask.long.byte 0x340 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x340 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x344 "GFXMMU_LUT616H,GFXMMU LUT entry 616 high" hexmask.long.tbyte 0x344 4.--21. 1. "LO,Line offset" line.long 0x348 "GFXMMU_LUT617L,GFXMMU LUT entry 617 low" hexmask.long.byte 0x348 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x348 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34C "GFXMMU_LUT617H,GFXMMU LUT entry 617 high" hexmask.long.tbyte 0x34C 4.--21. 1. "LO,Line offset" line.long 0x350 "GFXMMU_LUT618L,GFXMMU LUT entry 618 low" hexmask.long.byte 0x350 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x350 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x354 "GFXMMU_LUT618H,GFXMMU LUT entry 618 high" hexmask.long.tbyte 0x354 4.--21. 1. "LO,Line offset" line.long 0x358 "GFXMMU_LUT619L,GFXMMU LUT entry 619 low" hexmask.long.byte 0x358 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x358 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x35C "GFXMMU_LUT619H,GFXMMU LUT entry 619 high" hexmask.long.tbyte 0x35C 4.--21. 1. "LO,Line offset" line.long 0x360 "GFXMMU_LUT620L,GFXMMU LUT entry 620 low" hexmask.long.byte 0x360 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x360 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x364 "GFXMMU_LUT620H,GFXMMU LUT entry 620 high" hexmask.long.tbyte 0x364 4.--21. 1. "LO,Line offset" line.long 0x368 "GFXMMU_LUT621L,GFXMMU LUT entry 621 low" hexmask.long.byte 0x368 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x368 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x36C "GFXMMU_LUT621H,GFXMMU LUT entry 621 high" hexmask.long.tbyte 0x36C 4.--21. 1. "LO,Line offset" line.long 0x370 "GFXMMU_LUT622L,GFXMMU LUT entry 622 low" hexmask.long.byte 0x370 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x370 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x374 "GFXMMU_LUT622H,GFXMMU LUT entry 622 high" hexmask.long.tbyte 0x374 4.--21. 1. "LO,Line offset" line.long 0x378 "GFXMMU_LUT623L,GFXMMU LUT entry 623 low" hexmask.long.byte 0x378 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x378 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x37C "GFXMMU_LUT623H,GFXMMU LUT entry 623 high" hexmask.long.tbyte 0x37C 4.--21. 1. "LO,Line offset" line.long 0x380 "GFXMMU_LUT624L,GFXMMU LUT entry 624 low" hexmask.long.byte 0x380 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x380 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x384 "GFXMMU_LUT624H,GFXMMU LUT entry 624 high" hexmask.long.tbyte 0x384 4.--21. 1. "LO,Line offset" line.long 0x388 "GFXMMU_LUT625L,GFXMMU LUT entry 625 low" hexmask.long.byte 0x388 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x388 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x38C "GFXMMU_LUT625H,GFXMMU LUT entry 625 high" hexmask.long.tbyte 0x38C 4.--21. 1. "LO,Line offset" line.long 0x390 "GFXMMU_LUT626L,GFXMMU LUT entry 626 low" hexmask.long.byte 0x390 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x390 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x394 "GFXMMU_LUT626H,GFXMMU LUT entry 626 high" hexmask.long.tbyte 0x394 4.--21. 1. "LO,Line offset" line.long 0x398 "GFXMMU_LUT627L,GFXMMU LUT entry 627 low" hexmask.long.byte 0x398 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x398 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x39C "GFXMMU_LUT627H,GFXMMU LUT entry 627 high" hexmask.long.tbyte 0x39C 4.--21. 1. "LO,Line offset" line.long 0x3A0 "GFXMMU_LUT628L,GFXMMU LUT entry 628 low" hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3A4 "GFXMMU_LUT628H,GFXMMU LUT entry 628 high" hexmask.long.tbyte 0x3A4 4.--21. 1. "LO,Line offset" line.long 0x3A8 "GFXMMU_LUT629L,GFXMMU LUT entry 629 low" hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3AC "GFXMMU_LUT629H,GFXMMU LUT entry 629 high" hexmask.long.tbyte 0x3AC 4.--21. 1. "LO,Line offset" line.long 0x3B0 "GFXMMU_LUT630L,GFXMMU LUT entry 630 low" hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3B4 "GFXMMU_LUT630H,GFXMMU LUT entry 630 high" hexmask.long.tbyte 0x3B4 4.--21. 1. "LO,Line offset" line.long 0x3B8 "GFXMMU_LUT631L,GFXMMU LUT entry 631 low" hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3BC "GFXMMU_LUT631H,GFXMMU LUT entry 631 high" hexmask.long.tbyte 0x3BC 4.--21. 1. "LO,Line offset" line.long 0x3C0 "GFXMMU_LUT632L,GFXMMU LUT entry 632 low" hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C4 "GFXMMU_LUT632H,GFXMMU LUT entry 632 high" hexmask.long.tbyte 0x3C4 4.--21. 1. "LO,Line offset" line.long 0x3C8 "GFXMMU_LUT633L,GFXMMU LUT entry 633 low" hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3CC "GFXMMU_LUT633H,GFXMMU LUT entry 633 high" hexmask.long.tbyte 0x3CC 4.--21. 1. "LO,Line offset" line.long 0x3D0 "GFXMMU_LUT634L,GFXMMU LUT entry 634 low" hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3D4 "GFXMMU_LUT634H,GFXMMU LUT entry 634 high" hexmask.long.tbyte 0x3D4 4.--21. 1. "LO,Line offset" line.long 0x3D8 "GFXMMU_LUT635L,GFXMMU LUT entry 635 low" hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3DC "GFXMMU_LUT635H,GFXMMU LUT entry 635 high" hexmask.long.tbyte 0x3DC 4.--21. 1. "LO,Line offset" line.long 0x3E0 "GFXMMU_LUT636L,GFXMMU LUT entry 636 low" hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3E4 "GFXMMU_LUT636H,GFXMMU LUT entry 636 high" hexmask.long.tbyte 0x3E4 4.--21. 1. "LO,Line offset" line.long 0x3E8 "GFXMMU_LUT637L,GFXMMU LUT entry 637 low" hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3EC "GFXMMU_LUT637H,GFXMMU LUT entry 637 high" hexmask.long.tbyte 0x3EC 4.--21. 1. "LO,Line offset" line.long 0x3F0 "GFXMMU_LUT638L,GFXMMU LUT entry 638 low" hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3F4 "GFXMMU_LUT638H,GFXMMU LUT entry 638 high" hexmask.long.tbyte 0x3F4 4.--21. 1. "LO,Line offset" line.long 0x3F8 "GFXMMU_LUT639L,GFXMMU LUT entry 639 low" hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3FC "GFXMMU_LUT639H,GFXMMU LUT entry 639 high" hexmask.long.tbyte 0x3FC 4.--21. 1. "LO,Line offset" line.long 0x400 "GFXMMU_LUT640L,GFXMMU LUT entry 640 low" hexmask.long.byte 0x400 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x400 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x404 "GFXMMU_LUT640H,GFXMMU LUT entry 640 high" hexmask.long.tbyte 0x404 4.--21. 1. "LO,Line offset" line.long 0x408 "GFXMMU_LUT641L,GFXMMU LUT entry 641 low" hexmask.long.byte 0x408 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x408 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x40C "GFXMMU_LUT641H,GFXMMU LUT entry 641 high" hexmask.long.tbyte 0x40C 4.--21. 1. "LO,Line offset" line.long 0x410 "GFXMMU_LUT642L,GFXMMU LUT entry 642 low" hexmask.long.byte 0x410 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x410 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x414 "GFXMMU_LUT642H,GFXMMU LUT entry 642 high" hexmask.long.tbyte 0x414 4.--21. 1. "LO,Line offset" line.long 0x418 "GFXMMU_LUT643L,GFXMMU LUT entry 643 low" hexmask.long.byte 0x418 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x418 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x41C "GFXMMU_LUT643H,GFXMMU LUT entry 643 high" hexmask.long.tbyte 0x41C 4.--21. 1. "LO,Line offset" line.long 0x420 "GFXMMU_LUT644L,GFXMMU LUT entry 644 low" hexmask.long.byte 0x420 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x420 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x424 "GFXMMU_LUT644H,GFXMMU LUT entry 644 high" hexmask.long.tbyte 0x424 4.--21. 1. "LO,Line offset" line.long 0x428 "GFXMMU_LUT645L,GFXMMU LUT entry 645 low" hexmask.long.byte 0x428 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x428 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x42C "GFXMMU_LUT645H,GFXMMU LUT entry 645 high" hexmask.long.tbyte 0x42C 4.--21. 1. "LO,Line offset" line.long 0x430 "GFXMMU_LUT646L,GFXMMU LUT entry 646 low" hexmask.long.byte 0x430 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x430 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x434 "GFXMMU_LUT646H,GFXMMU LUT entry 646 high" hexmask.long.tbyte 0x434 4.--21. 1. "LO,Line offset" line.long 0x438 "GFXMMU_LUT647L,GFXMMU LUT entry 647 low" hexmask.long.byte 0x438 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x438 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x43C "GFXMMU_LUT647H,GFXMMU LUT entry 647 high" hexmask.long.tbyte 0x43C 4.--21. 1. "LO,Line offset" line.long 0x440 "GFXMMU_LUT648L,GFXMMU LUT entry 648 low" hexmask.long.byte 0x440 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x440 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x444 "GFXMMU_LUT648H,GFXMMU LUT entry 648 high" hexmask.long.tbyte 0x444 4.--21. 1. "LO,Line offset" line.long 0x448 "GFXMMU_LUT649L,GFXMMU LUT entry 649 low" hexmask.long.byte 0x448 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x448 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44C "GFXMMU_LUT649H,GFXMMU LUT entry 649 high" hexmask.long.tbyte 0x44C 4.--21. 1. "LO,Line offset" line.long 0x450 "GFXMMU_LUT650L,GFXMMU LUT entry 650 low" hexmask.long.byte 0x450 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x450 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x454 "GFXMMU_LUT650H,GFXMMU LUT entry 650 high" hexmask.long.tbyte 0x454 4.--21. 1. "LO,Line offset" line.long 0x458 "GFXMMU_LUT651L,GFXMMU LUT entry 651 low" hexmask.long.byte 0x458 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x458 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x45C "GFXMMU_LUT651H,GFXMMU LUT entry 651 high" hexmask.long.tbyte 0x45C 4.--21. 1. "LO,Line offset" line.long 0x460 "GFXMMU_LUT652L,GFXMMU LUT entry 652 low" hexmask.long.byte 0x460 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x460 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x464 "GFXMMU_LUT652H,GFXMMU LUT entry 652 high" hexmask.long.tbyte 0x464 4.--21. 1. "LO,Line offset" line.long 0x468 "GFXMMU_LUT653L,GFXMMU LUT entry 653 low" hexmask.long.byte 0x468 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x468 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x46C "GFXMMU_LUT653H,GFXMMU LUT entry 653 high" hexmask.long.tbyte 0x46C 4.--21. 1. "LO,Line offset" line.long 0x470 "GFXMMU_LUT654L,GFXMMU LUT entry 654 low" hexmask.long.byte 0x470 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x470 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x474 "GFXMMU_LUT654H,GFXMMU LUT entry 654 high" hexmask.long.tbyte 0x474 4.--21. 1. "LO,Line offset" line.long 0x478 "GFXMMU_LUT655L,GFXMMU LUT entry 655 low" hexmask.long.byte 0x478 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x478 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x47C "GFXMMU_LUT655H,GFXMMU LUT entry 655 high" hexmask.long.tbyte 0x47C 4.--21. 1. "LO,Line offset" line.long 0x480 "GFXMMU_LUT656L,GFXMMU LUT entry 656 low" hexmask.long.byte 0x480 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x480 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x484 "GFXMMU_LUT656H,GFXMMU LUT entry 656 high" hexmask.long.tbyte 0x484 4.--21. 1. "LO,Line offset" line.long 0x488 "GFXMMU_LUT657L,GFXMMU LUT entry 657 low" hexmask.long.byte 0x488 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x488 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x48C "GFXMMU_LUT657H,GFXMMU LUT entry 657 high" hexmask.long.tbyte 0x48C 4.--21. 1. "LO,Line offset" line.long 0x490 "GFXMMU_LUT658L,GFXMMU LUT entry 658 low" hexmask.long.byte 0x490 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x490 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x494 "GFXMMU_LUT658H,GFXMMU LUT entry 658 high" hexmask.long.tbyte 0x494 4.--21. 1. "LO,Line offset" line.long 0x498 "GFXMMU_LUT659L,GFXMMU LUT entry 659 low" hexmask.long.byte 0x498 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x498 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x49C "GFXMMU_LUT659H,GFXMMU LUT entry 659 high" hexmask.long.tbyte 0x49C 4.--21. 1. "LO,Line offset" line.long 0x4A0 "GFXMMU_LUT660L,GFXMMU LUT entry 660 low" hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4A4 "GFXMMU_LUT660H,GFXMMU LUT entry 660 high" hexmask.long.tbyte 0x4A4 4.--21. 1. "LO,Line offset" line.long 0x4A8 "GFXMMU_LUT661L,GFXMMU LUT entry 661 low" hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4AC "GFXMMU_LUT661H,GFXMMU LUT entry 661 high" hexmask.long.tbyte 0x4AC 4.--21. 1. "LO,Line offset" line.long 0x4B0 "GFXMMU_LUT662L,GFXMMU LUT entry 662 low" hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4B4 "GFXMMU_LUT662H,GFXMMU LUT entry 662 high" hexmask.long.tbyte 0x4B4 4.--21. 1. "LO,Line offset" line.long 0x4B8 "GFXMMU_LUT663L,GFXMMU LUT entry 663 low" hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4BC "GFXMMU_LUT663H,GFXMMU LUT entry 663 high" hexmask.long.tbyte 0x4BC 4.--21. 1. "LO,Line offset" line.long 0x4C0 "GFXMMU_LUT664L,GFXMMU LUT entry 664 low" hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C4 "GFXMMU_LUT664H,GFXMMU LUT entry 664 high" hexmask.long.tbyte 0x4C4 4.--21. 1. "LO,Line offset" line.long 0x4C8 "GFXMMU_LUT665L,GFXMMU LUT entry 665 low" hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4CC "GFXMMU_LUT665H,GFXMMU LUT entry 665 high" hexmask.long.tbyte 0x4CC 4.--21. 1. "LO,Line offset" line.long 0x4D0 "GFXMMU_LUT666L,GFXMMU LUT entry 666 low" hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4D4 "GFXMMU_LUT666H,GFXMMU LUT entry 666 high" hexmask.long.tbyte 0x4D4 4.--21. 1. "LO,Line offset" line.long 0x4D8 "GFXMMU_LUT667L,GFXMMU LUT entry 667 low" hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4DC "GFXMMU_LUT667H,GFXMMU LUT entry 667 high" hexmask.long.tbyte 0x4DC 4.--21. 1. "LO,Line offset" line.long 0x4E0 "GFXMMU_LUT668L,GFXMMU LUT entry 668 low" hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4E4 "GFXMMU_LUT668H,GFXMMU LUT entry 668 high" hexmask.long.tbyte 0x4E4 4.--21. 1. "LO,Line offset" line.long 0x4E8 "GFXMMU_LUT669L,GFXMMU LUT entry 669 low" hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4EC "GFXMMU_LUT669H,GFXMMU LUT entry 669 high" hexmask.long.tbyte 0x4EC 4.--21. 1. "LO,Line offset" line.long 0x4F0 "GFXMMU_LUT670L,GFXMMU LUT entry 670 low" hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4F4 "GFXMMU_LUT670H,GFXMMU LUT entry 670 high" hexmask.long.tbyte 0x4F4 4.--21. 1. "LO,Line offset" line.long 0x4F8 "GFXMMU_LUT671L,GFXMMU LUT entry 671 low" hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4FC "GFXMMU_LUT671H,GFXMMU LUT entry 671 high" hexmask.long.tbyte 0x4FC 4.--21. 1. "LO,Line offset" line.long 0x500 "GFXMMU_LUT672L,GFXMMU LUT entry 672 low" hexmask.long.byte 0x500 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x500 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x504 "GFXMMU_LUT672H,GFXMMU LUT entry 672 high" hexmask.long.tbyte 0x504 4.--21. 1. "LO,Line offset" line.long 0x508 "GFXMMU_LUT673L,GFXMMU LUT entry 673 low" hexmask.long.byte 0x508 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x508 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x50C "GFXMMU_LUT673H,GFXMMU LUT entry 673 high" hexmask.long.tbyte 0x50C 4.--21. 1. "LO,Line offset" line.long 0x510 "GFXMMU_LUT674L,GFXMMU LUT entry 674 low" hexmask.long.byte 0x510 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x510 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x514 "GFXMMU_LUT674H,GFXMMU LUT entry 674 high" hexmask.long.tbyte 0x514 4.--21. 1. "LO,Line offset" line.long 0x518 "GFXMMU_LUT675L,GFXMMU LUT entry 675 low" hexmask.long.byte 0x518 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x518 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x51C "GFXMMU_LUT675H,GFXMMU LUT entry 675 high" hexmask.long.tbyte 0x51C 4.--21. 1. "LO,Line offset" line.long 0x520 "GFXMMU_LUT676L,GFXMMU LUT entry 676 low" hexmask.long.byte 0x520 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x520 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x524 "GFXMMU_LUT676H,GFXMMU LUT entry 676 high" hexmask.long.tbyte 0x524 4.--21. 1. "LO,Line offset" line.long 0x528 "GFXMMU_LUT677L,GFXMMU LUT entry 677 low" hexmask.long.byte 0x528 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x528 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x52C "GFXMMU_LUT677H,GFXMMU LUT entry 677 high" hexmask.long.tbyte 0x52C 4.--21. 1. "LO,Line offset" line.long 0x530 "GFXMMU_LUT678L,GFXMMU LUT entry 678 low" hexmask.long.byte 0x530 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x530 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x534 "GFXMMU_LUT678H,GFXMMU LUT entry 678 high" hexmask.long.tbyte 0x534 4.--21. 1. "LO,Line offset" line.long 0x538 "GFXMMU_LUT679L,GFXMMU LUT entry 679 low" hexmask.long.byte 0x538 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x538 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x53C "GFXMMU_LUT679H,GFXMMU LUT entry 679 high" hexmask.long.tbyte 0x53C 4.--21. 1. "LO,Line offset" line.long 0x540 "GFXMMU_LUT680L,GFXMMU LUT entry 680 low" hexmask.long.byte 0x540 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x540 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x544 "GFXMMU_LUT680H,GFXMMU LUT entry 680 high" hexmask.long.tbyte 0x544 4.--21. 1. "LO,Line offset" line.long 0x548 "GFXMMU_LUT681L,GFXMMU LUT entry 681 low" hexmask.long.byte 0x548 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x548 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54C "GFXMMU_LUT681H,GFXMMU LUT entry 681 high" hexmask.long.tbyte 0x54C 4.--21. 1. "LO,Line offset" line.long 0x550 "GFXMMU_LUT682L,GFXMMU LUT entry 682 low" hexmask.long.byte 0x550 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x550 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x554 "GFXMMU_LUT682H,GFXMMU LUT entry 682 high" hexmask.long.tbyte 0x554 4.--21. 1. "LO,Line offset" line.long 0x558 "GFXMMU_LUT683L,GFXMMU LUT entry 683 low" hexmask.long.byte 0x558 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x558 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x55C "GFXMMU_LUT683H,GFXMMU LUT entry 683 high" hexmask.long.tbyte 0x55C 4.--21. 1. "LO,Line offset" line.long 0x560 "GFXMMU_LUT684L,GFXMMU LUT entry 684 low" hexmask.long.byte 0x560 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x560 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x564 "GFXMMU_LUT684H,GFXMMU LUT entry 684 high" hexmask.long.tbyte 0x564 4.--21. 1. "LO,Line offset" line.long 0x568 "GFXMMU_LUT685L,GFXMMU LUT entry 685 low" hexmask.long.byte 0x568 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x568 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x56C "GFXMMU_LUT685H,GFXMMU LUT entry 685 high" hexmask.long.tbyte 0x56C 4.--21. 1. "LO,Line offset" line.long 0x570 "GFXMMU_LUT686L,GFXMMU LUT entry 686 low" hexmask.long.byte 0x570 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x570 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x574 "GFXMMU_LUT686H,GFXMMU LUT entry 686 high" hexmask.long.tbyte 0x574 4.--21. 1. "LO,Line offset" line.long 0x578 "GFXMMU_LUT687L,GFXMMU LUT entry 687 low" hexmask.long.byte 0x578 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x578 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x57C "GFXMMU_LUT687H,GFXMMU LUT entry 687 high" hexmask.long.tbyte 0x57C 4.--21. 1. "LO,Line offset" line.long 0x580 "GFXMMU_LUT688L,GFXMMU LUT entry 688 low" hexmask.long.byte 0x580 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x580 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x584 "GFXMMU_LUT688H,GFXMMU LUT entry 688 high" hexmask.long.tbyte 0x584 4.--21. 1. "LO,Line offset" line.long 0x588 "GFXMMU_LUT689L,GFXMMU LUT entry 689 low" hexmask.long.byte 0x588 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x588 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x58C "GFXMMU_LUT689H,GFXMMU LUT entry 689 high" hexmask.long.tbyte 0x58C 4.--21. 1. "LO,Line offset" line.long 0x590 "GFXMMU_LUT690L,GFXMMU LUT entry 690 low" hexmask.long.byte 0x590 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x590 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x594 "GFXMMU_LUT690H,GFXMMU LUT entry 690 high" hexmask.long.tbyte 0x594 4.--21. 1. "LO,Line offset" line.long 0x598 "GFXMMU_LUT691L,GFXMMU LUT entry 691 low" hexmask.long.byte 0x598 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x598 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x59C "GFXMMU_LUT691H,GFXMMU LUT entry 691 high" hexmask.long.tbyte 0x59C 4.--21. 1. "LO,Line offset" line.long 0x5A0 "GFXMMU_LUT692L,GFXMMU LUT entry 692 low" hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5A4 "GFXMMU_LUT692H,GFXMMU LUT entry 692 high" hexmask.long.tbyte 0x5A4 4.--21. 1. "LO,Line offset" line.long 0x5A8 "GFXMMU_LUT693L,GFXMMU LUT entry 693 low" hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5AC "GFXMMU_LUT693H,GFXMMU LUT entry 693 high" hexmask.long.tbyte 0x5AC 4.--21. 1. "LO,Line offset" line.long 0x5B0 "GFXMMU_LUT694L,GFXMMU LUT entry 694 low" hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5B4 "GFXMMU_LUT694H,GFXMMU LUT entry 694 high" hexmask.long.tbyte 0x5B4 4.--21. 1. "LO,Line offset" line.long 0x5B8 "GFXMMU_LUT695L,GFXMMU LUT entry 695 low" hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5BC "GFXMMU_LUT695H,GFXMMU LUT entry 695 high" hexmask.long.tbyte 0x5BC 4.--21. 1. "LO,Line offset" line.long 0x5C0 "GFXMMU_LUT696L,GFXMMU LUT entry 696 low" hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C4 "GFXMMU_LUT696H,GFXMMU LUT entry 696 high" hexmask.long.tbyte 0x5C4 4.--21. 1. "LO,Line offset" line.long 0x5C8 "GFXMMU_LUT697L,GFXMMU LUT entry 697 low" hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5CC "GFXMMU_LUT697H,GFXMMU LUT entry 697 high" hexmask.long.tbyte 0x5CC 4.--21. 1. "LO,Line offset" line.long 0x5D0 "GFXMMU_LUT698L,GFXMMU LUT entry 698 low" hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5D4 "GFXMMU_LUT698H,GFXMMU LUT entry 698 high" hexmask.long.tbyte 0x5D4 4.--21. 1. "LO,Line offset" line.long 0x5D8 "GFXMMU_LUT699L,GFXMMU LUT entry 699 low" hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5DC "GFXMMU_LUT699H,GFXMMU LUT entry 699 high" hexmask.long.tbyte 0x5DC 4.--21. 1. "LO,Line offset" line.long 0x5E0 "GFXMMU_LUT700L,GFXMMU LUT entry 700 low" hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5E4 "GFXMMU_LUT700H,GFXMMU LUT entry 700 high" hexmask.long.tbyte 0x5E4 4.--21. 1. "LO,Line offset" line.long 0x5E8 "GFXMMU_LUT701L,GFXMMU LUT entry 701 low" hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5EC "GFXMMU_LUT701H,GFXMMU LUT entry 701 high" hexmask.long.tbyte 0x5EC 4.--21. 1. "LO,Line offset" line.long 0x5F0 "GFXMMU_LUT702L,GFXMMU LUT entry 702 low" hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5F4 "GFXMMU_LUT702H,GFXMMU LUT entry 702 high" hexmask.long.tbyte 0x5F4 4.--21. 1. "LO,Line offset" line.long 0x5F8 "GFXMMU_LUT703L,GFXMMU LUT entry 703 low" hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5FC "GFXMMU_LUT703H,GFXMMU LUT entry 703 high" hexmask.long.tbyte 0x5FC 4.--21. 1. "LO,Line offset" line.long 0x600 "GFXMMU_LUT704L,GFXMMU LUT entry 704 low" hexmask.long.byte 0x600 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x600 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x604 "GFXMMU_LUT704H,GFXMMU LUT entry 704 high" hexmask.long.tbyte 0x604 4.--21. 1. "LO,Line offset" line.long 0x608 "GFXMMU_LUT705L,GFXMMU LUT entry 705 low" hexmask.long.byte 0x608 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x608 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x60C "GFXMMU_LUT705H,GFXMMU LUT entry 705 high" hexmask.long.tbyte 0x60C 4.--21. 1. "LO,Line offset" line.long 0x610 "GFXMMU_LUT706L,GFXMMU LUT entry 706 low" hexmask.long.byte 0x610 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x610 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x614 "GFXMMU_LUT706H,GFXMMU LUT entry 706 high" hexmask.long.tbyte 0x614 4.--21. 1. "LO,Line offset" line.long 0x618 "GFXMMU_LUT707L,GFXMMU LUT entry 707 low" hexmask.long.byte 0x618 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x618 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x61C "GFXMMU_LUT707H,GFXMMU LUT entry 707 high" hexmask.long.tbyte 0x61C 4.--21. 1. "LO,Line offset" line.long 0x620 "GFXMMU_LUT708L,GFXMMU LUT entry 708 low" hexmask.long.byte 0x620 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x620 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x624 "GFXMMU_LUT708H,GFXMMU LUT entry 708 high" hexmask.long.tbyte 0x624 4.--21. 1. "LO,Line offset" line.long 0x628 "GFXMMU_LUT709L,GFXMMU LUT entry 709 low" hexmask.long.byte 0x628 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x628 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x62C "GFXMMU_LUT709H,GFXMMU LUT entry 709 high" hexmask.long.tbyte 0x62C 4.--21. 1. "LO,Line offset" line.long 0x630 "GFXMMU_LUT710L,GFXMMU LUT entry 710 low" hexmask.long.byte 0x630 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x630 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x634 "GFXMMU_LUT710H,GFXMMU LUT entry 710 high" hexmask.long.tbyte 0x634 4.--21. 1. "LO,Line offset" line.long 0x638 "GFXMMU_LUT711L,GFXMMU LUT entry 711 low" hexmask.long.byte 0x638 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x638 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x63C "GFXMMU_LUT711H,GFXMMU LUT entry 711 high" hexmask.long.tbyte 0x63C 4.--21. 1. "LO,Line offset" line.long 0x640 "GFXMMU_LUT712L,GFXMMU LUT entry 712 low" hexmask.long.byte 0x640 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x640 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x644 "GFXMMU_LUT712H,GFXMMU LUT entry 712 high" hexmask.long.tbyte 0x644 4.--21. 1. "LO,Line offset" line.long 0x648 "GFXMMU_LUT713L,GFXMMU LUT entry 713 low" hexmask.long.byte 0x648 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x648 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64C "GFXMMU_LUT713H,GFXMMU LUT entry 713 high" hexmask.long.tbyte 0x64C 4.--21. 1. "LO,Line offset" line.long 0x650 "GFXMMU_LUT714L,GFXMMU LUT entry 714 low" hexmask.long.byte 0x650 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x650 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x654 "GFXMMU_LUT714H,GFXMMU LUT entry 714 high" hexmask.long.tbyte 0x654 4.--21. 1. "LO,Line offset" line.long 0x658 "GFXMMU_LUT715L,GFXMMU LUT entry 715 low" hexmask.long.byte 0x658 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x658 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x65C "GFXMMU_LUT715H,GFXMMU LUT entry 715 high" hexmask.long.tbyte 0x65C 4.--21. 1. "LO,Line offset" line.long 0x660 "GFXMMU_LUT716L,GFXMMU LUT entry 716 low" hexmask.long.byte 0x660 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x660 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x664 "GFXMMU_LUT716H,GFXMMU LUT entry 716 high" hexmask.long.tbyte 0x664 4.--21. 1. "LO,Line offset" line.long 0x668 "GFXMMU_LUT717L,GFXMMU LUT entry 717 low" hexmask.long.byte 0x668 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x668 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x66C "GFXMMU_LUT717H,GFXMMU LUT entry 717 high" hexmask.long.tbyte 0x66C 4.--21. 1. "LO,Line offset" line.long 0x670 "GFXMMU_LUT718L,GFXMMU LUT entry 718 low" hexmask.long.byte 0x670 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x670 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x674 "GFXMMU_LUT718H,GFXMMU LUT entry 718 high" hexmask.long.tbyte 0x674 4.--21. 1. "LO,Line offset" line.long 0x678 "GFXMMU_LUT719L,GFXMMU LUT entry 719 low" hexmask.long.byte 0x678 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x678 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x67C "GFXMMU_LUT719H,GFXMMU LUT entry 719 high" hexmask.long.tbyte 0x67C 4.--21. 1. "LO,Line offset" line.long 0x680 "GFXMMU_LUT720L,GFXMMU LUT entry 720 low" hexmask.long.byte 0x680 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x680 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x684 "GFXMMU_LUT720H,GFXMMU LUT entry 720 high" hexmask.long.tbyte 0x684 4.--21. 1. "LO,Line offset" line.long 0x688 "GFXMMU_LUT721L,GFXMMU LUT entry 721 low" hexmask.long.byte 0x688 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x688 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x68C "GFXMMU_LUT721H,GFXMMU LUT entry 721 high" hexmask.long.tbyte 0x68C 4.--21. 1. "LO,Line offset" line.long 0x690 "GFXMMU_LUT722L,GFXMMU LUT entry 722 low" hexmask.long.byte 0x690 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x690 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x694 "GFXMMU_LUT722H,GFXMMU LUT entry 722 high" hexmask.long.tbyte 0x694 4.--21. 1. "LO,Line offset" line.long 0x698 "GFXMMU_LUT723L,GFXMMU LUT entry 723 low" hexmask.long.byte 0x698 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x698 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x69C "GFXMMU_LUT723H,GFXMMU LUT entry 723 high" hexmask.long.tbyte 0x69C 4.--21. 1. "LO,Line offset" line.long 0x6A0 "GFXMMU_LUT724L,GFXMMU LUT entry 724 low" hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6A4 "GFXMMU_LUT724H,GFXMMU LUT entry 724 high" hexmask.long.tbyte 0x6A4 4.--21. 1. "LO,Line offset" line.long 0x6A8 "GFXMMU_LUT725L,GFXMMU LUT entry 725 low" hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6AC "GFXMMU_LUT725H,GFXMMU LUT entry 725 high" hexmask.long.tbyte 0x6AC 4.--21. 1. "LO,Line offset" line.long 0x6B0 "GFXMMU_LUT726L,GFXMMU LUT entry 726 low" hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6B4 "GFXMMU_LUT726H,GFXMMU LUT entry 726 high" hexmask.long.tbyte 0x6B4 4.--21. 1. "LO,Line offset" line.long 0x6B8 "GFXMMU_LUT727L,GFXMMU LUT entry 727 low" hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6BC "GFXMMU_LUT727H,GFXMMU LUT entry 727 high" hexmask.long.tbyte 0x6BC 4.--21. 1. "LO,Line offset" line.long 0x6C0 "GFXMMU_LUT728L,GFXMMU LUT entry 728 low" hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C4 "GFXMMU_LUT728H,GFXMMU LUT entry 728 high" hexmask.long.tbyte 0x6C4 4.--21. 1. "LO,Line offset" line.long 0x6C8 "GFXMMU_LUT729L,GFXMMU LUT entry 729 low" hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6CC "GFXMMU_LUT729H,GFXMMU LUT entry 729 high" hexmask.long.tbyte 0x6CC 4.--21. 1. "LO,Line offset" line.long 0x6D0 "GFXMMU_LUT730L,GFXMMU LUT entry 730 low" hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6D4 "GFXMMU_LUT730H,GFXMMU LUT entry 730 high" hexmask.long.tbyte 0x6D4 4.--21. 1. "LO,Line offset" line.long 0x6D8 "GFXMMU_LUT731L,GFXMMU LUT entry 731 low" hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6DC "GFXMMU_LUT731H,GFXMMU LUT entry 731 high" hexmask.long.tbyte 0x6DC 4.--21. 1. "LO,Line offset" line.long 0x6E0 "GFXMMU_LUT732L,GFXMMU LUT entry 732 low" hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6E4 "GFXMMU_LUT732H,GFXMMU LUT entry 732 high" hexmask.long.tbyte 0x6E4 4.--21. 1. "LO,Line offset" line.long 0x6E8 "GFXMMU_LUT733L,GFXMMU LUT entry 733 low" hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6EC "GFXMMU_LUT733H,GFXMMU LUT entry 733 high" hexmask.long.tbyte 0x6EC 4.--21. 1. "LO,Line offset" line.long 0x6F0 "GFXMMU_LUT734L,GFXMMU LUT entry 734 low" hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6F4 "GFXMMU_LUT734H,GFXMMU LUT entry 734 high" hexmask.long.tbyte 0x6F4 4.--21. 1. "LO,Line offset" line.long 0x6F8 "GFXMMU_LUT735L,GFXMMU LUT entry 735 low" hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6FC "GFXMMU_LUT735H,GFXMMU LUT entry 735 high" hexmask.long.tbyte 0x6FC 4.--21. 1. "LO,Line offset" line.long 0x700 "GFXMMU_LUT736L,GFXMMU LUT entry 736 low" hexmask.long.byte 0x700 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x700 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x704 "GFXMMU_LUT736H,GFXMMU LUT entry 736 high" hexmask.long.tbyte 0x704 4.--21. 1. "LO,Line offset" line.long 0x708 "GFXMMU_LUT737L,GFXMMU LUT entry 737 low" hexmask.long.byte 0x708 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x708 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x70C "GFXMMU_LUT737H,GFXMMU LUT entry 737 high" hexmask.long.tbyte 0x70C 4.--21. 1. "LO,Line offset" line.long 0x710 "GFXMMU_LUT738L,GFXMMU LUT entry 738 low" hexmask.long.byte 0x710 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x710 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x714 "GFXMMU_LUT738H,GFXMMU LUT entry 738 high" hexmask.long.tbyte 0x714 4.--21. 1. "LO,Line offset" line.long 0x718 "GFXMMU_LUT739L,GFXMMU LUT entry 739 low" hexmask.long.byte 0x718 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x718 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x71C "GFXMMU_LUT739H,GFXMMU LUT entry 739 high" hexmask.long.tbyte 0x71C 4.--21. 1. "LO,Line offset" line.long 0x720 "GFXMMU_LUT740L,GFXMMU LUT entry 740 low" hexmask.long.byte 0x720 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x720 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x724 "GFXMMU_LUT740H,GFXMMU LUT entry 740 high" hexmask.long.tbyte 0x724 4.--21. 1. "LO,Line offset" line.long 0x728 "GFXMMU_LUT741L,GFXMMU LUT entry 741 low" hexmask.long.byte 0x728 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x728 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x72C "GFXMMU_LUT741H,GFXMMU LUT entry 741 high" hexmask.long.tbyte 0x72C 4.--21. 1. "LO,Line offset" line.long 0x730 "GFXMMU_LUT742L,GFXMMU LUT entry 742 low" hexmask.long.byte 0x730 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x730 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x734 "GFXMMU_LUT742H,GFXMMU LUT entry 742 high" hexmask.long.tbyte 0x734 4.--21. 1. "LO,Line offset" line.long 0x738 "GFXMMU_LUT743L,GFXMMU LUT entry 743 low" hexmask.long.byte 0x738 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x738 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x73C "GFXMMU_LUT743H,GFXMMU LUT entry 743 high" hexmask.long.tbyte 0x73C 4.--21. 1. "LO,Line offset" line.long 0x740 "GFXMMU_LUT744L,GFXMMU LUT entry 744 low" hexmask.long.byte 0x740 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x740 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x744 "GFXMMU_LUT744H,GFXMMU LUT entry 744 high" hexmask.long.tbyte 0x744 4.--21. 1. "LO,Line offset" line.long 0x748 "GFXMMU_LUT745L,GFXMMU LUT entry 745 low" hexmask.long.byte 0x748 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x748 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74C "GFXMMU_LUT745H,GFXMMU LUT entry 745 high" hexmask.long.tbyte 0x74C 4.--21. 1. "LO,Line offset" line.long 0x750 "GFXMMU_LUT746L,GFXMMU LUT entry 746 low" hexmask.long.byte 0x750 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x750 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x754 "GFXMMU_LUT746H,GFXMMU LUT entry 746 high" hexmask.long.tbyte 0x754 4.--21. 1. "LO,Line offset" line.long 0x758 "GFXMMU_LUT747L,GFXMMU LUT entry 747 low" hexmask.long.byte 0x758 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x758 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x75C "GFXMMU_LUT747H,GFXMMU LUT entry 747 high" hexmask.long.tbyte 0x75C 4.--21. 1. "LO,Line offset" line.long 0x760 "GFXMMU_LUT748L,GFXMMU LUT entry 748 low" hexmask.long.byte 0x760 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x760 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x764 "GFXMMU_LUT748H,GFXMMU LUT entry 748 high" hexmask.long.tbyte 0x764 4.--21. 1. "LO,Line offset" line.long 0x768 "GFXMMU_LUT749L,GFXMMU LUT entry 749 low" hexmask.long.byte 0x768 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x768 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x76C "GFXMMU_LUT749H,GFXMMU LUT entry 749 high" hexmask.long.tbyte 0x76C 4.--21. 1. "LO,Line offset" line.long 0x770 "GFXMMU_LUT750L,GFXMMU LUT entry 750 low" hexmask.long.byte 0x770 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x770 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x774 "GFXMMU_LUT750H,GFXMMU LUT entry 750 high" hexmask.long.tbyte 0x774 4.--21. 1. "LO,Line offset" line.long 0x778 "GFXMMU_LUT751L,GFXMMU LUT entry 751 low" hexmask.long.byte 0x778 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x778 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x77C "GFXMMU_LUT751H,GFXMMU LUT entry 751 high" hexmask.long.tbyte 0x77C 4.--21. 1. "LO,Line offset" line.long 0x780 "GFXMMU_LUT752L,GFXMMU LUT entry 752 low" hexmask.long.byte 0x780 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x780 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x784 "GFXMMU_LUT752H,GFXMMU LUT entry 752 high" hexmask.long.tbyte 0x784 4.--21. 1. "LO,Line offset" line.long 0x788 "GFXMMU_LUT753L,GFXMMU LUT entry 753 low" hexmask.long.byte 0x788 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x788 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x78C "GFXMMU_LUT753H,GFXMMU LUT entry 753 high" hexmask.long.tbyte 0x78C 4.--21. 1. "LO,Line offset" line.long 0x790 "GFXMMU_LUT754L,GFXMMU LUT entry 754 low" hexmask.long.byte 0x790 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x790 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x794 "GFXMMU_LUT754H,GFXMMU LUT entry 754 high" hexmask.long.tbyte 0x794 4.--21. 1. "LO,Line offset" line.long 0x798 "GFXMMU_LUT755L,GFXMMU LUT entry 755 low" hexmask.long.byte 0x798 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x798 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x79C "GFXMMU_LUT755H,GFXMMU LUT entry 755 high" hexmask.long.tbyte 0x79C 4.--21. 1. "LO,Line offset" line.long 0x7A0 "GFXMMU_LUT756L,GFXMMU LUT entry 756 low" hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7A4 "GFXMMU_LUT756H,GFXMMU LUT entry 756 high" hexmask.long.tbyte 0x7A4 4.--21. 1. "LO,Line offset" line.long 0x7A8 "GFXMMU_LUT757L,GFXMMU LUT entry 757 low" hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7AC "GFXMMU_LUT757H,GFXMMU LUT entry 757 high" hexmask.long.tbyte 0x7AC 4.--21. 1. "LO,Line offset" line.long 0x7B0 "GFXMMU_LUT758L,GFXMMU LUT entry 758 low" hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7B4 "GFXMMU_LUT758H,GFXMMU LUT entry 758 high" hexmask.long.tbyte 0x7B4 4.--21. 1. "LO,Line offset" line.long 0x7B8 "GFXMMU_LUT759L,GFXMMU LUT entry 759 low" hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7BC "GFXMMU_LUT759H,GFXMMU LUT entry 759 high" hexmask.long.tbyte 0x7BC 4.--21. 1. "LO,Line offset" line.long 0x7C0 "GFXMMU_LUT760L,GFXMMU LUT entry 760 low" hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C4 "GFXMMU_LUT760H,GFXMMU LUT entry 760 high" hexmask.long.tbyte 0x7C4 4.--21. 1. "LO,Line offset" line.long 0x7C8 "GFXMMU_LUT761L,GFXMMU LUT entry 761 low" hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7CC "GFXMMU_LUT761H,GFXMMU LUT entry 761 high" hexmask.long.tbyte 0x7CC 4.--21. 1. "LO,Line offset" line.long 0x7D0 "GFXMMU_LUT762L,GFXMMU LUT entry 762 low" hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7D4 "GFXMMU_LUT762H,GFXMMU LUT entry 762 high" hexmask.long.tbyte 0x7D4 4.--21. 1. "LO,Line offset" line.long 0x7D8 "GFXMMU_LUT763L,GFXMMU LUT entry 763 low" hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7DC "GFXMMU_LUT763H,GFXMMU LUT entry 763 high" hexmask.long.tbyte 0x7DC 4.--21. 1. "LO,Line offset" line.long 0x7E0 "GFXMMU_LUT764L,GFXMMU LUT entry 764 low" hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7E4 "GFXMMU_LUT764H,GFXMMU LUT entry 764 high" hexmask.long.tbyte 0x7E4 4.--21. 1. "LO,Line offset" line.long 0x7E8 "GFXMMU_LUT765L,GFXMMU LUT entry 765 low" hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7EC "GFXMMU_LUT765H,GFXMMU LUT entry 765 high" hexmask.long.tbyte 0x7EC 4.--21. 1. "LO,Line offset" line.long 0x7F0 "GFXMMU_LUT766L,GFXMMU LUT entry 766 low" hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7F4 "GFXMMU_LUT766H,GFXMMU LUT entry 766 high" hexmask.long.tbyte 0x7F4 4.--21. 1. "LO,Line offset" line.long 0x7F8 "GFXMMU_LUT767L,GFXMMU LUT entry 767 low" hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7FC "GFXMMU_LUT767H,GFXMMU LUT entry 767 high" hexmask.long.tbyte 0x7FC 4.--21. 1. "LO,Line offset" line.long 0x800 "GFXMMU_LUT768L,GFXMMU LUT entry 768 low" hexmask.long.byte 0x800 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x800 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x804 "GFXMMU_LUT768H,GFXMMU LUT entry 768 high" hexmask.long.tbyte 0x804 4.--21. 1. "LO,Line offset" line.long 0x808 "GFXMMU_LUT769L,GFXMMU LUT entry 769 low" hexmask.long.byte 0x808 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x808 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x80C "GFXMMU_LUT769H,GFXMMU LUT entry 769 high" hexmask.long.tbyte 0x80C 4.--21. 1. "LO,Line offset" line.long 0x810 "GFXMMU_LUT770L,GFXMMU LUT entry 770 low" hexmask.long.byte 0x810 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x810 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x814 "GFXMMU_LUT770H,GFXMMU LUT entry 770 high" hexmask.long.tbyte 0x814 4.--21. 1. "LO,Line offset" line.long 0x818 "GFXMMU_LUT771L,GFXMMU LUT entry 771 low" hexmask.long.byte 0x818 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x818 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x81C "GFXMMU_LUT771H,GFXMMU LUT entry 771 high" hexmask.long.tbyte 0x81C 4.--21. 1. "LO,Line offset" line.long 0x820 "GFXMMU_LUT772L,GFXMMU LUT entry 772 low" hexmask.long.byte 0x820 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x820 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x824 "GFXMMU_LUT772H,GFXMMU LUT entry 772 high" hexmask.long.tbyte 0x824 4.--21. 1. "LO,Line offset" line.long 0x828 "GFXMMU_LUT773L,GFXMMU LUT entry 773 low" hexmask.long.byte 0x828 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x828 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x82C "GFXMMU_LUT773H,GFXMMU LUT entry 773 high" hexmask.long.tbyte 0x82C 4.--21. 1. "LO,Line offset" line.long 0x830 "GFXMMU_LUT774L,GFXMMU LUT entry 774 low" hexmask.long.byte 0x830 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x830 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x834 "GFXMMU_LUT774H,GFXMMU LUT entry 774 high" hexmask.long.tbyte 0x834 4.--21. 1. "LO,Line offset" line.long 0x838 "GFXMMU_LUT775L,GFXMMU LUT entry 775 low" hexmask.long.byte 0x838 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x838 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x83C "GFXMMU_LUT775H,GFXMMU LUT entry 775 high" hexmask.long.tbyte 0x83C 4.--21. 1. "LO,Line offset" line.long 0x840 "GFXMMU_LUT776L,GFXMMU LUT entry 776 low" hexmask.long.byte 0x840 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x840 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x844 "GFXMMU_LUT776H,GFXMMU LUT entry 776 high" hexmask.long.tbyte 0x844 4.--21. 1. "LO,Line offset" line.long 0x848 "GFXMMU_LUT777L,GFXMMU LUT entry 777 low" hexmask.long.byte 0x848 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x848 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84C "GFXMMU_LUT777H,GFXMMU LUT entry 777 high" hexmask.long.tbyte 0x84C 4.--21. 1. "LO,Line offset" line.long 0x850 "GFXMMU_LUT778L,GFXMMU LUT entry 778 low" hexmask.long.byte 0x850 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x850 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x854 "GFXMMU_LUT778H,GFXMMU LUT entry 778 high" hexmask.long.tbyte 0x854 4.--21. 1. "LO,Line offset" line.long 0x858 "GFXMMU_LUT779L,GFXMMU LUT entry 779 low" hexmask.long.byte 0x858 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x858 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x85C "GFXMMU_LUT779H,GFXMMU LUT entry 779 high" hexmask.long.tbyte 0x85C 4.--21. 1. "LO,Line offset" line.long 0x860 "GFXMMU_LUT780L,GFXMMU LUT entry 780 low" hexmask.long.byte 0x860 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x860 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x864 "GFXMMU_LUT780H,GFXMMU LUT entry 780 high" hexmask.long.tbyte 0x864 4.--21. 1. "LO,Line offset" line.long 0x868 "GFXMMU_LUT781L,GFXMMU LUT entry 781 low" hexmask.long.byte 0x868 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x868 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x86C "GFXMMU_LUT781H,GFXMMU LUT entry 781 high" hexmask.long.tbyte 0x86C 4.--21. 1. "LO,Line offset" line.long 0x870 "GFXMMU_LUT782L,GFXMMU LUT entry 782 low" hexmask.long.byte 0x870 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x870 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x874 "GFXMMU_LUT782H,GFXMMU LUT entry 782 high" hexmask.long.tbyte 0x874 4.--21. 1. "LO,Line offset" line.long 0x878 "GFXMMU_LUT783L,GFXMMU LUT entry 783 low" hexmask.long.byte 0x878 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x878 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x87C "GFXMMU_LUT783H,GFXMMU LUT entry 783 high" hexmask.long.tbyte 0x87C 4.--21. 1. "LO,Line offset" line.long 0x880 "GFXMMU_LUT784L,GFXMMU LUT entry 784 low" hexmask.long.byte 0x880 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x880 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x884 "GFXMMU_LUT784H,GFXMMU LUT entry 784 high" hexmask.long.tbyte 0x884 4.--21. 1. "LO,Line offset" line.long 0x888 "GFXMMU_LUT785L,GFXMMU LUT entry 785 low" hexmask.long.byte 0x888 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x888 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x88C "GFXMMU_LUT785H,GFXMMU LUT entry 785 high" hexmask.long.tbyte 0x88C 4.--21. 1. "LO,Line offset" line.long 0x890 "GFXMMU_LUT786L,GFXMMU LUT entry 786 low" hexmask.long.byte 0x890 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x890 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x894 "GFXMMU_LUT786H,GFXMMU LUT entry 786 high" hexmask.long.tbyte 0x894 4.--21. 1. "LO,Line offset" line.long 0x898 "GFXMMU_LUT787L,GFXMMU LUT entry 787 low" hexmask.long.byte 0x898 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x898 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x89C "GFXMMU_LUT787H,GFXMMU LUT entry 787 high" hexmask.long.tbyte 0x89C 4.--21. 1. "LO,Line offset" line.long 0x8A0 "GFXMMU_LUT788L,GFXMMU LUT entry 788 low" hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8A4 "GFXMMU_LUT788H,GFXMMU LUT entry 788 high" hexmask.long.tbyte 0x8A4 4.--21. 1. "LO,Line offset" line.long 0x8A8 "GFXMMU_LUT789L,GFXMMU LUT entry 789 low" hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8AC "GFXMMU_LUT789H,GFXMMU LUT entry 789 high" hexmask.long.tbyte 0x8AC 4.--21. 1. "LO,Line offset" line.long 0x8B0 "GFXMMU_LUT790L,GFXMMU LUT entry 790 low" hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8B4 "GFXMMU_LUT790H,GFXMMU LUT entry 790 high" hexmask.long.tbyte 0x8B4 4.--21. 1. "LO,Line offset" line.long 0x8B8 "GFXMMU_LUT791L,GFXMMU LUT entry 791 low" hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8BC "GFXMMU_LUT791H,GFXMMU LUT entry 791 high" hexmask.long.tbyte 0x8BC 4.--21. 1. "LO,Line offset" line.long 0x8C0 "GFXMMU_LUT792L,GFXMMU LUT entry 792 low" hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C4 "GFXMMU_LUT792H,GFXMMU LUT entry 792 high" hexmask.long.tbyte 0x8C4 4.--21. 1. "LO,Line offset" line.long 0x8C8 "GFXMMU_LUT793L,GFXMMU LUT entry 793 low" hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8CC "GFXMMU_LUT793H,GFXMMU LUT entry 793 high" hexmask.long.tbyte 0x8CC 4.--21. 1. "LO,Line offset" line.long 0x8D0 "GFXMMU_LUT794L,GFXMMU LUT entry 794 low" hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8D4 "GFXMMU_LUT794H,GFXMMU LUT entry 794 high" hexmask.long.tbyte 0x8D4 4.--21. 1. "LO,Line offset" line.long 0x8D8 "GFXMMU_LUT795L,GFXMMU LUT entry 795 low" hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8DC "GFXMMU_LUT795H,GFXMMU LUT entry 795 high" hexmask.long.tbyte 0x8DC 4.--21. 1. "LO,Line offset" line.long 0x8E0 "GFXMMU_LUT796L,GFXMMU LUT entry 796 low" hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8E4 "GFXMMU_LUT796H,GFXMMU LUT entry 796 high" hexmask.long.tbyte 0x8E4 4.--21. 1. "LO,Line offset" line.long 0x8E8 "GFXMMU_LUT797L,GFXMMU LUT entry 797 low" hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8EC "GFXMMU_LUT797H,GFXMMU LUT entry 797 high" hexmask.long.tbyte 0x8EC 4.--21. 1. "LO,Line offset" line.long 0x8F0 "GFXMMU_LUT798L,GFXMMU LUT entry 798 low" hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8F4 "GFXMMU_LUT798H,GFXMMU LUT entry 798 high" hexmask.long.tbyte 0x8F4 4.--21. 1. "LO,Line offset" line.long 0x8F8 "GFXMMU_LUT799L,GFXMMU LUT entry 799 low" hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8FC "GFXMMU_LUT799H,GFXMMU LUT entry 799 high" hexmask.long.tbyte 0x8FC 4.--21. 1. "LO,Line offset" line.long 0x900 "GFXMMU_LUT800L,GFXMMU LUT entry 800 low" hexmask.long.byte 0x900 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x900 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x904 "GFXMMU_LUT800H,GFXMMU LUT entry 800 high" hexmask.long.tbyte 0x904 4.--21. 1. "LO,Line offset" line.long 0x908 "GFXMMU_LUT801L,GFXMMU LUT entry 801 low" hexmask.long.byte 0x908 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x908 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x90C "GFXMMU_LUT801H,GFXMMU LUT entry 801 high" hexmask.long.tbyte 0x90C 4.--21. 1. "LO,Line offset" line.long 0x910 "GFXMMU_LUT802L,GFXMMU LUT entry 802 low" hexmask.long.byte 0x910 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x910 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x914 "GFXMMU_LUT802H,GFXMMU LUT entry 802 high" hexmask.long.tbyte 0x914 4.--21. 1. "LO,Line offset" line.long 0x918 "GFXMMU_LUT803L,GFXMMU LUT entry 803 low" hexmask.long.byte 0x918 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x918 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x91C "GFXMMU_LUT803H,GFXMMU LUT entry 803 high" hexmask.long.tbyte 0x91C 4.--21. 1. "LO,Line offset" line.long 0x920 "GFXMMU_LUT804L,GFXMMU LUT entry 804 low" hexmask.long.byte 0x920 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x920 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x924 "GFXMMU_LUT804H,GFXMMU LUT entry 804 high" hexmask.long.tbyte 0x924 4.--21. 1. "LO,Line offset" line.long 0x928 "GFXMMU_LUT805L,GFXMMU LUT entry 805 low" hexmask.long.byte 0x928 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x928 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x92C "GFXMMU_LUT805H,GFXMMU LUT entry 805 high" hexmask.long.tbyte 0x92C 4.--21. 1. "LO,Line offset" line.long 0x930 "GFXMMU_LUT806L,GFXMMU LUT entry 806 low" hexmask.long.byte 0x930 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x930 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x934 "GFXMMU_LUT806H,GFXMMU LUT entry 806 high" hexmask.long.tbyte 0x934 4.--21. 1. "LO,Line offset" line.long 0x938 "GFXMMU_LUT807L,GFXMMU LUT entry 807 low" hexmask.long.byte 0x938 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x938 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x93C "GFXMMU_LUT807H,GFXMMU LUT entry 807 high" hexmask.long.tbyte 0x93C 4.--21. 1. "LO,Line offset" line.long 0x940 "GFXMMU_LUT808L,GFXMMU LUT entry 808 low" hexmask.long.byte 0x940 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x940 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x944 "GFXMMU_LUT808H,GFXMMU LUT entry 808 high" hexmask.long.tbyte 0x944 4.--21. 1. "LO,Line offset" line.long 0x948 "GFXMMU_LUT809L,GFXMMU LUT entry 809 low" hexmask.long.byte 0x948 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x948 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94C "GFXMMU_LUT809H,GFXMMU LUT entry 809 high" hexmask.long.tbyte 0x94C 4.--21. 1. "LO,Line offset" line.long 0x950 "GFXMMU_LUT810L,GFXMMU LUT entry 810 low" hexmask.long.byte 0x950 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x950 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x954 "GFXMMU_LUT810H,GFXMMU LUT entry 810 high" hexmask.long.tbyte 0x954 4.--21. 1. "LO,Line offset" line.long 0x958 "GFXMMU_LUT811L,GFXMMU LUT entry 811 low" hexmask.long.byte 0x958 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x958 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x95C "GFXMMU_LUT811H,GFXMMU LUT entry 811 high" hexmask.long.tbyte 0x95C 4.--21. 1. "LO,Line offset" line.long 0x960 "GFXMMU_LUT812L,GFXMMU LUT entry 812 low" hexmask.long.byte 0x960 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x960 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x964 "GFXMMU_LUT812H,GFXMMU LUT entry 812 high" hexmask.long.tbyte 0x964 4.--21. 1. "LO,Line offset" line.long 0x968 "GFXMMU_LUT813L,GFXMMU LUT entry 813 low" hexmask.long.byte 0x968 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x968 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x96C "GFXMMU_LUT813H,GFXMMU LUT entry 813 high" hexmask.long.tbyte 0x96C 4.--21. 1. "LO,Line offset" line.long 0x970 "GFXMMU_LUT814L,GFXMMU LUT entry 814 low" hexmask.long.byte 0x970 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x970 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x974 "GFXMMU_LUT814H,GFXMMU LUT entry 814 high" hexmask.long.tbyte 0x974 4.--21. 1. "LO,Line offset" line.long 0x978 "GFXMMU_LUT815L,GFXMMU LUT entry 815 low" hexmask.long.byte 0x978 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x978 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x97C "GFXMMU_LUT815H,GFXMMU LUT entry 815 high" hexmask.long.tbyte 0x97C 4.--21. 1. "LO,Line offset" line.long 0x980 "GFXMMU_LUT816L,GFXMMU LUT entry 816 low" hexmask.long.byte 0x980 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x980 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x984 "GFXMMU_LUT816H,GFXMMU LUT entry 816 high" hexmask.long.tbyte 0x984 4.--21. 1. "LO,Line offset" line.long 0x988 "GFXMMU_LUT817L,GFXMMU LUT entry 817 low" hexmask.long.byte 0x988 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x988 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x98C "GFXMMU_LUT817H,GFXMMU LUT entry 817 high" hexmask.long.tbyte 0x98C 4.--21. 1. "LO,Line offset" line.long 0x990 "GFXMMU_LUT818L,GFXMMU LUT entry 818 low" hexmask.long.byte 0x990 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x990 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x994 "GFXMMU_LUT818H,GFXMMU LUT entry 818 high" hexmask.long.tbyte 0x994 4.--21. 1. "LO,Line offset" line.long 0x998 "GFXMMU_LUT819L,GFXMMU LUT entry 819 low" hexmask.long.byte 0x998 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x998 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x99C "GFXMMU_LUT819H,GFXMMU LUT entry 819 high" hexmask.long.tbyte 0x99C 4.--21. 1. "LO,Line offset" line.long 0x9A0 "GFXMMU_LUT820L,GFXMMU LUT entry 820 low" hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9A4 "GFXMMU_LUT820H,GFXMMU LUT entry 820 high" hexmask.long.tbyte 0x9A4 4.--21. 1. "LO,Line offset" line.long 0x9A8 "GFXMMU_LUT821L,GFXMMU LUT entry 821 low" hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9AC "GFXMMU_LUT821H,GFXMMU LUT entry 821 high" hexmask.long.tbyte 0x9AC 4.--21. 1. "LO,Line offset" line.long 0x9B0 "GFXMMU_LUT822L,GFXMMU LUT entry 822 low" hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9B4 "GFXMMU_LUT822H,GFXMMU LUT entry 822 high" hexmask.long.tbyte 0x9B4 4.--21. 1. "LO,Line offset" line.long 0x9B8 "GFXMMU_LUT823L,GFXMMU LUT entry 823 low" hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9BC "GFXMMU_LUT823H,GFXMMU LUT entry 823 high" hexmask.long.tbyte 0x9BC 4.--21. 1. "LO,Line offset" line.long 0x9C0 "GFXMMU_LUT824L,GFXMMU LUT entry 824 low" hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C4 "GFXMMU_LUT824H,GFXMMU LUT entry 824 high" hexmask.long.tbyte 0x9C4 4.--21. 1. "LO,Line offset" line.long 0x9C8 "GFXMMU_LUT825L,GFXMMU LUT entry 825 low" hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9CC "GFXMMU_LUT825H,GFXMMU LUT entry 825 high" hexmask.long.tbyte 0x9CC 4.--21. 1. "LO,Line offset" line.long 0x9D0 "GFXMMU_LUT826L,GFXMMU LUT entry 826 low" hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9D4 "GFXMMU_LUT826H,GFXMMU LUT entry 826 high" hexmask.long.tbyte 0x9D4 4.--21. 1. "LO,Line offset" line.long 0x9D8 "GFXMMU_LUT827L,GFXMMU LUT entry 827 low" hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9DC "GFXMMU_LUT827H,GFXMMU LUT entry 827 high" hexmask.long.tbyte 0x9DC 4.--21. 1. "LO,Line offset" line.long 0x9E0 "GFXMMU_LUT828L,GFXMMU LUT entry 828 low" hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9E4 "GFXMMU_LUT828H,GFXMMU LUT entry 828 high" hexmask.long.tbyte 0x9E4 4.--21. 1. "LO,Line offset" line.long 0x9E8 "GFXMMU_LUT829L,GFXMMU LUT entry 829 low" hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9EC "GFXMMU_LUT829H,GFXMMU LUT entry 829 high" hexmask.long.tbyte 0x9EC 4.--21. 1. "LO,Line offset" line.long 0x9F0 "GFXMMU_LUT830L,GFXMMU LUT entry 830 low" hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9F4 "GFXMMU_LUT830H,GFXMMU LUT entry 830 high" hexmask.long.tbyte 0x9F4 4.--21. 1. "LO,Line offset" line.long 0x9F8 "GFXMMU_LUT831L,GFXMMU LUT entry 831 low" hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9FC "GFXMMU_LUT831H,GFXMMU LUT entry 831 high" hexmask.long.tbyte 0x9FC 4.--21. 1. "LO,Line offset" line.long 0xA00 "GFXMMU_LUT832L,GFXMMU LUT entry 832 low" hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA04 "GFXMMU_LUT832H,GFXMMU LUT entry 832 high" hexmask.long.tbyte 0xA04 4.--21. 1. "LO,Line offset" line.long 0xA08 "GFXMMU_LUT833L,GFXMMU LUT entry 833 low" hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA0C "GFXMMU_LUT833H,GFXMMU LUT entry 833 high" hexmask.long.tbyte 0xA0C 4.--21. 1. "LO,Line offset" line.long 0xA10 "GFXMMU_LUT834L,GFXMMU LUT entry 834 low" hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA14 "GFXMMU_LUT834H,GFXMMU LUT entry 834 high" hexmask.long.tbyte 0xA14 4.--21. 1. "LO,Line offset" line.long 0xA18 "GFXMMU_LUT835L,GFXMMU LUT entry 835 low" hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA1C "GFXMMU_LUT835H,GFXMMU LUT entry 835 high" hexmask.long.tbyte 0xA1C 4.--21. 1. "LO,Line offset" line.long 0xA20 "GFXMMU_LUT836L,GFXMMU LUT entry 836 low" hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA24 "GFXMMU_LUT836H,GFXMMU LUT entry 836 high" hexmask.long.tbyte 0xA24 4.--21. 1. "LO,Line offset" line.long 0xA28 "GFXMMU_LUT837L,GFXMMU LUT entry 837 low" hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA2C "GFXMMU_LUT837H,GFXMMU LUT entry 837 high" hexmask.long.tbyte 0xA2C 4.--21. 1. "LO,Line offset" line.long 0xA30 "GFXMMU_LUT838L,GFXMMU LUT entry 838 low" hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA34 "GFXMMU_LUT838H,GFXMMU LUT entry 838 high" hexmask.long.tbyte 0xA34 4.--21. 1. "LO,Line offset" line.long 0xA38 "GFXMMU_LUT839L,GFXMMU LUT entry 839 low" hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA3C "GFXMMU_LUT839H,GFXMMU LUT entry 839 high" hexmask.long.tbyte 0xA3C 4.--21. 1. "LO,Line offset" line.long 0xA40 "GFXMMU_LUT840L,GFXMMU LUT entry 840 low" hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA44 "GFXMMU_LUT840H,GFXMMU LUT entry 840 high" hexmask.long.tbyte 0xA44 4.--21. 1. "LO,Line offset" line.long 0xA48 "GFXMMU_LUT841L,GFXMMU LUT entry 841 low" hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4C "GFXMMU_LUT841H,GFXMMU LUT entry 841 high" hexmask.long.tbyte 0xA4C 4.--21. 1. "LO,Line offset" line.long 0xA50 "GFXMMU_LUT842L,GFXMMU LUT entry 842 low" hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA54 "GFXMMU_LUT842H,GFXMMU LUT entry 842 high" hexmask.long.tbyte 0xA54 4.--21. 1. "LO,Line offset" line.long 0xA58 "GFXMMU_LUT843L,GFXMMU LUT entry 843 low" hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA5C "GFXMMU_LUT843H,GFXMMU LUT entry 843 high" hexmask.long.tbyte 0xA5C 4.--21. 1. "LO,Line offset" line.long 0xA60 "GFXMMU_LUT844L,GFXMMU LUT entry 844 low" hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA64 "GFXMMU_LUT844H,GFXMMU LUT entry 844 high" hexmask.long.tbyte 0xA64 4.--21. 1. "LO,Line offset" line.long 0xA68 "GFXMMU_LUT845L,GFXMMU LUT entry 845 low" hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA6C "GFXMMU_LUT845H,GFXMMU LUT entry 845 high" hexmask.long.tbyte 0xA6C 4.--21. 1. "LO,Line offset" line.long 0xA70 "GFXMMU_LUT846L,GFXMMU LUT entry 846 low" hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA74 "GFXMMU_LUT846H,GFXMMU LUT entry 846 high" hexmask.long.tbyte 0xA74 4.--21. 1. "LO,Line offset" line.long 0xA78 "GFXMMU_LUT847L,GFXMMU LUT entry 847 low" hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA7C "GFXMMU_LUT847H,GFXMMU LUT entry 847 high" hexmask.long.tbyte 0xA7C 4.--21. 1. "LO,Line offset" line.long 0xA80 "GFXMMU_LUT848L,GFXMMU LUT entry 848 low" hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA84 "GFXMMU_LUT848H,GFXMMU LUT entry 848 high" hexmask.long.tbyte 0xA84 4.--21. 1. "LO,Line offset" line.long 0xA88 "GFXMMU_LUT849L,GFXMMU LUT entry 849 low" hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA8C "GFXMMU_LUT849H,GFXMMU LUT entry 849 high" hexmask.long.tbyte 0xA8C 4.--21. 1. "LO,Line offset" line.long 0xA90 "GFXMMU_LUT850L,GFXMMU LUT entry 850 low" hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA94 "GFXMMU_LUT850H,GFXMMU LUT entry 850 high" hexmask.long.tbyte 0xA94 4.--21. 1. "LO,Line offset" line.long 0xA98 "GFXMMU_LUT851L,GFXMMU LUT entry 851 low" hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA9C "GFXMMU_LUT851H,GFXMMU LUT entry 851 high" hexmask.long.tbyte 0xA9C 4.--21. 1. "LO,Line offset" line.long 0xAA0 "GFXMMU_LUT852L,GFXMMU LUT entry 852 low" hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAA4 "GFXMMU_LUT852H,GFXMMU LUT entry 852 high" hexmask.long.tbyte 0xAA4 4.--21. 1. "LO,Line offset" line.long 0xAA8 "GFXMMU_LUT853L,GFXMMU LUT entry 853 low" hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAAC "GFXMMU_LUT853H,GFXMMU LUT entry 853 high" hexmask.long.tbyte 0xAAC 4.--21. 1. "LO,Line offset" line.long 0xAB0 "GFXMMU_LUT854L,GFXMMU LUT entry 854 low" hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAB4 "GFXMMU_LUT854H,GFXMMU LUT entry 854 high" hexmask.long.tbyte 0xAB4 4.--21. 1. "LO,Line offset" line.long 0xAB8 "GFXMMU_LUT855L,GFXMMU LUT entry 855 low" hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xABC "GFXMMU_LUT855H,GFXMMU LUT entry 855 high" hexmask.long.tbyte 0xABC 4.--21. 1. "LO,Line offset" line.long 0xAC0 "GFXMMU_LUT856L,GFXMMU LUT entry 856 low" hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC4 "GFXMMU_LUT856H,GFXMMU LUT entry 856 high" hexmask.long.tbyte 0xAC4 4.--21. 1. "LO,Line offset" line.long 0xAC8 "GFXMMU_LUT857L,GFXMMU LUT entry 857 low" hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xACC "GFXMMU_LUT857H,GFXMMU LUT entry 857 high" hexmask.long.tbyte 0xACC 4.--21. 1. "LO,Line offset" line.long 0xAD0 "GFXMMU_LUT858L,GFXMMU LUT entry 858 low" hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAD4 "GFXMMU_LUT858H,GFXMMU LUT entry 858 high" hexmask.long.tbyte 0xAD4 4.--21. 1. "LO,Line offset" line.long 0xAD8 "GFXMMU_LUT859L,GFXMMU LUT entry 859 low" hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xADC "GFXMMU_LUT859H,GFXMMU LUT entry 859 high" hexmask.long.tbyte 0xADC 4.--21. 1. "LO,Line offset" line.long 0xAE0 "GFXMMU_LUT860L,GFXMMU LUT entry 860 low" hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAE4 "GFXMMU_LUT860H,GFXMMU LUT entry 860 high" hexmask.long.tbyte 0xAE4 4.--21. 1. "LO,Line offset" line.long 0xAE8 "GFXMMU_LUT861L,GFXMMU LUT entry 861 low" hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAEC "GFXMMU_LUT861H,GFXMMU LUT entry 861 high" hexmask.long.tbyte 0xAEC 4.--21. 1. "LO,Line offset" line.long 0xAF0 "GFXMMU_LUT862L,GFXMMU LUT entry 862 low" hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAF4 "GFXMMU_LUT862H,GFXMMU LUT entry 862 high" hexmask.long.tbyte 0xAF4 4.--21. 1. "LO,Line offset" line.long 0xAF8 "GFXMMU_LUT863L,GFXMMU LUT entry 863 low" hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAFC "GFXMMU_LUT863H,GFXMMU LUT entry 863 high" hexmask.long.tbyte 0xAFC 4.--21. 1. "LO,Line offset" line.long 0xB00 "GFXMMU_LUT864L,GFXMMU LUT entry 864 low" hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB04 "GFXMMU_LUT864H,GFXMMU LUT entry 864 high" hexmask.long.tbyte 0xB04 4.--21. 1. "LO,Line offset" line.long 0xB08 "GFXMMU_LUT865L,GFXMMU LUT entry 865 low" hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB0C "GFXMMU_LUT865H,GFXMMU LUT entry 865 high" hexmask.long.tbyte 0xB0C 4.--21. 1. "LO,Line offset" line.long 0xB10 "GFXMMU_LUT866L,GFXMMU LUT entry 866 low" hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB14 "GFXMMU_LUT866H,GFXMMU LUT entry 866 high" hexmask.long.tbyte 0xB14 4.--21. 1. "LO,Line offset" line.long 0xB18 "GFXMMU_LUT867L,GFXMMU LUT entry 867 low" hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB1C "GFXMMU_LUT867H,GFXMMU LUT entry 867 high" hexmask.long.tbyte 0xB1C 4.--21. 1. "LO,Line offset" line.long 0xB20 "GFXMMU_LUT868L,GFXMMU LUT entry 868 low" hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB24 "GFXMMU_LUT868H,GFXMMU LUT entry 868 high" hexmask.long.tbyte 0xB24 4.--21. 1. "LO,Line offset" line.long 0xB28 "GFXMMU_LUT869L,GFXMMU LUT entry 869 low" hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB2C "GFXMMU_LUT869H,GFXMMU LUT entry 869 high" hexmask.long.tbyte 0xB2C 4.--21. 1. "LO,Line offset" line.long 0xB30 "GFXMMU_LUT870L,GFXMMU LUT entry 870 low" hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB34 "GFXMMU_LUT870H,GFXMMU LUT entry 870 high" hexmask.long.tbyte 0xB34 4.--21. 1. "LO,Line offset" line.long 0xB38 "GFXMMU_LUT871L,GFXMMU LUT entry 871 low" hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB3C "GFXMMU_LUT871H,GFXMMU LUT entry 871 high" hexmask.long.tbyte 0xB3C 4.--21. 1. "LO,Line offset" line.long 0xB40 "GFXMMU_LUT872L,GFXMMU LUT entry 872 low" hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB44 "GFXMMU_LUT872H,GFXMMU LUT entry 872 high" hexmask.long.tbyte 0xB44 4.--21. 1. "LO,Line offset" line.long 0xB48 "GFXMMU_LUT873L,GFXMMU LUT entry 873 low" hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4C "GFXMMU_LUT873H,GFXMMU LUT entry 873 high" hexmask.long.tbyte 0xB4C 4.--21. 1. "LO,Line offset" line.long 0xB50 "GFXMMU_LUT874L,GFXMMU LUT entry 874 low" hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB54 "GFXMMU_LUT874H,GFXMMU LUT entry 874 high" hexmask.long.tbyte 0xB54 4.--21. 1. "LO,Line offset" line.long 0xB58 "GFXMMU_LUT875L,GFXMMU LUT entry 875 low" hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB5C "GFXMMU_LUT875H,GFXMMU LUT entry 875 high" hexmask.long.tbyte 0xB5C 4.--21. 1. "LO,Line offset" line.long 0xB60 "GFXMMU_LUT876L,GFXMMU LUT entry 876 low" hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB64 "GFXMMU_LUT876H,GFXMMU LUT entry 876 high" hexmask.long.tbyte 0xB64 4.--21. 1. "LO,Line offset" line.long 0xB68 "GFXMMU_LUT877L,GFXMMU LUT entry 877 low" hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB6C "GFXMMU_LUT877H,GFXMMU LUT entry 877 high" hexmask.long.tbyte 0xB6C 4.--21. 1. "LO,Line offset" line.long 0xB70 "GFXMMU_LUT878L,GFXMMU LUT entry 878 low" hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB74 "GFXMMU_LUT878H,GFXMMU LUT entry 878 high" hexmask.long.tbyte 0xB74 4.--21. 1. "LO,Line offset" line.long 0xB78 "GFXMMU_LUT879L,GFXMMU LUT entry 879 low" hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB7C "GFXMMU_LUT879H,GFXMMU LUT entry 879 high" hexmask.long.tbyte 0xB7C 4.--21. 1. "LO,Line offset" line.long 0xB80 "GFXMMU_LUT880L,GFXMMU LUT entry 880 low" hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB84 "GFXMMU_LUT880H,GFXMMU LUT entry 880 high" hexmask.long.tbyte 0xB84 4.--21. 1. "LO,Line offset" line.long 0xB88 "GFXMMU_LUT881L,GFXMMU LUT entry 881 low" hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB8C "GFXMMU_LUT881H,GFXMMU LUT entry 881 high" hexmask.long.tbyte 0xB8C 4.--21. 1. "LO,Line offset" line.long 0xB90 "GFXMMU_LUT882L,GFXMMU LUT entry 882 low" hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB94 "GFXMMU_LUT882H,GFXMMU LUT entry 882 high" hexmask.long.tbyte 0xB94 4.--21. 1. "LO,Line offset" line.long 0xB98 "GFXMMU_LUT883L,GFXMMU LUT entry 883 low" hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB9C "GFXMMU_LUT883H,GFXMMU LUT entry 883 high" hexmask.long.tbyte 0xB9C 4.--21. 1. "LO,Line offset" line.long 0xBA0 "GFXMMU_LUT884L,GFXMMU LUT entry 884 low" hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBA4 "GFXMMU_LUT884H,GFXMMU LUT entry 884 high" hexmask.long.tbyte 0xBA4 4.--21. 1. "LO,Line offset" line.long 0xBA8 "GFXMMU_LUT885L,GFXMMU LUT entry 885 low" hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBAC "GFXMMU_LUT885H,GFXMMU LUT entry 885 high" hexmask.long.tbyte 0xBAC 4.--21. 1. "LO,Line offset" line.long 0xBB0 "GFXMMU_LUT886L,GFXMMU LUT entry 886 low" hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBB4 "GFXMMU_LUT886H,GFXMMU LUT entry 886 high" hexmask.long.tbyte 0xBB4 4.--21. 1. "LO,Line offset" line.long 0xBB8 "GFXMMU_LUT887L,GFXMMU LUT entry 887 low" hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBBC "GFXMMU_LUT887H,GFXMMU LUT entry 887 high" hexmask.long.tbyte 0xBBC 4.--21. 1. "LO,Line offset" line.long 0xBC0 "GFXMMU_LUT888L,GFXMMU LUT entry 888 low" hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC4 "GFXMMU_LUT888H,GFXMMU LUT entry 888 high" hexmask.long.tbyte 0xBC4 4.--21. 1. "LO,Line offset" line.long 0xBC8 "GFXMMU_LUT889L,GFXMMU LUT entry 889 low" hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBCC "GFXMMU_LUT889H,GFXMMU LUT entry 889 high" hexmask.long.tbyte 0xBCC 4.--21. 1. "LO,Line offset" line.long 0xBD0 "GFXMMU_LUT890L,GFXMMU LUT entry 890 low" hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBD4 "GFXMMU_LUT890H,GFXMMU LUT entry 890 high" hexmask.long.tbyte 0xBD4 4.--21. 1. "LO,Line offset" line.long 0xBD8 "GFXMMU_LUT891L,GFXMMU LUT entry 891 low" hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBDC "GFXMMU_LUT891H,GFXMMU LUT entry 891 high" hexmask.long.tbyte 0xBDC 4.--21. 1. "LO,Line offset" line.long 0xBE0 "GFXMMU_LUT892L,GFXMMU LUT entry 892 low" hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBE4 "GFXMMU_LUT892H,GFXMMU LUT entry 892 high" hexmask.long.tbyte 0xBE4 4.--21. 1. "LO,Line offset" line.long 0xBE8 "GFXMMU_LUT893L,GFXMMU LUT entry 893 low" hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBEC "GFXMMU_LUT893H,GFXMMU LUT entry 893 high" hexmask.long.tbyte 0xBEC 4.--21. 1. "LO,Line offset" line.long 0xBF0 "GFXMMU_LUT894L,GFXMMU LUT entry 894 low" hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBF4 "GFXMMU_LUT894H,GFXMMU LUT entry 894 high" hexmask.long.tbyte 0xBF4 4.--21. 1. "LO,Line offset" line.long 0xBF8 "GFXMMU_LUT895L,GFXMMU LUT entry 895 low" hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBFC "GFXMMU_LUT895H,GFXMMU LUT entry 895 high" hexmask.long.tbyte 0xBFC 4.--21. 1. "LO,Line offset" line.long 0xC00 "GFXMMU_LUT896L,GFXMMU LUT entry 896 low" hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC04 "GFXMMU_LUT896H,GFXMMU LUT entry 896 high" hexmask.long.tbyte 0xC04 4.--21. 1. "LO,Line offset" line.long 0xC08 "GFXMMU_LUT897L,GFXMMU LUT entry 897 low" hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC0C "GFXMMU_LUT897H,GFXMMU LUT entry 897 high" hexmask.long.tbyte 0xC0C 4.--21. 1. "LO,Line offset" line.long 0xC10 "GFXMMU_LUT898L,GFXMMU LUT entry 898 low" hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC14 "GFXMMU_LUT898H,GFXMMU LUT entry 898 high" hexmask.long.tbyte 0xC14 4.--21. 1. "LO,Line offset" line.long 0xC18 "GFXMMU_LUT899L,GFXMMU LUT entry 899 low" hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC1C "GFXMMU_LUT899H,GFXMMU LUT entry 899 high" hexmask.long.tbyte 0xC1C 4.--21. 1. "LO,Line offset" line.long 0xC20 "GFXMMU_LUT900L,GFXMMU LUT entry 900 low" hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC24 "GFXMMU_LUT900H,GFXMMU LUT entry 900 high" hexmask.long.tbyte 0xC24 4.--21. 1. "LO,Line offset" line.long 0xC28 "GFXMMU_LUT901L,GFXMMU LUT entry 901 low" hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC2C "GFXMMU_LUT901H,GFXMMU LUT entry 901 high" hexmask.long.tbyte 0xC2C 4.--21. 1. "LO,Line offset" line.long 0xC30 "GFXMMU_LUT902L,GFXMMU LUT entry 902 low" hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC34 "GFXMMU_LUT902H,GFXMMU LUT entry 902 high" hexmask.long.tbyte 0xC34 4.--21. 1. "LO,Line offset" line.long 0xC38 "GFXMMU_LUT903L,GFXMMU LUT entry 903 low" hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC3C "GFXMMU_LUT903H,GFXMMU LUT entry 903 high" hexmask.long.tbyte 0xC3C 4.--21. 1. "LO,Line offset" line.long 0xC40 "GFXMMU_LUT904L,GFXMMU LUT entry 904 low" hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC44 "GFXMMU_LUT904H,GFXMMU LUT entry 904 high" hexmask.long.tbyte 0xC44 4.--21. 1. "LO,Line offset" line.long 0xC48 "GFXMMU_LUT905L,GFXMMU LUT entry 905 low" hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4C "GFXMMU_LUT905H,GFXMMU LUT entry 905 high" hexmask.long.tbyte 0xC4C 4.--21. 1. "LO,Line offset" line.long 0xC50 "GFXMMU_LUT906L,GFXMMU LUT entry 906 low" hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC54 "GFXMMU_LUT906H,GFXMMU LUT entry 906 high" hexmask.long.tbyte 0xC54 4.--21. 1. "LO,Line offset" line.long 0xC58 "GFXMMU_LUT907L,GFXMMU LUT entry 907 low" hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC5C "GFXMMU_LUT907H,GFXMMU LUT entry 907 high" hexmask.long.tbyte 0xC5C 4.--21. 1. "LO,Line offset" line.long 0xC60 "GFXMMU_LUT908L,GFXMMU LUT entry 908 low" hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC64 "GFXMMU_LUT908H,GFXMMU LUT entry 908 high" hexmask.long.tbyte 0xC64 4.--21. 1. "LO,Line offset" line.long 0xC68 "GFXMMU_LUT909L,GFXMMU LUT entry 909 low" hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC6C "GFXMMU_LUT909H,GFXMMU LUT entry 909 high" hexmask.long.tbyte 0xC6C 4.--21. 1. "LO,Line offset" line.long 0xC70 "GFXMMU_LUT910L,GFXMMU LUT entry 910 low" hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC74 "GFXMMU_LUT910H,GFXMMU LUT entry 910 high" hexmask.long.tbyte 0xC74 4.--21. 1. "LO,Line offset" line.long 0xC78 "GFXMMU_LUT911L,GFXMMU LUT entry 911 low" hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC7C "GFXMMU_LUT911H,GFXMMU LUT entry 911 high" hexmask.long.tbyte 0xC7C 4.--21. 1. "LO,Line offset" line.long 0xC80 "GFXMMU_LUT912L,GFXMMU LUT entry 912 low" hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC84 "GFXMMU_LUT912H,GFXMMU LUT entry 912 high" hexmask.long.tbyte 0xC84 4.--21. 1. "LO,Line offset" line.long 0xC88 "GFXMMU_LUT913L,GFXMMU LUT entry 913 low" hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC8C "GFXMMU_LUT913H,GFXMMU LUT entry 913 high" hexmask.long.tbyte 0xC8C 4.--21. 1. "LO,Line offset" line.long 0xC90 "GFXMMU_LUT914L,GFXMMU LUT entry 914 low" hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC94 "GFXMMU_LUT914H,GFXMMU LUT entry 914 high" hexmask.long.tbyte 0xC94 4.--21. 1. "LO,Line offset" line.long 0xC98 "GFXMMU_LUT915L,GFXMMU LUT entry 915 low" hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC9C "GFXMMU_LUT915H,GFXMMU LUT entry 915 high" hexmask.long.tbyte 0xC9C 4.--21. 1. "LO,Line offset" line.long 0xCA0 "GFXMMU_LUT916L,GFXMMU LUT entry 916 low" hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCA4 "GFXMMU_LUT916H,GFXMMU LUT entry 916 high" hexmask.long.tbyte 0xCA4 4.--21. 1. "LO,Line offset" line.long 0xCA8 "GFXMMU_LUT917L,GFXMMU LUT entry 917 low" hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCAC "GFXMMU_LUT917H,GFXMMU LUT entry 917 high" hexmask.long.tbyte 0xCAC 4.--21. 1. "LO,Line offset" line.long 0xCB0 "GFXMMU_LUT918L,GFXMMU LUT entry 918 low" hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCB4 "GFXMMU_LUT918H,GFXMMU LUT entry 918 high" hexmask.long.tbyte 0xCB4 4.--21. 1. "LO,Line offset" line.long 0xCB8 "GFXMMU_LUT919L,GFXMMU LUT entry 919 low" hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCBC "GFXMMU_LUT919H,GFXMMU LUT entry 919 high" hexmask.long.tbyte 0xCBC 4.--21. 1. "LO,Line offset" line.long 0xCC0 "GFXMMU_LUT920L,GFXMMU LUT entry 920 low" hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC4 "GFXMMU_LUT920H,GFXMMU LUT entry 920 high" hexmask.long.tbyte 0xCC4 4.--21. 1. "LO,Line offset" line.long 0xCC8 "GFXMMU_LUT921L,GFXMMU LUT entry 921 low" hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCCC "GFXMMU_LUT921H,GFXMMU LUT entry 921 high" hexmask.long.tbyte 0xCCC 4.--21. 1. "LO,Line offset" line.long 0xCD0 "GFXMMU_LUT922L,GFXMMU LUT entry 922 low" hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCD4 "GFXMMU_LUT922H,GFXMMU LUT entry 922 high" hexmask.long.tbyte 0xCD4 4.--21. 1. "LO,Line offset" line.long 0xCD8 "GFXMMU_LUT923L,GFXMMU LUT entry 923 low" hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCDC "GFXMMU_LUT923H,GFXMMU LUT entry 923 high" hexmask.long.tbyte 0xCDC 4.--21. 1. "LO,Line offset" line.long 0xCE0 "GFXMMU_LUT924L,GFXMMU LUT entry 924 low" hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCE4 "GFXMMU_LUT924H,GFXMMU LUT entry 924 high" hexmask.long.tbyte 0xCE4 4.--21. 1. "LO,Line offset" line.long 0xCE8 "GFXMMU_LUT925L,GFXMMU LUT entry 925 low" hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCEC "GFXMMU_LUT925H,GFXMMU LUT entry 925 high" hexmask.long.tbyte 0xCEC 4.--21. 1. "LO,Line offset" line.long 0xCF0 "GFXMMU_LUT926L,GFXMMU LUT entry 926 low" hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCF4 "GFXMMU_LUT926H,GFXMMU LUT entry 926 high" hexmask.long.tbyte 0xCF4 4.--21. 1. "LO,Line offset" line.long 0xCF8 "GFXMMU_LUT927L,GFXMMU LUT entry 927 low" hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCFC "GFXMMU_LUT927H,GFXMMU LUT entry 927 high" hexmask.long.tbyte 0xCFC 4.--21. 1. "LO,Line offset" line.long 0xD00 "GFXMMU_LUT928L,GFXMMU LUT entry 928 low" hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD04 "GFXMMU_LUT928H,GFXMMU LUT entry 928 high" hexmask.long.tbyte 0xD04 4.--21. 1. "LO,Line offset" line.long 0xD08 "GFXMMU_LUT929L,GFXMMU LUT entry 929 low" hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD0C "GFXMMU_LUT929H,GFXMMU LUT entry 929 high" hexmask.long.tbyte 0xD0C 4.--21. 1. "LO,Line offset" line.long 0xD10 "GFXMMU_LUT930L,GFXMMU LUT entry 930 low" hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD14 "GFXMMU_LUT930H,GFXMMU LUT entry 930 high" hexmask.long.tbyte 0xD14 4.--21. 1. "LO,Line offset" line.long 0xD18 "GFXMMU_LUT931L,GFXMMU LUT entry 931 low" hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD1C "GFXMMU_LUT931H,GFXMMU LUT entry 931 high" hexmask.long.tbyte 0xD1C 4.--21. 1. "LO,Line offset" line.long 0xD20 "GFXMMU_LUT932L,GFXMMU LUT entry 932 low" hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD24 "GFXMMU_LUT932H,GFXMMU LUT entry 932 high" hexmask.long.tbyte 0xD24 4.--21. 1. "LO,Line offset" line.long 0xD28 "GFXMMU_LUT933L,GFXMMU LUT entry 933 low" hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD2C "GFXMMU_LUT933H,GFXMMU LUT entry 933 high" hexmask.long.tbyte 0xD2C 4.--21. 1. "LO,Line offset" line.long 0xD30 "GFXMMU_LUT934L,GFXMMU LUT entry 934 low" hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD34 "GFXMMU_LUT934H,GFXMMU LUT entry 934 high" hexmask.long.tbyte 0xD34 4.--21. 1. "LO,Line offset" line.long 0xD38 "GFXMMU_LUT935L,GFXMMU LUT entry 935 low" hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD3C "GFXMMU_LUT935H,GFXMMU LUT entry 935 high" hexmask.long.tbyte 0xD3C 4.--21. 1. "LO,Line offset" line.long 0xD40 "GFXMMU_LUT936L,GFXMMU LUT entry 936 low" hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD44 "GFXMMU_LUT936H,GFXMMU LUT entry 936 high" hexmask.long.tbyte 0xD44 4.--21. 1. "LO,Line offset" line.long 0xD48 "GFXMMU_LUT937L,GFXMMU LUT entry 937 low" hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4C "GFXMMU_LUT937H,GFXMMU LUT entry 937 high" hexmask.long.tbyte 0xD4C 4.--21. 1. "LO,Line offset" line.long 0xD50 "GFXMMU_LUT938L,GFXMMU LUT entry 938 low" hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD54 "GFXMMU_LUT938H,GFXMMU LUT entry 938 high" hexmask.long.tbyte 0xD54 4.--21. 1. "LO,Line offset" line.long 0xD58 "GFXMMU_LUT939L,GFXMMU LUT entry 939 low" hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD5C "GFXMMU_LUT939H,GFXMMU LUT entry 939 high" hexmask.long.tbyte 0xD5C 4.--21. 1. "LO,Line offset" line.long 0xD60 "GFXMMU_LUT940L,GFXMMU LUT entry 940 low" hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD64 "GFXMMU_LUT940H,GFXMMU LUT entry 940 high" hexmask.long.tbyte 0xD64 4.--21. 1. "LO,Line offset" line.long 0xD68 "GFXMMU_LUT941L,GFXMMU LUT entry 941 low" hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD6C "GFXMMU_LUT941H,GFXMMU LUT entry 941 high" hexmask.long.tbyte 0xD6C 4.--21. 1. "LO,Line offset" line.long 0xD70 "GFXMMU_LUT942L,GFXMMU LUT entry 942 low" hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD74 "GFXMMU_LUT942H,GFXMMU LUT entry 942 high" hexmask.long.tbyte 0xD74 4.--21. 1. "LO,Line offset" line.long 0xD78 "GFXMMU_LUT943L,GFXMMU LUT entry 943 low" hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD7C "GFXMMU_LUT943H,GFXMMU LUT entry 943 high" hexmask.long.tbyte 0xD7C 4.--21. 1. "LO,Line offset" line.long 0xD80 "GFXMMU_LUT944L,GFXMMU LUT entry 944 low" hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD84 "GFXMMU_LUT944H,GFXMMU LUT entry 944 high" hexmask.long.tbyte 0xD84 4.--21. 1. "LO,Line offset" line.long 0xD88 "GFXMMU_LUT945L,GFXMMU LUT entry 945 low" hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD8C "GFXMMU_LUT945H,GFXMMU LUT entry 945 high" hexmask.long.tbyte 0xD8C 4.--21. 1. "LO,Line offset" line.long 0xD90 "GFXMMU_LUT946L,GFXMMU LUT entry 946 low" hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD94 "GFXMMU_LUT946H,GFXMMU LUT entry 946 high" hexmask.long.tbyte 0xD94 4.--21. 1. "LO,Line offset" line.long 0xD98 "GFXMMU_LUT947L,GFXMMU LUT entry 947 low" hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD9C "GFXMMU_LUT947H,GFXMMU LUT entry 947 high" hexmask.long.tbyte 0xD9C 4.--21. 1. "LO,Line offset" line.long 0xDA0 "GFXMMU_LUT948L,GFXMMU LUT entry 948 low" hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDA4 "GFXMMU_LUT948H,GFXMMU LUT entry 948 high" hexmask.long.tbyte 0xDA4 4.--21. 1. "LO,Line offset" line.long 0xDA8 "GFXMMU_LUT949L,GFXMMU LUT entry 949 low" hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDAC "GFXMMU_LUT949H,GFXMMU LUT entry 949 high" hexmask.long.tbyte 0xDAC 4.--21. 1. "LO,Line offset" line.long 0xDB0 "GFXMMU_LUT950L,GFXMMU LUT entry 950 low" hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDB4 "GFXMMU_LUT950H,GFXMMU LUT entry 950 high" hexmask.long.tbyte 0xDB4 4.--21. 1. "LO,Line offset" line.long 0xDB8 "GFXMMU_LUT951L,GFXMMU LUT entry 951 low" hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDBC "GFXMMU_LUT951H,GFXMMU LUT entry 951 high" hexmask.long.tbyte 0xDBC 4.--21. 1. "LO,Line offset" line.long 0xDC0 "GFXMMU_LUT952L,GFXMMU LUT entry 952 low" hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC4 "GFXMMU_LUT952H,GFXMMU LUT entry 952 high" hexmask.long.tbyte 0xDC4 4.--21. 1. "LO,Line offset" line.long 0xDC8 "GFXMMU_LUT953L,GFXMMU LUT entry 953 low" hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDCC "GFXMMU_LUT953H,GFXMMU LUT entry 953 high" hexmask.long.tbyte 0xDCC 4.--21. 1. "LO,Line offset" line.long 0xDD0 "GFXMMU_LUT954L,GFXMMU LUT entry 954 low" hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDD4 "GFXMMU_LUT954H,GFXMMU LUT entry 954 high" hexmask.long.tbyte 0xDD4 4.--21. 1. "LO,Line offset" line.long 0xDD8 "GFXMMU_LUT955L,GFXMMU LUT entry 955 low" hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDDC "GFXMMU_LUT955H,GFXMMU LUT entry 955 high" hexmask.long.tbyte 0xDDC 4.--21. 1. "LO,Line offset" line.long 0xDE0 "GFXMMU_LUT956L,GFXMMU LUT entry 956 low" hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDE4 "GFXMMU_LUT956H,GFXMMU LUT entry 956 high" hexmask.long.tbyte 0xDE4 4.--21. 1. "LO,Line offset" line.long 0xDE8 "GFXMMU_LUT957L,GFXMMU LUT entry 957 low" hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDEC "GFXMMU_LUT957H,GFXMMU LUT entry 957 high" hexmask.long.tbyte 0xDEC 4.--21. 1. "LO,Line offset" line.long 0xDF0 "GFXMMU_LUT958L,GFXMMU LUT entry 958 low" hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDF4 "GFXMMU_LUT958H,GFXMMU LUT entry 958 high" hexmask.long.tbyte 0xDF4 4.--21. 1. "LO,Line offset" line.long 0xDF8 "GFXMMU_LUT959L,GFXMMU LUT entry 959 low" hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDFC "GFXMMU_LUT959H,GFXMMU LUT entry 959 high" hexmask.long.tbyte 0xDFC 4.--21. 1. "LO,Line offset" line.long 0xE00 "GFXMMU_LUT960L,GFXMMU LUT entry 960 low" hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE04 "GFXMMU_LUT960H,GFXMMU LUT entry 960 high" hexmask.long.tbyte 0xE04 4.--21. 1. "LO,Line offset" line.long 0xE08 "GFXMMU_LUT961L,GFXMMU LUT entry 961 low" hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE0C "GFXMMU_LUT961H,GFXMMU LUT entry 961 high" hexmask.long.tbyte 0xE0C 4.--21. 1. "LO,Line offset" line.long 0xE10 "GFXMMU_LUT962L,GFXMMU LUT entry 962 low" hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE14 "GFXMMU_LUT962H,GFXMMU LUT entry 962 high" hexmask.long.tbyte 0xE14 4.--21. 1. "LO,Line offset" line.long 0xE18 "GFXMMU_LUT963L,GFXMMU LUT entry 963 low" hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE1C "GFXMMU_LUT963H,GFXMMU LUT entry 963 high" hexmask.long.tbyte 0xE1C 4.--21. 1. "LO,Line offset" line.long 0xE20 "GFXMMU_LUT964L,GFXMMU LUT entry 964 low" hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE24 "GFXMMU_LUT964H,GFXMMU LUT entry 964 high" hexmask.long.tbyte 0xE24 4.--21. 1. "LO,Line offset" line.long 0xE28 "GFXMMU_LUT965L,GFXMMU LUT entry 965 low" hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE2C "GFXMMU_LUT965H,GFXMMU LUT entry 965 high" hexmask.long.tbyte 0xE2C 4.--21. 1. "LO,Line offset" line.long 0xE30 "GFXMMU_LUT966L,GFXMMU LUT entry 966 low" hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE34 "GFXMMU_LUT966H,GFXMMU LUT entry 966 high" hexmask.long.tbyte 0xE34 4.--21. 1. "LO,Line offset" line.long 0xE38 "GFXMMU_LUT967L,GFXMMU LUT entry 967 low" hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE3C "GFXMMU_LUT967H,GFXMMU LUT entry 967 high" hexmask.long.tbyte 0xE3C 4.--21. 1. "LO,Line offset" line.long 0xE40 "GFXMMU_LUT968L,GFXMMU LUT entry 968 low" hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE44 "GFXMMU_LUT968H,GFXMMU LUT entry 968 high" hexmask.long.tbyte 0xE44 4.--21. 1. "LO,Line offset" line.long 0xE48 "GFXMMU_LUT969L,GFXMMU LUT entry 969 low" hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4C "GFXMMU_LUT969H,GFXMMU LUT entry 969 high" hexmask.long.tbyte 0xE4C 4.--21. 1. "LO,Line offset" line.long 0xE50 "GFXMMU_LUT970L,GFXMMU LUT entry 970 low" hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE54 "GFXMMU_LUT970H,GFXMMU LUT entry 970 high" hexmask.long.tbyte 0xE54 4.--21. 1. "LO,Line offset" line.long 0xE58 "GFXMMU_LUT971L,GFXMMU LUT entry 971 low" hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE5C "GFXMMU_LUT971H,GFXMMU LUT entry 971 high" hexmask.long.tbyte 0xE5C 4.--21. 1. "LO,Line offset" line.long 0xE60 "GFXMMU_LUT972L,GFXMMU LUT entry 972 low" hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE64 "GFXMMU_LUT972H,GFXMMU LUT entry 972 high" hexmask.long.tbyte 0xE64 4.--21. 1. "LO,Line offset" line.long 0xE68 "GFXMMU_LUT973L,GFXMMU LUT entry 973 low" hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE6C "GFXMMU_LUT973H,GFXMMU LUT entry 973 high" hexmask.long.tbyte 0xE6C 4.--21. 1. "LO,Line offset" line.long 0xE70 "GFXMMU_LUT974L,GFXMMU LUT entry 974 low" hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE74 "GFXMMU_LUT974H,GFXMMU LUT entry 974 high" hexmask.long.tbyte 0xE74 4.--21. 1. "LO,Line offset" line.long 0xE78 "GFXMMU_LUT975L,GFXMMU LUT entry 975 low" hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE7C "GFXMMU_LUT975H,GFXMMU LUT entry 975 high" hexmask.long.tbyte 0xE7C 4.--21. 1. "LO,Line offset" line.long 0xE80 "GFXMMU_LUT976L,GFXMMU LUT entry 976 low" hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE84 "GFXMMU_LUT976H,GFXMMU LUT entry 976 high" hexmask.long.tbyte 0xE84 4.--21. 1. "LO,Line offset" line.long 0xE88 "GFXMMU_LUT977L,GFXMMU LUT entry 977 low" hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE8C "GFXMMU_LUT977H,GFXMMU LUT entry 977 high" hexmask.long.tbyte 0xE8C 4.--21. 1. "LO,Line offset" line.long 0xE90 "GFXMMU_LUT978L,GFXMMU LUT entry 978 low" hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE94 "GFXMMU_LUT978H,GFXMMU LUT entry 978 high" hexmask.long.tbyte 0xE94 4.--21. 1. "LO,Line offset" line.long 0xE98 "GFXMMU_LUT979L,GFXMMU LUT entry 979 low" hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE9C "GFXMMU_LUT979H,GFXMMU LUT entry 979 high" hexmask.long.tbyte 0xE9C 4.--21. 1. "LO,Line offset" line.long 0xEA0 "GFXMMU_LUT980L,GFXMMU LUT entry 980 low" hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEA4 "GFXMMU_LUT980H,GFXMMU LUT entry 980 high" hexmask.long.tbyte 0xEA4 4.--21. 1. "LO,Line offset" line.long 0xEA8 "GFXMMU_LUT981L,GFXMMU LUT entry 981 low" hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEAC "GFXMMU_LUT981H,GFXMMU LUT entry 981 high" hexmask.long.tbyte 0xEAC 4.--21. 1. "LO,Line offset" line.long 0xEB0 "GFXMMU_LUT982L,GFXMMU LUT entry 982 low" hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEB4 "GFXMMU_LUT982H,GFXMMU LUT entry 982 high" hexmask.long.tbyte 0xEB4 4.--21. 1. "LO,Line offset" line.long 0xEB8 "GFXMMU_LUT983L,GFXMMU LUT entry 983 low" hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEBC "GFXMMU_LUT983H,GFXMMU LUT entry 983 high" hexmask.long.tbyte 0xEBC 4.--21. 1. "LO,Line offset" line.long 0xEC0 "GFXMMU_LUT984L,GFXMMU LUT entry 984 low" hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC4 "GFXMMU_LUT984H,GFXMMU LUT entry 984 high" hexmask.long.tbyte 0xEC4 4.--21. 1. "LO,Line offset" line.long 0xEC8 "GFXMMU_LUT985L,GFXMMU LUT entry 985 low" hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xECC "GFXMMU_LUT985H,GFXMMU LUT entry 985 high" hexmask.long.tbyte 0xECC 4.--21. 1. "LO,Line offset" line.long 0xED0 "GFXMMU_LUT986L,GFXMMU LUT entry 986 low" hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xED0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xED4 "GFXMMU_LUT986H,GFXMMU LUT entry 986 high" hexmask.long.tbyte 0xED4 4.--21. 1. "LO,Line offset" line.long 0xED8 "GFXMMU_LUT987L,GFXMMU LUT entry 987 low" hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xED8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEDC "GFXMMU_LUT987H,GFXMMU LUT entry 987 high" hexmask.long.tbyte 0xEDC 4.--21. 1. "LO,Line offset" line.long 0xEE0 "GFXMMU_LUT988L,GFXMMU LUT entry 988 low" hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEE4 "GFXMMU_LUT988H,GFXMMU LUT entry 988 high" hexmask.long.tbyte 0xEE4 4.--21. 1. "LO,Line offset" line.long 0xEE8 "GFXMMU_LUT989L,GFXMMU LUT entry 989 low" hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEEC "GFXMMU_LUT989H,GFXMMU LUT entry 989 high" hexmask.long.tbyte 0xEEC 4.--21. 1. "LO,Line offset" line.long 0xEF0 "GFXMMU_LUT990L,GFXMMU LUT entry 990 low" hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEF4 "GFXMMU_LUT990H,GFXMMU LUT entry 990 high" hexmask.long.tbyte 0xEF4 4.--21. 1. "LO,Line offset" line.long 0xEF8 "GFXMMU_LUT991L,GFXMMU LUT entry 991 low" hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEFC "GFXMMU_LUT991H,GFXMMU LUT entry 991 high" hexmask.long.tbyte 0xEFC 4.--21. 1. "LO,Line offset" line.long 0xF00 "GFXMMU_LUT992L,GFXMMU LUT entry 992 low" hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF04 "GFXMMU_LUT992H,GFXMMU LUT entry 992 high" hexmask.long.tbyte 0xF04 4.--21. 1. "LO,Line offset" line.long 0xF08 "GFXMMU_LUT993L,GFXMMU LUT entry 993 low" hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF0C "GFXMMU_LUT993H,GFXMMU LUT entry 993 high" hexmask.long.tbyte 0xF0C 4.--21. 1. "LO,Line offset" line.long 0xF10 "GFXMMU_LUT994L,GFXMMU LUT entry 994 low" hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF14 "GFXMMU_LUT994H,GFXMMU LUT entry 994 high" hexmask.long.tbyte 0xF14 4.--21. 1. "LO,Line offset" line.long 0xF18 "GFXMMU_LUT995L,GFXMMU LUT entry 995 low" hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF1C "GFXMMU_LUT995H,GFXMMU LUT entry 995 high" hexmask.long.tbyte 0xF1C 4.--21. 1. "LO,Line offset" line.long 0xF20 "GFXMMU_LUT996L,GFXMMU LUT entry 996 low" hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF24 "GFXMMU_LUT996H,GFXMMU LUT entry 996 high" hexmask.long.tbyte 0xF24 4.--21. 1. "LO,Line offset" line.long 0xF28 "GFXMMU_LUT997L,GFXMMU LUT entry 997 low" hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF2C "GFXMMU_LUT997H,GFXMMU LUT entry 997 high" hexmask.long.tbyte 0xF2C 4.--21. 1. "LO,Line offset" line.long 0xF30 "GFXMMU_LUT998L,GFXMMU LUT entry 998 low" hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF34 "GFXMMU_LUT998H,GFXMMU LUT entry 998 high" hexmask.long.tbyte 0xF34 4.--21. 1. "LO,Line offset" line.long 0xF38 "GFXMMU_LUT999L,GFXMMU LUT entry 999 low" hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF3C "GFXMMU_LUT999H,GFXMMU LUT entry 999 high" hexmask.long.tbyte 0xF3C 4.--21. 1. "LO,Line offset" line.long 0xF40 "GFXMMU_LUT1000L,GFXMMU LUT entry 1000 low" hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF44 "GFXMMU_LUT1000H,GFXMMU LUT entry 1000 high" hexmask.long.tbyte 0xF44 4.--21. 1. "LO,Line offset" line.long 0xF48 "GFXMMU_LUT1001L,GFXMMU LUT entry 1001 low" hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4C "GFXMMU_LUT1001H,GFXMMU LUT entry 1001 high" hexmask.long.tbyte 0xF4C 4.--21. 1. "LO,Line offset" line.long 0xF50 "GFXMMU_LUT1002L,GFXMMU LUT entry 1002 low" hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF54 "GFXMMU_LUT1002H,GFXMMU LUT entry 1002 high" hexmask.long.tbyte 0xF54 4.--21. 1. "LO,Line offset" line.long 0xF58 "GFXMMU_LUT1003L,GFXMMU LUT entry 1003 low" hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF5C "GFXMMU_LUT1003H,GFXMMU LUT entry 1003 high" hexmask.long.tbyte 0xF5C 4.--21. 1. "LO,Line offset" line.long 0xF60 "GFXMMU_LUT1004L,GFXMMU LUT entry 1004 low" hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF64 "GFXMMU_LUT1004H,GFXMMU LUT entry 1004 high" hexmask.long.tbyte 0xF64 4.--21. 1. "LO,Line offset" line.long 0xF68 "GFXMMU_LUT1005L,GFXMMU LUT entry 1005 low" hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF6C "GFXMMU_LUT1005H,GFXMMU LUT entry 1005 high" hexmask.long.tbyte 0xF6C 4.--21. 1. "LO,Line offset" line.long 0xF70 "GFXMMU_LUT1006L,GFXMMU LUT entry 1006 low" hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF74 "GFXMMU_LUT1006H,GFXMMU LUT entry 1006 high" hexmask.long.tbyte 0xF74 4.--21. 1. "LO,Line offset" line.long 0xF78 "GFXMMU_LUT1007L,GFXMMU LUT entry 1007 low" hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF7C "GFXMMU_LUT1007H,GFXMMU LUT entry 1007 high" hexmask.long.tbyte 0xF7C 4.--21. 1. "LO,Line offset" line.long 0xF80 "GFXMMU_LUT1008L,GFXMMU LUT entry 1008 low" hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF84 "GFXMMU_LUT1008H,GFXMMU LUT entry 1008 high" hexmask.long.tbyte 0xF84 4.--21. 1. "LO,Line offset" line.long 0xF88 "GFXMMU_LUT1009L,GFXMMU LUT entry 1009 low" hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF8C "GFXMMU_LUT1009H,GFXMMU LUT entry 1009 high" hexmask.long.tbyte 0xF8C 4.--21. 1. "LO,Line offset" line.long 0xF90 "GFXMMU_LUT1010L,GFXMMU LUT entry 1010 low" hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF94 "GFXMMU_LUT1010H,GFXMMU LUT entry 1010 high" hexmask.long.tbyte 0xF94 4.--21. 1. "LO,Line offset" line.long 0xF98 "GFXMMU_LUT1011L,GFXMMU LUT entry 1011 low" hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF9C "GFXMMU_LUT1011H,GFXMMU LUT entry 1011 high" hexmask.long.tbyte 0xF9C 4.--21. 1. "LO,Line offset" line.long 0xFA0 "GFXMMU_LUT1012L,GFXMMU LUT entry 1012 low" hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFA4 "GFXMMU_LUT1012H,GFXMMU LUT entry 1012 high" hexmask.long.tbyte 0xFA4 4.--21. 1. "LO,Line offset" line.long 0xFA8 "GFXMMU_LUT1013L,GFXMMU LUT entry 1013 low" hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFAC "GFXMMU_LUT1013H,GFXMMU LUT entry 1013 high" hexmask.long.tbyte 0xFAC 4.--21. 1. "LO,Line offset" line.long 0xFB0 "GFXMMU_LUT1014L,GFXMMU LUT entry 1014 low" hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFB4 "GFXMMU_LUT1014H,GFXMMU LUT entry 1014 high" hexmask.long.tbyte 0xFB4 4.--21. 1. "LO,Line offset" line.long 0xFB8 "GFXMMU_LUT1015L,GFXMMU LUT entry 1015 low" hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFBC "GFXMMU_LUT1015H,GFXMMU LUT entry 1015 high" hexmask.long.tbyte 0xFBC 4.--21. 1. "LO,Line offset" line.long 0xFC0 "GFXMMU_LUT1016L,GFXMMU LUT entry 1016 low" hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC4 "GFXMMU_LUT1016H,GFXMMU LUT entry 1016 high" hexmask.long.tbyte 0xFC4 4.--21. 1. "LO,Line offset" line.long 0xFC8 "GFXMMU_LUT1017L,GFXMMU LUT entry 1017 low" hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFCC "GFXMMU_LUT1017H,GFXMMU LUT entry 1017 high" hexmask.long.tbyte 0xFCC 4.--21. 1. "LO,Line offset" line.long 0xFD0 "GFXMMU_LUT1018L,GFXMMU LUT entry 1018 low" hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFD4 "GFXMMU_LUT1018H,GFXMMU LUT entry 1018 high" hexmask.long.tbyte 0xFD4 4.--21. 1. "LO,Line offset" line.long 0xFD8 "GFXMMU_LUT1019L,GFXMMU LUT entry 1019 low" hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFDC "GFXMMU_LUT1019H,GFXMMU LUT entry 1019 high" hexmask.long.tbyte 0xFDC 4.--21. 1. "LO,Line offset" line.long 0xFE0 "GFXMMU_LUT1020L,GFXMMU LUT entry 1020 low" hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFE4 "GFXMMU_LUT1020H,GFXMMU LUT entry 1020 high" hexmask.long.tbyte 0xFE4 4.--21. 1. "LO,Line offset" line.long 0xFE8 "GFXMMU_LUT1021L,GFXMMU LUT entry 1021 low" hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFEC "GFXMMU_LUT1021H,GFXMMU LUT entry 1021 high" hexmask.long.tbyte 0xFEC 4.--21. 1. "LO,Line offset" line.long 0xFF0 "GFXMMU_LUT1022L,GFXMMU LUT entry 1022 low" hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFF4 "GFXMMU_LUT1022H,GFXMMU LUT entry 1022 high" hexmask.long.tbyte 0xFF4 4.--21. 1. "LO,Line offset" line.long 0xFF8 "GFXMMU_LUT1023L,GFXMMU LUT entry 1023 low" hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFFC "GFXMMU_LUT1023H,GFXMMU LUT entry 1023 high" hexmask.long.tbyte 0xFFC 4.--21. 1. "LO,Line offset" tree.end tree "SEC_GFXMMU" base ad:0x5002C000 group.long 0x0++0x3 line.long 0x0 "GFXMMU_CR,GFXMMU configuration register" bitfld.long 0x0 17. "OB,Outter bufferability" "0: No bufferable,1: Bufferable" bitfld.long 0x0 16. "OC,Outter cachability" "0: No cachable,1: Cachable" newline bitfld.long 0x0 12. "PD,Prefetch disable" "0: Prefetch enable,1: Prefetch disable" bitfld.long 0x0 11. "FC,Force caching" "0: Caching not forced,1: Caching forced" newline bitfld.long 0x0 9.--10. "CLB,Cache lock buffer" "0: Cache locked on buffer 0,1: Cache locked on buffer 1,2: Cache locked on buffer 2,3: Cache locked on buffer 3" bitfld.long 0x0 8. "CL,Cache lock" "0: Cache not locked,1: Cache locked to a buffer" newline bitfld.long 0x0 7. "CE,Cache enable" "0: Cache disable,1: Cache enable" bitfld.long 0x0 6. "BM192,192 Block mode" "0: 256 blocks per line,1: 192 blocks per line" newline bitfld.long 0x0 4. "AMEIE,AHB master error interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 3. "B3OIE,Buffer 3 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 2. "B2OIE,Buffer 2 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 1. "B1OIE,Buffer 1 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 0. "B0OIE,Buffer 0 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" rgroup.long 0x4++0x3 line.long 0x0 "GFXMMU_SR,GFXMMU status register" bitfld.long 0x0 4. "AMEF,AHB master error flag" "0,1" bitfld.long 0x0 3. "B3OF,Buffer 3 overflow flag" "0,1" newline bitfld.long 0x0 2. "B2OF,Buffer 2 overflow flag" "0,1" bitfld.long 0x0 1. "B1OF,Buffer 1 overflow flag" "0,1" newline bitfld.long 0x0 0. "B0OF,Buffer 0 overflow flag" "0,1" group.long 0x8++0xB line.long 0x0 "GFXMMU_FCR,GFXMMU flag clear register" bitfld.long 0x0 4. "CAMEF,Clear AHB master error flag" "0,1" bitfld.long 0x0 3. "CB3OF,Clear buffer 3 overflow flag" "0,1" newline bitfld.long 0x0 2. "CB2OF,Clear buffer 2 overflow flag" "0,1" bitfld.long 0x0 1. "CB1OF,Clear buffer 1 overflow flag" "0,1" newline bitfld.long 0x0 0. "CB0OF,Clear buffer 0 overflow flag" "0,1" line.long 0x4 "GFXMMU_CCR,GFXMMU cache control register" bitfld.long 0x4 1. "FI,Force invalidate" "0: Invalidation process complete,1: Force invalidation/invalidation process on going" bitfld.long 0x4 0. "FF,Force flush" "0: Flushing process complete,1: Force flush/flushing process on going" line.long 0x8 "GFXMMU_DVR,GFXMMU default value register" hexmask.long 0x8 0.--31. 1. "DV,Default value" group.long 0x20++0xF line.long 0x0 "GFXMMU_B0CR,GFXMMU buffer 0 configuration register" hexmask.long.word 0x0 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x0 4.--22. 1. "PBO,Physical buffer offset" line.long 0x4 "GFXMMU_B1CR,GFXMMU buffer 1 configuration register" hexmask.long.word 0x4 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x4 4.--22. 1. "PBO,Physical buffer offset" line.long 0x8 "GFXMMU_B2CR,GFXMMU buffer 2 configuration register" hexmask.long.word 0x8 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x8 4.--22. 1. "PBO,Physical buffer offset" line.long 0xC "GFXMMU_B3CR,GFXMMU buffer 3 configuration register" hexmask.long.word 0xC 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0xC 4.--22. 1. "PBO,Physical buffer offset" group.long 0x1000++0xFFF line.long 0x0 "GFXMMU_LUT0L,GFXMMU LUT entry 0 low" hexmask.long.byte 0x0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4 "GFXMMU_LUT0H,GFXMMU LUT entry 0 high" hexmask.long.tbyte 0x4 4.--21. 1. "LO,Line offset" line.long 0x8 "GFXMMU_LUT1L,GFXMMU LUT entry 1 low" hexmask.long.byte 0x8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC "GFXMMU_LUT1H,GFXMMU LUT entry 1 high" hexmask.long.tbyte 0xC 4.--21. 1. "LO,Line offset" line.long 0x10 "GFXMMU_LUT2L,GFXMMU LUT entry 2 low" hexmask.long.byte 0x10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14 "GFXMMU_LUT2H,GFXMMU LUT entry 2 high" hexmask.long.tbyte 0x14 4.--21. 1. "LO,Line offset" line.long 0x18 "GFXMMU_LUT3L,GFXMMU LUT entry 3 low" hexmask.long.byte 0x18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C "GFXMMU_LUT3H,GFXMMU LUT entry 3 high" hexmask.long.tbyte 0x1C 4.--21. 1. "LO,Line offset" line.long 0x20 "GFXMMU_LUT4L,GFXMMU LUT entry 4 low" hexmask.long.byte 0x20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24 "GFXMMU_LUT4H,GFXMMU LUT entry 4 high" hexmask.long.tbyte 0x24 4.--21. 1. "LO,Line offset" line.long 0x28 "GFXMMU_LUT5L,GFXMMU LUT entry 5 low" hexmask.long.byte 0x28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C "GFXMMU_LUT5H,GFXMMU LUT entry 5 high" hexmask.long.tbyte 0x2C 4.--21. 1. "LO,Line offset" line.long 0x30 "GFXMMU_LUT6L,GFXMMU LUT entry 6 low" hexmask.long.byte 0x30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34 "GFXMMU_LUT6H,GFXMMU LUT entry 6 high" hexmask.long.tbyte 0x34 4.--21. 1. "LO,Line offset" line.long 0x38 "GFXMMU_LUT7L,GFXMMU LUT entry 7 low" hexmask.long.byte 0x38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C "GFXMMU_LUT7H,GFXMMU LUT entry 7 high" hexmask.long.tbyte 0x3C 4.--21. 1. "LO,Line offset" line.long 0x40 "GFXMMU_LUT8L,GFXMMU LUT entry 8 low" hexmask.long.byte 0x40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44 "GFXMMU_LUT8H,GFXMMU LUT entry 8 high" hexmask.long.tbyte 0x44 4.--21. 1. "LO,Line offset" line.long 0x48 "GFXMMU_LUT9L,GFXMMU LUT entry 9 low" hexmask.long.byte 0x48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C "GFXMMU_LUT9H,GFXMMU LUT entry 9 high" hexmask.long.tbyte 0x4C 4.--21. 1. "LO,Line offset" line.long 0x50 "GFXMMU_LUT10L,GFXMMU LUT entry 10 low" hexmask.long.byte 0x50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54 "GFXMMU_LUT10H,GFXMMU LUT entry 10 high" hexmask.long.tbyte 0x54 4.--21. 1. "LO,Line offset" line.long 0x58 "GFXMMU_LUT11L,GFXMMU LUT entry 11 low" hexmask.long.byte 0x58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C "GFXMMU_LUT11H,GFXMMU LUT entry 11 high" hexmask.long.tbyte 0x5C 4.--21. 1. "LO,Line offset" line.long 0x60 "GFXMMU_LUT12L,GFXMMU LUT entry 12 low" hexmask.long.byte 0x60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64 "GFXMMU_LUT12H,GFXMMU LUT entry 12 high" hexmask.long.tbyte 0x64 4.--21. 1. "LO,Line offset" line.long 0x68 "GFXMMU_LUT13L,GFXMMU LUT entry 13 low" hexmask.long.byte 0x68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C "GFXMMU_LUT13H,GFXMMU LUT entry 13 high" hexmask.long.tbyte 0x6C 4.--21. 1. "LO,Line offset" line.long 0x70 "GFXMMU_LUT14L,GFXMMU LUT entry 14 low" hexmask.long.byte 0x70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74 "GFXMMU_LUT14H,GFXMMU LUT entry 14 high" hexmask.long.tbyte 0x74 4.--21. 1. "LO,Line offset" line.long 0x78 "GFXMMU_LUT15L,GFXMMU LUT entry 15 low" hexmask.long.byte 0x78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C "GFXMMU_LUT15H,GFXMMU LUT entry 15 high" hexmask.long.tbyte 0x7C 4.--21. 1. "LO,Line offset" line.long 0x80 "GFXMMU_LUT16L,GFXMMU LUT entry 16 low" hexmask.long.byte 0x80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84 "GFXMMU_LUT16H,GFXMMU LUT entry 16 high" hexmask.long.tbyte 0x84 4.--21. 1. "LO,Line offset" line.long 0x88 "GFXMMU_LUT17L,GFXMMU LUT entry 17 low" hexmask.long.byte 0x88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C "GFXMMU_LUT17H,GFXMMU LUT entry 17 high" hexmask.long.tbyte 0x8C 4.--21. 1. "LO,Line offset" line.long 0x90 "GFXMMU_LUT18L,GFXMMU LUT entry 18 low" hexmask.long.byte 0x90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94 "GFXMMU_LUT18H,GFXMMU LUT entry 18 high" hexmask.long.tbyte 0x94 4.--21. 1. "LO,Line offset" line.long 0x98 "GFXMMU_LUT19L,GFXMMU LUT entry 19 low" hexmask.long.byte 0x98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C "GFXMMU_LUT19H,GFXMMU LUT entry 19 high" hexmask.long.tbyte 0x9C 4.--21. 1. "LO,Line offset" line.long 0xA0 "GFXMMU_LUT20L,GFXMMU LUT entry 20 low" hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4 "GFXMMU_LUT20H,GFXMMU LUT entry 20 high" hexmask.long.tbyte 0xA4 4.--21. 1. "LO,Line offset" line.long 0xA8 "GFXMMU_LUT21L,GFXMMU LUT entry 21 low" hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC "GFXMMU_LUT21H,GFXMMU LUT entry 21 high" hexmask.long.tbyte 0xAC 4.--21. 1. "LO,Line offset" line.long 0xB0 "GFXMMU_LUT22L,GFXMMU LUT entry 22 low" hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4 "GFXMMU_LUT22H,GFXMMU LUT entry 22 high" hexmask.long.tbyte 0xB4 4.--21. 1. "LO,Line offset" line.long 0xB8 "GFXMMU_LUT23L,GFXMMU LUT entry 23 low" hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC "GFXMMU_LUT23H,GFXMMU LUT entry 23 high" hexmask.long.tbyte 0xBC 4.--21. 1. "LO,Line offset" line.long 0xC0 "GFXMMU_LUT24L,GFXMMU LUT entry 24 low" hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4 "GFXMMU_LUT24H,GFXMMU LUT entry 24 high" hexmask.long.tbyte 0xC4 4.--21. 1. "LO,Line offset" line.long 0xC8 "GFXMMU_LUT25L,GFXMMU LUT entry 25 low" hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC "GFXMMU_LUT25H,GFXMMU LUT entry 25 high" hexmask.long.tbyte 0xCC 4.--21. 1. "LO,Line offset" line.long 0xD0 "GFXMMU_LUT26L,GFXMMU LUT entry 26 low" hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4 "GFXMMU_LUT26H,GFXMMU LUT entry 26 high" hexmask.long.tbyte 0xD4 4.--21. 1. "LO,Line offset" line.long 0xD8 "GFXMMU_LUT27L,GFXMMU LUT entry 27 low" hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC "GFXMMU_LUT27H,GFXMMU LUT entry 27 high" hexmask.long.tbyte 0xDC 4.--21. 1. "LO,Line offset" line.long 0xE0 "GFXMMU_LUT28L,GFXMMU LUT entry 28 low" hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4 "GFXMMU_LUT28H,GFXMMU LUT entry 28 high" hexmask.long.tbyte 0xE4 4.--21. 1. "LO,Line offset" line.long 0xE8 "GFXMMU_LUT29L,GFXMMU LUT entry 29 low" hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC "GFXMMU_LUT29H,GFXMMU LUT entry 29 high" hexmask.long.tbyte 0xEC 4.--21. 1. "LO,Line offset" line.long 0xF0 "GFXMMU_LUT30L,GFXMMU LUT entry 30 low" hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4 "GFXMMU_LUT30H,GFXMMU LUT entry 30 high" hexmask.long.tbyte 0xF4 4.--21. 1. "LO,Line offset" line.long 0xF8 "GFXMMU_LUT31L,GFXMMU LUT entry 31 low" hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC "GFXMMU_LUT31H,GFXMMU LUT entry 31 high" hexmask.long.tbyte 0xFC 4.--21. 1. "LO,Line offset" line.long 0x100 "GFXMMU_LUT32L,GFXMMU LUT entry 32 low" hexmask.long.byte 0x100 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x100 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x104 "GFXMMU_LUT32H,GFXMMU LUT entry 32 high" hexmask.long.tbyte 0x104 4.--21. 1. "LO,Line offset" line.long 0x108 "GFXMMU_LUT33L,GFXMMU LUT entry 33 low" hexmask.long.byte 0x108 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x108 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x10C "GFXMMU_LUT33H,GFXMMU LUT entry 33 high" hexmask.long.tbyte 0x10C 4.--21. 1. "LO,Line offset" line.long 0x110 "GFXMMU_LUT34L,GFXMMU LUT entry 34 low" hexmask.long.byte 0x110 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x110 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x114 "GFXMMU_LUT34H,GFXMMU LUT entry 34 high" hexmask.long.tbyte 0x114 4.--21. 1. "LO,Line offset" line.long 0x118 "GFXMMU_LUT35L,GFXMMU LUT entry 35 low" hexmask.long.byte 0x118 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x118 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x11C "GFXMMU_LUT35H,GFXMMU LUT entry 35 high" hexmask.long.tbyte 0x11C 4.--21. 1. "LO,Line offset" line.long 0x120 "GFXMMU_LUT36L,GFXMMU LUT entry 36 low" hexmask.long.byte 0x120 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x120 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x124 "GFXMMU_LUT36H,GFXMMU LUT entry 36 high" hexmask.long.tbyte 0x124 4.--21. 1. "LO,Line offset" line.long 0x128 "GFXMMU_LUT37L,GFXMMU LUT entry 37 low" hexmask.long.byte 0x128 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x128 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x12C "GFXMMU_LUT37H,GFXMMU LUT entry 37 high" hexmask.long.tbyte 0x12C 4.--21. 1. "LO,Line offset" line.long 0x130 "GFXMMU_LUT38L,GFXMMU LUT entry 38 low" hexmask.long.byte 0x130 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x130 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x134 "GFXMMU_LUT38H,GFXMMU LUT entry 38 high" hexmask.long.tbyte 0x134 4.--21. 1. "LO,Line offset" line.long 0x138 "GFXMMU_LUT39L,GFXMMU LUT entry 39 low" hexmask.long.byte 0x138 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x138 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x13C "GFXMMU_LUT39H,GFXMMU LUT entry 39 high" hexmask.long.tbyte 0x13C 4.--21. 1. "LO,Line offset" line.long 0x140 "GFXMMU_LUT40L,GFXMMU LUT entry 40 low" hexmask.long.byte 0x140 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x140 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x144 "GFXMMU_LUT40H,GFXMMU LUT entry 40 high" hexmask.long.tbyte 0x144 4.--21. 1. "LO,Line offset" line.long 0x148 "GFXMMU_LUT41L,GFXMMU LUT entry 41 low" hexmask.long.byte 0x148 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x148 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14C "GFXMMU_LUT41H,GFXMMU LUT entry 41 high" hexmask.long.tbyte 0x14C 4.--21. 1. "LO,Line offset" line.long 0x150 "GFXMMU_LUT42L,GFXMMU LUT entry 42 low" hexmask.long.byte 0x150 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x150 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x154 "GFXMMU_LUT42H,GFXMMU LUT entry 42 high" hexmask.long.tbyte 0x154 4.--21. 1. "LO,Line offset" line.long 0x158 "GFXMMU_LUT43L,GFXMMU LUT entry 43 low" hexmask.long.byte 0x158 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x158 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x15C "GFXMMU_LUT43H,GFXMMU LUT entry 43 high" hexmask.long.tbyte 0x15C 4.--21. 1. "LO,Line offset" line.long 0x160 "GFXMMU_LUT44L,GFXMMU LUT entry 44 low" hexmask.long.byte 0x160 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x160 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x164 "GFXMMU_LUT44H,GFXMMU LUT entry 44 high" hexmask.long.tbyte 0x164 4.--21. 1. "LO,Line offset" line.long 0x168 "GFXMMU_LUT45L,GFXMMU LUT entry 45 low" hexmask.long.byte 0x168 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x168 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x16C "GFXMMU_LUT45H,GFXMMU LUT entry 45 high" hexmask.long.tbyte 0x16C 4.--21. 1. "LO,Line offset" line.long 0x170 "GFXMMU_LUT46L,GFXMMU LUT entry 46 low" hexmask.long.byte 0x170 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x170 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x174 "GFXMMU_LUT46H,GFXMMU LUT entry 46 high" hexmask.long.tbyte 0x174 4.--21. 1. "LO,Line offset" line.long 0x178 "GFXMMU_LUT47L,GFXMMU LUT entry 47 low" hexmask.long.byte 0x178 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x178 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x17C "GFXMMU_LUT47H,GFXMMU LUT entry 47 high" hexmask.long.tbyte 0x17C 4.--21. 1. "LO,Line offset" line.long 0x180 "GFXMMU_LUT48L,GFXMMU LUT entry 48 low" hexmask.long.byte 0x180 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x180 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x184 "GFXMMU_LUT48H,GFXMMU LUT entry 48 high" hexmask.long.tbyte 0x184 4.--21. 1. "LO,Line offset" line.long 0x188 "GFXMMU_LUT49L,GFXMMU LUT entry 49 low" hexmask.long.byte 0x188 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x188 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x18C "GFXMMU_LUT49H,GFXMMU LUT entry 49 high" hexmask.long.tbyte 0x18C 4.--21. 1. "LO,Line offset" line.long 0x190 "GFXMMU_LUT50L,GFXMMU LUT entry 50 low" hexmask.long.byte 0x190 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x190 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x194 "GFXMMU_LUT50H,GFXMMU LUT entry 50 high" hexmask.long.tbyte 0x194 4.--21. 1. "LO,Line offset" line.long 0x198 "GFXMMU_LUT51L,GFXMMU LUT entry 51 low" hexmask.long.byte 0x198 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x198 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x19C "GFXMMU_LUT51H,GFXMMU LUT entry 51 high" hexmask.long.tbyte 0x19C 4.--21. 1. "LO,Line offset" line.long 0x1A0 "GFXMMU_LUT52L,GFXMMU LUT entry 52 low" hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1A4 "GFXMMU_LUT52H,GFXMMU LUT entry 52 high" hexmask.long.tbyte 0x1A4 4.--21. 1. "LO,Line offset" line.long 0x1A8 "GFXMMU_LUT53L,GFXMMU LUT entry 53 low" hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1AC "GFXMMU_LUT53H,GFXMMU LUT entry 53 high" hexmask.long.tbyte 0x1AC 4.--21. 1. "LO,Line offset" line.long 0x1B0 "GFXMMU_LUT54L,GFXMMU LUT entry 54 low" hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1B4 "GFXMMU_LUT54H,GFXMMU LUT entry 54 high" hexmask.long.tbyte 0x1B4 4.--21. 1. "LO,Line offset" line.long 0x1B8 "GFXMMU_LUT55L,GFXMMU LUT entry 55 low" hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1BC "GFXMMU_LUT55H,GFXMMU LUT entry 55 high" hexmask.long.tbyte 0x1BC 4.--21. 1. "LO,Line offset" line.long 0x1C0 "GFXMMU_LUT56L,GFXMMU LUT entry 56 low" hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C4 "GFXMMU_LUT56H,GFXMMU LUT entry 56 high" hexmask.long.tbyte 0x1C4 4.--21. 1. "LO,Line offset" line.long 0x1C8 "GFXMMU_LUT57L,GFXMMU LUT entry 57 low" hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1CC "GFXMMU_LUT57H,GFXMMU LUT entry 57 high" hexmask.long.tbyte 0x1CC 4.--21. 1. "LO,Line offset" line.long 0x1D0 "GFXMMU_LUT58L,GFXMMU LUT entry 58 low" hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1D4 "GFXMMU_LUT58H,GFXMMU LUT entry 58 high" hexmask.long.tbyte 0x1D4 4.--21. 1. "LO,Line offset" line.long 0x1D8 "GFXMMU_LUT59L,GFXMMU LUT entry 59 low" hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1DC "GFXMMU_LUT59H,GFXMMU LUT entry 59 high" hexmask.long.tbyte 0x1DC 4.--21. 1. "LO,Line offset" line.long 0x1E0 "GFXMMU_LUT60L,GFXMMU LUT entry 60 low" hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1E4 "GFXMMU_LUT60H,GFXMMU LUT entry 60 high" hexmask.long.tbyte 0x1E4 4.--21. 1. "LO,Line offset" line.long 0x1E8 "GFXMMU_LUT61L,GFXMMU LUT entry 61 low" hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1EC "GFXMMU_LUT61H,GFXMMU LUT entry 61 high" hexmask.long.tbyte 0x1EC 4.--21. 1. "LO,Line offset" line.long 0x1F0 "GFXMMU_LUT62L,GFXMMU LUT entry 62 low" hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1F4 "GFXMMU_LUT62H,GFXMMU LUT entry 62 high" hexmask.long.tbyte 0x1F4 4.--21. 1. "LO,Line offset" line.long 0x1F8 "GFXMMU_LUT63L,GFXMMU LUT entry 63 low" hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1FC "GFXMMU_LUT63H,GFXMMU LUT entry 63 high" hexmask.long.tbyte 0x1FC 4.--21. 1. "LO,Line offset" line.long 0x200 "GFXMMU_LUT64L,GFXMMU LUT entry 64 low" hexmask.long.byte 0x200 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x200 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x204 "GFXMMU_LUT64H,GFXMMU LUT entry 64 high" hexmask.long.tbyte 0x204 4.--21. 1. "LO,Line offset" line.long 0x208 "GFXMMU_LUT65L,GFXMMU LUT entry 65 low" hexmask.long.byte 0x208 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x208 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x20C "GFXMMU_LUT65H,GFXMMU LUT entry 65 high" hexmask.long.tbyte 0x20C 4.--21. 1. "LO,Line offset" line.long 0x210 "GFXMMU_LUT66L,GFXMMU LUT entry 66 low" hexmask.long.byte 0x210 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x210 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x214 "GFXMMU_LUT66H,GFXMMU LUT entry 66 high" hexmask.long.tbyte 0x214 4.--21. 1. "LO,Line offset" line.long 0x218 "GFXMMU_LUT67L,GFXMMU LUT entry 67 low" hexmask.long.byte 0x218 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x218 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x21C "GFXMMU_LUT67H,GFXMMU LUT entry 67 high" hexmask.long.tbyte 0x21C 4.--21. 1. "LO,Line offset" line.long 0x220 "GFXMMU_LUT68L,GFXMMU LUT entry 68 low" hexmask.long.byte 0x220 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x220 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x224 "GFXMMU_LUT68H,GFXMMU LUT entry 68 high" hexmask.long.tbyte 0x224 4.--21. 1. "LO,Line offset" line.long 0x228 "GFXMMU_LUT69L,GFXMMU LUT entry 69 low" hexmask.long.byte 0x228 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x228 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x22C "GFXMMU_LUT69H,GFXMMU LUT entry 69 high" hexmask.long.tbyte 0x22C 4.--21. 1. "LO,Line offset" line.long 0x230 "GFXMMU_LUT70L,GFXMMU LUT entry 70 low" hexmask.long.byte 0x230 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x230 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x234 "GFXMMU_LUT70H,GFXMMU LUT entry 70 high" hexmask.long.tbyte 0x234 4.--21. 1. "LO,Line offset" line.long 0x238 "GFXMMU_LUT71L,GFXMMU LUT entry 71 low" hexmask.long.byte 0x238 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x238 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x23C "GFXMMU_LUT71H,GFXMMU LUT entry 71 high" hexmask.long.tbyte 0x23C 4.--21. 1. "LO,Line offset" line.long 0x240 "GFXMMU_LUT72L,GFXMMU LUT entry 72 low" hexmask.long.byte 0x240 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x240 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x244 "GFXMMU_LUT72H,GFXMMU LUT entry 72 high" hexmask.long.tbyte 0x244 4.--21. 1. "LO,Line offset" line.long 0x248 "GFXMMU_LUT73L,GFXMMU LUT entry 73 low" hexmask.long.byte 0x248 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x248 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24C "GFXMMU_LUT73H,GFXMMU LUT entry 73 high" hexmask.long.tbyte 0x24C 4.--21. 1. "LO,Line offset" line.long 0x250 "GFXMMU_LUT74L,GFXMMU LUT entry 74 low" hexmask.long.byte 0x250 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x250 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x254 "GFXMMU_LUT74H,GFXMMU LUT entry 74 high" hexmask.long.tbyte 0x254 4.--21. 1. "LO,Line offset" line.long 0x258 "GFXMMU_LUT75L,GFXMMU LUT entry 75 low" hexmask.long.byte 0x258 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x258 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x25C "GFXMMU_LUT75H,GFXMMU LUT entry 75 high" hexmask.long.tbyte 0x25C 4.--21. 1. "LO,Line offset" line.long 0x260 "GFXMMU_LUT76L,GFXMMU LUT entry 76 low" hexmask.long.byte 0x260 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x260 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x264 "GFXMMU_LUT76H,GFXMMU LUT entry 76 high" hexmask.long.tbyte 0x264 4.--21. 1. "LO,Line offset" line.long 0x268 "GFXMMU_LUT77L,GFXMMU LUT entry 77 low" hexmask.long.byte 0x268 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x268 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x26C "GFXMMU_LUT77H,GFXMMU LUT entry 77 high" hexmask.long.tbyte 0x26C 4.--21. 1. "LO,Line offset" line.long 0x270 "GFXMMU_LUT78L,GFXMMU LUT entry 78 low" hexmask.long.byte 0x270 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x270 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x274 "GFXMMU_LUT78H,GFXMMU LUT entry 78 high" hexmask.long.tbyte 0x274 4.--21. 1. "LO,Line offset" line.long 0x278 "GFXMMU_LUT79L,GFXMMU LUT entry 79 low" hexmask.long.byte 0x278 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x278 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x27C "GFXMMU_LUT79H,GFXMMU LUT entry 79 high" hexmask.long.tbyte 0x27C 4.--21. 1. "LO,Line offset" line.long 0x280 "GFXMMU_LUT80L,GFXMMU LUT entry 80 low" hexmask.long.byte 0x280 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x280 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x284 "GFXMMU_LUT80H,GFXMMU LUT entry 80 high" hexmask.long.tbyte 0x284 4.--21. 1. "LO,Line offset" line.long 0x288 "GFXMMU_LUT81L,GFXMMU LUT entry 81 low" hexmask.long.byte 0x288 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x288 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x28C "GFXMMU_LUT81H,GFXMMU LUT entry 81 high" hexmask.long.tbyte 0x28C 4.--21. 1. "LO,Line offset" line.long 0x290 "GFXMMU_LUT82L,GFXMMU LUT entry 82 low" hexmask.long.byte 0x290 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x290 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x294 "GFXMMU_LUT82H,GFXMMU LUT entry 82 high" hexmask.long.tbyte 0x294 4.--21. 1. "LO,Line offset" line.long 0x298 "GFXMMU_LUT83L,GFXMMU LUT entry 83 low" hexmask.long.byte 0x298 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x298 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x29C "GFXMMU_LUT83H,GFXMMU LUT entry 83 high" hexmask.long.tbyte 0x29C 4.--21. 1. "LO,Line offset" line.long 0x2A0 "GFXMMU_LUT84L,GFXMMU LUT entry 84 low" hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2A4 "GFXMMU_LUT84H,GFXMMU LUT entry 84 high" hexmask.long.tbyte 0x2A4 4.--21. 1. "LO,Line offset" line.long 0x2A8 "GFXMMU_LUT85L,GFXMMU LUT entry 85 low" hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2AC "GFXMMU_LUT85H,GFXMMU LUT entry 85 high" hexmask.long.tbyte 0x2AC 4.--21. 1. "LO,Line offset" line.long 0x2B0 "GFXMMU_LUT86L,GFXMMU LUT entry 86 low" hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2B4 "GFXMMU_LUT86H,GFXMMU LUT entry 86 high" hexmask.long.tbyte 0x2B4 4.--21. 1. "LO,Line offset" line.long 0x2B8 "GFXMMU_LUT87L,GFXMMU LUT entry 87 low" hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2BC "GFXMMU_LUT87H,GFXMMU LUT entry 87 high" hexmask.long.tbyte 0x2BC 4.--21. 1. "LO,Line offset" line.long 0x2C0 "GFXMMU_LUT88L,GFXMMU LUT entry 88 low" hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C4 "GFXMMU_LUT88H,GFXMMU LUT entry 88 high" hexmask.long.tbyte 0x2C4 4.--21. 1. "LO,Line offset" line.long 0x2C8 "GFXMMU_LUT89L,GFXMMU LUT entry 89 low" hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2CC "GFXMMU_LUT89H,GFXMMU LUT entry 89 high" hexmask.long.tbyte 0x2CC 4.--21. 1. "LO,Line offset" line.long 0x2D0 "GFXMMU_LUT90L,GFXMMU LUT entry 90 low" hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2D4 "GFXMMU_LUT90H,GFXMMU LUT entry 90 high" hexmask.long.tbyte 0x2D4 4.--21. 1. "LO,Line offset" line.long 0x2D8 "GFXMMU_LUT91L,GFXMMU LUT entry 91 low" hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2DC "GFXMMU_LUT91H,GFXMMU LUT entry 91 high" hexmask.long.tbyte 0x2DC 4.--21. 1. "LO,Line offset" line.long 0x2E0 "GFXMMU_LUT92L,GFXMMU LUT entry 92 low" hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2E4 "GFXMMU_LUT92H,GFXMMU LUT entry 92 high" hexmask.long.tbyte 0x2E4 4.--21. 1. "LO,Line offset" line.long 0x2E8 "GFXMMU_LUT93L,GFXMMU LUT entry 93 low" hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2EC "GFXMMU_LUT93H,GFXMMU LUT entry 93 high" hexmask.long.tbyte 0x2EC 4.--21. 1. "LO,Line offset" line.long 0x2F0 "GFXMMU_LUT94L,GFXMMU LUT entry 94 low" hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2F4 "GFXMMU_LUT94H,GFXMMU LUT entry 94 high" hexmask.long.tbyte 0x2F4 4.--21. 1. "LO,Line offset" line.long 0x2F8 "GFXMMU_LUT95L,GFXMMU LUT entry 95 low" hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2FC "GFXMMU_LUT95H,GFXMMU LUT entry 95 high" hexmask.long.tbyte 0x2FC 4.--21. 1. "LO,Line offset" line.long 0x300 "GFXMMU_LUT96L,GFXMMU LUT entry 96 low" hexmask.long.byte 0x300 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x300 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x304 "GFXMMU_LUT96H,GFXMMU LUT entry 96 high" hexmask.long.tbyte 0x304 4.--21. 1. "LO,Line offset" line.long 0x308 "GFXMMU_LUT97L,GFXMMU LUT entry 97 low" hexmask.long.byte 0x308 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x308 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x30C "GFXMMU_LUT97H,GFXMMU LUT entry 97 high" hexmask.long.tbyte 0x30C 4.--21. 1. "LO,Line offset" line.long 0x310 "GFXMMU_LUT98L,GFXMMU LUT entry 98 low" hexmask.long.byte 0x310 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x310 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x314 "GFXMMU_LUT98H,GFXMMU LUT entry 98 high" hexmask.long.tbyte 0x314 4.--21. 1. "LO,Line offset" line.long 0x318 "GFXMMU_LUT99L,GFXMMU LUT entry 99 low" hexmask.long.byte 0x318 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x318 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x31C "GFXMMU_LUT99H,GFXMMU LUT entry 99 high" hexmask.long.tbyte 0x31C 4.--21. 1. "LO,Line offset" line.long 0x320 "GFXMMU_LUT100L,GFXMMU LUT entry 100 low" hexmask.long.byte 0x320 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x320 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x324 "GFXMMU_LUT100H,GFXMMU LUT entry 100 high" hexmask.long.tbyte 0x324 4.--21. 1. "LO,Line offset" line.long 0x328 "GFXMMU_LUT101L,GFXMMU LUT entry 101 low" hexmask.long.byte 0x328 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x328 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x32C "GFXMMU_LUT101H,GFXMMU LUT entry 101 high" hexmask.long.tbyte 0x32C 4.--21. 1. "LO,Line offset" line.long 0x330 "GFXMMU_LUT102L,GFXMMU LUT entry 102 low" hexmask.long.byte 0x330 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x330 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x334 "GFXMMU_LUT102H,GFXMMU LUT entry 102 high" hexmask.long.tbyte 0x334 4.--21. 1. "LO,Line offset" line.long 0x338 "GFXMMU_LUT103L,GFXMMU LUT entry 103 low" hexmask.long.byte 0x338 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x338 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x33C "GFXMMU_LUT103H,GFXMMU LUT entry 103 high" hexmask.long.tbyte 0x33C 4.--21. 1. "LO,Line offset" line.long 0x340 "GFXMMU_LUT104L,GFXMMU LUT entry 104 low" hexmask.long.byte 0x340 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x340 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x344 "GFXMMU_LUT104H,GFXMMU LUT entry 104 high" hexmask.long.tbyte 0x344 4.--21. 1. "LO,Line offset" line.long 0x348 "GFXMMU_LUT105L,GFXMMU LUT entry 105 low" hexmask.long.byte 0x348 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x348 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34C "GFXMMU_LUT105H,GFXMMU LUT entry 105 high" hexmask.long.tbyte 0x34C 4.--21. 1. "LO,Line offset" line.long 0x350 "GFXMMU_LUT106L,GFXMMU LUT entry 106 low" hexmask.long.byte 0x350 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x350 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x354 "GFXMMU_LUT106H,GFXMMU LUT entry 106 high" hexmask.long.tbyte 0x354 4.--21. 1. "LO,Line offset" line.long 0x358 "GFXMMU_LUT107L,GFXMMU LUT entry 107 low" hexmask.long.byte 0x358 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x358 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x35C "GFXMMU_LUT107H,GFXMMU LUT entry 107 high" hexmask.long.tbyte 0x35C 4.--21. 1. "LO,Line offset" line.long 0x360 "GFXMMU_LUT108L,GFXMMU LUT entry 108 low" hexmask.long.byte 0x360 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x360 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x364 "GFXMMU_LUT108H,GFXMMU LUT entry 108 high" hexmask.long.tbyte 0x364 4.--21. 1. "LO,Line offset" line.long 0x368 "GFXMMU_LUT109L,GFXMMU LUT entry 109 low" hexmask.long.byte 0x368 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x368 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x36C "GFXMMU_LUT109H,GFXMMU LUT entry 109 high" hexmask.long.tbyte 0x36C 4.--21. 1. "LO,Line offset" line.long 0x370 "GFXMMU_LUT110L,GFXMMU LUT entry 110 low" hexmask.long.byte 0x370 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x370 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x374 "GFXMMU_LUT110H,GFXMMU LUT entry 110 high" hexmask.long.tbyte 0x374 4.--21. 1. "LO,Line offset" line.long 0x378 "GFXMMU_LUT111L,GFXMMU LUT entry 111 low" hexmask.long.byte 0x378 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x378 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x37C "GFXMMU_LUT111H,GFXMMU LUT entry 111 high" hexmask.long.tbyte 0x37C 4.--21. 1. "LO,Line offset" line.long 0x380 "GFXMMU_LUT112L,GFXMMU LUT entry 112 low" hexmask.long.byte 0x380 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x380 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x384 "GFXMMU_LUT112H,GFXMMU LUT entry 112 high" hexmask.long.tbyte 0x384 4.--21. 1. "LO,Line offset" line.long 0x388 "GFXMMU_LUT113L,GFXMMU LUT entry 113 low" hexmask.long.byte 0x388 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x388 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x38C "GFXMMU_LUT113H,GFXMMU LUT entry 113 high" hexmask.long.tbyte 0x38C 4.--21. 1. "LO,Line offset" line.long 0x390 "GFXMMU_LUT114L,GFXMMU LUT entry 114 low" hexmask.long.byte 0x390 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x390 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x394 "GFXMMU_LUT114H,GFXMMU LUT entry 114 high" hexmask.long.tbyte 0x394 4.--21. 1. "LO,Line offset" line.long 0x398 "GFXMMU_LUT115L,GFXMMU LUT entry 115 low" hexmask.long.byte 0x398 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x398 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x39C "GFXMMU_LUT115H,GFXMMU LUT entry 115 high" hexmask.long.tbyte 0x39C 4.--21. 1. "LO,Line offset" line.long 0x3A0 "GFXMMU_LUT116L,GFXMMU LUT entry 116 low" hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3A4 "GFXMMU_LUT116H,GFXMMU LUT entry 116 high" hexmask.long.tbyte 0x3A4 4.--21. 1. "LO,Line offset" line.long 0x3A8 "GFXMMU_LUT117L,GFXMMU LUT entry 117 low" hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3AC "GFXMMU_LUT117H,GFXMMU LUT entry 117 high" hexmask.long.tbyte 0x3AC 4.--21. 1. "LO,Line offset" line.long 0x3B0 "GFXMMU_LUT118L,GFXMMU LUT entry 118 low" hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3B4 "GFXMMU_LUT118H,GFXMMU LUT entry 118 high" hexmask.long.tbyte 0x3B4 4.--21. 1. "LO,Line offset" line.long 0x3B8 "GFXMMU_LUT119L,GFXMMU LUT entry 119 low" hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3BC "GFXMMU_LUT119H,GFXMMU LUT entry 119 high" hexmask.long.tbyte 0x3BC 4.--21. 1. "LO,Line offset" line.long 0x3C0 "GFXMMU_LUT120L,GFXMMU LUT entry 120 low" hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C4 "GFXMMU_LUT120H,GFXMMU LUT entry 120 high" hexmask.long.tbyte 0x3C4 4.--21. 1. "LO,Line offset" line.long 0x3C8 "GFXMMU_LUT121L,GFXMMU LUT entry 121 low" hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3CC "GFXMMU_LUT121H,GFXMMU LUT entry 121 high" hexmask.long.tbyte 0x3CC 4.--21. 1. "LO,Line offset" line.long 0x3D0 "GFXMMU_LUT122L,GFXMMU LUT entry 122 low" hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3D4 "GFXMMU_LUT122H,GFXMMU LUT entry 122 high" hexmask.long.tbyte 0x3D4 4.--21. 1. "LO,Line offset" line.long 0x3D8 "GFXMMU_LUT123L,GFXMMU LUT entry 123 low" hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3DC "GFXMMU_LUT123H,GFXMMU LUT entry 123 high" hexmask.long.tbyte 0x3DC 4.--21. 1. "LO,Line offset" line.long 0x3E0 "GFXMMU_LUT124L,GFXMMU LUT entry 124 low" hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3E4 "GFXMMU_LUT124H,GFXMMU LUT entry 124 high" hexmask.long.tbyte 0x3E4 4.--21. 1. "LO,Line offset" line.long 0x3E8 "GFXMMU_LUT125L,GFXMMU LUT entry 125 low" hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3EC "GFXMMU_LUT125H,GFXMMU LUT entry 125 high" hexmask.long.tbyte 0x3EC 4.--21. 1. "LO,Line offset" line.long 0x3F0 "GFXMMU_LUT126L,GFXMMU LUT entry 126 low" hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3F4 "GFXMMU_LUT126H,GFXMMU LUT entry 126 high" hexmask.long.tbyte 0x3F4 4.--21. 1. "LO,Line offset" line.long 0x3F8 "GFXMMU_LUT127L,GFXMMU LUT entry 127 low" hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3FC "GFXMMU_LUT127H,GFXMMU LUT entry 127 high" hexmask.long.tbyte 0x3FC 4.--21. 1. "LO,Line offset" line.long 0x400 "GFXMMU_LUT128L,GFXMMU LUT entry 128 low" hexmask.long.byte 0x400 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x400 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x404 "GFXMMU_LUT128H,GFXMMU LUT entry 128 high" hexmask.long.tbyte 0x404 4.--21. 1. "LO,Line offset" line.long 0x408 "GFXMMU_LUT129L,GFXMMU LUT entry 129 low" hexmask.long.byte 0x408 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x408 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x40C "GFXMMU_LUT129H,GFXMMU LUT entry 129 high" hexmask.long.tbyte 0x40C 4.--21. 1. "LO,Line offset" line.long 0x410 "GFXMMU_LUT130L,GFXMMU LUT entry 130 low" hexmask.long.byte 0x410 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x410 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x414 "GFXMMU_LUT130H,GFXMMU LUT entry 130 high" hexmask.long.tbyte 0x414 4.--21. 1. "LO,Line offset" line.long 0x418 "GFXMMU_LUT131L,GFXMMU LUT entry 131 low" hexmask.long.byte 0x418 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x418 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x41C "GFXMMU_LUT131H,GFXMMU LUT entry 131 high" hexmask.long.tbyte 0x41C 4.--21. 1. "LO,Line offset" line.long 0x420 "GFXMMU_LUT132L,GFXMMU LUT entry 132 low" hexmask.long.byte 0x420 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x420 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x424 "GFXMMU_LUT132H,GFXMMU LUT entry 132 high" hexmask.long.tbyte 0x424 4.--21. 1. "LO,Line offset" line.long 0x428 "GFXMMU_LUT133L,GFXMMU LUT entry 133 low" hexmask.long.byte 0x428 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x428 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x42C "GFXMMU_LUT133H,GFXMMU LUT entry 133 high" hexmask.long.tbyte 0x42C 4.--21. 1. "LO,Line offset" line.long 0x430 "GFXMMU_LUT134L,GFXMMU LUT entry 134 low" hexmask.long.byte 0x430 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x430 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x434 "GFXMMU_LUT134H,GFXMMU LUT entry 134 high" hexmask.long.tbyte 0x434 4.--21. 1. "LO,Line offset" line.long 0x438 "GFXMMU_LUT135L,GFXMMU LUT entry 135 low" hexmask.long.byte 0x438 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x438 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x43C "GFXMMU_LUT135H,GFXMMU LUT entry 135 high" hexmask.long.tbyte 0x43C 4.--21. 1. "LO,Line offset" line.long 0x440 "GFXMMU_LUT136L,GFXMMU LUT entry 136 low" hexmask.long.byte 0x440 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x440 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x444 "GFXMMU_LUT136H,GFXMMU LUT entry 136 high" hexmask.long.tbyte 0x444 4.--21. 1. "LO,Line offset" line.long 0x448 "GFXMMU_LUT137L,GFXMMU LUT entry 137 low" hexmask.long.byte 0x448 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x448 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44C "GFXMMU_LUT137H,GFXMMU LUT entry 137 high" hexmask.long.tbyte 0x44C 4.--21. 1. "LO,Line offset" line.long 0x450 "GFXMMU_LUT138L,GFXMMU LUT entry 138 low" hexmask.long.byte 0x450 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x450 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x454 "GFXMMU_LUT138H,GFXMMU LUT entry 138 high" hexmask.long.tbyte 0x454 4.--21. 1. "LO,Line offset" line.long 0x458 "GFXMMU_LUT139L,GFXMMU LUT entry 139 low" hexmask.long.byte 0x458 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x458 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x45C "GFXMMU_LUT139H,GFXMMU LUT entry 139 high" hexmask.long.tbyte 0x45C 4.--21. 1. "LO,Line offset" line.long 0x460 "GFXMMU_LUT140L,GFXMMU LUT entry 140 low" hexmask.long.byte 0x460 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x460 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x464 "GFXMMU_LUT140H,GFXMMU LUT entry 140 high" hexmask.long.tbyte 0x464 4.--21. 1. "LO,Line offset" line.long 0x468 "GFXMMU_LUT141L,GFXMMU LUT entry 141 low" hexmask.long.byte 0x468 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x468 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x46C "GFXMMU_LUT141H,GFXMMU LUT entry 141 high" hexmask.long.tbyte 0x46C 4.--21. 1. "LO,Line offset" line.long 0x470 "GFXMMU_LUT142L,GFXMMU LUT entry 142 low" hexmask.long.byte 0x470 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x470 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x474 "GFXMMU_LUT142H,GFXMMU LUT entry 142 high" hexmask.long.tbyte 0x474 4.--21. 1. "LO,Line offset" line.long 0x478 "GFXMMU_LUT143L,GFXMMU LUT entry 143 low" hexmask.long.byte 0x478 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x478 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x47C "GFXMMU_LUT143H,GFXMMU LUT entry 143 high" hexmask.long.tbyte 0x47C 4.--21. 1. "LO,Line offset" line.long 0x480 "GFXMMU_LUT144L,GFXMMU LUT entry 144 low" hexmask.long.byte 0x480 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x480 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x484 "GFXMMU_LUT144H,GFXMMU LUT entry 144 high" hexmask.long.tbyte 0x484 4.--21. 1. "LO,Line offset" line.long 0x488 "GFXMMU_LUT145L,GFXMMU LUT entry 145 low" hexmask.long.byte 0x488 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x488 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x48C "GFXMMU_LUT145H,GFXMMU LUT entry 145 high" hexmask.long.tbyte 0x48C 4.--21. 1. "LO,Line offset" line.long 0x490 "GFXMMU_LUT146L,GFXMMU LUT entry 146 low" hexmask.long.byte 0x490 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x490 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x494 "GFXMMU_LUT146H,GFXMMU LUT entry 146 high" hexmask.long.tbyte 0x494 4.--21. 1. "LO,Line offset" line.long 0x498 "GFXMMU_LUT147L,GFXMMU LUT entry 147 low" hexmask.long.byte 0x498 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x498 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x49C "GFXMMU_LUT147H,GFXMMU LUT entry 147 high" hexmask.long.tbyte 0x49C 4.--21. 1. "LO,Line offset" line.long 0x4A0 "GFXMMU_LUT148L,GFXMMU LUT entry 148 low" hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4A4 "GFXMMU_LUT148H,GFXMMU LUT entry 148 high" hexmask.long.tbyte 0x4A4 4.--21. 1. "LO,Line offset" line.long 0x4A8 "GFXMMU_LUT149L,GFXMMU LUT entry 149 low" hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4AC "GFXMMU_LUT149H,GFXMMU LUT entry 149 high" hexmask.long.tbyte 0x4AC 4.--21. 1. "LO,Line offset" line.long 0x4B0 "GFXMMU_LUT150L,GFXMMU LUT entry 150 low" hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4B4 "GFXMMU_LUT150H,GFXMMU LUT entry 150 high" hexmask.long.tbyte 0x4B4 4.--21. 1. "LO,Line offset" line.long 0x4B8 "GFXMMU_LUT151L,GFXMMU LUT entry 151 low" hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4BC "GFXMMU_LUT151H,GFXMMU LUT entry 151 high" hexmask.long.tbyte 0x4BC 4.--21. 1. "LO,Line offset" line.long 0x4C0 "GFXMMU_LUT152L,GFXMMU LUT entry 152 low" hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C4 "GFXMMU_LUT152H,GFXMMU LUT entry 152 high" hexmask.long.tbyte 0x4C4 4.--21. 1. "LO,Line offset" line.long 0x4C8 "GFXMMU_LUT153L,GFXMMU LUT entry 153 low" hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4CC "GFXMMU_LUT153H,GFXMMU LUT entry 153 high" hexmask.long.tbyte 0x4CC 4.--21. 1. "LO,Line offset" line.long 0x4D0 "GFXMMU_LUT154L,GFXMMU LUT entry 154 low" hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4D4 "GFXMMU_LUT154H,GFXMMU LUT entry 154 high" hexmask.long.tbyte 0x4D4 4.--21. 1. "LO,Line offset" line.long 0x4D8 "GFXMMU_LUT155L,GFXMMU LUT entry 155 low" hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4DC "GFXMMU_LUT155H,GFXMMU LUT entry 155 high" hexmask.long.tbyte 0x4DC 4.--21. 1. "LO,Line offset" line.long 0x4E0 "GFXMMU_LUT156L,GFXMMU LUT entry 156 low" hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4E4 "GFXMMU_LUT156H,GFXMMU LUT entry 156 high" hexmask.long.tbyte 0x4E4 4.--21. 1. "LO,Line offset" line.long 0x4E8 "GFXMMU_LUT157L,GFXMMU LUT entry 157 low" hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4EC "GFXMMU_LUT157H,GFXMMU LUT entry 157 high" hexmask.long.tbyte 0x4EC 4.--21. 1. "LO,Line offset" line.long 0x4F0 "GFXMMU_LUT158L,GFXMMU LUT entry 158 low" hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4F4 "GFXMMU_LUT158H,GFXMMU LUT entry 158 high" hexmask.long.tbyte 0x4F4 4.--21. 1. "LO,Line offset" line.long 0x4F8 "GFXMMU_LUT159L,GFXMMU LUT entry 159 low" hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4FC "GFXMMU_LUT159H,GFXMMU LUT entry 159 high" hexmask.long.tbyte 0x4FC 4.--21. 1. "LO,Line offset" line.long 0x500 "GFXMMU_LUT160L,GFXMMU LUT entry 160 low" hexmask.long.byte 0x500 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x500 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x504 "GFXMMU_LUT160H,GFXMMU LUT entry 160 high" hexmask.long.tbyte 0x504 4.--21. 1. "LO,Line offset" line.long 0x508 "GFXMMU_LUT161L,GFXMMU LUT entry 161 low" hexmask.long.byte 0x508 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x508 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x50C "GFXMMU_LUT161H,GFXMMU LUT entry 161 high" hexmask.long.tbyte 0x50C 4.--21. 1. "LO,Line offset" line.long 0x510 "GFXMMU_LUT162L,GFXMMU LUT entry 162 low" hexmask.long.byte 0x510 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x510 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x514 "GFXMMU_LUT162H,GFXMMU LUT entry 162 high" hexmask.long.tbyte 0x514 4.--21. 1. "LO,Line offset" line.long 0x518 "GFXMMU_LUT163L,GFXMMU LUT entry 163 low" hexmask.long.byte 0x518 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x518 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x51C "GFXMMU_LUT163H,GFXMMU LUT entry 163 high" hexmask.long.tbyte 0x51C 4.--21. 1. "LO,Line offset" line.long 0x520 "GFXMMU_LUT164L,GFXMMU LUT entry 164 low" hexmask.long.byte 0x520 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x520 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x524 "GFXMMU_LUT164H,GFXMMU LUT entry 164 high" hexmask.long.tbyte 0x524 4.--21. 1. "LO,Line offset" line.long 0x528 "GFXMMU_LUT165L,GFXMMU LUT entry 165 low" hexmask.long.byte 0x528 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x528 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x52C "GFXMMU_LUT165H,GFXMMU LUT entry 165 high" hexmask.long.tbyte 0x52C 4.--21. 1. "LO,Line offset" line.long 0x530 "GFXMMU_LUT166L,GFXMMU LUT entry 166 low" hexmask.long.byte 0x530 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x530 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x534 "GFXMMU_LUT166H,GFXMMU LUT entry 166 high" hexmask.long.tbyte 0x534 4.--21. 1. "LO,Line offset" line.long 0x538 "GFXMMU_LUT167L,GFXMMU LUT entry 167 low" hexmask.long.byte 0x538 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x538 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x53C "GFXMMU_LUT167H,GFXMMU LUT entry 167 high" hexmask.long.tbyte 0x53C 4.--21. 1. "LO,Line offset" line.long 0x540 "GFXMMU_LUT168L,GFXMMU LUT entry 168 low" hexmask.long.byte 0x540 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x540 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x544 "GFXMMU_LUT168H,GFXMMU LUT entry 168 high" hexmask.long.tbyte 0x544 4.--21. 1. "LO,Line offset" line.long 0x548 "GFXMMU_LUT169L,GFXMMU LUT entry 169 low" hexmask.long.byte 0x548 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x548 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54C "GFXMMU_LUT169H,GFXMMU LUT entry 169 high" hexmask.long.tbyte 0x54C 4.--21. 1. "LO,Line offset" line.long 0x550 "GFXMMU_LUT170L,GFXMMU LUT entry 170 low" hexmask.long.byte 0x550 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x550 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x554 "GFXMMU_LUT170H,GFXMMU LUT entry 170 high" hexmask.long.tbyte 0x554 4.--21. 1. "LO,Line offset" line.long 0x558 "GFXMMU_LUT171L,GFXMMU LUT entry 171 low" hexmask.long.byte 0x558 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x558 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x55C "GFXMMU_LUT171H,GFXMMU LUT entry 171 high" hexmask.long.tbyte 0x55C 4.--21. 1. "LO,Line offset" line.long 0x560 "GFXMMU_LUT172L,GFXMMU LUT entry 172 low" hexmask.long.byte 0x560 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x560 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x564 "GFXMMU_LUT172H,GFXMMU LUT entry 172 high" hexmask.long.tbyte 0x564 4.--21. 1. "LO,Line offset" line.long 0x568 "GFXMMU_LUT173L,GFXMMU LUT entry 173 low" hexmask.long.byte 0x568 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x568 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x56C "GFXMMU_LUT173H,GFXMMU LUT entry 173 high" hexmask.long.tbyte 0x56C 4.--21. 1. "LO,Line offset" line.long 0x570 "GFXMMU_LUT174L,GFXMMU LUT entry 174 low" hexmask.long.byte 0x570 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x570 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x574 "GFXMMU_LUT174H,GFXMMU LUT entry 174 high" hexmask.long.tbyte 0x574 4.--21. 1. "LO,Line offset" line.long 0x578 "GFXMMU_LUT175L,GFXMMU LUT entry 175 low" hexmask.long.byte 0x578 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x578 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x57C "GFXMMU_LUT175H,GFXMMU LUT entry 175 high" hexmask.long.tbyte 0x57C 4.--21. 1. "LO,Line offset" line.long 0x580 "GFXMMU_LUT176L,GFXMMU LUT entry 176 low" hexmask.long.byte 0x580 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x580 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x584 "GFXMMU_LUT176H,GFXMMU LUT entry 176 high" hexmask.long.tbyte 0x584 4.--21. 1. "LO,Line offset" line.long 0x588 "GFXMMU_LUT177L,GFXMMU LUT entry 177 low" hexmask.long.byte 0x588 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x588 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x58C "GFXMMU_LUT177H,GFXMMU LUT entry 177 high" hexmask.long.tbyte 0x58C 4.--21. 1. "LO,Line offset" line.long 0x590 "GFXMMU_LUT178L,GFXMMU LUT entry 178 low" hexmask.long.byte 0x590 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x590 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x594 "GFXMMU_LUT178H,GFXMMU LUT entry 178 high" hexmask.long.tbyte 0x594 4.--21. 1. "LO,Line offset" line.long 0x598 "GFXMMU_LUT179L,GFXMMU LUT entry 179 low" hexmask.long.byte 0x598 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x598 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x59C "GFXMMU_LUT179H,GFXMMU LUT entry 179 high" hexmask.long.tbyte 0x59C 4.--21. 1. "LO,Line offset" line.long 0x5A0 "GFXMMU_LUT180L,GFXMMU LUT entry 180 low" hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5A4 "GFXMMU_LUT180H,GFXMMU LUT entry 180 high" hexmask.long.tbyte 0x5A4 4.--21. 1. "LO,Line offset" line.long 0x5A8 "GFXMMU_LUT181L,GFXMMU LUT entry 181 low" hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5AC "GFXMMU_LUT181H,GFXMMU LUT entry 181 high" hexmask.long.tbyte 0x5AC 4.--21. 1. "LO,Line offset" line.long 0x5B0 "GFXMMU_LUT182L,GFXMMU LUT entry 182 low" hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5B4 "GFXMMU_LUT182H,GFXMMU LUT entry 182 high" hexmask.long.tbyte 0x5B4 4.--21. 1. "LO,Line offset" line.long 0x5B8 "GFXMMU_LUT183L,GFXMMU LUT entry 183 low" hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5BC "GFXMMU_LUT183H,GFXMMU LUT entry 183 high" hexmask.long.tbyte 0x5BC 4.--21. 1. "LO,Line offset" line.long 0x5C0 "GFXMMU_LUT184L,GFXMMU LUT entry 184 low" hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C4 "GFXMMU_LUT184H,GFXMMU LUT entry 184 high" hexmask.long.tbyte 0x5C4 4.--21. 1. "LO,Line offset" line.long 0x5C8 "GFXMMU_LUT185L,GFXMMU LUT entry 185 low" hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5CC "GFXMMU_LUT185H,GFXMMU LUT entry 185 high" hexmask.long.tbyte 0x5CC 4.--21. 1. "LO,Line offset" line.long 0x5D0 "GFXMMU_LUT186L,GFXMMU LUT entry 186 low" hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5D4 "GFXMMU_LUT186H,GFXMMU LUT entry 186 high" hexmask.long.tbyte 0x5D4 4.--21. 1. "LO,Line offset" line.long 0x5D8 "GFXMMU_LUT187L,GFXMMU LUT entry 187 low" hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5DC "GFXMMU_LUT187H,GFXMMU LUT entry 187 high" hexmask.long.tbyte 0x5DC 4.--21. 1. "LO,Line offset" line.long 0x5E0 "GFXMMU_LUT188L,GFXMMU LUT entry 188 low" hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5E4 "GFXMMU_LUT188H,GFXMMU LUT entry 188 high" hexmask.long.tbyte 0x5E4 4.--21. 1. "LO,Line offset" line.long 0x5E8 "GFXMMU_LUT189L,GFXMMU LUT entry 189 low" hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5EC "GFXMMU_LUT189H,GFXMMU LUT entry 189 high" hexmask.long.tbyte 0x5EC 4.--21. 1. "LO,Line offset" line.long 0x5F0 "GFXMMU_LUT190L,GFXMMU LUT entry 190 low" hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5F4 "GFXMMU_LUT190H,GFXMMU LUT entry 190 high" hexmask.long.tbyte 0x5F4 4.--21. 1. "LO,Line offset" line.long 0x5F8 "GFXMMU_LUT191L,GFXMMU LUT entry 191 low" hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5FC "GFXMMU_LUT191H,GFXMMU LUT entry 191 high" hexmask.long.tbyte 0x5FC 4.--21. 1. "LO,Line offset" line.long 0x600 "GFXMMU_LUT192L,GFXMMU LUT entry 192 low" hexmask.long.byte 0x600 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x600 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x604 "GFXMMU_LUT192H,GFXMMU LUT entry 192 high" hexmask.long.tbyte 0x604 4.--21. 1. "LO,Line offset" line.long 0x608 "GFXMMU_LUT193L,GFXMMU LUT entry 193 low" hexmask.long.byte 0x608 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x608 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x60C "GFXMMU_LUT193H,GFXMMU LUT entry 193 high" hexmask.long.tbyte 0x60C 4.--21. 1. "LO,Line offset" line.long 0x610 "GFXMMU_LUT194L,GFXMMU LUT entry 194 low" hexmask.long.byte 0x610 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x610 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x614 "GFXMMU_LUT194H,GFXMMU LUT entry 194 high" hexmask.long.tbyte 0x614 4.--21. 1. "LO,Line offset" line.long 0x618 "GFXMMU_LUT195L,GFXMMU LUT entry 195 low" hexmask.long.byte 0x618 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x618 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x61C "GFXMMU_LUT195H,GFXMMU LUT entry 195 high" hexmask.long.tbyte 0x61C 4.--21. 1. "LO,Line offset" line.long 0x620 "GFXMMU_LUT196L,GFXMMU LUT entry 196 low" hexmask.long.byte 0x620 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x620 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x624 "GFXMMU_LUT196H,GFXMMU LUT entry 196 high" hexmask.long.tbyte 0x624 4.--21. 1. "LO,Line offset" line.long 0x628 "GFXMMU_LUT197L,GFXMMU LUT entry 197 low" hexmask.long.byte 0x628 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x628 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x62C "GFXMMU_LUT197H,GFXMMU LUT entry 197 high" hexmask.long.tbyte 0x62C 4.--21. 1. "LO,Line offset" line.long 0x630 "GFXMMU_LUT198L,GFXMMU LUT entry 198 low" hexmask.long.byte 0x630 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x630 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x634 "GFXMMU_LUT198H,GFXMMU LUT entry 198 high" hexmask.long.tbyte 0x634 4.--21. 1. "LO,Line offset" line.long 0x638 "GFXMMU_LUT199L,GFXMMU LUT entry 199 low" hexmask.long.byte 0x638 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x638 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x63C "GFXMMU_LUT199H,GFXMMU LUT entry 199 high" hexmask.long.tbyte 0x63C 4.--21. 1. "LO,Line offset" line.long 0x640 "GFXMMU_LUT200L,GFXMMU LUT entry 200 low" hexmask.long.byte 0x640 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x640 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x644 "GFXMMU_LUT200H,GFXMMU LUT entry 200 high" hexmask.long.tbyte 0x644 4.--21. 1. "LO,Line offset" line.long 0x648 "GFXMMU_LUT201L,GFXMMU LUT entry 201 low" hexmask.long.byte 0x648 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x648 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64C "GFXMMU_LUT201H,GFXMMU LUT entry 201 high" hexmask.long.tbyte 0x64C 4.--21. 1. "LO,Line offset" line.long 0x650 "GFXMMU_LUT202L,GFXMMU LUT entry 202 low" hexmask.long.byte 0x650 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x650 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x654 "GFXMMU_LUT202H,GFXMMU LUT entry 202 high" hexmask.long.tbyte 0x654 4.--21. 1. "LO,Line offset" line.long 0x658 "GFXMMU_LUT203L,GFXMMU LUT entry 203 low" hexmask.long.byte 0x658 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x658 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x65C "GFXMMU_LUT203H,GFXMMU LUT entry 203 high" hexmask.long.tbyte 0x65C 4.--21. 1. "LO,Line offset" line.long 0x660 "GFXMMU_LUT204L,GFXMMU LUT entry 204 low" hexmask.long.byte 0x660 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x660 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x664 "GFXMMU_LUT204H,GFXMMU LUT entry 204 high" hexmask.long.tbyte 0x664 4.--21. 1. "LO,Line offset" line.long 0x668 "GFXMMU_LUT205L,GFXMMU LUT entry 205 low" hexmask.long.byte 0x668 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x668 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x66C "GFXMMU_LUT205H,GFXMMU LUT entry 205 high" hexmask.long.tbyte 0x66C 4.--21. 1. "LO,Line offset" line.long 0x670 "GFXMMU_LUT206L,GFXMMU LUT entry 206 low" hexmask.long.byte 0x670 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x670 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x674 "GFXMMU_LUT206H,GFXMMU LUT entry 206 high" hexmask.long.tbyte 0x674 4.--21. 1. "LO,Line offset" line.long 0x678 "GFXMMU_LUT207L,GFXMMU LUT entry 207 low" hexmask.long.byte 0x678 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x678 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x67C "GFXMMU_LUT207H,GFXMMU LUT entry 207 high" hexmask.long.tbyte 0x67C 4.--21. 1. "LO,Line offset" line.long 0x680 "GFXMMU_LUT208L,GFXMMU LUT entry 208 low" hexmask.long.byte 0x680 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x680 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x684 "GFXMMU_LUT208H,GFXMMU LUT entry 208 high" hexmask.long.tbyte 0x684 4.--21. 1. "LO,Line offset" line.long 0x688 "GFXMMU_LUT209L,GFXMMU LUT entry 209 low" hexmask.long.byte 0x688 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x688 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x68C "GFXMMU_LUT209H,GFXMMU LUT entry 209 high" hexmask.long.tbyte 0x68C 4.--21. 1. "LO,Line offset" line.long 0x690 "GFXMMU_LUT210L,GFXMMU LUT entry 210 low" hexmask.long.byte 0x690 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x690 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x694 "GFXMMU_LUT210H,GFXMMU LUT entry 210 high" hexmask.long.tbyte 0x694 4.--21. 1. "LO,Line offset" line.long 0x698 "GFXMMU_LUT211L,GFXMMU LUT entry 211 low" hexmask.long.byte 0x698 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x698 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x69C "GFXMMU_LUT211H,GFXMMU LUT entry 211 high" hexmask.long.tbyte 0x69C 4.--21. 1. "LO,Line offset" line.long 0x6A0 "GFXMMU_LUT212L,GFXMMU LUT entry 212 low" hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6A4 "GFXMMU_LUT212H,GFXMMU LUT entry 212 high" hexmask.long.tbyte 0x6A4 4.--21. 1. "LO,Line offset" line.long 0x6A8 "GFXMMU_LUT213L,GFXMMU LUT entry 213 low" hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6AC "GFXMMU_LUT213H,GFXMMU LUT entry 213 high" hexmask.long.tbyte 0x6AC 4.--21. 1. "LO,Line offset" line.long 0x6B0 "GFXMMU_LUT214L,GFXMMU LUT entry 214 low" hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6B4 "GFXMMU_LUT214H,GFXMMU LUT entry 214 high" hexmask.long.tbyte 0x6B4 4.--21. 1. "LO,Line offset" line.long 0x6B8 "GFXMMU_LUT215L,GFXMMU LUT entry 215 low" hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6BC "GFXMMU_LUT215H,GFXMMU LUT entry 215 high" hexmask.long.tbyte 0x6BC 4.--21. 1. "LO,Line offset" line.long 0x6C0 "GFXMMU_LUT216L,GFXMMU LUT entry 216 low" hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C4 "GFXMMU_LUT216H,GFXMMU LUT entry 216 high" hexmask.long.tbyte 0x6C4 4.--21. 1. "LO,Line offset" line.long 0x6C8 "GFXMMU_LUT217L,GFXMMU LUT entry 217 low" hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6CC "GFXMMU_LUT217H,GFXMMU LUT entry 217 high" hexmask.long.tbyte 0x6CC 4.--21. 1. "LO,Line offset" line.long 0x6D0 "GFXMMU_LUT218L,GFXMMU LUT entry 218 low" hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6D4 "GFXMMU_LUT218H,GFXMMU LUT entry 218 high" hexmask.long.tbyte 0x6D4 4.--21. 1. "LO,Line offset" line.long 0x6D8 "GFXMMU_LUT219L,GFXMMU LUT entry 219 low" hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6DC "GFXMMU_LUT219H,GFXMMU LUT entry 219 high" hexmask.long.tbyte 0x6DC 4.--21. 1. "LO,Line offset" line.long 0x6E0 "GFXMMU_LUT220L,GFXMMU LUT entry 220 low" hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6E4 "GFXMMU_LUT220H,GFXMMU LUT entry 220 high" hexmask.long.tbyte 0x6E4 4.--21. 1. "LO,Line offset" line.long 0x6E8 "GFXMMU_LUT221L,GFXMMU LUT entry 221 low" hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6EC "GFXMMU_LUT221H,GFXMMU LUT entry 221 high" hexmask.long.tbyte 0x6EC 4.--21. 1. "LO,Line offset" line.long 0x6F0 "GFXMMU_LUT222L,GFXMMU LUT entry 222 low" hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6F4 "GFXMMU_LUT222H,GFXMMU LUT entry 222 high" hexmask.long.tbyte 0x6F4 4.--21. 1. "LO,Line offset" line.long 0x6F8 "GFXMMU_LUT223L,GFXMMU LUT entry 223 low" hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6FC "GFXMMU_LUT223H,GFXMMU LUT entry 223 high" hexmask.long.tbyte 0x6FC 4.--21. 1. "LO,Line offset" line.long 0x700 "GFXMMU_LUT224L,GFXMMU LUT entry 224 low" hexmask.long.byte 0x700 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x700 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x704 "GFXMMU_LUT224H,GFXMMU LUT entry 224 high" hexmask.long.tbyte 0x704 4.--21. 1. "LO,Line offset" line.long 0x708 "GFXMMU_LUT225L,GFXMMU LUT entry 225 low" hexmask.long.byte 0x708 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x708 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x70C "GFXMMU_LUT225H,GFXMMU LUT entry 225 high" hexmask.long.tbyte 0x70C 4.--21. 1. "LO,Line offset" line.long 0x710 "GFXMMU_LUT226L,GFXMMU LUT entry 226 low" hexmask.long.byte 0x710 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x710 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x714 "GFXMMU_LUT226H,GFXMMU LUT entry 226 high" hexmask.long.tbyte 0x714 4.--21. 1. "LO,Line offset" line.long 0x718 "GFXMMU_LUT227L,GFXMMU LUT entry 227 low" hexmask.long.byte 0x718 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x718 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x71C "GFXMMU_LUT227H,GFXMMU LUT entry 227 high" hexmask.long.tbyte 0x71C 4.--21. 1. "LO,Line offset" line.long 0x720 "GFXMMU_LUT228L,GFXMMU LUT entry 228 low" hexmask.long.byte 0x720 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x720 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x724 "GFXMMU_LUT228H,GFXMMU LUT entry 228 high" hexmask.long.tbyte 0x724 4.--21. 1. "LO,Line offset" line.long 0x728 "GFXMMU_LUT229L,GFXMMU LUT entry 229 low" hexmask.long.byte 0x728 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x728 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x72C "GFXMMU_LUT229H,GFXMMU LUT entry 229 high" hexmask.long.tbyte 0x72C 4.--21. 1. "LO,Line offset" line.long 0x730 "GFXMMU_LUT230L,GFXMMU LUT entry 230 low" hexmask.long.byte 0x730 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x730 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x734 "GFXMMU_LUT230H,GFXMMU LUT entry 230 high" hexmask.long.tbyte 0x734 4.--21. 1. "LO,Line offset" line.long 0x738 "GFXMMU_LUT231L,GFXMMU LUT entry 231 low" hexmask.long.byte 0x738 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x738 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x73C "GFXMMU_LUT231H,GFXMMU LUT entry 231 high" hexmask.long.tbyte 0x73C 4.--21. 1. "LO,Line offset" line.long 0x740 "GFXMMU_LUT232L,GFXMMU LUT entry 232 low" hexmask.long.byte 0x740 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x740 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x744 "GFXMMU_LUT232H,GFXMMU LUT entry 232 high" hexmask.long.tbyte 0x744 4.--21. 1. "LO,Line offset" line.long 0x748 "GFXMMU_LUT233L,GFXMMU LUT entry 233 low" hexmask.long.byte 0x748 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x748 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74C "GFXMMU_LUT233H,GFXMMU LUT entry 233 high" hexmask.long.tbyte 0x74C 4.--21. 1. "LO,Line offset" line.long 0x750 "GFXMMU_LUT234L,GFXMMU LUT entry 234 low" hexmask.long.byte 0x750 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x750 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x754 "GFXMMU_LUT234H,GFXMMU LUT entry 234 high" hexmask.long.tbyte 0x754 4.--21. 1. "LO,Line offset" line.long 0x758 "GFXMMU_LUT235L,GFXMMU LUT entry 235 low" hexmask.long.byte 0x758 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x758 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x75C "GFXMMU_LUT235H,GFXMMU LUT entry 235 high" hexmask.long.tbyte 0x75C 4.--21. 1. "LO,Line offset" line.long 0x760 "GFXMMU_LUT236L,GFXMMU LUT entry 236 low" hexmask.long.byte 0x760 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x760 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x764 "GFXMMU_LUT236H,GFXMMU LUT entry 236 high" hexmask.long.tbyte 0x764 4.--21. 1. "LO,Line offset" line.long 0x768 "GFXMMU_LUT237L,GFXMMU LUT entry 237 low" hexmask.long.byte 0x768 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x768 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x76C "GFXMMU_LUT237H,GFXMMU LUT entry 237 high" hexmask.long.tbyte 0x76C 4.--21. 1. "LO,Line offset" line.long 0x770 "GFXMMU_LUT238L,GFXMMU LUT entry 238 low" hexmask.long.byte 0x770 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x770 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x774 "GFXMMU_LUT238H,GFXMMU LUT entry 238 high" hexmask.long.tbyte 0x774 4.--21. 1. "LO,Line offset" line.long 0x778 "GFXMMU_LUT239L,GFXMMU LUT entry 239 low" hexmask.long.byte 0x778 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x778 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x77C "GFXMMU_LUT239H,GFXMMU LUT entry 239 high" hexmask.long.tbyte 0x77C 4.--21. 1. "LO,Line offset" line.long 0x780 "GFXMMU_LUT240L,GFXMMU LUT entry 240 low" hexmask.long.byte 0x780 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x780 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x784 "GFXMMU_LUT240H,GFXMMU LUT entry 240 high" hexmask.long.tbyte 0x784 4.--21. 1. "LO,Line offset" line.long 0x788 "GFXMMU_LUT241L,GFXMMU LUT entry 241 low" hexmask.long.byte 0x788 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x788 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x78C "GFXMMU_LUT241H,GFXMMU LUT entry 241 high" hexmask.long.tbyte 0x78C 4.--21. 1. "LO,Line offset" line.long 0x790 "GFXMMU_LUT242L,GFXMMU LUT entry 242 low" hexmask.long.byte 0x790 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x790 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x794 "GFXMMU_LUT242H,GFXMMU LUT entry 242 high" hexmask.long.tbyte 0x794 4.--21. 1. "LO,Line offset" line.long 0x798 "GFXMMU_LUT243L,GFXMMU LUT entry 243 low" hexmask.long.byte 0x798 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x798 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x79C "GFXMMU_LUT243H,GFXMMU LUT entry 243 high" hexmask.long.tbyte 0x79C 4.--21. 1. "LO,Line offset" line.long 0x7A0 "GFXMMU_LUT244L,GFXMMU LUT entry 244 low" hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7A4 "GFXMMU_LUT244H,GFXMMU LUT entry 244 high" hexmask.long.tbyte 0x7A4 4.--21. 1. "LO,Line offset" line.long 0x7A8 "GFXMMU_LUT245L,GFXMMU LUT entry 245 low" hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7AC "GFXMMU_LUT245H,GFXMMU LUT entry 245 high" hexmask.long.tbyte 0x7AC 4.--21. 1. "LO,Line offset" line.long 0x7B0 "GFXMMU_LUT246L,GFXMMU LUT entry 246 low" hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7B4 "GFXMMU_LUT246H,GFXMMU LUT entry 246 high" hexmask.long.tbyte 0x7B4 4.--21. 1. "LO,Line offset" line.long 0x7B8 "GFXMMU_LUT247L,GFXMMU LUT entry 247 low" hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7BC "GFXMMU_LUT247H,GFXMMU LUT entry 247 high" hexmask.long.tbyte 0x7BC 4.--21. 1. "LO,Line offset" line.long 0x7C0 "GFXMMU_LUT248L,GFXMMU LUT entry 248 low" hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C4 "GFXMMU_LUT248H,GFXMMU LUT entry 248 high" hexmask.long.tbyte 0x7C4 4.--21. 1. "LO,Line offset" line.long 0x7C8 "GFXMMU_LUT249L,GFXMMU LUT entry 249 low" hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7CC "GFXMMU_LUT249H,GFXMMU LUT entry 249 high" hexmask.long.tbyte 0x7CC 4.--21. 1. "LO,Line offset" line.long 0x7D0 "GFXMMU_LUT250L,GFXMMU LUT entry 250 low" hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7D4 "GFXMMU_LUT250H,GFXMMU LUT entry 250 high" hexmask.long.tbyte 0x7D4 4.--21. 1. "LO,Line offset" line.long 0x7D8 "GFXMMU_LUT251L,GFXMMU LUT entry 251 low" hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7DC "GFXMMU_LUT251H,GFXMMU LUT entry 251 high" hexmask.long.tbyte 0x7DC 4.--21. 1. "LO,Line offset" line.long 0x7E0 "GFXMMU_LUT252L,GFXMMU LUT entry 252 low" hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7E4 "GFXMMU_LUT252H,GFXMMU LUT entry 252 high" hexmask.long.tbyte 0x7E4 4.--21. 1. "LO,Line offset" line.long 0x7E8 "GFXMMU_LUT253L,GFXMMU LUT entry 253 low" hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7EC "GFXMMU_LUT253H,GFXMMU LUT entry 253 high" hexmask.long.tbyte 0x7EC 4.--21. 1. "LO,Line offset" line.long 0x7F0 "GFXMMU_LUT254L,GFXMMU LUT entry 254 low" hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7F4 "GFXMMU_LUT254H,GFXMMU LUT entry 254 high" hexmask.long.tbyte 0x7F4 4.--21. 1. "LO,Line offset" line.long 0x7F8 "GFXMMU_LUT255L,GFXMMU LUT entry 255 low" hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7FC "GFXMMU_LUT255H,GFXMMU LUT entry 255 high" hexmask.long.tbyte 0x7FC 4.--21. 1. "LO,Line offset" line.long 0x800 "GFXMMU_LUT256L,GFXMMU LUT entry 256 low" hexmask.long.byte 0x800 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x800 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x804 "GFXMMU_LUT256H,GFXMMU LUT entry 256 high" hexmask.long.tbyte 0x804 4.--21. 1. "LO,Line offset" line.long 0x808 "GFXMMU_LUT257L,GFXMMU LUT entry 257 low" hexmask.long.byte 0x808 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x808 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x80C "GFXMMU_LUT257H,GFXMMU LUT entry 257 high" hexmask.long.tbyte 0x80C 4.--21. 1. "LO,Line offset" line.long 0x810 "GFXMMU_LUT258L,GFXMMU LUT entry 258 low" hexmask.long.byte 0x810 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x810 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x814 "GFXMMU_LUT258H,GFXMMU LUT entry 258 high" hexmask.long.tbyte 0x814 4.--21. 1. "LO,Line offset" line.long 0x818 "GFXMMU_LUT259L,GFXMMU LUT entry 259 low" hexmask.long.byte 0x818 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x818 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x81C "GFXMMU_LUT259H,GFXMMU LUT entry 259 high" hexmask.long.tbyte 0x81C 4.--21. 1. "LO,Line offset" line.long 0x820 "GFXMMU_LUT260L,GFXMMU LUT entry 260 low" hexmask.long.byte 0x820 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x820 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x824 "GFXMMU_LUT260H,GFXMMU LUT entry 260 high" hexmask.long.tbyte 0x824 4.--21. 1. "LO,Line offset" line.long 0x828 "GFXMMU_LUT261L,GFXMMU LUT entry 261 low" hexmask.long.byte 0x828 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x828 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x82C "GFXMMU_LUT261H,GFXMMU LUT entry 261 high" hexmask.long.tbyte 0x82C 4.--21. 1. "LO,Line offset" line.long 0x830 "GFXMMU_LUT262L,GFXMMU LUT entry 262 low" hexmask.long.byte 0x830 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x830 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x834 "GFXMMU_LUT262H,GFXMMU LUT entry 262 high" hexmask.long.tbyte 0x834 4.--21. 1. "LO,Line offset" line.long 0x838 "GFXMMU_LUT263L,GFXMMU LUT entry 263 low" hexmask.long.byte 0x838 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x838 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x83C "GFXMMU_LUT263H,GFXMMU LUT entry 263 high" hexmask.long.tbyte 0x83C 4.--21. 1. "LO,Line offset" line.long 0x840 "GFXMMU_LUT264L,GFXMMU LUT entry 264 low" hexmask.long.byte 0x840 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x840 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x844 "GFXMMU_LUT264H,GFXMMU LUT entry 264 high" hexmask.long.tbyte 0x844 4.--21. 1. "LO,Line offset" line.long 0x848 "GFXMMU_LUT265L,GFXMMU LUT entry 265 low" hexmask.long.byte 0x848 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x848 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84C "GFXMMU_LUT265H,GFXMMU LUT entry 265 high" hexmask.long.tbyte 0x84C 4.--21. 1. "LO,Line offset" line.long 0x850 "GFXMMU_LUT266L,GFXMMU LUT entry 266 low" hexmask.long.byte 0x850 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x850 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x854 "GFXMMU_LUT266H,GFXMMU LUT entry 266 high" hexmask.long.tbyte 0x854 4.--21. 1. "LO,Line offset" line.long 0x858 "GFXMMU_LUT267L,GFXMMU LUT entry 267 low" hexmask.long.byte 0x858 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x858 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x85C "GFXMMU_LUT267H,GFXMMU LUT entry 267 high" hexmask.long.tbyte 0x85C 4.--21. 1. "LO,Line offset" line.long 0x860 "GFXMMU_LUT268L,GFXMMU LUT entry 268 low" hexmask.long.byte 0x860 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x860 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x864 "GFXMMU_LUT268H,GFXMMU LUT entry 268 high" hexmask.long.tbyte 0x864 4.--21. 1. "LO,Line offset" line.long 0x868 "GFXMMU_LUT269L,GFXMMU LUT entry 269 low" hexmask.long.byte 0x868 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x868 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x86C "GFXMMU_LUT269H,GFXMMU LUT entry 269 high" hexmask.long.tbyte 0x86C 4.--21. 1. "LO,Line offset" line.long 0x870 "GFXMMU_LUT270L,GFXMMU LUT entry 270 low" hexmask.long.byte 0x870 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x870 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x874 "GFXMMU_LUT270H,GFXMMU LUT entry 270 high" hexmask.long.tbyte 0x874 4.--21. 1. "LO,Line offset" line.long 0x878 "GFXMMU_LUT271L,GFXMMU LUT entry 271 low" hexmask.long.byte 0x878 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x878 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x87C "GFXMMU_LUT271H,GFXMMU LUT entry 271 high" hexmask.long.tbyte 0x87C 4.--21. 1. "LO,Line offset" line.long 0x880 "GFXMMU_LUT272L,GFXMMU LUT entry 272 low" hexmask.long.byte 0x880 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x880 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x884 "GFXMMU_LUT272H,GFXMMU LUT entry 272 high" hexmask.long.tbyte 0x884 4.--21. 1. "LO,Line offset" line.long 0x888 "GFXMMU_LUT273L,GFXMMU LUT entry 273 low" hexmask.long.byte 0x888 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x888 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x88C "GFXMMU_LUT273H,GFXMMU LUT entry 273 high" hexmask.long.tbyte 0x88C 4.--21. 1. "LO,Line offset" line.long 0x890 "GFXMMU_LUT274L,GFXMMU LUT entry 274 low" hexmask.long.byte 0x890 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x890 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x894 "GFXMMU_LUT274H,GFXMMU LUT entry 274 high" hexmask.long.tbyte 0x894 4.--21. 1. "LO,Line offset" line.long 0x898 "GFXMMU_LUT275L,GFXMMU LUT entry 275 low" hexmask.long.byte 0x898 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x898 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x89C "GFXMMU_LUT275H,GFXMMU LUT entry 275 high" hexmask.long.tbyte 0x89C 4.--21. 1. "LO,Line offset" line.long 0x8A0 "GFXMMU_LUT276L,GFXMMU LUT entry 276 low" hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8A4 "GFXMMU_LUT276H,GFXMMU LUT entry 276 high" hexmask.long.tbyte 0x8A4 4.--21. 1. "LO,Line offset" line.long 0x8A8 "GFXMMU_LUT277L,GFXMMU LUT entry 277 low" hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8AC "GFXMMU_LUT277H,GFXMMU LUT entry 277 high" hexmask.long.tbyte 0x8AC 4.--21. 1. "LO,Line offset" line.long 0x8B0 "GFXMMU_LUT278L,GFXMMU LUT entry 278 low" hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8B4 "GFXMMU_LUT278H,GFXMMU LUT entry 278 high" hexmask.long.tbyte 0x8B4 4.--21. 1. "LO,Line offset" line.long 0x8B8 "GFXMMU_LUT279L,GFXMMU LUT entry 279 low" hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8BC "GFXMMU_LUT279H,GFXMMU LUT entry 279 high" hexmask.long.tbyte 0x8BC 4.--21. 1. "LO,Line offset" line.long 0x8C0 "GFXMMU_LUT280L,GFXMMU LUT entry 280 low" hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C4 "GFXMMU_LUT280H,GFXMMU LUT entry 280 high" hexmask.long.tbyte 0x8C4 4.--21. 1. "LO,Line offset" line.long 0x8C8 "GFXMMU_LUT281L,GFXMMU LUT entry 281 low" hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8CC "GFXMMU_LUT281H,GFXMMU LUT entry 281 high" hexmask.long.tbyte 0x8CC 4.--21. 1. "LO,Line offset" line.long 0x8D0 "GFXMMU_LUT282L,GFXMMU LUT entry 282 low" hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8D4 "GFXMMU_LUT282H,GFXMMU LUT entry 282 high" hexmask.long.tbyte 0x8D4 4.--21. 1. "LO,Line offset" line.long 0x8D8 "GFXMMU_LUT283L,GFXMMU LUT entry 283 low" hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8DC "GFXMMU_LUT283H,GFXMMU LUT entry 283 high" hexmask.long.tbyte 0x8DC 4.--21. 1. "LO,Line offset" line.long 0x8E0 "GFXMMU_LUT284L,GFXMMU LUT entry 284 low" hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8E4 "GFXMMU_LUT284H,GFXMMU LUT entry 284 high" hexmask.long.tbyte 0x8E4 4.--21. 1. "LO,Line offset" line.long 0x8E8 "GFXMMU_LUT285L,GFXMMU LUT entry 285 low" hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8EC "GFXMMU_LUT285H,GFXMMU LUT entry 285 high" hexmask.long.tbyte 0x8EC 4.--21. 1. "LO,Line offset" line.long 0x8F0 "GFXMMU_LUT286L,GFXMMU LUT entry 286 low" hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8F4 "GFXMMU_LUT286H,GFXMMU LUT entry 286 high" hexmask.long.tbyte 0x8F4 4.--21. 1. "LO,Line offset" line.long 0x8F8 "GFXMMU_LUT287L,GFXMMU LUT entry 287 low" hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8FC "GFXMMU_LUT287H,GFXMMU LUT entry 287 high" hexmask.long.tbyte 0x8FC 4.--21. 1. "LO,Line offset" line.long 0x900 "GFXMMU_LUT288L,GFXMMU LUT entry 288 low" hexmask.long.byte 0x900 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x900 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x904 "GFXMMU_LUT288H,GFXMMU LUT entry 288 high" hexmask.long.tbyte 0x904 4.--21. 1. "LO,Line offset" line.long 0x908 "GFXMMU_LUT289L,GFXMMU LUT entry 289 low" hexmask.long.byte 0x908 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x908 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x90C "GFXMMU_LUT289H,GFXMMU LUT entry 289 high" hexmask.long.tbyte 0x90C 4.--21. 1. "LO,Line offset" line.long 0x910 "GFXMMU_LUT290L,GFXMMU LUT entry 290 low" hexmask.long.byte 0x910 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x910 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x914 "GFXMMU_LUT290H,GFXMMU LUT entry 290 high" hexmask.long.tbyte 0x914 4.--21. 1. "LO,Line offset" line.long 0x918 "GFXMMU_LUT291L,GFXMMU LUT entry 291 low" hexmask.long.byte 0x918 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x918 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x91C "GFXMMU_LUT291H,GFXMMU LUT entry 291 high" hexmask.long.tbyte 0x91C 4.--21. 1. "LO,Line offset" line.long 0x920 "GFXMMU_LUT292L,GFXMMU LUT entry 292 low" hexmask.long.byte 0x920 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x920 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x924 "GFXMMU_LUT292H,GFXMMU LUT entry 292 high" hexmask.long.tbyte 0x924 4.--21. 1. "LO,Line offset" line.long 0x928 "GFXMMU_LUT293L,GFXMMU LUT entry 293 low" hexmask.long.byte 0x928 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x928 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x92C "GFXMMU_LUT293H,GFXMMU LUT entry 293 high" hexmask.long.tbyte 0x92C 4.--21. 1. "LO,Line offset" line.long 0x930 "GFXMMU_LUT294L,GFXMMU LUT entry 294 low" hexmask.long.byte 0x930 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x930 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x934 "GFXMMU_LUT294H,GFXMMU LUT entry 294 high" hexmask.long.tbyte 0x934 4.--21. 1. "LO,Line offset" line.long 0x938 "GFXMMU_LUT295L,GFXMMU LUT entry 295 low" hexmask.long.byte 0x938 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x938 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x93C "GFXMMU_LUT295H,GFXMMU LUT entry 295 high" hexmask.long.tbyte 0x93C 4.--21. 1. "LO,Line offset" line.long 0x940 "GFXMMU_LUT296L,GFXMMU LUT entry 296 low" hexmask.long.byte 0x940 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x940 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x944 "GFXMMU_LUT296H,GFXMMU LUT entry 296 high" hexmask.long.tbyte 0x944 4.--21. 1. "LO,Line offset" line.long 0x948 "GFXMMU_LUT297L,GFXMMU LUT entry 297 low" hexmask.long.byte 0x948 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x948 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94C "GFXMMU_LUT297H,GFXMMU LUT entry 297 high" hexmask.long.tbyte 0x94C 4.--21. 1. "LO,Line offset" line.long 0x950 "GFXMMU_LUT298L,GFXMMU LUT entry 298 low" hexmask.long.byte 0x950 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x950 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x954 "GFXMMU_LUT298H,GFXMMU LUT entry 298 high" hexmask.long.tbyte 0x954 4.--21. 1. "LO,Line offset" line.long 0x958 "GFXMMU_LUT299L,GFXMMU LUT entry 299 low" hexmask.long.byte 0x958 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x958 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x95C "GFXMMU_LUT299H,GFXMMU LUT entry 299 high" hexmask.long.tbyte 0x95C 4.--21. 1. "LO,Line offset" line.long 0x960 "GFXMMU_LUT300L,GFXMMU LUT entry 300 low" hexmask.long.byte 0x960 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x960 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x964 "GFXMMU_LUT300H,GFXMMU LUT entry 300 high" hexmask.long.tbyte 0x964 4.--21. 1. "LO,Line offset" line.long 0x968 "GFXMMU_LUT301L,GFXMMU LUT entry 301 low" hexmask.long.byte 0x968 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x968 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x96C "GFXMMU_LUT301H,GFXMMU LUT entry 301 high" hexmask.long.tbyte 0x96C 4.--21. 1. "LO,Line offset" line.long 0x970 "GFXMMU_LUT302L,GFXMMU LUT entry 302 low" hexmask.long.byte 0x970 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x970 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x974 "GFXMMU_LUT302H,GFXMMU LUT entry 302 high" hexmask.long.tbyte 0x974 4.--21. 1. "LO,Line offset" line.long 0x978 "GFXMMU_LUT303L,GFXMMU LUT entry 303 low" hexmask.long.byte 0x978 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x978 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x97C "GFXMMU_LUT303H,GFXMMU LUT entry 303 high" hexmask.long.tbyte 0x97C 4.--21. 1. "LO,Line offset" line.long 0x980 "GFXMMU_LUT304L,GFXMMU LUT entry 304 low" hexmask.long.byte 0x980 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x980 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x984 "GFXMMU_LUT304H,GFXMMU LUT entry 304 high" hexmask.long.tbyte 0x984 4.--21. 1. "LO,Line offset" line.long 0x988 "GFXMMU_LUT305L,GFXMMU LUT entry 305 low" hexmask.long.byte 0x988 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x988 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x98C "GFXMMU_LUT305H,GFXMMU LUT entry 305 high" hexmask.long.tbyte 0x98C 4.--21. 1. "LO,Line offset" line.long 0x990 "GFXMMU_LUT306L,GFXMMU LUT entry 306 low" hexmask.long.byte 0x990 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x990 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x994 "GFXMMU_LUT306H,GFXMMU LUT entry 306 high" hexmask.long.tbyte 0x994 4.--21. 1. "LO,Line offset" line.long 0x998 "GFXMMU_LUT307L,GFXMMU LUT entry 307 low" hexmask.long.byte 0x998 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x998 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x99C "GFXMMU_LUT307H,GFXMMU LUT entry 307 high" hexmask.long.tbyte 0x99C 4.--21. 1. "LO,Line offset" line.long 0x9A0 "GFXMMU_LUT308L,GFXMMU LUT entry 308 low" hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9A4 "GFXMMU_LUT308H,GFXMMU LUT entry 308 high" hexmask.long.tbyte 0x9A4 4.--21. 1. "LO,Line offset" line.long 0x9A8 "GFXMMU_LUT309L,GFXMMU LUT entry 309 low" hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9AC "GFXMMU_LUT309H,GFXMMU LUT entry 309 high" hexmask.long.tbyte 0x9AC 4.--21. 1. "LO,Line offset" line.long 0x9B0 "GFXMMU_LUT310L,GFXMMU LUT entry 310 low" hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9B4 "GFXMMU_LUT310H,GFXMMU LUT entry 310 high" hexmask.long.tbyte 0x9B4 4.--21. 1. "LO,Line offset" line.long 0x9B8 "GFXMMU_LUT311L,GFXMMU LUT entry 311 low" hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9BC "GFXMMU_LUT311H,GFXMMU LUT entry 311 high" hexmask.long.tbyte 0x9BC 4.--21. 1. "LO,Line offset" line.long 0x9C0 "GFXMMU_LUT312L,GFXMMU LUT entry 312 low" hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C4 "GFXMMU_LUT312H,GFXMMU LUT entry 312 high" hexmask.long.tbyte 0x9C4 4.--21. 1. "LO,Line offset" line.long 0x9C8 "GFXMMU_LUT313L,GFXMMU LUT entry 313 low" hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9CC "GFXMMU_LUT313H,GFXMMU LUT entry 313 high" hexmask.long.tbyte 0x9CC 4.--21. 1. "LO,Line offset" line.long 0x9D0 "GFXMMU_LUT314L,GFXMMU LUT entry 314 low" hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9D4 "GFXMMU_LUT314H,GFXMMU LUT entry 314 high" hexmask.long.tbyte 0x9D4 4.--21. 1. "LO,Line offset" line.long 0x9D8 "GFXMMU_LUT315L,GFXMMU LUT entry 315 low" hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9DC "GFXMMU_LUT315H,GFXMMU LUT entry 315 high" hexmask.long.tbyte 0x9DC 4.--21. 1. "LO,Line offset" line.long 0x9E0 "GFXMMU_LUT316L,GFXMMU LUT entry 316 low" hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9E4 "GFXMMU_LUT316H,GFXMMU LUT entry 316 high" hexmask.long.tbyte 0x9E4 4.--21. 1. "LO,Line offset" line.long 0x9E8 "GFXMMU_LUT317L,GFXMMU LUT entry 317 low" hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9EC "GFXMMU_LUT317H,GFXMMU LUT entry 317 high" hexmask.long.tbyte 0x9EC 4.--21. 1. "LO,Line offset" line.long 0x9F0 "GFXMMU_LUT318L,GFXMMU LUT entry 318 low" hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9F4 "GFXMMU_LUT318H,GFXMMU LUT entry 318 high" hexmask.long.tbyte 0x9F4 4.--21. 1. "LO,Line offset" line.long 0x9F8 "GFXMMU_LUT319L,GFXMMU LUT entry 319 low" hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9FC "GFXMMU_LUT319H,GFXMMU LUT entry 319 high" hexmask.long.tbyte 0x9FC 4.--21. 1. "LO,Line offset" line.long 0xA00 "GFXMMU_LUT320L,GFXMMU LUT entry 320 low" hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA04 "GFXMMU_LUT320H,GFXMMU LUT entry 320 high" hexmask.long.tbyte 0xA04 4.--21. 1. "LO,Line offset" line.long 0xA08 "GFXMMU_LUT321L,GFXMMU LUT entry 321 low" hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA0C "GFXMMU_LUT321H,GFXMMU LUT entry 321 high" hexmask.long.tbyte 0xA0C 4.--21. 1. "LO,Line offset" line.long 0xA10 "GFXMMU_LUT322L,GFXMMU LUT entry 322 low" hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA14 "GFXMMU_LUT322H,GFXMMU LUT entry 322 high" hexmask.long.tbyte 0xA14 4.--21. 1. "LO,Line offset" line.long 0xA18 "GFXMMU_LUT323L,GFXMMU LUT entry 323 low" hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA1C "GFXMMU_LUT323H,GFXMMU LUT entry 323 high" hexmask.long.tbyte 0xA1C 4.--21. 1. "LO,Line offset" line.long 0xA20 "GFXMMU_LUT324L,GFXMMU LUT entry 324 low" hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA24 "GFXMMU_LUT324H,GFXMMU LUT entry 324 high" hexmask.long.tbyte 0xA24 4.--21. 1. "LO,Line offset" line.long 0xA28 "GFXMMU_LUT325L,GFXMMU LUT entry 325 low" hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA2C "GFXMMU_LUT325H,GFXMMU LUT entry 325 high" hexmask.long.tbyte 0xA2C 4.--21. 1. "LO,Line offset" line.long 0xA30 "GFXMMU_LUT326L,GFXMMU LUT entry 326 low" hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA34 "GFXMMU_LUT326H,GFXMMU LUT entry 326 high" hexmask.long.tbyte 0xA34 4.--21. 1. "LO,Line offset" line.long 0xA38 "GFXMMU_LUT327L,GFXMMU LUT entry 327 low" hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA3C "GFXMMU_LUT327H,GFXMMU LUT entry 327 high" hexmask.long.tbyte 0xA3C 4.--21. 1. "LO,Line offset" line.long 0xA40 "GFXMMU_LUT328L,GFXMMU LUT entry 328 low" hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA44 "GFXMMU_LUT328H,GFXMMU LUT entry 328 high" hexmask.long.tbyte 0xA44 4.--21. 1. "LO,Line offset" line.long 0xA48 "GFXMMU_LUT329L,GFXMMU LUT entry 329 low" hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4C "GFXMMU_LUT329H,GFXMMU LUT entry 329 high" hexmask.long.tbyte 0xA4C 4.--21. 1. "LO,Line offset" line.long 0xA50 "GFXMMU_LUT330L,GFXMMU LUT entry 330 low" hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA54 "GFXMMU_LUT330H,GFXMMU LUT entry 330 high" hexmask.long.tbyte 0xA54 4.--21. 1. "LO,Line offset" line.long 0xA58 "GFXMMU_LUT331L,GFXMMU LUT entry 331 low" hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA5C "GFXMMU_LUT331H,GFXMMU LUT entry 331 high" hexmask.long.tbyte 0xA5C 4.--21. 1. "LO,Line offset" line.long 0xA60 "GFXMMU_LUT332L,GFXMMU LUT entry 332 low" hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA64 "GFXMMU_LUT332H,GFXMMU LUT entry 332 high" hexmask.long.tbyte 0xA64 4.--21. 1. "LO,Line offset" line.long 0xA68 "GFXMMU_LUT333L,GFXMMU LUT entry 333 low" hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA6C "GFXMMU_LUT333H,GFXMMU LUT entry 333 high" hexmask.long.tbyte 0xA6C 4.--21. 1. "LO,Line offset" line.long 0xA70 "GFXMMU_LUT334L,GFXMMU LUT entry 334 low" hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA74 "GFXMMU_LUT334H,GFXMMU LUT entry 334 high" hexmask.long.tbyte 0xA74 4.--21. 1. "LO,Line offset" line.long 0xA78 "GFXMMU_LUT335L,GFXMMU LUT entry 335 low" hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA7C "GFXMMU_LUT335H,GFXMMU LUT entry 335 high" hexmask.long.tbyte 0xA7C 4.--21. 1. "LO,Line offset" line.long 0xA80 "GFXMMU_LUT336L,GFXMMU LUT entry 336 low" hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA84 "GFXMMU_LUT336H,GFXMMU LUT entry 336 high" hexmask.long.tbyte 0xA84 4.--21. 1. "LO,Line offset" line.long 0xA88 "GFXMMU_LUT337L,GFXMMU LUT entry 337 low" hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA8C "GFXMMU_LUT337H,GFXMMU LUT entry 337 high" hexmask.long.tbyte 0xA8C 4.--21. 1. "LO,Line offset" line.long 0xA90 "GFXMMU_LUT338L,GFXMMU LUT entry 338 low" hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA94 "GFXMMU_LUT338H,GFXMMU LUT entry 338 high" hexmask.long.tbyte 0xA94 4.--21. 1. "LO,Line offset" line.long 0xA98 "GFXMMU_LUT339L,GFXMMU LUT entry 339 low" hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA9C "GFXMMU_LUT339H,GFXMMU LUT entry 339 high" hexmask.long.tbyte 0xA9C 4.--21. 1. "LO,Line offset" line.long 0xAA0 "GFXMMU_LUT340L,GFXMMU LUT entry 340 low" hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAA4 "GFXMMU_LUT340H,GFXMMU LUT entry 340 high" hexmask.long.tbyte 0xAA4 4.--21. 1. "LO,Line offset" line.long 0xAA8 "GFXMMU_LUT341L,GFXMMU LUT entry 341 low" hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAAC "GFXMMU_LUT341H,GFXMMU LUT entry 341 high" hexmask.long.tbyte 0xAAC 4.--21. 1. "LO,Line offset" line.long 0xAB0 "GFXMMU_LUT342L,GFXMMU LUT entry 342 low" hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAB4 "GFXMMU_LUT342H,GFXMMU LUT entry 342 high" hexmask.long.tbyte 0xAB4 4.--21. 1. "LO,Line offset" line.long 0xAB8 "GFXMMU_LUT343L,GFXMMU LUT entry 343 low" hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xABC "GFXMMU_LUT343H,GFXMMU LUT entry 343 high" hexmask.long.tbyte 0xABC 4.--21. 1. "LO,Line offset" line.long 0xAC0 "GFXMMU_LUT344L,GFXMMU LUT entry 344 low" hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC4 "GFXMMU_LUT344H,GFXMMU LUT entry 344 high" hexmask.long.tbyte 0xAC4 4.--21. 1. "LO,Line offset" line.long 0xAC8 "GFXMMU_LUT345L,GFXMMU LUT entry 345 low" hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xACC "GFXMMU_LUT345H,GFXMMU LUT entry 345 high" hexmask.long.tbyte 0xACC 4.--21. 1. "LO,Line offset" line.long 0xAD0 "GFXMMU_LUT346L,GFXMMU LUT entry 346 low" hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAD4 "GFXMMU_LUT346H,GFXMMU LUT entry 346 high" hexmask.long.tbyte 0xAD4 4.--21. 1. "LO,Line offset" line.long 0xAD8 "GFXMMU_LUT347L,GFXMMU LUT entry 347 low" hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xADC "GFXMMU_LUT347H,GFXMMU LUT entry 347 high" hexmask.long.tbyte 0xADC 4.--21. 1. "LO,Line offset" line.long 0xAE0 "GFXMMU_LUT348L,GFXMMU LUT entry 348 low" hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAE4 "GFXMMU_LUT348H,GFXMMU LUT entry 348 high" hexmask.long.tbyte 0xAE4 4.--21. 1. "LO,Line offset" line.long 0xAE8 "GFXMMU_LUT349L,GFXMMU LUT entry 349 low" hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAEC "GFXMMU_LUT349H,GFXMMU LUT entry 349 high" hexmask.long.tbyte 0xAEC 4.--21. 1. "LO,Line offset" line.long 0xAF0 "GFXMMU_LUT350L,GFXMMU LUT entry 350 low" hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAF4 "GFXMMU_LUT350H,GFXMMU LUT entry 350 high" hexmask.long.tbyte 0xAF4 4.--21. 1. "LO,Line offset" line.long 0xAF8 "GFXMMU_LUT351L,GFXMMU LUT entry 351 low" hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAFC "GFXMMU_LUT351H,GFXMMU LUT entry 351 high" hexmask.long.tbyte 0xAFC 4.--21. 1. "LO,Line offset" line.long 0xB00 "GFXMMU_LUT352L,GFXMMU LUT entry 352 low" hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB04 "GFXMMU_LUT352H,GFXMMU LUT entry 352 high" hexmask.long.tbyte 0xB04 4.--21. 1. "LO,Line offset" line.long 0xB08 "GFXMMU_LUT353L,GFXMMU LUT entry 353 low" hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB0C "GFXMMU_LUT353H,GFXMMU LUT entry 353 high" hexmask.long.tbyte 0xB0C 4.--21. 1. "LO,Line offset" line.long 0xB10 "GFXMMU_LUT354L,GFXMMU LUT entry 354 low" hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB14 "GFXMMU_LUT354H,GFXMMU LUT entry 354 high" hexmask.long.tbyte 0xB14 4.--21. 1. "LO,Line offset" line.long 0xB18 "GFXMMU_LUT355L,GFXMMU LUT entry 355 low" hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB1C "GFXMMU_LUT355H,GFXMMU LUT entry 355 high" hexmask.long.tbyte 0xB1C 4.--21. 1. "LO,Line offset" line.long 0xB20 "GFXMMU_LUT356L,GFXMMU LUT entry 356 low" hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB24 "GFXMMU_LUT356H,GFXMMU LUT entry 356 high" hexmask.long.tbyte 0xB24 4.--21. 1. "LO,Line offset" line.long 0xB28 "GFXMMU_LUT357L,GFXMMU LUT entry 357 low" hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB2C "GFXMMU_LUT357H,GFXMMU LUT entry 357 high" hexmask.long.tbyte 0xB2C 4.--21. 1. "LO,Line offset" line.long 0xB30 "GFXMMU_LUT358L,GFXMMU LUT entry 358 low" hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB34 "GFXMMU_LUT358H,GFXMMU LUT entry 358 high" hexmask.long.tbyte 0xB34 4.--21. 1. "LO,Line offset" line.long 0xB38 "GFXMMU_LUT359L,GFXMMU LUT entry 359 low" hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB3C "GFXMMU_LUT359H,GFXMMU LUT entry 359 high" hexmask.long.tbyte 0xB3C 4.--21. 1. "LO,Line offset" line.long 0xB40 "GFXMMU_LUT360L,GFXMMU LUT entry 360 low" hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB44 "GFXMMU_LUT360H,GFXMMU LUT entry 360 high" hexmask.long.tbyte 0xB44 4.--21. 1. "LO,Line offset" line.long 0xB48 "GFXMMU_LUT361L,GFXMMU LUT entry 361 low" hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4C "GFXMMU_LUT361H,GFXMMU LUT entry 361 high" hexmask.long.tbyte 0xB4C 4.--21. 1. "LO,Line offset" line.long 0xB50 "GFXMMU_LUT362L,GFXMMU LUT entry 362 low" hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB54 "GFXMMU_LUT362H,GFXMMU LUT entry 362 high" hexmask.long.tbyte 0xB54 4.--21. 1. "LO,Line offset" line.long 0xB58 "GFXMMU_LUT363L,GFXMMU LUT entry 363 low" hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB5C "GFXMMU_LUT363H,GFXMMU LUT entry 363 high" hexmask.long.tbyte 0xB5C 4.--21. 1. "LO,Line offset" line.long 0xB60 "GFXMMU_LUT364L,GFXMMU LUT entry 364 low" hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB64 "GFXMMU_LUT364H,GFXMMU LUT entry 364 high" hexmask.long.tbyte 0xB64 4.--21. 1. "LO,Line offset" line.long 0xB68 "GFXMMU_LUT365L,GFXMMU LUT entry 365 low" hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB6C "GFXMMU_LUT365H,GFXMMU LUT entry 365 high" hexmask.long.tbyte 0xB6C 4.--21. 1. "LO,Line offset" line.long 0xB70 "GFXMMU_LUT366L,GFXMMU LUT entry 366 low" hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB74 "GFXMMU_LUT366H,GFXMMU LUT entry 366 high" hexmask.long.tbyte 0xB74 4.--21. 1. "LO,Line offset" line.long 0xB78 "GFXMMU_LUT367L,GFXMMU LUT entry 367 low" hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB7C "GFXMMU_LUT367H,GFXMMU LUT entry 367 high" hexmask.long.tbyte 0xB7C 4.--21. 1. "LO,Line offset" line.long 0xB80 "GFXMMU_LUT368L,GFXMMU LUT entry 368 low" hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB84 "GFXMMU_LUT368H,GFXMMU LUT entry 368 high" hexmask.long.tbyte 0xB84 4.--21. 1. "LO,Line offset" line.long 0xB88 "GFXMMU_LUT369L,GFXMMU LUT entry 369 low" hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB8C "GFXMMU_LUT369H,GFXMMU LUT entry 369 high" hexmask.long.tbyte 0xB8C 4.--21. 1. "LO,Line offset" line.long 0xB90 "GFXMMU_LUT370L,GFXMMU LUT entry 370 low" hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB94 "GFXMMU_LUT370H,GFXMMU LUT entry 370 high" hexmask.long.tbyte 0xB94 4.--21. 1. "LO,Line offset" line.long 0xB98 "GFXMMU_LUT371L,GFXMMU LUT entry 371 low" hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB9C "GFXMMU_LUT371H,GFXMMU LUT entry 371 high" hexmask.long.tbyte 0xB9C 4.--21. 1. "LO,Line offset" line.long 0xBA0 "GFXMMU_LUT372L,GFXMMU LUT entry 372 low" hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBA4 "GFXMMU_LUT372H,GFXMMU LUT entry 372 high" hexmask.long.tbyte 0xBA4 4.--21. 1. "LO,Line offset" line.long 0xBA8 "GFXMMU_LUT373L,GFXMMU LUT entry 373 low" hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBAC "GFXMMU_LUT373H,GFXMMU LUT entry 373 high" hexmask.long.tbyte 0xBAC 4.--21. 1. "LO,Line offset" line.long 0xBB0 "GFXMMU_LUT374L,GFXMMU LUT entry 374 low" hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBB4 "GFXMMU_LUT374H,GFXMMU LUT entry 374 high" hexmask.long.tbyte 0xBB4 4.--21. 1. "LO,Line offset" line.long 0xBB8 "GFXMMU_LUT375L,GFXMMU LUT entry 375 low" hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBBC "GFXMMU_LUT375H,GFXMMU LUT entry 375 high" hexmask.long.tbyte 0xBBC 4.--21. 1. "LO,Line offset" line.long 0xBC0 "GFXMMU_LUT376L,GFXMMU LUT entry 376 low" hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC4 "GFXMMU_LUT376H,GFXMMU LUT entry 376 high" hexmask.long.tbyte 0xBC4 4.--21. 1. "LO,Line offset" line.long 0xBC8 "GFXMMU_LUT377L,GFXMMU LUT entry 377 low" hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBCC "GFXMMU_LUT377H,GFXMMU LUT entry 377 high" hexmask.long.tbyte 0xBCC 4.--21. 1. "LO,Line offset" line.long 0xBD0 "GFXMMU_LUT378L,GFXMMU LUT entry 378 low" hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBD4 "GFXMMU_LUT378H,GFXMMU LUT entry 378 high" hexmask.long.tbyte 0xBD4 4.--21. 1. "LO,Line offset" line.long 0xBD8 "GFXMMU_LUT379L,GFXMMU LUT entry 379 low" hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBDC "GFXMMU_LUT379H,GFXMMU LUT entry 379 high" hexmask.long.tbyte 0xBDC 4.--21. 1. "LO,Line offset" line.long 0xBE0 "GFXMMU_LUT380L,GFXMMU LUT entry 380 low" hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBE4 "GFXMMU_LUT380H,GFXMMU LUT entry 380 high" hexmask.long.tbyte 0xBE4 4.--21. 1. "LO,Line offset" line.long 0xBE8 "GFXMMU_LUT381L,GFXMMU LUT entry 381 low" hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBEC "GFXMMU_LUT381H,GFXMMU LUT entry 381 high" hexmask.long.tbyte 0xBEC 4.--21. 1. "LO,Line offset" line.long 0xBF0 "GFXMMU_LUT382L,GFXMMU LUT entry 382 low" hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBF4 "GFXMMU_LUT382H,GFXMMU LUT entry 382 high" hexmask.long.tbyte 0xBF4 4.--21. 1. "LO,Line offset" line.long 0xBF8 "GFXMMU_LUT383L,GFXMMU LUT entry 383 low" hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBFC "GFXMMU_LUT383H,GFXMMU LUT entry 383 high" hexmask.long.tbyte 0xBFC 4.--21. 1. "LO,Line offset" line.long 0xC00 "GFXMMU_LUT384L,GFXMMU LUT entry 384 low" hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC04 "GFXMMU_LUT384H,GFXMMU LUT entry 384 high" hexmask.long.tbyte 0xC04 4.--21. 1. "LO,Line offset" line.long 0xC08 "GFXMMU_LUT385L,GFXMMU LUT entry 385 low" hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC0C "GFXMMU_LUT385H,GFXMMU LUT entry 385 high" hexmask.long.tbyte 0xC0C 4.--21. 1. "LO,Line offset" line.long 0xC10 "GFXMMU_LUT386L,GFXMMU LUT entry 386 low" hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC14 "GFXMMU_LUT386H,GFXMMU LUT entry 386 high" hexmask.long.tbyte 0xC14 4.--21. 1. "LO,Line offset" line.long 0xC18 "GFXMMU_LUT387L,GFXMMU LUT entry 387 low" hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC1C "GFXMMU_LUT387H,GFXMMU LUT entry 387 high" hexmask.long.tbyte 0xC1C 4.--21. 1. "LO,Line offset" line.long 0xC20 "GFXMMU_LUT388L,GFXMMU LUT entry 388 low" hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC24 "GFXMMU_LUT388H,GFXMMU LUT entry 388 high" hexmask.long.tbyte 0xC24 4.--21. 1. "LO,Line offset" line.long 0xC28 "GFXMMU_LUT389L,GFXMMU LUT entry 389 low" hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC2C "GFXMMU_LUT389H,GFXMMU LUT entry 389 high" hexmask.long.tbyte 0xC2C 4.--21. 1. "LO,Line offset" line.long 0xC30 "GFXMMU_LUT390L,GFXMMU LUT entry 390 low" hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC34 "GFXMMU_LUT390H,GFXMMU LUT entry 390 high" hexmask.long.tbyte 0xC34 4.--21. 1. "LO,Line offset" line.long 0xC38 "GFXMMU_LUT391L,GFXMMU LUT entry 391 low" hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC3C "GFXMMU_LUT391H,GFXMMU LUT entry 391 high" hexmask.long.tbyte 0xC3C 4.--21. 1. "LO,Line offset" line.long 0xC40 "GFXMMU_LUT392L,GFXMMU LUT entry 392 low" hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC44 "GFXMMU_LUT392H,GFXMMU LUT entry 392 high" hexmask.long.tbyte 0xC44 4.--21. 1. "LO,Line offset" line.long 0xC48 "GFXMMU_LUT393L,GFXMMU LUT entry 393 low" hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4C "GFXMMU_LUT393H,GFXMMU LUT entry 393 high" hexmask.long.tbyte 0xC4C 4.--21. 1. "LO,Line offset" line.long 0xC50 "GFXMMU_LUT394L,GFXMMU LUT entry 394 low" hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC54 "GFXMMU_LUT394H,GFXMMU LUT entry 394 high" hexmask.long.tbyte 0xC54 4.--21. 1. "LO,Line offset" line.long 0xC58 "GFXMMU_LUT395L,GFXMMU LUT entry 395 low" hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC5C "GFXMMU_LUT395H,GFXMMU LUT entry 395 high" hexmask.long.tbyte 0xC5C 4.--21. 1. "LO,Line offset" line.long 0xC60 "GFXMMU_LUT396L,GFXMMU LUT entry 396 low" hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC64 "GFXMMU_LUT396H,GFXMMU LUT entry 396 high" hexmask.long.tbyte 0xC64 4.--21. 1. "LO,Line offset" line.long 0xC68 "GFXMMU_LUT397L,GFXMMU LUT entry 397 low" hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC6C "GFXMMU_LUT397H,GFXMMU LUT entry 397 high" hexmask.long.tbyte 0xC6C 4.--21. 1. "LO,Line offset" line.long 0xC70 "GFXMMU_LUT398L,GFXMMU LUT entry 398 low" hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC74 "GFXMMU_LUT398H,GFXMMU LUT entry 398 high" hexmask.long.tbyte 0xC74 4.--21. 1. "LO,Line offset" line.long 0xC78 "GFXMMU_LUT399L,GFXMMU LUT entry 399 low" hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC7C "GFXMMU_LUT399H,GFXMMU LUT entry 399 high" hexmask.long.tbyte 0xC7C 4.--21. 1. "LO,Line offset" line.long 0xC80 "GFXMMU_LUT400L,GFXMMU LUT entry 400 low" hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC84 "GFXMMU_LUT400H,GFXMMU LUT entry 400 high" hexmask.long.tbyte 0xC84 4.--21. 1. "LO,Line offset" line.long 0xC88 "GFXMMU_LUT401L,GFXMMU LUT entry 401 low" hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC8C "GFXMMU_LUT401H,GFXMMU LUT entry 401 high" hexmask.long.tbyte 0xC8C 4.--21. 1. "LO,Line offset" line.long 0xC90 "GFXMMU_LUT402L,GFXMMU LUT entry 402 low" hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC94 "GFXMMU_LUT402H,GFXMMU LUT entry 402 high" hexmask.long.tbyte 0xC94 4.--21. 1. "LO,Line offset" line.long 0xC98 "GFXMMU_LUT403L,GFXMMU LUT entry 403 low" hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC9C "GFXMMU_LUT403H,GFXMMU LUT entry 403 high" hexmask.long.tbyte 0xC9C 4.--21. 1. "LO,Line offset" line.long 0xCA0 "GFXMMU_LUT404L,GFXMMU LUT entry 404 low" hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCA4 "GFXMMU_LUT404H,GFXMMU LUT entry 404 high" hexmask.long.tbyte 0xCA4 4.--21. 1. "LO,Line offset" line.long 0xCA8 "GFXMMU_LUT405L,GFXMMU LUT entry 405 low" hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCAC "GFXMMU_LUT405H,GFXMMU LUT entry 405 high" hexmask.long.tbyte 0xCAC 4.--21. 1. "LO,Line offset" line.long 0xCB0 "GFXMMU_LUT406L,GFXMMU LUT entry 406 low" hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCB4 "GFXMMU_LUT406H,GFXMMU LUT entry 406 high" hexmask.long.tbyte 0xCB4 4.--21. 1. "LO,Line offset" line.long 0xCB8 "GFXMMU_LUT407L,GFXMMU LUT entry 407 low" hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCBC "GFXMMU_LUT407H,GFXMMU LUT entry 407 high" hexmask.long.tbyte 0xCBC 4.--21. 1. "LO,Line offset" line.long 0xCC0 "GFXMMU_LUT408L,GFXMMU LUT entry 408 low" hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC4 "GFXMMU_LUT408H,GFXMMU LUT entry 408 high" hexmask.long.tbyte 0xCC4 4.--21. 1. "LO,Line offset" line.long 0xCC8 "GFXMMU_LUT409L,GFXMMU LUT entry 409 low" hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCCC "GFXMMU_LUT409H,GFXMMU LUT entry 409 high" hexmask.long.tbyte 0xCCC 4.--21. 1. "LO,Line offset" line.long 0xCD0 "GFXMMU_LUT410L,GFXMMU LUT entry 410 low" hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCD4 "GFXMMU_LUT410H,GFXMMU LUT entry 410 high" hexmask.long.tbyte 0xCD4 4.--21. 1. "LO,Line offset" line.long 0xCD8 "GFXMMU_LUT411L,GFXMMU LUT entry 411 low" hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCDC "GFXMMU_LUT411H,GFXMMU LUT entry 411 high" hexmask.long.tbyte 0xCDC 4.--21. 1. "LO,Line offset" line.long 0xCE0 "GFXMMU_LUT412L,GFXMMU LUT entry 412 low" hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCE4 "GFXMMU_LUT412H,GFXMMU LUT entry 412 high" hexmask.long.tbyte 0xCE4 4.--21. 1. "LO,Line offset" line.long 0xCE8 "GFXMMU_LUT413L,GFXMMU LUT entry 413 low" hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCEC "GFXMMU_LUT413H,GFXMMU LUT entry 413 high" hexmask.long.tbyte 0xCEC 4.--21. 1. "LO,Line offset" line.long 0xCF0 "GFXMMU_LUT414L,GFXMMU LUT entry 414 low" hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCF4 "GFXMMU_LUT414H,GFXMMU LUT entry 414 high" hexmask.long.tbyte 0xCF4 4.--21. 1. "LO,Line offset" line.long 0xCF8 "GFXMMU_LUT415L,GFXMMU LUT entry 415 low" hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCFC "GFXMMU_LUT415H,GFXMMU LUT entry 415 high" hexmask.long.tbyte 0xCFC 4.--21. 1. "LO,Line offset" line.long 0xD00 "GFXMMU_LUT416L,GFXMMU LUT entry 416 low" hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD04 "GFXMMU_LUT416H,GFXMMU LUT entry 416 high" hexmask.long.tbyte 0xD04 4.--21. 1. "LO,Line offset" line.long 0xD08 "GFXMMU_LUT417L,GFXMMU LUT entry 417 low" hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD0C "GFXMMU_LUT417H,GFXMMU LUT entry 417 high" hexmask.long.tbyte 0xD0C 4.--21. 1. "LO,Line offset" line.long 0xD10 "GFXMMU_LUT418L,GFXMMU LUT entry 418 low" hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD14 "GFXMMU_LUT418H,GFXMMU LUT entry 418 high" hexmask.long.tbyte 0xD14 4.--21. 1. "LO,Line offset" line.long 0xD18 "GFXMMU_LUT419L,GFXMMU LUT entry 419 low" hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD1C "GFXMMU_LUT419H,GFXMMU LUT entry 419 high" hexmask.long.tbyte 0xD1C 4.--21. 1. "LO,Line offset" line.long 0xD20 "GFXMMU_LUT420L,GFXMMU LUT entry 420 low" hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD24 "GFXMMU_LUT420H,GFXMMU LUT entry 420 high" hexmask.long.tbyte 0xD24 4.--21. 1. "LO,Line offset" line.long 0xD28 "GFXMMU_LUT421L,GFXMMU LUT entry 421 low" hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD2C "GFXMMU_LUT421H,GFXMMU LUT entry 421 high" hexmask.long.tbyte 0xD2C 4.--21. 1. "LO,Line offset" line.long 0xD30 "GFXMMU_LUT422L,GFXMMU LUT entry 422 low" hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD34 "GFXMMU_LUT422H,GFXMMU LUT entry 422 high" hexmask.long.tbyte 0xD34 4.--21. 1. "LO,Line offset" line.long 0xD38 "GFXMMU_LUT423L,GFXMMU LUT entry 423 low" hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD3C "GFXMMU_LUT423H,GFXMMU LUT entry 423 high" hexmask.long.tbyte 0xD3C 4.--21. 1. "LO,Line offset" line.long 0xD40 "GFXMMU_LUT424L,GFXMMU LUT entry 424 low" hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD44 "GFXMMU_LUT424H,GFXMMU LUT entry 424 high" hexmask.long.tbyte 0xD44 4.--21. 1. "LO,Line offset" line.long 0xD48 "GFXMMU_LUT425L,GFXMMU LUT entry 425 low" hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4C "GFXMMU_LUT425H,GFXMMU LUT entry 425 high" hexmask.long.tbyte 0xD4C 4.--21. 1. "LO,Line offset" line.long 0xD50 "GFXMMU_LUT426L,GFXMMU LUT entry 426 low" hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD54 "GFXMMU_LUT426H,GFXMMU LUT entry 426 high" hexmask.long.tbyte 0xD54 4.--21. 1. "LO,Line offset" line.long 0xD58 "GFXMMU_LUT427L,GFXMMU LUT entry 427 low" hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD5C "GFXMMU_LUT427H,GFXMMU LUT entry 427 high" hexmask.long.tbyte 0xD5C 4.--21. 1. "LO,Line offset" line.long 0xD60 "GFXMMU_LUT428L,GFXMMU LUT entry 428 low" hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD64 "GFXMMU_LUT428H,GFXMMU LUT entry 428 high" hexmask.long.tbyte 0xD64 4.--21. 1. "LO,Line offset" line.long 0xD68 "GFXMMU_LUT429L,GFXMMU LUT entry 429 low" hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD6C "GFXMMU_LUT429H,GFXMMU LUT entry 429 high" hexmask.long.tbyte 0xD6C 4.--21. 1. "LO,Line offset" line.long 0xD70 "GFXMMU_LUT430L,GFXMMU LUT entry 430 low" hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD74 "GFXMMU_LUT430H,GFXMMU LUT entry 430 high" hexmask.long.tbyte 0xD74 4.--21. 1. "LO,Line offset" line.long 0xD78 "GFXMMU_LUT431L,GFXMMU LUT entry 431 low" hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD7C "GFXMMU_LUT431H,GFXMMU LUT entry 431 high" hexmask.long.tbyte 0xD7C 4.--21. 1. "LO,Line offset" line.long 0xD80 "GFXMMU_LUT432L,GFXMMU LUT entry 432 low" hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD84 "GFXMMU_LUT432H,GFXMMU LUT entry 432 high" hexmask.long.tbyte 0xD84 4.--21. 1. "LO,Line offset" line.long 0xD88 "GFXMMU_LUT433L,GFXMMU LUT entry 433 low" hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD8C "GFXMMU_LUT433H,GFXMMU LUT entry 433 high" hexmask.long.tbyte 0xD8C 4.--21. 1. "LO,Line offset" line.long 0xD90 "GFXMMU_LUT434L,GFXMMU LUT entry 434 low" hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD94 "GFXMMU_LUT434H,GFXMMU LUT entry 434 high" hexmask.long.tbyte 0xD94 4.--21. 1. "LO,Line offset" line.long 0xD98 "GFXMMU_LUT435L,GFXMMU LUT entry 435 low" hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD9C "GFXMMU_LUT435H,GFXMMU LUT entry 435 high" hexmask.long.tbyte 0xD9C 4.--21. 1. "LO,Line offset" line.long 0xDA0 "GFXMMU_LUT436L,GFXMMU LUT entry 436 low" hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDA4 "GFXMMU_LUT436H,GFXMMU LUT entry 436 high" hexmask.long.tbyte 0xDA4 4.--21. 1. "LO,Line offset" line.long 0xDA8 "GFXMMU_LUT437L,GFXMMU LUT entry 437 low" hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDAC "GFXMMU_LUT437H,GFXMMU LUT entry 437 high" hexmask.long.tbyte 0xDAC 4.--21. 1. "LO,Line offset" line.long 0xDB0 "GFXMMU_LUT438L,GFXMMU LUT entry 438 low" hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDB4 "GFXMMU_LUT438H,GFXMMU LUT entry 438 high" hexmask.long.tbyte 0xDB4 4.--21. 1. "LO,Line offset" line.long 0xDB8 "GFXMMU_LUT439L,GFXMMU LUT entry 439 low" hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDBC "GFXMMU_LUT439H,GFXMMU LUT entry 439 high" hexmask.long.tbyte 0xDBC 4.--21. 1. "LO,Line offset" line.long 0xDC0 "GFXMMU_LUT440L,GFXMMU LUT entry 440 low" hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC4 "GFXMMU_LUT440H,GFXMMU LUT entry 440 high" hexmask.long.tbyte 0xDC4 4.--21. 1. "LO,Line offset" line.long 0xDC8 "GFXMMU_LUT441L,GFXMMU LUT entry 441 low" hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDCC "GFXMMU_LUT441H,GFXMMU LUT entry 441 high" hexmask.long.tbyte 0xDCC 4.--21. 1. "LO,Line offset" line.long 0xDD0 "GFXMMU_LUT442L,GFXMMU LUT entry 442 low" hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDD4 "GFXMMU_LUT442H,GFXMMU LUT entry 442 high" hexmask.long.tbyte 0xDD4 4.--21. 1. "LO,Line offset" line.long 0xDD8 "GFXMMU_LUT443L,GFXMMU LUT entry 443 low" hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDDC "GFXMMU_LUT443H,GFXMMU LUT entry 443 high" hexmask.long.tbyte 0xDDC 4.--21. 1. "LO,Line offset" line.long 0xDE0 "GFXMMU_LUT444L,GFXMMU LUT entry 444 low" hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDE4 "GFXMMU_LUT444H,GFXMMU LUT entry 444 high" hexmask.long.tbyte 0xDE4 4.--21. 1. "LO,Line offset" line.long 0xDE8 "GFXMMU_LUT445L,GFXMMU LUT entry 445 low" hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDEC "GFXMMU_LUT445H,GFXMMU LUT entry 445 high" hexmask.long.tbyte 0xDEC 4.--21. 1. "LO,Line offset" line.long 0xDF0 "GFXMMU_LUT446L,GFXMMU LUT entry 446 low" hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDF4 "GFXMMU_LUT446H,GFXMMU LUT entry 446 high" hexmask.long.tbyte 0xDF4 4.--21. 1. "LO,Line offset" line.long 0xDF8 "GFXMMU_LUT447L,GFXMMU LUT entry 447 low" hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDFC "GFXMMU_LUT447H,GFXMMU LUT entry 447 high" hexmask.long.tbyte 0xDFC 4.--21. 1. "LO,Line offset" line.long 0xE00 "GFXMMU_LUT448L,GFXMMU LUT entry 448 low" hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE04 "GFXMMU_LUT448H,GFXMMU LUT entry 448 high" hexmask.long.tbyte 0xE04 4.--21. 1. "LO,Line offset" line.long 0xE08 "GFXMMU_LUT449L,GFXMMU LUT entry 449 low" hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE0C "GFXMMU_LUT449H,GFXMMU LUT entry 449 high" hexmask.long.tbyte 0xE0C 4.--21. 1. "LO,Line offset" line.long 0xE10 "GFXMMU_LUT450L,GFXMMU LUT entry 450 low" hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE14 "GFXMMU_LUT450H,GFXMMU LUT entry 450 high" hexmask.long.tbyte 0xE14 4.--21. 1. "LO,Line offset" line.long 0xE18 "GFXMMU_LUT451L,GFXMMU LUT entry 451 low" hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE1C "GFXMMU_LUT451H,GFXMMU LUT entry 451 high" hexmask.long.tbyte 0xE1C 4.--21. 1. "LO,Line offset" line.long 0xE20 "GFXMMU_LUT452L,GFXMMU LUT entry 452 low" hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE24 "GFXMMU_LUT452H,GFXMMU LUT entry 452 high" hexmask.long.tbyte 0xE24 4.--21. 1. "LO,Line offset" line.long 0xE28 "GFXMMU_LUT453L,GFXMMU LUT entry 453 low" hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE2C "GFXMMU_LUT453H,GFXMMU LUT entry 453 high" hexmask.long.tbyte 0xE2C 4.--21. 1. "LO,Line offset" line.long 0xE30 "GFXMMU_LUT454L,GFXMMU LUT entry 454 low" hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE34 "GFXMMU_LUT454H,GFXMMU LUT entry 454 high" hexmask.long.tbyte 0xE34 4.--21. 1. "LO,Line offset" line.long 0xE38 "GFXMMU_LUT455L,GFXMMU LUT entry 455 low" hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE3C "GFXMMU_LUT455H,GFXMMU LUT entry 455 high" hexmask.long.tbyte 0xE3C 4.--21. 1. "LO,Line offset" line.long 0xE40 "GFXMMU_LUT456L,GFXMMU LUT entry 456 low" hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE44 "GFXMMU_LUT456H,GFXMMU LUT entry 456 high" hexmask.long.tbyte 0xE44 4.--21. 1. "LO,Line offset" line.long 0xE48 "GFXMMU_LUT457L,GFXMMU LUT entry 457 low" hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4C "GFXMMU_LUT457H,GFXMMU LUT entry 457 high" hexmask.long.tbyte 0xE4C 4.--21. 1. "LO,Line offset" line.long 0xE50 "GFXMMU_LUT458L,GFXMMU LUT entry 458 low" hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE54 "GFXMMU_LUT458H,GFXMMU LUT entry 458 high" hexmask.long.tbyte 0xE54 4.--21. 1. "LO,Line offset" line.long 0xE58 "GFXMMU_LUT459L,GFXMMU LUT entry 459 low" hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE5C "GFXMMU_LUT459H,GFXMMU LUT entry 459 high" hexmask.long.tbyte 0xE5C 4.--21. 1. "LO,Line offset" line.long 0xE60 "GFXMMU_LUT460L,GFXMMU LUT entry 460 low" hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE64 "GFXMMU_LUT460H,GFXMMU LUT entry 460 high" hexmask.long.tbyte 0xE64 4.--21. 1. "LO,Line offset" line.long 0xE68 "GFXMMU_LUT461L,GFXMMU LUT entry 461 low" hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE6C "GFXMMU_LUT461H,GFXMMU LUT entry 461 high" hexmask.long.tbyte 0xE6C 4.--21. 1. "LO,Line offset" line.long 0xE70 "GFXMMU_LUT462L,GFXMMU LUT entry 462 low" hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE74 "GFXMMU_LUT462H,GFXMMU LUT entry 462 high" hexmask.long.tbyte 0xE74 4.--21. 1. "LO,Line offset" line.long 0xE78 "GFXMMU_LUT463L,GFXMMU LUT entry 463 low" hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE7C "GFXMMU_LUT463H,GFXMMU LUT entry 463 high" hexmask.long.tbyte 0xE7C 4.--21. 1. "LO,Line offset" line.long 0xE80 "GFXMMU_LUT464L,GFXMMU LUT entry 464 low" hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE84 "GFXMMU_LUT464H,GFXMMU LUT entry 464 high" hexmask.long.tbyte 0xE84 4.--21. 1. "LO,Line offset" line.long 0xE88 "GFXMMU_LUT465L,GFXMMU LUT entry 465 low" hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE8C "GFXMMU_LUT465H,GFXMMU LUT entry 465 high" hexmask.long.tbyte 0xE8C 4.--21. 1. "LO,Line offset" line.long 0xE90 "GFXMMU_LUT466L,GFXMMU LUT entry 466 low" hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE94 "GFXMMU_LUT466H,GFXMMU LUT entry 466 high" hexmask.long.tbyte 0xE94 4.--21. 1. "LO,Line offset" line.long 0xE98 "GFXMMU_LUT467L,GFXMMU LUT entry 467 low" hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE9C "GFXMMU_LUT467H,GFXMMU LUT entry 467 high" hexmask.long.tbyte 0xE9C 4.--21. 1. "LO,Line offset" line.long 0xEA0 "GFXMMU_LUT468L,GFXMMU LUT entry 468 low" hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEA4 "GFXMMU_LUT468H,GFXMMU LUT entry 468 high" hexmask.long.tbyte 0xEA4 4.--21. 1. "LO,Line offset" line.long 0xEA8 "GFXMMU_LUT469L,GFXMMU LUT entry 469 low" hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEAC "GFXMMU_LUT469H,GFXMMU LUT entry 469 high" hexmask.long.tbyte 0xEAC 4.--21. 1. "LO,Line offset" line.long 0xEB0 "GFXMMU_LUT470L,GFXMMU LUT entry 470 low" hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEB4 "GFXMMU_LUT470H,GFXMMU LUT entry 470 high" hexmask.long.tbyte 0xEB4 4.--21. 1. "LO,Line offset" line.long 0xEB8 "GFXMMU_LUT471L,GFXMMU LUT entry 471 low" hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEBC "GFXMMU_LUT471H,GFXMMU LUT entry 471 high" hexmask.long.tbyte 0xEBC 4.--21. 1. "LO,Line offset" line.long 0xEC0 "GFXMMU_LUT472L,GFXMMU LUT entry 472 low" hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC4 "GFXMMU_LUT472H,GFXMMU LUT entry 472 high" hexmask.long.tbyte 0xEC4 4.--21. 1. "LO,Line offset" line.long 0xEC8 "GFXMMU_LUT473L,GFXMMU LUT entry 473 low" hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xECC "GFXMMU_LUT473H,GFXMMU LUT entry 473 high" hexmask.long.tbyte 0xECC 4.--21. 1. "LO,Line offset" line.long 0xED0 "GFXMMU_LUT474L,GFXMMU LUT entry 474 low" hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xED0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xED4 "GFXMMU_LUT474H,GFXMMU LUT entry 474 high" hexmask.long.tbyte 0xED4 4.--21. 1. "LO,Line offset" line.long 0xED8 "GFXMMU_LUT475L,GFXMMU LUT entry 475 low" hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xED8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEDC "GFXMMU_LUT475H,GFXMMU LUT entry 475 high" hexmask.long.tbyte 0xEDC 4.--21. 1. "LO,Line offset" line.long 0xEE0 "GFXMMU_LUT476L,GFXMMU LUT entry 476 low" hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEE4 "GFXMMU_LUT476H,GFXMMU LUT entry 476 high" hexmask.long.tbyte 0xEE4 4.--21. 1. "LO,Line offset" line.long 0xEE8 "GFXMMU_LUT477L,GFXMMU LUT entry 477 low" hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEEC "GFXMMU_LUT477H,GFXMMU LUT entry 477 high" hexmask.long.tbyte 0xEEC 4.--21. 1. "LO,Line offset" line.long 0xEF0 "GFXMMU_LUT478L,GFXMMU LUT entry 478 low" hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEF4 "GFXMMU_LUT478H,GFXMMU LUT entry 478 high" hexmask.long.tbyte 0xEF4 4.--21. 1. "LO,Line offset" line.long 0xEF8 "GFXMMU_LUT479L,GFXMMU LUT entry 479 low" hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEFC "GFXMMU_LUT479H,GFXMMU LUT entry 479 high" hexmask.long.tbyte 0xEFC 4.--21. 1. "LO,Line offset" line.long 0xF00 "GFXMMU_LUT480L,GFXMMU LUT entry 480 low" hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF04 "GFXMMU_LUT480H,GFXMMU LUT entry 480 high" hexmask.long.tbyte 0xF04 4.--21. 1. "LO,Line offset" line.long 0xF08 "GFXMMU_LUT481L,GFXMMU LUT entry 481 low" hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF0C "GFXMMU_LUT481H,GFXMMU LUT entry 481 high" hexmask.long.tbyte 0xF0C 4.--21. 1. "LO,Line offset" line.long 0xF10 "GFXMMU_LUT482L,GFXMMU LUT entry 482 low" hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF14 "GFXMMU_LUT482H,GFXMMU LUT entry 482 high" hexmask.long.tbyte 0xF14 4.--21. 1. "LO,Line offset" line.long 0xF18 "GFXMMU_LUT483L,GFXMMU LUT entry 483 low" hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF1C "GFXMMU_LUT483H,GFXMMU LUT entry 483 high" hexmask.long.tbyte 0xF1C 4.--21. 1. "LO,Line offset" line.long 0xF20 "GFXMMU_LUT484L,GFXMMU LUT entry 484 low" hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF24 "GFXMMU_LUT484H,GFXMMU LUT entry 484 high" hexmask.long.tbyte 0xF24 4.--21. 1. "LO,Line offset" line.long 0xF28 "GFXMMU_LUT485L,GFXMMU LUT entry 485 low" hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF2C "GFXMMU_LUT485H,GFXMMU LUT entry 485 high" hexmask.long.tbyte 0xF2C 4.--21. 1. "LO,Line offset" line.long 0xF30 "GFXMMU_LUT486L,GFXMMU LUT entry 486 low" hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF34 "GFXMMU_LUT486H,GFXMMU LUT entry 486 high" hexmask.long.tbyte 0xF34 4.--21. 1. "LO,Line offset" line.long 0xF38 "GFXMMU_LUT487L,GFXMMU LUT entry 487 low" hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF3C "GFXMMU_LUT487H,GFXMMU LUT entry 487 high" hexmask.long.tbyte 0xF3C 4.--21. 1. "LO,Line offset" line.long 0xF40 "GFXMMU_LUT488L,GFXMMU LUT entry 488 low" hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF44 "GFXMMU_LUT488H,GFXMMU LUT entry 488 high" hexmask.long.tbyte 0xF44 4.--21. 1. "LO,Line offset" line.long 0xF48 "GFXMMU_LUT489L,GFXMMU LUT entry 489 low" hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4C "GFXMMU_LUT489H,GFXMMU LUT entry 489 high" hexmask.long.tbyte 0xF4C 4.--21. 1. "LO,Line offset" line.long 0xF50 "GFXMMU_LUT490L,GFXMMU LUT entry 490 low" hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF54 "GFXMMU_LUT490H,GFXMMU LUT entry 490 high" hexmask.long.tbyte 0xF54 4.--21. 1. "LO,Line offset" line.long 0xF58 "GFXMMU_LUT491L,GFXMMU LUT entry 491 low" hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF5C "GFXMMU_LUT491H,GFXMMU LUT entry 491 high" hexmask.long.tbyte 0xF5C 4.--21. 1. "LO,Line offset" line.long 0xF60 "GFXMMU_LUT492L,GFXMMU LUT entry 492 low" hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF64 "GFXMMU_LUT492H,GFXMMU LUT entry 492 high" hexmask.long.tbyte 0xF64 4.--21. 1. "LO,Line offset" line.long 0xF68 "GFXMMU_LUT493L,GFXMMU LUT entry 493 low" hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF6C "GFXMMU_LUT493H,GFXMMU LUT entry 493 high" hexmask.long.tbyte 0xF6C 4.--21. 1. "LO,Line offset" line.long 0xF70 "GFXMMU_LUT494L,GFXMMU LUT entry 494 low" hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF74 "GFXMMU_LUT494H,GFXMMU LUT entry 494 high" hexmask.long.tbyte 0xF74 4.--21. 1. "LO,Line offset" line.long 0xF78 "GFXMMU_LUT495L,GFXMMU LUT entry 495 low" hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF7C "GFXMMU_LUT495H,GFXMMU LUT entry 495 high" hexmask.long.tbyte 0xF7C 4.--21. 1. "LO,Line offset" line.long 0xF80 "GFXMMU_LUT496L,GFXMMU LUT entry 496 low" hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF84 "GFXMMU_LUT496H,GFXMMU LUT entry 496 high" hexmask.long.tbyte 0xF84 4.--21. 1. "LO,Line offset" line.long 0xF88 "GFXMMU_LUT497L,GFXMMU LUT entry 497 low" hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF8C "GFXMMU_LUT497H,GFXMMU LUT entry 497 high" hexmask.long.tbyte 0xF8C 4.--21. 1. "LO,Line offset" line.long 0xF90 "GFXMMU_LUT498L,GFXMMU LUT entry 498 low" hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF94 "GFXMMU_LUT498H,GFXMMU LUT entry 498 high" hexmask.long.tbyte 0xF94 4.--21. 1. "LO,Line offset" line.long 0xF98 "GFXMMU_LUT499L,GFXMMU LUT entry 499 low" hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF9C "GFXMMU_LUT499H,GFXMMU LUT entry 499 high" hexmask.long.tbyte 0xF9C 4.--21. 1. "LO,Line offset" line.long 0xFA0 "GFXMMU_LUT500L,GFXMMU LUT entry 500 low" hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFA4 "GFXMMU_LUT500H,GFXMMU LUT entry 500 high" hexmask.long.tbyte 0xFA4 4.--21. 1. "LO,Line offset" line.long 0xFA8 "GFXMMU_LUT501L,GFXMMU LUT entry 501 low" hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFAC "GFXMMU_LUT501H,GFXMMU LUT entry 501 high" hexmask.long.tbyte 0xFAC 4.--21. 1. "LO,Line offset" line.long 0xFB0 "GFXMMU_LUT502L,GFXMMU LUT entry 502 low" hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFB4 "GFXMMU_LUT502H,GFXMMU LUT entry 502 high" hexmask.long.tbyte 0xFB4 4.--21. 1. "LO,Line offset" line.long 0xFB8 "GFXMMU_LUT503L,GFXMMU LUT entry 503 low" hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFBC "GFXMMU_LUT503H,GFXMMU LUT entry 503 high" hexmask.long.tbyte 0xFBC 4.--21. 1. "LO,Line offset" line.long 0xFC0 "GFXMMU_LUT504L,GFXMMU LUT entry 504 low" hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC4 "GFXMMU_LUT504H,GFXMMU LUT entry 504 high" hexmask.long.tbyte 0xFC4 4.--21. 1. "LO,Line offset" line.long 0xFC8 "GFXMMU_LUT505L,GFXMMU LUT entry 505 low" hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFCC "GFXMMU_LUT505H,GFXMMU LUT entry 505 high" hexmask.long.tbyte 0xFCC 4.--21. 1. "LO,Line offset" line.long 0xFD0 "GFXMMU_LUT506L,GFXMMU LUT entry 506 low" hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFD4 "GFXMMU_LUT506H,GFXMMU LUT entry 506 high" hexmask.long.tbyte 0xFD4 4.--21. 1. "LO,Line offset" line.long 0xFD8 "GFXMMU_LUT507L,GFXMMU LUT entry 507 low" hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFDC "GFXMMU_LUT507H,GFXMMU LUT entry 507 high" hexmask.long.tbyte 0xFDC 4.--21. 1. "LO,Line offset" line.long 0xFE0 "GFXMMU_LUT508L,GFXMMU LUT entry 508 low" hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFE4 "GFXMMU_LUT508H,GFXMMU LUT entry 508 high" hexmask.long.tbyte 0xFE4 4.--21. 1. "LO,Line offset" line.long 0xFE8 "GFXMMU_LUT509L,GFXMMU LUT entry 509 low" hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFEC "GFXMMU_LUT509H,GFXMMU LUT entry 509 high" hexmask.long.tbyte 0xFEC 4.--21. 1. "LO,Line offset" line.long 0xFF0 "GFXMMU_LUT510L,GFXMMU LUT entry 510 low" hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFF4 "GFXMMU_LUT510H,GFXMMU LUT entry 510 high" hexmask.long.tbyte 0xFF4 4.--21. 1. "LO,Line offset" line.long 0xFF8 "GFXMMU_LUT511L,GFXMMU LUT entry 511 low" hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFFC "GFXMMU_LUT511H,GFXMMU LUT entry 511 high" hexmask.long.tbyte 0xFFC 4.--21. 1. "LO,Line offset" group.long 0x2000++0xFFF line.long 0x0 "GFXMMU_LUT512L,GFXMMU LUT entry 512 low" hexmask.long.byte 0x0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4 "GFXMMU_LUT512H,GFXMMU LUT entry 512 high" hexmask.long.tbyte 0x4 4.--21. 1. "LO,Line offset" line.long 0x8 "GFXMMU_LUT513L,GFXMMU LUT entry 513 low" hexmask.long.byte 0x8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC "GFXMMU_LUT513H,GFXMMU LUT entry 513 high" hexmask.long.tbyte 0xC 4.--21. 1. "LO,Line offset" line.long 0x10 "GFXMMU_LUT514L,GFXMMU LUT entry 514 low" hexmask.long.byte 0x10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14 "GFXMMU_LUT514H,GFXMMU LUT entry 514 high" hexmask.long.tbyte 0x14 4.--21. 1. "LO,Line offset" line.long 0x18 "GFXMMU_LUT515L,GFXMMU LUT entry 515 low" hexmask.long.byte 0x18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C "GFXMMU_LUT515H,GFXMMU LUT entry 515 high" hexmask.long.tbyte 0x1C 4.--21. 1. "LO,Line offset" line.long 0x20 "GFXMMU_LUT516L,GFXMMU LUT entry 516 low" hexmask.long.byte 0x20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24 "GFXMMU_LUT516H,GFXMMU LUT entry 516 high" hexmask.long.tbyte 0x24 4.--21. 1. "LO,Line offset" line.long 0x28 "GFXMMU_LUT517L,GFXMMU LUT entry 517 low" hexmask.long.byte 0x28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C "GFXMMU_LUT517H,GFXMMU LUT entry 517 high" hexmask.long.tbyte 0x2C 4.--21. 1. "LO,Line offset" line.long 0x30 "GFXMMU_LUT518L,GFXMMU LUT entry 518 low" hexmask.long.byte 0x30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34 "GFXMMU_LUT518H,GFXMMU LUT entry 518 high" hexmask.long.tbyte 0x34 4.--21. 1. "LO,Line offset" line.long 0x38 "GFXMMU_LUT519L,GFXMMU LUT entry 519 low" hexmask.long.byte 0x38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C "GFXMMU_LUT519H,GFXMMU LUT entry 519 high" hexmask.long.tbyte 0x3C 4.--21. 1. "LO,Line offset" line.long 0x40 "GFXMMU_LUT520L,GFXMMU LUT entry 520 low" hexmask.long.byte 0x40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44 "GFXMMU_LUT520H,GFXMMU LUT entry 520 high" hexmask.long.tbyte 0x44 4.--21. 1. "LO,Line offset" line.long 0x48 "GFXMMU_LUT521L,GFXMMU LUT entry 521 low" hexmask.long.byte 0x48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C "GFXMMU_LUT521H,GFXMMU LUT entry 521 high" hexmask.long.tbyte 0x4C 4.--21. 1. "LO,Line offset" line.long 0x50 "GFXMMU_LUT522L,GFXMMU LUT entry 522 low" hexmask.long.byte 0x50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54 "GFXMMU_LUT522H,GFXMMU LUT entry 522 high" hexmask.long.tbyte 0x54 4.--21. 1. "LO,Line offset" line.long 0x58 "GFXMMU_LUT523L,GFXMMU LUT entry 523 low" hexmask.long.byte 0x58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C "GFXMMU_LUT523H,GFXMMU LUT entry 523 high" hexmask.long.tbyte 0x5C 4.--21. 1. "LO,Line offset" line.long 0x60 "GFXMMU_LUT524L,GFXMMU LUT entry 524 low" hexmask.long.byte 0x60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64 "GFXMMU_LUT524H,GFXMMU LUT entry 524 high" hexmask.long.tbyte 0x64 4.--21. 1. "LO,Line offset" line.long 0x68 "GFXMMU_LUT525L,GFXMMU LUT entry 525 low" hexmask.long.byte 0x68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C "GFXMMU_LUT525H,GFXMMU LUT entry 525 high" hexmask.long.tbyte 0x6C 4.--21. 1. "LO,Line offset" line.long 0x70 "GFXMMU_LUT526L,GFXMMU LUT entry 526 low" hexmask.long.byte 0x70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74 "GFXMMU_LUT526H,GFXMMU LUT entry 526 high" hexmask.long.tbyte 0x74 4.--21. 1. "LO,Line offset" line.long 0x78 "GFXMMU_LUT527L,GFXMMU LUT entry 527 low" hexmask.long.byte 0x78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C "GFXMMU_LUT527H,GFXMMU LUT entry 527 high" hexmask.long.tbyte 0x7C 4.--21. 1. "LO,Line offset" line.long 0x80 "GFXMMU_LUT528L,GFXMMU LUT entry 528 low" hexmask.long.byte 0x80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84 "GFXMMU_LUT528H,GFXMMU LUT entry 528 high" hexmask.long.tbyte 0x84 4.--21. 1. "LO,Line offset" line.long 0x88 "GFXMMU_LUT529L,GFXMMU LUT entry 529 low" hexmask.long.byte 0x88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C "GFXMMU_LUT529H,GFXMMU LUT entry 529 high" hexmask.long.tbyte 0x8C 4.--21. 1. "LO,Line offset" line.long 0x90 "GFXMMU_LUT530L,GFXMMU LUT entry 530 low" hexmask.long.byte 0x90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94 "GFXMMU_LUT530H,GFXMMU LUT entry 530 high" hexmask.long.tbyte 0x94 4.--21. 1. "LO,Line offset" line.long 0x98 "GFXMMU_LUT531L,GFXMMU LUT entry 531 low" hexmask.long.byte 0x98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C "GFXMMU_LUT531H,GFXMMU LUT entry 531 high" hexmask.long.tbyte 0x9C 4.--21. 1. "LO,Line offset" line.long 0xA0 "GFXMMU_LUT532L,GFXMMU LUT entry 532 low" hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4 "GFXMMU_LUT532H,GFXMMU LUT entry 532 high" hexmask.long.tbyte 0xA4 4.--21. 1. "LO,Line offset" line.long 0xA8 "GFXMMU_LUT533L,GFXMMU LUT entry 533 low" hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC "GFXMMU_LUT533H,GFXMMU LUT entry 533 high" hexmask.long.tbyte 0xAC 4.--21. 1. "LO,Line offset" line.long 0xB0 "GFXMMU_LUT534L,GFXMMU LUT entry 534 low" hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4 "GFXMMU_LUT534H,GFXMMU LUT entry 534 high" hexmask.long.tbyte 0xB4 4.--21. 1. "LO,Line offset" line.long 0xB8 "GFXMMU_LUT535L,GFXMMU LUT entry 535 low" hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC "GFXMMU_LUT535H,GFXMMU LUT entry 535 high" hexmask.long.tbyte 0xBC 4.--21. 1. "LO,Line offset" line.long 0xC0 "GFXMMU_LUT536L,GFXMMU LUT entry 536 low" hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4 "GFXMMU_LUT536H,GFXMMU LUT entry 536 high" hexmask.long.tbyte 0xC4 4.--21. 1. "LO,Line offset" line.long 0xC8 "GFXMMU_LUT537L,GFXMMU LUT entry 537 low" hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC "GFXMMU_LUT537H,GFXMMU LUT entry 537 high" hexmask.long.tbyte 0xCC 4.--21. 1. "LO,Line offset" line.long 0xD0 "GFXMMU_LUT538L,GFXMMU LUT entry 538 low" hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4 "GFXMMU_LUT538H,GFXMMU LUT entry 538 high" hexmask.long.tbyte 0xD4 4.--21. 1. "LO,Line offset" line.long 0xD8 "GFXMMU_LUT539L,GFXMMU LUT entry 539 low" hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC "GFXMMU_LUT539H,GFXMMU LUT entry 539 high" hexmask.long.tbyte 0xDC 4.--21. 1. "LO,Line offset" line.long 0xE0 "GFXMMU_LUT540L,GFXMMU LUT entry 540 low" hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4 "GFXMMU_LUT540H,GFXMMU LUT entry 540 high" hexmask.long.tbyte 0xE4 4.--21. 1. "LO,Line offset" line.long 0xE8 "GFXMMU_LUT541L,GFXMMU LUT entry 541 low" hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC "GFXMMU_LUT541H,GFXMMU LUT entry 541 high" hexmask.long.tbyte 0xEC 4.--21. 1. "LO,Line offset" line.long 0xF0 "GFXMMU_LUT542L,GFXMMU LUT entry 542 low" hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4 "GFXMMU_LUT542H,GFXMMU LUT entry 542 high" hexmask.long.tbyte 0xF4 4.--21. 1. "LO,Line offset" line.long 0xF8 "GFXMMU_LUT543L,GFXMMU LUT entry 543 low" hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC "GFXMMU_LUT543H,GFXMMU LUT entry 543 high" hexmask.long.tbyte 0xFC 4.--21. 1. "LO,Line offset" line.long 0x100 "GFXMMU_LUT544L,GFXMMU LUT entry 544 low" hexmask.long.byte 0x100 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x100 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x104 "GFXMMU_LUT544H,GFXMMU LUT entry 544 high" hexmask.long.tbyte 0x104 4.--21. 1. "LO,Line offset" line.long 0x108 "GFXMMU_LUT545L,GFXMMU LUT entry 545 low" hexmask.long.byte 0x108 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x108 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x10C "GFXMMU_LUT545H,GFXMMU LUT entry 545 high" hexmask.long.tbyte 0x10C 4.--21. 1. "LO,Line offset" line.long 0x110 "GFXMMU_LUT546L,GFXMMU LUT entry 546 low" hexmask.long.byte 0x110 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x110 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x114 "GFXMMU_LUT546H,GFXMMU LUT entry 546 high" hexmask.long.tbyte 0x114 4.--21. 1. "LO,Line offset" line.long 0x118 "GFXMMU_LUT547L,GFXMMU LUT entry 547 low" hexmask.long.byte 0x118 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x118 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x11C "GFXMMU_LUT547H,GFXMMU LUT entry 547 high" hexmask.long.tbyte 0x11C 4.--21. 1. "LO,Line offset" line.long 0x120 "GFXMMU_LUT548L,GFXMMU LUT entry 548 low" hexmask.long.byte 0x120 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x120 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x124 "GFXMMU_LUT548H,GFXMMU LUT entry 548 high" hexmask.long.tbyte 0x124 4.--21. 1. "LO,Line offset" line.long 0x128 "GFXMMU_LUT549L,GFXMMU LUT entry 549 low" hexmask.long.byte 0x128 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x128 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x12C "GFXMMU_LUT549H,GFXMMU LUT entry 549 high" hexmask.long.tbyte 0x12C 4.--21. 1. "LO,Line offset" line.long 0x130 "GFXMMU_LUT550L,GFXMMU LUT entry 550 low" hexmask.long.byte 0x130 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x130 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x134 "GFXMMU_LUT550H,GFXMMU LUT entry 550 high" hexmask.long.tbyte 0x134 4.--21. 1. "LO,Line offset" line.long 0x138 "GFXMMU_LUT551L,GFXMMU LUT entry 551 low" hexmask.long.byte 0x138 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x138 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x13C "GFXMMU_LUT551H,GFXMMU LUT entry 551 high" hexmask.long.tbyte 0x13C 4.--21. 1. "LO,Line offset" line.long 0x140 "GFXMMU_LUT552L,GFXMMU LUT entry 552 low" hexmask.long.byte 0x140 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x140 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x144 "GFXMMU_LUT552H,GFXMMU LUT entry 552 high" hexmask.long.tbyte 0x144 4.--21. 1. "LO,Line offset" line.long 0x148 "GFXMMU_LUT553L,GFXMMU LUT entry 553 low" hexmask.long.byte 0x148 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x148 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14C "GFXMMU_LUT553H,GFXMMU LUT entry 553 high" hexmask.long.tbyte 0x14C 4.--21. 1. "LO,Line offset" line.long 0x150 "GFXMMU_LUT554L,GFXMMU LUT entry 554 low" hexmask.long.byte 0x150 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x150 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x154 "GFXMMU_LUT554H,GFXMMU LUT entry 554 high" hexmask.long.tbyte 0x154 4.--21. 1. "LO,Line offset" line.long 0x158 "GFXMMU_LUT555L,GFXMMU LUT entry 555 low" hexmask.long.byte 0x158 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x158 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x15C "GFXMMU_LUT555H,GFXMMU LUT entry 555 high" hexmask.long.tbyte 0x15C 4.--21. 1. "LO,Line offset" line.long 0x160 "GFXMMU_LUT556L,GFXMMU LUT entry 556 low" hexmask.long.byte 0x160 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x160 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x164 "GFXMMU_LUT556H,GFXMMU LUT entry 556 high" hexmask.long.tbyte 0x164 4.--21. 1. "LO,Line offset" line.long 0x168 "GFXMMU_LUT557L,GFXMMU LUT entry 557 low" hexmask.long.byte 0x168 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x168 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x16C "GFXMMU_LUT557H,GFXMMU LUT entry 557 high" hexmask.long.tbyte 0x16C 4.--21. 1. "LO,Line offset" line.long 0x170 "GFXMMU_LUT558L,GFXMMU LUT entry 558 low" hexmask.long.byte 0x170 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x170 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x174 "GFXMMU_LUT558H,GFXMMU LUT entry 558 high" hexmask.long.tbyte 0x174 4.--21. 1. "LO,Line offset" line.long 0x178 "GFXMMU_LUT559L,GFXMMU LUT entry 559 low" hexmask.long.byte 0x178 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x178 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x17C "GFXMMU_LUT559H,GFXMMU LUT entry 559 high" hexmask.long.tbyte 0x17C 4.--21. 1. "LO,Line offset" line.long 0x180 "GFXMMU_LUT560L,GFXMMU LUT entry 560 low" hexmask.long.byte 0x180 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x180 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x184 "GFXMMU_LUT560H,GFXMMU LUT entry 560 high" hexmask.long.tbyte 0x184 4.--21. 1. "LO,Line offset" line.long 0x188 "GFXMMU_LUT561L,GFXMMU LUT entry 561 low" hexmask.long.byte 0x188 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x188 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x18C "GFXMMU_LUT561H,GFXMMU LUT entry 561 high" hexmask.long.tbyte 0x18C 4.--21. 1. "LO,Line offset" line.long 0x190 "GFXMMU_LUT562L,GFXMMU LUT entry 562 low" hexmask.long.byte 0x190 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x190 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x194 "GFXMMU_LUT562H,GFXMMU LUT entry 562 high" hexmask.long.tbyte 0x194 4.--21. 1. "LO,Line offset" line.long 0x198 "GFXMMU_LUT563L,GFXMMU LUT entry 563 low" hexmask.long.byte 0x198 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x198 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x19C "GFXMMU_LUT563H,GFXMMU LUT entry 563 high" hexmask.long.tbyte 0x19C 4.--21. 1. "LO,Line offset" line.long 0x1A0 "GFXMMU_LUT564L,GFXMMU LUT entry 564 low" hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1A4 "GFXMMU_LUT564H,GFXMMU LUT entry 564 high" hexmask.long.tbyte 0x1A4 4.--21. 1. "LO,Line offset" line.long 0x1A8 "GFXMMU_LUT565L,GFXMMU LUT entry 565 low" hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1AC "GFXMMU_LUT565H,GFXMMU LUT entry 565 high" hexmask.long.tbyte 0x1AC 4.--21. 1. "LO,Line offset" line.long 0x1B0 "GFXMMU_LUT566L,GFXMMU LUT entry 566 low" hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1B4 "GFXMMU_LUT566H,GFXMMU LUT entry 566 high" hexmask.long.tbyte 0x1B4 4.--21. 1. "LO,Line offset" line.long 0x1B8 "GFXMMU_LUT567L,GFXMMU LUT entry 567 low" hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1BC "GFXMMU_LUT567H,GFXMMU LUT entry 567 high" hexmask.long.tbyte 0x1BC 4.--21. 1. "LO,Line offset" line.long 0x1C0 "GFXMMU_LUT568L,GFXMMU LUT entry 568 low" hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C4 "GFXMMU_LUT568H,GFXMMU LUT entry 568 high" hexmask.long.tbyte 0x1C4 4.--21. 1. "LO,Line offset" line.long 0x1C8 "GFXMMU_LUT569L,GFXMMU LUT entry 569 low" hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1CC "GFXMMU_LUT569H,GFXMMU LUT entry 569 high" hexmask.long.tbyte 0x1CC 4.--21. 1. "LO,Line offset" line.long 0x1D0 "GFXMMU_LUT570L,GFXMMU LUT entry 570 low" hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1D4 "GFXMMU_LUT570H,GFXMMU LUT entry 570 high" hexmask.long.tbyte 0x1D4 4.--21. 1. "LO,Line offset" line.long 0x1D8 "GFXMMU_LUT571L,GFXMMU LUT entry 571 low" hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1DC "GFXMMU_LUT571H,GFXMMU LUT entry 571 high" hexmask.long.tbyte 0x1DC 4.--21. 1. "LO,Line offset" line.long 0x1E0 "GFXMMU_LUT572L,GFXMMU LUT entry 572 low" hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1E4 "GFXMMU_LUT572H,GFXMMU LUT entry 572 high" hexmask.long.tbyte 0x1E4 4.--21. 1. "LO,Line offset" line.long 0x1E8 "GFXMMU_LUT573L,GFXMMU LUT entry 573 low" hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1EC "GFXMMU_LUT573H,GFXMMU LUT entry 573 high" hexmask.long.tbyte 0x1EC 4.--21. 1. "LO,Line offset" line.long 0x1F0 "GFXMMU_LUT574L,GFXMMU LUT entry 574 low" hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1F4 "GFXMMU_LUT574H,GFXMMU LUT entry 574 high" hexmask.long.tbyte 0x1F4 4.--21. 1. "LO,Line offset" line.long 0x1F8 "GFXMMU_LUT575L,GFXMMU LUT entry 575 low" hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1FC "GFXMMU_LUT575H,GFXMMU LUT entry 575 high" hexmask.long.tbyte 0x1FC 4.--21. 1. "LO,Line offset" line.long 0x200 "GFXMMU_LUT576L,GFXMMU LUT entry 576 low" hexmask.long.byte 0x200 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x200 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x204 "GFXMMU_LUT576H,GFXMMU LUT entry 576 high" hexmask.long.tbyte 0x204 4.--21. 1. "LO,Line offset" line.long 0x208 "GFXMMU_LUT577L,GFXMMU LUT entry 577 low" hexmask.long.byte 0x208 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x208 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x20C "GFXMMU_LUT577H,GFXMMU LUT entry 577 high" hexmask.long.tbyte 0x20C 4.--21. 1. "LO,Line offset" line.long 0x210 "GFXMMU_LUT578L,GFXMMU LUT entry 578 low" hexmask.long.byte 0x210 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x210 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x214 "GFXMMU_LUT578H,GFXMMU LUT entry 578 high" hexmask.long.tbyte 0x214 4.--21. 1. "LO,Line offset" line.long 0x218 "GFXMMU_LUT579L,GFXMMU LUT entry 579 low" hexmask.long.byte 0x218 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x218 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x21C "GFXMMU_LUT579H,GFXMMU LUT entry 579 high" hexmask.long.tbyte 0x21C 4.--21. 1. "LO,Line offset" line.long 0x220 "GFXMMU_LUT580L,GFXMMU LUT entry 580 low" hexmask.long.byte 0x220 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x220 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x224 "GFXMMU_LUT580H,GFXMMU LUT entry 580 high" hexmask.long.tbyte 0x224 4.--21. 1. "LO,Line offset" line.long 0x228 "GFXMMU_LUT581L,GFXMMU LUT entry 581 low" hexmask.long.byte 0x228 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x228 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x22C "GFXMMU_LUT581H,GFXMMU LUT entry 581 high" hexmask.long.tbyte 0x22C 4.--21. 1. "LO,Line offset" line.long 0x230 "GFXMMU_LUT582L,GFXMMU LUT entry 582 low" hexmask.long.byte 0x230 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x230 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x234 "GFXMMU_LUT582H,GFXMMU LUT entry 582 high" hexmask.long.tbyte 0x234 4.--21. 1. "LO,Line offset" line.long 0x238 "GFXMMU_LUT583L,GFXMMU LUT entry 583 low" hexmask.long.byte 0x238 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x238 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x23C "GFXMMU_LUT583H,GFXMMU LUT entry 583 high" hexmask.long.tbyte 0x23C 4.--21. 1. "LO,Line offset" line.long 0x240 "GFXMMU_LUT584L,GFXMMU LUT entry 584 low" hexmask.long.byte 0x240 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x240 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x244 "GFXMMU_LUT584H,GFXMMU LUT entry 584 high" hexmask.long.tbyte 0x244 4.--21. 1. "LO,Line offset" line.long 0x248 "GFXMMU_LUT585L,GFXMMU LUT entry 585 low" hexmask.long.byte 0x248 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x248 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24C "GFXMMU_LUT585H,GFXMMU LUT entry 585 high" hexmask.long.tbyte 0x24C 4.--21. 1. "LO,Line offset" line.long 0x250 "GFXMMU_LUT586L,GFXMMU LUT entry 586 low" hexmask.long.byte 0x250 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x250 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x254 "GFXMMU_LUT586H,GFXMMU LUT entry 586 high" hexmask.long.tbyte 0x254 4.--21. 1. "LO,Line offset" line.long 0x258 "GFXMMU_LUT587L,GFXMMU LUT entry 587 low" hexmask.long.byte 0x258 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x258 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x25C "GFXMMU_LUT587H,GFXMMU LUT entry 587 high" hexmask.long.tbyte 0x25C 4.--21. 1. "LO,Line offset" line.long 0x260 "GFXMMU_LUT588L,GFXMMU LUT entry 588 low" hexmask.long.byte 0x260 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x260 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x264 "GFXMMU_LUT588H,GFXMMU LUT entry 588 high" hexmask.long.tbyte 0x264 4.--21. 1. "LO,Line offset" line.long 0x268 "GFXMMU_LUT589L,GFXMMU LUT entry 589 low" hexmask.long.byte 0x268 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x268 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x26C "GFXMMU_LUT589H,GFXMMU LUT entry 589 high" hexmask.long.tbyte 0x26C 4.--21. 1. "LO,Line offset" line.long 0x270 "GFXMMU_LUT590L,GFXMMU LUT entry 590 low" hexmask.long.byte 0x270 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x270 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x274 "GFXMMU_LUT590H,GFXMMU LUT entry 590 high" hexmask.long.tbyte 0x274 4.--21. 1. "LO,Line offset" line.long 0x278 "GFXMMU_LUT591L,GFXMMU LUT entry 591 low" hexmask.long.byte 0x278 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x278 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x27C "GFXMMU_LUT591H,GFXMMU LUT entry 591 high" hexmask.long.tbyte 0x27C 4.--21. 1. "LO,Line offset" line.long 0x280 "GFXMMU_LUT592L,GFXMMU LUT entry 592 low" hexmask.long.byte 0x280 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x280 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x284 "GFXMMU_LUT592H,GFXMMU LUT entry 592 high" hexmask.long.tbyte 0x284 4.--21. 1. "LO,Line offset" line.long 0x288 "GFXMMU_LUT593L,GFXMMU LUT entry 593 low" hexmask.long.byte 0x288 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x288 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x28C "GFXMMU_LUT593H,GFXMMU LUT entry 593 high" hexmask.long.tbyte 0x28C 4.--21. 1. "LO,Line offset" line.long 0x290 "GFXMMU_LUT594L,GFXMMU LUT entry 594 low" hexmask.long.byte 0x290 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x290 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x294 "GFXMMU_LUT594H,GFXMMU LUT entry 594 high" hexmask.long.tbyte 0x294 4.--21. 1. "LO,Line offset" line.long 0x298 "GFXMMU_LUT595L,GFXMMU LUT entry 595 low" hexmask.long.byte 0x298 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x298 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x29C "GFXMMU_LUT595H,GFXMMU LUT entry 595 high" hexmask.long.tbyte 0x29C 4.--21. 1. "LO,Line offset" line.long 0x2A0 "GFXMMU_LUT596L,GFXMMU LUT entry 596 low" hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2A4 "GFXMMU_LUT596H,GFXMMU LUT entry 596 high" hexmask.long.tbyte 0x2A4 4.--21. 1. "LO,Line offset" line.long 0x2A8 "GFXMMU_LUT597L,GFXMMU LUT entry 597 low" hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2AC "GFXMMU_LUT597H,GFXMMU LUT entry 597 high" hexmask.long.tbyte 0x2AC 4.--21. 1. "LO,Line offset" line.long 0x2B0 "GFXMMU_LUT598L,GFXMMU LUT entry 598 low" hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2B4 "GFXMMU_LUT598H,GFXMMU LUT entry 598 high" hexmask.long.tbyte 0x2B4 4.--21. 1. "LO,Line offset" line.long 0x2B8 "GFXMMU_LUT599L,GFXMMU LUT entry 599 low" hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2BC "GFXMMU_LUT599H,GFXMMU LUT entry 599 high" hexmask.long.tbyte 0x2BC 4.--21. 1. "LO,Line offset" line.long 0x2C0 "GFXMMU_LUT600L,GFXMMU LUT entry 600 low" hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C4 "GFXMMU_LUT600H,GFXMMU LUT entry 600 high" hexmask.long.tbyte 0x2C4 4.--21. 1. "LO,Line offset" line.long 0x2C8 "GFXMMU_LUT601L,GFXMMU LUT entry 601 low" hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2CC "GFXMMU_LUT601H,GFXMMU LUT entry 601 high" hexmask.long.tbyte 0x2CC 4.--21. 1. "LO,Line offset" line.long 0x2D0 "GFXMMU_LUT602L,GFXMMU LUT entry 602 low" hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2D4 "GFXMMU_LUT602H,GFXMMU LUT entry 602 high" hexmask.long.tbyte 0x2D4 4.--21. 1. "LO,Line offset" line.long 0x2D8 "GFXMMU_LUT603L,GFXMMU LUT entry 603 low" hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2DC "GFXMMU_LUT603H,GFXMMU LUT entry 603 high" hexmask.long.tbyte 0x2DC 4.--21. 1. "LO,Line offset" line.long 0x2E0 "GFXMMU_LUT604L,GFXMMU LUT entry 604 low" hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2E4 "GFXMMU_LUT604H,GFXMMU LUT entry 604 high" hexmask.long.tbyte 0x2E4 4.--21. 1. "LO,Line offset" line.long 0x2E8 "GFXMMU_LUT605L,GFXMMU LUT entry 605 low" hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2EC "GFXMMU_LUT605H,GFXMMU LUT entry 605 high" hexmask.long.tbyte 0x2EC 4.--21. 1. "LO,Line offset" line.long 0x2F0 "GFXMMU_LUT606L,GFXMMU LUT entry 606 low" hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2F4 "GFXMMU_LUT606H,GFXMMU LUT entry 606 high" hexmask.long.tbyte 0x2F4 4.--21. 1. "LO,Line offset" line.long 0x2F8 "GFXMMU_LUT607L,GFXMMU LUT entry 607 low" hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2FC "GFXMMU_LUT607H,GFXMMU LUT entry 607 high" hexmask.long.tbyte 0x2FC 4.--21. 1. "LO,Line offset" line.long 0x300 "GFXMMU_LUT608L,GFXMMU LUT entry 608 low" hexmask.long.byte 0x300 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x300 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x304 "GFXMMU_LUT608H,GFXMMU LUT entry 608 high" hexmask.long.tbyte 0x304 4.--21. 1. "LO,Line offset" line.long 0x308 "GFXMMU_LUT609L,GFXMMU LUT entry 609 low" hexmask.long.byte 0x308 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x308 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x30C "GFXMMU_LUT609H,GFXMMU LUT entry 609 high" hexmask.long.tbyte 0x30C 4.--21. 1. "LO,Line offset" line.long 0x310 "GFXMMU_LUT610L,GFXMMU LUT entry 610 low" hexmask.long.byte 0x310 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x310 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x314 "GFXMMU_LUT610H,GFXMMU LUT entry 610 high" hexmask.long.tbyte 0x314 4.--21. 1. "LO,Line offset" line.long 0x318 "GFXMMU_LUT611L,GFXMMU LUT entry 611 low" hexmask.long.byte 0x318 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x318 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x31C "GFXMMU_LUT611H,GFXMMU LUT entry 611 high" hexmask.long.tbyte 0x31C 4.--21. 1. "LO,Line offset" line.long 0x320 "GFXMMU_LUT612L,GFXMMU LUT entry 612 low" hexmask.long.byte 0x320 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x320 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x324 "GFXMMU_LUT612H,GFXMMU LUT entry 612 high" hexmask.long.tbyte 0x324 4.--21. 1. "LO,Line offset" line.long 0x328 "GFXMMU_LUT613L,GFXMMU LUT entry 613 low" hexmask.long.byte 0x328 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x328 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x32C "GFXMMU_LUT613H,GFXMMU LUT entry 613 high" hexmask.long.tbyte 0x32C 4.--21. 1. "LO,Line offset" line.long 0x330 "GFXMMU_LUT614L,GFXMMU LUT entry 614 low" hexmask.long.byte 0x330 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x330 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x334 "GFXMMU_LUT614H,GFXMMU LUT entry 614 high" hexmask.long.tbyte 0x334 4.--21. 1. "LO,Line offset" line.long 0x338 "GFXMMU_LUT615L,GFXMMU LUT entry 615 low" hexmask.long.byte 0x338 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x338 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x33C "GFXMMU_LUT615H,GFXMMU LUT entry 615 high" hexmask.long.tbyte 0x33C 4.--21. 1. "LO,Line offset" line.long 0x340 "GFXMMU_LUT616L,GFXMMU LUT entry 616 low" hexmask.long.byte 0x340 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x340 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x344 "GFXMMU_LUT616H,GFXMMU LUT entry 616 high" hexmask.long.tbyte 0x344 4.--21. 1. "LO,Line offset" line.long 0x348 "GFXMMU_LUT617L,GFXMMU LUT entry 617 low" hexmask.long.byte 0x348 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x348 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34C "GFXMMU_LUT617H,GFXMMU LUT entry 617 high" hexmask.long.tbyte 0x34C 4.--21. 1. "LO,Line offset" line.long 0x350 "GFXMMU_LUT618L,GFXMMU LUT entry 618 low" hexmask.long.byte 0x350 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x350 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x354 "GFXMMU_LUT618H,GFXMMU LUT entry 618 high" hexmask.long.tbyte 0x354 4.--21. 1. "LO,Line offset" line.long 0x358 "GFXMMU_LUT619L,GFXMMU LUT entry 619 low" hexmask.long.byte 0x358 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x358 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x35C "GFXMMU_LUT619H,GFXMMU LUT entry 619 high" hexmask.long.tbyte 0x35C 4.--21. 1. "LO,Line offset" line.long 0x360 "GFXMMU_LUT620L,GFXMMU LUT entry 620 low" hexmask.long.byte 0x360 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x360 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x364 "GFXMMU_LUT620H,GFXMMU LUT entry 620 high" hexmask.long.tbyte 0x364 4.--21. 1. "LO,Line offset" line.long 0x368 "GFXMMU_LUT621L,GFXMMU LUT entry 621 low" hexmask.long.byte 0x368 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x368 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x36C "GFXMMU_LUT621H,GFXMMU LUT entry 621 high" hexmask.long.tbyte 0x36C 4.--21. 1. "LO,Line offset" line.long 0x370 "GFXMMU_LUT622L,GFXMMU LUT entry 622 low" hexmask.long.byte 0x370 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x370 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x374 "GFXMMU_LUT622H,GFXMMU LUT entry 622 high" hexmask.long.tbyte 0x374 4.--21. 1. "LO,Line offset" line.long 0x378 "GFXMMU_LUT623L,GFXMMU LUT entry 623 low" hexmask.long.byte 0x378 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x378 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x37C "GFXMMU_LUT623H,GFXMMU LUT entry 623 high" hexmask.long.tbyte 0x37C 4.--21. 1. "LO,Line offset" line.long 0x380 "GFXMMU_LUT624L,GFXMMU LUT entry 624 low" hexmask.long.byte 0x380 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x380 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x384 "GFXMMU_LUT624H,GFXMMU LUT entry 624 high" hexmask.long.tbyte 0x384 4.--21. 1. "LO,Line offset" line.long 0x388 "GFXMMU_LUT625L,GFXMMU LUT entry 625 low" hexmask.long.byte 0x388 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x388 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x38C "GFXMMU_LUT625H,GFXMMU LUT entry 625 high" hexmask.long.tbyte 0x38C 4.--21. 1. "LO,Line offset" line.long 0x390 "GFXMMU_LUT626L,GFXMMU LUT entry 626 low" hexmask.long.byte 0x390 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x390 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x394 "GFXMMU_LUT626H,GFXMMU LUT entry 626 high" hexmask.long.tbyte 0x394 4.--21. 1. "LO,Line offset" line.long 0x398 "GFXMMU_LUT627L,GFXMMU LUT entry 627 low" hexmask.long.byte 0x398 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x398 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x39C "GFXMMU_LUT627H,GFXMMU LUT entry 627 high" hexmask.long.tbyte 0x39C 4.--21. 1. "LO,Line offset" line.long 0x3A0 "GFXMMU_LUT628L,GFXMMU LUT entry 628 low" hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3A4 "GFXMMU_LUT628H,GFXMMU LUT entry 628 high" hexmask.long.tbyte 0x3A4 4.--21. 1. "LO,Line offset" line.long 0x3A8 "GFXMMU_LUT629L,GFXMMU LUT entry 629 low" hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3AC "GFXMMU_LUT629H,GFXMMU LUT entry 629 high" hexmask.long.tbyte 0x3AC 4.--21. 1. "LO,Line offset" line.long 0x3B0 "GFXMMU_LUT630L,GFXMMU LUT entry 630 low" hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3B4 "GFXMMU_LUT630H,GFXMMU LUT entry 630 high" hexmask.long.tbyte 0x3B4 4.--21. 1. "LO,Line offset" line.long 0x3B8 "GFXMMU_LUT631L,GFXMMU LUT entry 631 low" hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3BC "GFXMMU_LUT631H,GFXMMU LUT entry 631 high" hexmask.long.tbyte 0x3BC 4.--21. 1. "LO,Line offset" line.long 0x3C0 "GFXMMU_LUT632L,GFXMMU LUT entry 632 low" hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C4 "GFXMMU_LUT632H,GFXMMU LUT entry 632 high" hexmask.long.tbyte 0x3C4 4.--21. 1. "LO,Line offset" line.long 0x3C8 "GFXMMU_LUT633L,GFXMMU LUT entry 633 low" hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3CC "GFXMMU_LUT633H,GFXMMU LUT entry 633 high" hexmask.long.tbyte 0x3CC 4.--21. 1. "LO,Line offset" line.long 0x3D0 "GFXMMU_LUT634L,GFXMMU LUT entry 634 low" hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3D4 "GFXMMU_LUT634H,GFXMMU LUT entry 634 high" hexmask.long.tbyte 0x3D4 4.--21. 1. "LO,Line offset" line.long 0x3D8 "GFXMMU_LUT635L,GFXMMU LUT entry 635 low" hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3DC "GFXMMU_LUT635H,GFXMMU LUT entry 635 high" hexmask.long.tbyte 0x3DC 4.--21. 1. "LO,Line offset" line.long 0x3E0 "GFXMMU_LUT636L,GFXMMU LUT entry 636 low" hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3E4 "GFXMMU_LUT636H,GFXMMU LUT entry 636 high" hexmask.long.tbyte 0x3E4 4.--21. 1. "LO,Line offset" line.long 0x3E8 "GFXMMU_LUT637L,GFXMMU LUT entry 637 low" hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3EC "GFXMMU_LUT637H,GFXMMU LUT entry 637 high" hexmask.long.tbyte 0x3EC 4.--21. 1. "LO,Line offset" line.long 0x3F0 "GFXMMU_LUT638L,GFXMMU LUT entry 638 low" hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3F4 "GFXMMU_LUT638H,GFXMMU LUT entry 638 high" hexmask.long.tbyte 0x3F4 4.--21. 1. "LO,Line offset" line.long 0x3F8 "GFXMMU_LUT639L,GFXMMU LUT entry 639 low" hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3FC "GFXMMU_LUT639H,GFXMMU LUT entry 639 high" hexmask.long.tbyte 0x3FC 4.--21. 1. "LO,Line offset" line.long 0x400 "GFXMMU_LUT640L,GFXMMU LUT entry 640 low" hexmask.long.byte 0x400 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x400 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x404 "GFXMMU_LUT640H,GFXMMU LUT entry 640 high" hexmask.long.tbyte 0x404 4.--21. 1. "LO,Line offset" line.long 0x408 "GFXMMU_LUT641L,GFXMMU LUT entry 641 low" hexmask.long.byte 0x408 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x408 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x40C "GFXMMU_LUT641H,GFXMMU LUT entry 641 high" hexmask.long.tbyte 0x40C 4.--21. 1. "LO,Line offset" line.long 0x410 "GFXMMU_LUT642L,GFXMMU LUT entry 642 low" hexmask.long.byte 0x410 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x410 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x414 "GFXMMU_LUT642H,GFXMMU LUT entry 642 high" hexmask.long.tbyte 0x414 4.--21. 1. "LO,Line offset" line.long 0x418 "GFXMMU_LUT643L,GFXMMU LUT entry 643 low" hexmask.long.byte 0x418 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x418 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x41C "GFXMMU_LUT643H,GFXMMU LUT entry 643 high" hexmask.long.tbyte 0x41C 4.--21. 1. "LO,Line offset" line.long 0x420 "GFXMMU_LUT644L,GFXMMU LUT entry 644 low" hexmask.long.byte 0x420 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x420 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x424 "GFXMMU_LUT644H,GFXMMU LUT entry 644 high" hexmask.long.tbyte 0x424 4.--21. 1. "LO,Line offset" line.long 0x428 "GFXMMU_LUT645L,GFXMMU LUT entry 645 low" hexmask.long.byte 0x428 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x428 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x42C "GFXMMU_LUT645H,GFXMMU LUT entry 645 high" hexmask.long.tbyte 0x42C 4.--21. 1. "LO,Line offset" line.long 0x430 "GFXMMU_LUT646L,GFXMMU LUT entry 646 low" hexmask.long.byte 0x430 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x430 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x434 "GFXMMU_LUT646H,GFXMMU LUT entry 646 high" hexmask.long.tbyte 0x434 4.--21. 1. "LO,Line offset" line.long 0x438 "GFXMMU_LUT647L,GFXMMU LUT entry 647 low" hexmask.long.byte 0x438 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x438 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x43C "GFXMMU_LUT647H,GFXMMU LUT entry 647 high" hexmask.long.tbyte 0x43C 4.--21. 1. "LO,Line offset" line.long 0x440 "GFXMMU_LUT648L,GFXMMU LUT entry 648 low" hexmask.long.byte 0x440 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x440 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x444 "GFXMMU_LUT648H,GFXMMU LUT entry 648 high" hexmask.long.tbyte 0x444 4.--21. 1. "LO,Line offset" line.long 0x448 "GFXMMU_LUT649L,GFXMMU LUT entry 649 low" hexmask.long.byte 0x448 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x448 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44C "GFXMMU_LUT649H,GFXMMU LUT entry 649 high" hexmask.long.tbyte 0x44C 4.--21. 1. "LO,Line offset" line.long 0x450 "GFXMMU_LUT650L,GFXMMU LUT entry 650 low" hexmask.long.byte 0x450 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x450 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x454 "GFXMMU_LUT650H,GFXMMU LUT entry 650 high" hexmask.long.tbyte 0x454 4.--21. 1. "LO,Line offset" line.long 0x458 "GFXMMU_LUT651L,GFXMMU LUT entry 651 low" hexmask.long.byte 0x458 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x458 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x45C "GFXMMU_LUT651H,GFXMMU LUT entry 651 high" hexmask.long.tbyte 0x45C 4.--21. 1. "LO,Line offset" line.long 0x460 "GFXMMU_LUT652L,GFXMMU LUT entry 652 low" hexmask.long.byte 0x460 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x460 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x464 "GFXMMU_LUT652H,GFXMMU LUT entry 652 high" hexmask.long.tbyte 0x464 4.--21. 1. "LO,Line offset" line.long 0x468 "GFXMMU_LUT653L,GFXMMU LUT entry 653 low" hexmask.long.byte 0x468 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x468 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x46C "GFXMMU_LUT653H,GFXMMU LUT entry 653 high" hexmask.long.tbyte 0x46C 4.--21. 1. "LO,Line offset" line.long 0x470 "GFXMMU_LUT654L,GFXMMU LUT entry 654 low" hexmask.long.byte 0x470 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x470 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x474 "GFXMMU_LUT654H,GFXMMU LUT entry 654 high" hexmask.long.tbyte 0x474 4.--21. 1. "LO,Line offset" line.long 0x478 "GFXMMU_LUT655L,GFXMMU LUT entry 655 low" hexmask.long.byte 0x478 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x478 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x47C "GFXMMU_LUT655H,GFXMMU LUT entry 655 high" hexmask.long.tbyte 0x47C 4.--21. 1. "LO,Line offset" line.long 0x480 "GFXMMU_LUT656L,GFXMMU LUT entry 656 low" hexmask.long.byte 0x480 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x480 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x484 "GFXMMU_LUT656H,GFXMMU LUT entry 656 high" hexmask.long.tbyte 0x484 4.--21. 1. "LO,Line offset" line.long 0x488 "GFXMMU_LUT657L,GFXMMU LUT entry 657 low" hexmask.long.byte 0x488 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x488 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x48C "GFXMMU_LUT657H,GFXMMU LUT entry 657 high" hexmask.long.tbyte 0x48C 4.--21. 1. "LO,Line offset" line.long 0x490 "GFXMMU_LUT658L,GFXMMU LUT entry 658 low" hexmask.long.byte 0x490 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x490 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x494 "GFXMMU_LUT658H,GFXMMU LUT entry 658 high" hexmask.long.tbyte 0x494 4.--21. 1. "LO,Line offset" line.long 0x498 "GFXMMU_LUT659L,GFXMMU LUT entry 659 low" hexmask.long.byte 0x498 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x498 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x49C "GFXMMU_LUT659H,GFXMMU LUT entry 659 high" hexmask.long.tbyte 0x49C 4.--21. 1. "LO,Line offset" line.long 0x4A0 "GFXMMU_LUT660L,GFXMMU LUT entry 660 low" hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4A4 "GFXMMU_LUT660H,GFXMMU LUT entry 660 high" hexmask.long.tbyte 0x4A4 4.--21. 1. "LO,Line offset" line.long 0x4A8 "GFXMMU_LUT661L,GFXMMU LUT entry 661 low" hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4AC "GFXMMU_LUT661H,GFXMMU LUT entry 661 high" hexmask.long.tbyte 0x4AC 4.--21. 1. "LO,Line offset" line.long 0x4B0 "GFXMMU_LUT662L,GFXMMU LUT entry 662 low" hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4B4 "GFXMMU_LUT662H,GFXMMU LUT entry 662 high" hexmask.long.tbyte 0x4B4 4.--21. 1. "LO,Line offset" line.long 0x4B8 "GFXMMU_LUT663L,GFXMMU LUT entry 663 low" hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4BC "GFXMMU_LUT663H,GFXMMU LUT entry 663 high" hexmask.long.tbyte 0x4BC 4.--21. 1. "LO,Line offset" line.long 0x4C0 "GFXMMU_LUT664L,GFXMMU LUT entry 664 low" hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C4 "GFXMMU_LUT664H,GFXMMU LUT entry 664 high" hexmask.long.tbyte 0x4C4 4.--21. 1. "LO,Line offset" line.long 0x4C8 "GFXMMU_LUT665L,GFXMMU LUT entry 665 low" hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4CC "GFXMMU_LUT665H,GFXMMU LUT entry 665 high" hexmask.long.tbyte 0x4CC 4.--21. 1. "LO,Line offset" line.long 0x4D0 "GFXMMU_LUT666L,GFXMMU LUT entry 666 low" hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4D4 "GFXMMU_LUT666H,GFXMMU LUT entry 666 high" hexmask.long.tbyte 0x4D4 4.--21. 1. "LO,Line offset" line.long 0x4D8 "GFXMMU_LUT667L,GFXMMU LUT entry 667 low" hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4DC "GFXMMU_LUT667H,GFXMMU LUT entry 667 high" hexmask.long.tbyte 0x4DC 4.--21. 1. "LO,Line offset" line.long 0x4E0 "GFXMMU_LUT668L,GFXMMU LUT entry 668 low" hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4E4 "GFXMMU_LUT668H,GFXMMU LUT entry 668 high" hexmask.long.tbyte 0x4E4 4.--21. 1. "LO,Line offset" line.long 0x4E8 "GFXMMU_LUT669L,GFXMMU LUT entry 669 low" hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4EC "GFXMMU_LUT669H,GFXMMU LUT entry 669 high" hexmask.long.tbyte 0x4EC 4.--21. 1. "LO,Line offset" line.long 0x4F0 "GFXMMU_LUT670L,GFXMMU LUT entry 670 low" hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4F4 "GFXMMU_LUT670H,GFXMMU LUT entry 670 high" hexmask.long.tbyte 0x4F4 4.--21. 1. "LO,Line offset" line.long 0x4F8 "GFXMMU_LUT671L,GFXMMU LUT entry 671 low" hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4FC "GFXMMU_LUT671H,GFXMMU LUT entry 671 high" hexmask.long.tbyte 0x4FC 4.--21. 1. "LO,Line offset" line.long 0x500 "GFXMMU_LUT672L,GFXMMU LUT entry 672 low" hexmask.long.byte 0x500 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x500 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x504 "GFXMMU_LUT672H,GFXMMU LUT entry 672 high" hexmask.long.tbyte 0x504 4.--21. 1. "LO,Line offset" line.long 0x508 "GFXMMU_LUT673L,GFXMMU LUT entry 673 low" hexmask.long.byte 0x508 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x508 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x50C "GFXMMU_LUT673H,GFXMMU LUT entry 673 high" hexmask.long.tbyte 0x50C 4.--21. 1. "LO,Line offset" line.long 0x510 "GFXMMU_LUT674L,GFXMMU LUT entry 674 low" hexmask.long.byte 0x510 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x510 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x514 "GFXMMU_LUT674H,GFXMMU LUT entry 674 high" hexmask.long.tbyte 0x514 4.--21. 1. "LO,Line offset" line.long 0x518 "GFXMMU_LUT675L,GFXMMU LUT entry 675 low" hexmask.long.byte 0x518 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x518 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x51C "GFXMMU_LUT675H,GFXMMU LUT entry 675 high" hexmask.long.tbyte 0x51C 4.--21. 1. "LO,Line offset" line.long 0x520 "GFXMMU_LUT676L,GFXMMU LUT entry 676 low" hexmask.long.byte 0x520 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x520 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x524 "GFXMMU_LUT676H,GFXMMU LUT entry 676 high" hexmask.long.tbyte 0x524 4.--21. 1. "LO,Line offset" line.long 0x528 "GFXMMU_LUT677L,GFXMMU LUT entry 677 low" hexmask.long.byte 0x528 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x528 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x52C "GFXMMU_LUT677H,GFXMMU LUT entry 677 high" hexmask.long.tbyte 0x52C 4.--21. 1. "LO,Line offset" line.long 0x530 "GFXMMU_LUT678L,GFXMMU LUT entry 678 low" hexmask.long.byte 0x530 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x530 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x534 "GFXMMU_LUT678H,GFXMMU LUT entry 678 high" hexmask.long.tbyte 0x534 4.--21. 1. "LO,Line offset" line.long 0x538 "GFXMMU_LUT679L,GFXMMU LUT entry 679 low" hexmask.long.byte 0x538 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x538 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x53C "GFXMMU_LUT679H,GFXMMU LUT entry 679 high" hexmask.long.tbyte 0x53C 4.--21. 1. "LO,Line offset" line.long 0x540 "GFXMMU_LUT680L,GFXMMU LUT entry 680 low" hexmask.long.byte 0x540 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x540 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x544 "GFXMMU_LUT680H,GFXMMU LUT entry 680 high" hexmask.long.tbyte 0x544 4.--21. 1. "LO,Line offset" line.long 0x548 "GFXMMU_LUT681L,GFXMMU LUT entry 681 low" hexmask.long.byte 0x548 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x548 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54C "GFXMMU_LUT681H,GFXMMU LUT entry 681 high" hexmask.long.tbyte 0x54C 4.--21. 1. "LO,Line offset" line.long 0x550 "GFXMMU_LUT682L,GFXMMU LUT entry 682 low" hexmask.long.byte 0x550 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x550 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x554 "GFXMMU_LUT682H,GFXMMU LUT entry 682 high" hexmask.long.tbyte 0x554 4.--21. 1. "LO,Line offset" line.long 0x558 "GFXMMU_LUT683L,GFXMMU LUT entry 683 low" hexmask.long.byte 0x558 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x558 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x55C "GFXMMU_LUT683H,GFXMMU LUT entry 683 high" hexmask.long.tbyte 0x55C 4.--21. 1. "LO,Line offset" line.long 0x560 "GFXMMU_LUT684L,GFXMMU LUT entry 684 low" hexmask.long.byte 0x560 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x560 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x564 "GFXMMU_LUT684H,GFXMMU LUT entry 684 high" hexmask.long.tbyte 0x564 4.--21. 1. "LO,Line offset" line.long 0x568 "GFXMMU_LUT685L,GFXMMU LUT entry 685 low" hexmask.long.byte 0x568 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x568 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x56C "GFXMMU_LUT685H,GFXMMU LUT entry 685 high" hexmask.long.tbyte 0x56C 4.--21. 1. "LO,Line offset" line.long 0x570 "GFXMMU_LUT686L,GFXMMU LUT entry 686 low" hexmask.long.byte 0x570 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x570 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x574 "GFXMMU_LUT686H,GFXMMU LUT entry 686 high" hexmask.long.tbyte 0x574 4.--21. 1. "LO,Line offset" line.long 0x578 "GFXMMU_LUT687L,GFXMMU LUT entry 687 low" hexmask.long.byte 0x578 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x578 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x57C "GFXMMU_LUT687H,GFXMMU LUT entry 687 high" hexmask.long.tbyte 0x57C 4.--21. 1. "LO,Line offset" line.long 0x580 "GFXMMU_LUT688L,GFXMMU LUT entry 688 low" hexmask.long.byte 0x580 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x580 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x584 "GFXMMU_LUT688H,GFXMMU LUT entry 688 high" hexmask.long.tbyte 0x584 4.--21. 1. "LO,Line offset" line.long 0x588 "GFXMMU_LUT689L,GFXMMU LUT entry 689 low" hexmask.long.byte 0x588 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x588 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x58C "GFXMMU_LUT689H,GFXMMU LUT entry 689 high" hexmask.long.tbyte 0x58C 4.--21. 1. "LO,Line offset" line.long 0x590 "GFXMMU_LUT690L,GFXMMU LUT entry 690 low" hexmask.long.byte 0x590 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x590 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x594 "GFXMMU_LUT690H,GFXMMU LUT entry 690 high" hexmask.long.tbyte 0x594 4.--21. 1. "LO,Line offset" line.long 0x598 "GFXMMU_LUT691L,GFXMMU LUT entry 691 low" hexmask.long.byte 0x598 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x598 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x59C "GFXMMU_LUT691H,GFXMMU LUT entry 691 high" hexmask.long.tbyte 0x59C 4.--21. 1. "LO,Line offset" line.long 0x5A0 "GFXMMU_LUT692L,GFXMMU LUT entry 692 low" hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5A4 "GFXMMU_LUT692H,GFXMMU LUT entry 692 high" hexmask.long.tbyte 0x5A4 4.--21. 1. "LO,Line offset" line.long 0x5A8 "GFXMMU_LUT693L,GFXMMU LUT entry 693 low" hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5AC "GFXMMU_LUT693H,GFXMMU LUT entry 693 high" hexmask.long.tbyte 0x5AC 4.--21. 1. "LO,Line offset" line.long 0x5B0 "GFXMMU_LUT694L,GFXMMU LUT entry 694 low" hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5B4 "GFXMMU_LUT694H,GFXMMU LUT entry 694 high" hexmask.long.tbyte 0x5B4 4.--21. 1. "LO,Line offset" line.long 0x5B8 "GFXMMU_LUT695L,GFXMMU LUT entry 695 low" hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5BC "GFXMMU_LUT695H,GFXMMU LUT entry 695 high" hexmask.long.tbyte 0x5BC 4.--21. 1. "LO,Line offset" line.long 0x5C0 "GFXMMU_LUT696L,GFXMMU LUT entry 696 low" hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C4 "GFXMMU_LUT696H,GFXMMU LUT entry 696 high" hexmask.long.tbyte 0x5C4 4.--21. 1. "LO,Line offset" line.long 0x5C8 "GFXMMU_LUT697L,GFXMMU LUT entry 697 low" hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5CC "GFXMMU_LUT697H,GFXMMU LUT entry 697 high" hexmask.long.tbyte 0x5CC 4.--21. 1. "LO,Line offset" line.long 0x5D0 "GFXMMU_LUT698L,GFXMMU LUT entry 698 low" hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5D4 "GFXMMU_LUT698H,GFXMMU LUT entry 698 high" hexmask.long.tbyte 0x5D4 4.--21. 1. "LO,Line offset" line.long 0x5D8 "GFXMMU_LUT699L,GFXMMU LUT entry 699 low" hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5DC "GFXMMU_LUT699H,GFXMMU LUT entry 699 high" hexmask.long.tbyte 0x5DC 4.--21. 1. "LO,Line offset" line.long 0x5E0 "GFXMMU_LUT700L,GFXMMU LUT entry 700 low" hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5E4 "GFXMMU_LUT700H,GFXMMU LUT entry 700 high" hexmask.long.tbyte 0x5E4 4.--21. 1. "LO,Line offset" line.long 0x5E8 "GFXMMU_LUT701L,GFXMMU LUT entry 701 low" hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5EC "GFXMMU_LUT701H,GFXMMU LUT entry 701 high" hexmask.long.tbyte 0x5EC 4.--21. 1. "LO,Line offset" line.long 0x5F0 "GFXMMU_LUT702L,GFXMMU LUT entry 702 low" hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5F4 "GFXMMU_LUT702H,GFXMMU LUT entry 702 high" hexmask.long.tbyte 0x5F4 4.--21. 1. "LO,Line offset" line.long 0x5F8 "GFXMMU_LUT703L,GFXMMU LUT entry 703 low" hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5FC "GFXMMU_LUT703H,GFXMMU LUT entry 703 high" hexmask.long.tbyte 0x5FC 4.--21. 1. "LO,Line offset" line.long 0x600 "GFXMMU_LUT704L,GFXMMU LUT entry 704 low" hexmask.long.byte 0x600 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x600 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x604 "GFXMMU_LUT704H,GFXMMU LUT entry 704 high" hexmask.long.tbyte 0x604 4.--21. 1. "LO,Line offset" line.long 0x608 "GFXMMU_LUT705L,GFXMMU LUT entry 705 low" hexmask.long.byte 0x608 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x608 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x60C "GFXMMU_LUT705H,GFXMMU LUT entry 705 high" hexmask.long.tbyte 0x60C 4.--21. 1. "LO,Line offset" line.long 0x610 "GFXMMU_LUT706L,GFXMMU LUT entry 706 low" hexmask.long.byte 0x610 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x610 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x614 "GFXMMU_LUT706H,GFXMMU LUT entry 706 high" hexmask.long.tbyte 0x614 4.--21. 1. "LO,Line offset" line.long 0x618 "GFXMMU_LUT707L,GFXMMU LUT entry 707 low" hexmask.long.byte 0x618 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x618 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x61C "GFXMMU_LUT707H,GFXMMU LUT entry 707 high" hexmask.long.tbyte 0x61C 4.--21. 1. "LO,Line offset" line.long 0x620 "GFXMMU_LUT708L,GFXMMU LUT entry 708 low" hexmask.long.byte 0x620 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x620 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x624 "GFXMMU_LUT708H,GFXMMU LUT entry 708 high" hexmask.long.tbyte 0x624 4.--21. 1. "LO,Line offset" line.long 0x628 "GFXMMU_LUT709L,GFXMMU LUT entry 709 low" hexmask.long.byte 0x628 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x628 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x62C "GFXMMU_LUT709H,GFXMMU LUT entry 709 high" hexmask.long.tbyte 0x62C 4.--21. 1. "LO,Line offset" line.long 0x630 "GFXMMU_LUT710L,GFXMMU LUT entry 710 low" hexmask.long.byte 0x630 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x630 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x634 "GFXMMU_LUT710H,GFXMMU LUT entry 710 high" hexmask.long.tbyte 0x634 4.--21. 1. "LO,Line offset" line.long 0x638 "GFXMMU_LUT711L,GFXMMU LUT entry 711 low" hexmask.long.byte 0x638 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x638 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x63C "GFXMMU_LUT711H,GFXMMU LUT entry 711 high" hexmask.long.tbyte 0x63C 4.--21. 1. "LO,Line offset" line.long 0x640 "GFXMMU_LUT712L,GFXMMU LUT entry 712 low" hexmask.long.byte 0x640 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x640 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x644 "GFXMMU_LUT712H,GFXMMU LUT entry 712 high" hexmask.long.tbyte 0x644 4.--21. 1. "LO,Line offset" line.long 0x648 "GFXMMU_LUT713L,GFXMMU LUT entry 713 low" hexmask.long.byte 0x648 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x648 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64C "GFXMMU_LUT713H,GFXMMU LUT entry 713 high" hexmask.long.tbyte 0x64C 4.--21. 1. "LO,Line offset" line.long 0x650 "GFXMMU_LUT714L,GFXMMU LUT entry 714 low" hexmask.long.byte 0x650 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x650 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x654 "GFXMMU_LUT714H,GFXMMU LUT entry 714 high" hexmask.long.tbyte 0x654 4.--21. 1. "LO,Line offset" line.long 0x658 "GFXMMU_LUT715L,GFXMMU LUT entry 715 low" hexmask.long.byte 0x658 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x658 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x65C "GFXMMU_LUT715H,GFXMMU LUT entry 715 high" hexmask.long.tbyte 0x65C 4.--21. 1. "LO,Line offset" line.long 0x660 "GFXMMU_LUT716L,GFXMMU LUT entry 716 low" hexmask.long.byte 0x660 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x660 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x664 "GFXMMU_LUT716H,GFXMMU LUT entry 716 high" hexmask.long.tbyte 0x664 4.--21. 1. "LO,Line offset" line.long 0x668 "GFXMMU_LUT717L,GFXMMU LUT entry 717 low" hexmask.long.byte 0x668 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x668 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x66C "GFXMMU_LUT717H,GFXMMU LUT entry 717 high" hexmask.long.tbyte 0x66C 4.--21. 1. "LO,Line offset" line.long 0x670 "GFXMMU_LUT718L,GFXMMU LUT entry 718 low" hexmask.long.byte 0x670 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x670 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x674 "GFXMMU_LUT718H,GFXMMU LUT entry 718 high" hexmask.long.tbyte 0x674 4.--21. 1. "LO,Line offset" line.long 0x678 "GFXMMU_LUT719L,GFXMMU LUT entry 719 low" hexmask.long.byte 0x678 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x678 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x67C "GFXMMU_LUT719H,GFXMMU LUT entry 719 high" hexmask.long.tbyte 0x67C 4.--21. 1. "LO,Line offset" line.long 0x680 "GFXMMU_LUT720L,GFXMMU LUT entry 720 low" hexmask.long.byte 0x680 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x680 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x684 "GFXMMU_LUT720H,GFXMMU LUT entry 720 high" hexmask.long.tbyte 0x684 4.--21. 1. "LO,Line offset" line.long 0x688 "GFXMMU_LUT721L,GFXMMU LUT entry 721 low" hexmask.long.byte 0x688 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x688 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x68C "GFXMMU_LUT721H,GFXMMU LUT entry 721 high" hexmask.long.tbyte 0x68C 4.--21. 1. "LO,Line offset" line.long 0x690 "GFXMMU_LUT722L,GFXMMU LUT entry 722 low" hexmask.long.byte 0x690 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x690 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x694 "GFXMMU_LUT722H,GFXMMU LUT entry 722 high" hexmask.long.tbyte 0x694 4.--21. 1. "LO,Line offset" line.long 0x698 "GFXMMU_LUT723L,GFXMMU LUT entry 723 low" hexmask.long.byte 0x698 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x698 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x69C "GFXMMU_LUT723H,GFXMMU LUT entry 723 high" hexmask.long.tbyte 0x69C 4.--21. 1. "LO,Line offset" line.long 0x6A0 "GFXMMU_LUT724L,GFXMMU LUT entry 724 low" hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6A4 "GFXMMU_LUT724H,GFXMMU LUT entry 724 high" hexmask.long.tbyte 0x6A4 4.--21. 1. "LO,Line offset" line.long 0x6A8 "GFXMMU_LUT725L,GFXMMU LUT entry 725 low" hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6AC "GFXMMU_LUT725H,GFXMMU LUT entry 725 high" hexmask.long.tbyte 0x6AC 4.--21. 1. "LO,Line offset" line.long 0x6B0 "GFXMMU_LUT726L,GFXMMU LUT entry 726 low" hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6B4 "GFXMMU_LUT726H,GFXMMU LUT entry 726 high" hexmask.long.tbyte 0x6B4 4.--21. 1. "LO,Line offset" line.long 0x6B8 "GFXMMU_LUT727L,GFXMMU LUT entry 727 low" hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6BC "GFXMMU_LUT727H,GFXMMU LUT entry 727 high" hexmask.long.tbyte 0x6BC 4.--21. 1. "LO,Line offset" line.long 0x6C0 "GFXMMU_LUT728L,GFXMMU LUT entry 728 low" hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C4 "GFXMMU_LUT728H,GFXMMU LUT entry 728 high" hexmask.long.tbyte 0x6C4 4.--21. 1. "LO,Line offset" line.long 0x6C8 "GFXMMU_LUT729L,GFXMMU LUT entry 729 low" hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6CC "GFXMMU_LUT729H,GFXMMU LUT entry 729 high" hexmask.long.tbyte 0x6CC 4.--21. 1. "LO,Line offset" line.long 0x6D0 "GFXMMU_LUT730L,GFXMMU LUT entry 730 low" hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6D4 "GFXMMU_LUT730H,GFXMMU LUT entry 730 high" hexmask.long.tbyte 0x6D4 4.--21. 1. "LO,Line offset" line.long 0x6D8 "GFXMMU_LUT731L,GFXMMU LUT entry 731 low" hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6DC "GFXMMU_LUT731H,GFXMMU LUT entry 731 high" hexmask.long.tbyte 0x6DC 4.--21. 1. "LO,Line offset" line.long 0x6E0 "GFXMMU_LUT732L,GFXMMU LUT entry 732 low" hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6E4 "GFXMMU_LUT732H,GFXMMU LUT entry 732 high" hexmask.long.tbyte 0x6E4 4.--21. 1. "LO,Line offset" line.long 0x6E8 "GFXMMU_LUT733L,GFXMMU LUT entry 733 low" hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6EC "GFXMMU_LUT733H,GFXMMU LUT entry 733 high" hexmask.long.tbyte 0x6EC 4.--21. 1. "LO,Line offset" line.long 0x6F0 "GFXMMU_LUT734L,GFXMMU LUT entry 734 low" hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6F4 "GFXMMU_LUT734H,GFXMMU LUT entry 734 high" hexmask.long.tbyte 0x6F4 4.--21. 1. "LO,Line offset" line.long 0x6F8 "GFXMMU_LUT735L,GFXMMU LUT entry 735 low" hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6FC "GFXMMU_LUT735H,GFXMMU LUT entry 735 high" hexmask.long.tbyte 0x6FC 4.--21. 1. "LO,Line offset" line.long 0x700 "GFXMMU_LUT736L,GFXMMU LUT entry 736 low" hexmask.long.byte 0x700 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x700 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x704 "GFXMMU_LUT736H,GFXMMU LUT entry 736 high" hexmask.long.tbyte 0x704 4.--21. 1. "LO,Line offset" line.long 0x708 "GFXMMU_LUT737L,GFXMMU LUT entry 737 low" hexmask.long.byte 0x708 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x708 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x70C "GFXMMU_LUT737H,GFXMMU LUT entry 737 high" hexmask.long.tbyte 0x70C 4.--21. 1. "LO,Line offset" line.long 0x710 "GFXMMU_LUT738L,GFXMMU LUT entry 738 low" hexmask.long.byte 0x710 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x710 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x714 "GFXMMU_LUT738H,GFXMMU LUT entry 738 high" hexmask.long.tbyte 0x714 4.--21. 1. "LO,Line offset" line.long 0x718 "GFXMMU_LUT739L,GFXMMU LUT entry 739 low" hexmask.long.byte 0x718 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x718 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x71C "GFXMMU_LUT739H,GFXMMU LUT entry 739 high" hexmask.long.tbyte 0x71C 4.--21. 1. "LO,Line offset" line.long 0x720 "GFXMMU_LUT740L,GFXMMU LUT entry 740 low" hexmask.long.byte 0x720 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x720 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x724 "GFXMMU_LUT740H,GFXMMU LUT entry 740 high" hexmask.long.tbyte 0x724 4.--21. 1. "LO,Line offset" line.long 0x728 "GFXMMU_LUT741L,GFXMMU LUT entry 741 low" hexmask.long.byte 0x728 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x728 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x72C "GFXMMU_LUT741H,GFXMMU LUT entry 741 high" hexmask.long.tbyte 0x72C 4.--21. 1. "LO,Line offset" line.long 0x730 "GFXMMU_LUT742L,GFXMMU LUT entry 742 low" hexmask.long.byte 0x730 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x730 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x734 "GFXMMU_LUT742H,GFXMMU LUT entry 742 high" hexmask.long.tbyte 0x734 4.--21. 1. "LO,Line offset" line.long 0x738 "GFXMMU_LUT743L,GFXMMU LUT entry 743 low" hexmask.long.byte 0x738 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x738 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x73C "GFXMMU_LUT743H,GFXMMU LUT entry 743 high" hexmask.long.tbyte 0x73C 4.--21. 1. "LO,Line offset" line.long 0x740 "GFXMMU_LUT744L,GFXMMU LUT entry 744 low" hexmask.long.byte 0x740 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x740 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x744 "GFXMMU_LUT744H,GFXMMU LUT entry 744 high" hexmask.long.tbyte 0x744 4.--21. 1. "LO,Line offset" line.long 0x748 "GFXMMU_LUT745L,GFXMMU LUT entry 745 low" hexmask.long.byte 0x748 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x748 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74C "GFXMMU_LUT745H,GFXMMU LUT entry 745 high" hexmask.long.tbyte 0x74C 4.--21. 1. "LO,Line offset" line.long 0x750 "GFXMMU_LUT746L,GFXMMU LUT entry 746 low" hexmask.long.byte 0x750 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x750 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x754 "GFXMMU_LUT746H,GFXMMU LUT entry 746 high" hexmask.long.tbyte 0x754 4.--21. 1. "LO,Line offset" line.long 0x758 "GFXMMU_LUT747L,GFXMMU LUT entry 747 low" hexmask.long.byte 0x758 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x758 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x75C "GFXMMU_LUT747H,GFXMMU LUT entry 747 high" hexmask.long.tbyte 0x75C 4.--21. 1. "LO,Line offset" line.long 0x760 "GFXMMU_LUT748L,GFXMMU LUT entry 748 low" hexmask.long.byte 0x760 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x760 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x764 "GFXMMU_LUT748H,GFXMMU LUT entry 748 high" hexmask.long.tbyte 0x764 4.--21. 1. "LO,Line offset" line.long 0x768 "GFXMMU_LUT749L,GFXMMU LUT entry 749 low" hexmask.long.byte 0x768 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x768 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x76C "GFXMMU_LUT749H,GFXMMU LUT entry 749 high" hexmask.long.tbyte 0x76C 4.--21. 1. "LO,Line offset" line.long 0x770 "GFXMMU_LUT750L,GFXMMU LUT entry 750 low" hexmask.long.byte 0x770 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x770 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x774 "GFXMMU_LUT750H,GFXMMU LUT entry 750 high" hexmask.long.tbyte 0x774 4.--21. 1. "LO,Line offset" line.long 0x778 "GFXMMU_LUT751L,GFXMMU LUT entry 751 low" hexmask.long.byte 0x778 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x778 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x77C "GFXMMU_LUT751H,GFXMMU LUT entry 751 high" hexmask.long.tbyte 0x77C 4.--21. 1. "LO,Line offset" line.long 0x780 "GFXMMU_LUT752L,GFXMMU LUT entry 752 low" hexmask.long.byte 0x780 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x780 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x784 "GFXMMU_LUT752H,GFXMMU LUT entry 752 high" hexmask.long.tbyte 0x784 4.--21. 1. "LO,Line offset" line.long 0x788 "GFXMMU_LUT753L,GFXMMU LUT entry 753 low" hexmask.long.byte 0x788 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x788 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x78C "GFXMMU_LUT753H,GFXMMU LUT entry 753 high" hexmask.long.tbyte 0x78C 4.--21. 1. "LO,Line offset" line.long 0x790 "GFXMMU_LUT754L,GFXMMU LUT entry 754 low" hexmask.long.byte 0x790 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x790 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x794 "GFXMMU_LUT754H,GFXMMU LUT entry 754 high" hexmask.long.tbyte 0x794 4.--21. 1. "LO,Line offset" line.long 0x798 "GFXMMU_LUT755L,GFXMMU LUT entry 755 low" hexmask.long.byte 0x798 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x798 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x79C "GFXMMU_LUT755H,GFXMMU LUT entry 755 high" hexmask.long.tbyte 0x79C 4.--21. 1. "LO,Line offset" line.long 0x7A0 "GFXMMU_LUT756L,GFXMMU LUT entry 756 low" hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7A4 "GFXMMU_LUT756H,GFXMMU LUT entry 756 high" hexmask.long.tbyte 0x7A4 4.--21. 1. "LO,Line offset" line.long 0x7A8 "GFXMMU_LUT757L,GFXMMU LUT entry 757 low" hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7AC "GFXMMU_LUT757H,GFXMMU LUT entry 757 high" hexmask.long.tbyte 0x7AC 4.--21. 1. "LO,Line offset" line.long 0x7B0 "GFXMMU_LUT758L,GFXMMU LUT entry 758 low" hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7B4 "GFXMMU_LUT758H,GFXMMU LUT entry 758 high" hexmask.long.tbyte 0x7B4 4.--21. 1. "LO,Line offset" line.long 0x7B8 "GFXMMU_LUT759L,GFXMMU LUT entry 759 low" hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7BC "GFXMMU_LUT759H,GFXMMU LUT entry 759 high" hexmask.long.tbyte 0x7BC 4.--21. 1. "LO,Line offset" line.long 0x7C0 "GFXMMU_LUT760L,GFXMMU LUT entry 760 low" hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C4 "GFXMMU_LUT760H,GFXMMU LUT entry 760 high" hexmask.long.tbyte 0x7C4 4.--21. 1. "LO,Line offset" line.long 0x7C8 "GFXMMU_LUT761L,GFXMMU LUT entry 761 low" hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7CC "GFXMMU_LUT761H,GFXMMU LUT entry 761 high" hexmask.long.tbyte 0x7CC 4.--21. 1. "LO,Line offset" line.long 0x7D0 "GFXMMU_LUT762L,GFXMMU LUT entry 762 low" hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7D4 "GFXMMU_LUT762H,GFXMMU LUT entry 762 high" hexmask.long.tbyte 0x7D4 4.--21. 1. "LO,Line offset" line.long 0x7D8 "GFXMMU_LUT763L,GFXMMU LUT entry 763 low" hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7DC "GFXMMU_LUT763H,GFXMMU LUT entry 763 high" hexmask.long.tbyte 0x7DC 4.--21. 1. "LO,Line offset" line.long 0x7E0 "GFXMMU_LUT764L,GFXMMU LUT entry 764 low" hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7E4 "GFXMMU_LUT764H,GFXMMU LUT entry 764 high" hexmask.long.tbyte 0x7E4 4.--21. 1. "LO,Line offset" line.long 0x7E8 "GFXMMU_LUT765L,GFXMMU LUT entry 765 low" hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7EC "GFXMMU_LUT765H,GFXMMU LUT entry 765 high" hexmask.long.tbyte 0x7EC 4.--21. 1. "LO,Line offset" line.long 0x7F0 "GFXMMU_LUT766L,GFXMMU LUT entry 766 low" hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7F4 "GFXMMU_LUT766H,GFXMMU LUT entry 766 high" hexmask.long.tbyte 0x7F4 4.--21. 1. "LO,Line offset" line.long 0x7F8 "GFXMMU_LUT767L,GFXMMU LUT entry 767 low" hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7FC "GFXMMU_LUT767H,GFXMMU LUT entry 767 high" hexmask.long.tbyte 0x7FC 4.--21. 1. "LO,Line offset" line.long 0x800 "GFXMMU_LUT768L,GFXMMU LUT entry 768 low" hexmask.long.byte 0x800 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x800 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x804 "GFXMMU_LUT768H,GFXMMU LUT entry 768 high" hexmask.long.tbyte 0x804 4.--21. 1. "LO,Line offset" line.long 0x808 "GFXMMU_LUT769L,GFXMMU LUT entry 769 low" hexmask.long.byte 0x808 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x808 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x80C "GFXMMU_LUT769H,GFXMMU LUT entry 769 high" hexmask.long.tbyte 0x80C 4.--21. 1. "LO,Line offset" line.long 0x810 "GFXMMU_LUT770L,GFXMMU LUT entry 770 low" hexmask.long.byte 0x810 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x810 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x814 "GFXMMU_LUT770H,GFXMMU LUT entry 770 high" hexmask.long.tbyte 0x814 4.--21. 1. "LO,Line offset" line.long 0x818 "GFXMMU_LUT771L,GFXMMU LUT entry 771 low" hexmask.long.byte 0x818 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x818 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x81C "GFXMMU_LUT771H,GFXMMU LUT entry 771 high" hexmask.long.tbyte 0x81C 4.--21. 1. "LO,Line offset" line.long 0x820 "GFXMMU_LUT772L,GFXMMU LUT entry 772 low" hexmask.long.byte 0x820 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x820 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x824 "GFXMMU_LUT772H,GFXMMU LUT entry 772 high" hexmask.long.tbyte 0x824 4.--21. 1. "LO,Line offset" line.long 0x828 "GFXMMU_LUT773L,GFXMMU LUT entry 773 low" hexmask.long.byte 0x828 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x828 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x82C "GFXMMU_LUT773H,GFXMMU LUT entry 773 high" hexmask.long.tbyte 0x82C 4.--21. 1. "LO,Line offset" line.long 0x830 "GFXMMU_LUT774L,GFXMMU LUT entry 774 low" hexmask.long.byte 0x830 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x830 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x834 "GFXMMU_LUT774H,GFXMMU LUT entry 774 high" hexmask.long.tbyte 0x834 4.--21. 1. "LO,Line offset" line.long 0x838 "GFXMMU_LUT775L,GFXMMU LUT entry 775 low" hexmask.long.byte 0x838 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x838 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x83C "GFXMMU_LUT775H,GFXMMU LUT entry 775 high" hexmask.long.tbyte 0x83C 4.--21. 1. "LO,Line offset" line.long 0x840 "GFXMMU_LUT776L,GFXMMU LUT entry 776 low" hexmask.long.byte 0x840 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x840 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x844 "GFXMMU_LUT776H,GFXMMU LUT entry 776 high" hexmask.long.tbyte 0x844 4.--21. 1. "LO,Line offset" line.long 0x848 "GFXMMU_LUT777L,GFXMMU LUT entry 777 low" hexmask.long.byte 0x848 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x848 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84C "GFXMMU_LUT777H,GFXMMU LUT entry 777 high" hexmask.long.tbyte 0x84C 4.--21. 1. "LO,Line offset" line.long 0x850 "GFXMMU_LUT778L,GFXMMU LUT entry 778 low" hexmask.long.byte 0x850 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x850 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x854 "GFXMMU_LUT778H,GFXMMU LUT entry 778 high" hexmask.long.tbyte 0x854 4.--21. 1. "LO,Line offset" line.long 0x858 "GFXMMU_LUT779L,GFXMMU LUT entry 779 low" hexmask.long.byte 0x858 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x858 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x85C "GFXMMU_LUT779H,GFXMMU LUT entry 779 high" hexmask.long.tbyte 0x85C 4.--21. 1. "LO,Line offset" line.long 0x860 "GFXMMU_LUT780L,GFXMMU LUT entry 780 low" hexmask.long.byte 0x860 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x860 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x864 "GFXMMU_LUT780H,GFXMMU LUT entry 780 high" hexmask.long.tbyte 0x864 4.--21. 1. "LO,Line offset" line.long 0x868 "GFXMMU_LUT781L,GFXMMU LUT entry 781 low" hexmask.long.byte 0x868 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x868 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x86C "GFXMMU_LUT781H,GFXMMU LUT entry 781 high" hexmask.long.tbyte 0x86C 4.--21. 1. "LO,Line offset" line.long 0x870 "GFXMMU_LUT782L,GFXMMU LUT entry 782 low" hexmask.long.byte 0x870 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x870 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x874 "GFXMMU_LUT782H,GFXMMU LUT entry 782 high" hexmask.long.tbyte 0x874 4.--21. 1. "LO,Line offset" line.long 0x878 "GFXMMU_LUT783L,GFXMMU LUT entry 783 low" hexmask.long.byte 0x878 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x878 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x87C "GFXMMU_LUT783H,GFXMMU LUT entry 783 high" hexmask.long.tbyte 0x87C 4.--21. 1. "LO,Line offset" line.long 0x880 "GFXMMU_LUT784L,GFXMMU LUT entry 784 low" hexmask.long.byte 0x880 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x880 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x884 "GFXMMU_LUT784H,GFXMMU LUT entry 784 high" hexmask.long.tbyte 0x884 4.--21. 1. "LO,Line offset" line.long 0x888 "GFXMMU_LUT785L,GFXMMU LUT entry 785 low" hexmask.long.byte 0x888 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x888 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x88C "GFXMMU_LUT785H,GFXMMU LUT entry 785 high" hexmask.long.tbyte 0x88C 4.--21. 1. "LO,Line offset" line.long 0x890 "GFXMMU_LUT786L,GFXMMU LUT entry 786 low" hexmask.long.byte 0x890 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x890 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x894 "GFXMMU_LUT786H,GFXMMU LUT entry 786 high" hexmask.long.tbyte 0x894 4.--21. 1. "LO,Line offset" line.long 0x898 "GFXMMU_LUT787L,GFXMMU LUT entry 787 low" hexmask.long.byte 0x898 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x898 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x89C "GFXMMU_LUT787H,GFXMMU LUT entry 787 high" hexmask.long.tbyte 0x89C 4.--21. 1. "LO,Line offset" line.long 0x8A0 "GFXMMU_LUT788L,GFXMMU LUT entry 788 low" hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8A4 "GFXMMU_LUT788H,GFXMMU LUT entry 788 high" hexmask.long.tbyte 0x8A4 4.--21. 1. "LO,Line offset" line.long 0x8A8 "GFXMMU_LUT789L,GFXMMU LUT entry 789 low" hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8AC "GFXMMU_LUT789H,GFXMMU LUT entry 789 high" hexmask.long.tbyte 0x8AC 4.--21. 1. "LO,Line offset" line.long 0x8B0 "GFXMMU_LUT790L,GFXMMU LUT entry 790 low" hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8B4 "GFXMMU_LUT790H,GFXMMU LUT entry 790 high" hexmask.long.tbyte 0x8B4 4.--21. 1. "LO,Line offset" line.long 0x8B8 "GFXMMU_LUT791L,GFXMMU LUT entry 791 low" hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8BC "GFXMMU_LUT791H,GFXMMU LUT entry 791 high" hexmask.long.tbyte 0x8BC 4.--21. 1. "LO,Line offset" line.long 0x8C0 "GFXMMU_LUT792L,GFXMMU LUT entry 792 low" hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C4 "GFXMMU_LUT792H,GFXMMU LUT entry 792 high" hexmask.long.tbyte 0x8C4 4.--21. 1. "LO,Line offset" line.long 0x8C8 "GFXMMU_LUT793L,GFXMMU LUT entry 793 low" hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8CC "GFXMMU_LUT793H,GFXMMU LUT entry 793 high" hexmask.long.tbyte 0x8CC 4.--21. 1. "LO,Line offset" line.long 0x8D0 "GFXMMU_LUT794L,GFXMMU LUT entry 794 low" hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8D4 "GFXMMU_LUT794H,GFXMMU LUT entry 794 high" hexmask.long.tbyte 0x8D4 4.--21. 1. "LO,Line offset" line.long 0x8D8 "GFXMMU_LUT795L,GFXMMU LUT entry 795 low" hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8DC "GFXMMU_LUT795H,GFXMMU LUT entry 795 high" hexmask.long.tbyte 0x8DC 4.--21. 1. "LO,Line offset" line.long 0x8E0 "GFXMMU_LUT796L,GFXMMU LUT entry 796 low" hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8E4 "GFXMMU_LUT796H,GFXMMU LUT entry 796 high" hexmask.long.tbyte 0x8E4 4.--21. 1. "LO,Line offset" line.long 0x8E8 "GFXMMU_LUT797L,GFXMMU LUT entry 797 low" hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8EC "GFXMMU_LUT797H,GFXMMU LUT entry 797 high" hexmask.long.tbyte 0x8EC 4.--21. 1. "LO,Line offset" line.long 0x8F0 "GFXMMU_LUT798L,GFXMMU LUT entry 798 low" hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8F4 "GFXMMU_LUT798H,GFXMMU LUT entry 798 high" hexmask.long.tbyte 0x8F4 4.--21. 1. "LO,Line offset" line.long 0x8F8 "GFXMMU_LUT799L,GFXMMU LUT entry 799 low" hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8FC "GFXMMU_LUT799H,GFXMMU LUT entry 799 high" hexmask.long.tbyte 0x8FC 4.--21. 1. "LO,Line offset" line.long 0x900 "GFXMMU_LUT800L,GFXMMU LUT entry 800 low" hexmask.long.byte 0x900 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x900 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x904 "GFXMMU_LUT800H,GFXMMU LUT entry 800 high" hexmask.long.tbyte 0x904 4.--21. 1. "LO,Line offset" line.long 0x908 "GFXMMU_LUT801L,GFXMMU LUT entry 801 low" hexmask.long.byte 0x908 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x908 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x90C "GFXMMU_LUT801H,GFXMMU LUT entry 801 high" hexmask.long.tbyte 0x90C 4.--21. 1. "LO,Line offset" line.long 0x910 "GFXMMU_LUT802L,GFXMMU LUT entry 802 low" hexmask.long.byte 0x910 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x910 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x914 "GFXMMU_LUT802H,GFXMMU LUT entry 802 high" hexmask.long.tbyte 0x914 4.--21. 1. "LO,Line offset" line.long 0x918 "GFXMMU_LUT803L,GFXMMU LUT entry 803 low" hexmask.long.byte 0x918 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x918 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x91C "GFXMMU_LUT803H,GFXMMU LUT entry 803 high" hexmask.long.tbyte 0x91C 4.--21. 1. "LO,Line offset" line.long 0x920 "GFXMMU_LUT804L,GFXMMU LUT entry 804 low" hexmask.long.byte 0x920 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x920 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x924 "GFXMMU_LUT804H,GFXMMU LUT entry 804 high" hexmask.long.tbyte 0x924 4.--21. 1. "LO,Line offset" line.long 0x928 "GFXMMU_LUT805L,GFXMMU LUT entry 805 low" hexmask.long.byte 0x928 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x928 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x92C "GFXMMU_LUT805H,GFXMMU LUT entry 805 high" hexmask.long.tbyte 0x92C 4.--21. 1. "LO,Line offset" line.long 0x930 "GFXMMU_LUT806L,GFXMMU LUT entry 806 low" hexmask.long.byte 0x930 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x930 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x934 "GFXMMU_LUT806H,GFXMMU LUT entry 806 high" hexmask.long.tbyte 0x934 4.--21. 1. "LO,Line offset" line.long 0x938 "GFXMMU_LUT807L,GFXMMU LUT entry 807 low" hexmask.long.byte 0x938 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x938 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x93C "GFXMMU_LUT807H,GFXMMU LUT entry 807 high" hexmask.long.tbyte 0x93C 4.--21. 1. "LO,Line offset" line.long 0x940 "GFXMMU_LUT808L,GFXMMU LUT entry 808 low" hexmask.long.byte 0x940 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x940 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x944 "GFXMMU_LUT808H,GFXMMU LUT entry 808 high" hexmask.long.tbyte 0x944 4.--21. 1. "LO,Line offset" line.long 0x948 "GFXMMU_LUT809L,GFXMMU LUT entry 809 low" hexmask.long.byte 0x948 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x948 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94C "GFXMMU_LUT809H,GFXMMU LUT entry 809 high" hexmask.long.tbyte 0x94C 4.--21. 1. "LO,Line offset" line.long 0x950 "GFXMMU_LUT810L,GFXMMU LUT entry 810 low" hexmask.long.byte 0x950 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x950 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x954 "GFXMMU_LUT810H,GFXMMU LUT entry 810 high" hexmask.long.tbyte 0x954 4.--21. 1. "LO,Line offset" line.long 0x958 "GFXMMU_LUT811L,GFXMMU LUT entry 811 low" hexmask.long.byte 0x958 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x958 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x95C "GFXMMU_LUT811H,GFXMMU LUT entry 811 high" hexmask.long.tbyte 0x95C 4.--21. 1. "LO,Line offset" line.long 0x960 "GFXMMU_LUT812L,GFXMMU LUT entry 812 low" hexmask.long.byte 0x960 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x960 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x964 "GFXMMU_LUT812H,GFXMMU LUT entry 812 high" hexmask.long.tbyte 0x964 4.--21. 1. "LO,Line offset" line.long 0x968 "GFXMMU_LUT813L,GFXMMU LUT entry 813 low" hexmask.long.byte 0x968 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x968 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x96C "GFXMMU_LUT813H,GFXMMU LUT entry 813 high" hexmask.long.tbyte 0x96C 4.--21. 1. "LO,Line offset" line.long 0x970 "GFXMMU_LUT814L,GFXMMU LUT entry 814 low" hexmask.long.byte 0x970 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x970 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x974 "GFXMMU_LUT814H,GFXMMU LUT entry 814 high" hexmask.long.tbyte 0x974 4.--21. 1. "LO,Line offset" line.long 0x978 "GFXMMU_LUT815L,GFXMMU LUT entry 815 low" hexmask.long.byte 0x978 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x978 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x97C "GFXMMU_LUT815H,GFXMMU LUT entry 815 high" hexmask.long.tbyte 0x97C 4.--21. 1. "LO,Line offset" line.long 0x980 "GFXMMU_LUT816L,GFXMMU LUT entry 816 low" hexmask.long.byte 0x980 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x980 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x984 "GFXMMU_LUT816H,GFXMMU LUT entry 816 high" hexmask.long.tbyte 0x984 4.--21. 1. "LO,Line offset" line.long 0x988 "GFXMMU_LUT817L,GFXMMU LUT entry 817 low" hexmask.long.byte 0x988 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x988 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x98C "GFXMMU_LUT817H,GFXMMU LUT entry 817 high" hexmask.long.tbyte 0x98C 4.--21. 1. "LO,Line offset" line.long 0x990 "GFXMMU_LUT818L,GFXMMU LUT entry 818 low" hexmask.long.byte 0x990 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x990 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x994 "GFXMMU_LUT818H,GFXMMU LUT entry 818 high" hexmask.long.tbyte 0x994 4.--21. 1. "LO,Line offset" line.long 0x998 "GFXMMU_LUT819L,GFXMMU LUT entry 819 low" hexmask.long.byte 0x998 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x998 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x99C "GFXMMU_LUT819H,GFXMMU LUT entry 819 high" hexmask.long.tbyte 0x99C 4.--21. 1. "LO,Line offset" line.long 0x9A0 "GFXMMU_LUT820L,GFXMMU LUT entry 820 low" hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9A4 "GFXMMU_LUT820H,GFXMMU LUT entry 820 high" hexmask.long.tbyte 0x9A4 4.--21. 1. "LO,Line offset" line.long 0x9A8 "GFXMMU_LUT821L,GFXMMU LUT entry 821 low" hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9AC "GFXMMU_LUT821H,GFXMMU LUT entry 821 high" hexmask.long.tbyte 0x9AC 4.--21. 1. "LO,Line offset" line.long 0x9B0 "GFXMMU_LUT822L,GFXMMU LUT entry 822 low" hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9B4 "GFXMMU_LUT822H,GFXMMU LUT entry 822 high" hexmask.long.tbyte 0x9B4 4.--21. 1. "LO,Line offset" line.long 0x9B8 "GFXMMU_LUT823L,GFXMMU LUT entry 823 low" hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9BC "GFXMMU_LUT823H,GFXMMU LUT entry 823 high" hexmask.long.tbyte 0x9BC 4.--21. 1. "LO,Line offset" line.long 0x9C0 "GFXMMU_LUT824L,GFXMMU LUT entry 824 low" hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C4 "GFXMMU_LUT824H,GFXMMU LUT entry 824 high" hexmask.long.tbyte 0x9C4 4.--21. 1. "LO,Line offset" line.long 0x9C8 "GFXMMU_LUT825L,GFXMMU LUT entry 825 low" hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9CC "GFXMMU_LUT825H,GFXMMU LUT entry 825 high" hexmask.long.tbyte 0x9CC 4.--21. 1. "LO,Line offset" line.long 0x9D0 "GFXMMU_LUT826L,GFXMMU LUT entry 826 low" hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9D4 "GFXMMU_LUT826H,GFXMMU LUT entry 826 high" hexmask.long.tbyte 0x9D4 4.--21. 1. "LO,Line offset" line.long 0x9D8 "GFXMMU_LUT827L,GFXMMU LUT entry 827 low" hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9DC "GFXMMU_LUT827H,GFXMMU LUT entry 827 high" hexmask.long.tbyte 0x9DC 4.--21. 1. "LO,Line offset" line.long 0x9E0 "GFXMMU_LUT828L,GFXMMU LUT entry 828 low" hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9E4 "GFXMMU_LUT828H,GFXMMU LUT entry 828 high" hexmask.long.tbyte 0x9E4 4.--21. 1. "LO,Line offset" line.long 0x9E8 "GFXMMU_LUT829L,GFXMMU LUT entry 829 low" hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9EC "GFXMMU_LUT829H,GFXMMU LUT entry 829 high" hexmask.long.tbyte 0x9EC 4.--21. 1. "LO,Line offset" line.long 0x9F0 "GFXMMU_LUT830L,GFXMMU LUT entry 830 low" hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9F4 "GFXMMU_LUT830H,GFXMMU LUT entry 830 high" hexmask.long.tbyte 0x9F4 4.--21. 1. "LO,Line offset" line.long 0x9F8 "GFXMMU_LUT831L,GFXMMU LUT entry 831 low" hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9FC "GFXMMU_LUT831H,GFXMMU LUT entry 831 high" hexmask.long.tbyte 0x9FC 4.--21. 1. "LO,Line offset" line.long 0xA00 "GFXMMU_LUT832L,GFXMMU LUT entry 832 low" hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA04 "GFXMMU_LUT832H,GFXMMU LUT entry 832 high" hexmask.long.tbyte 0xA04 4.--21. 1. "LO,Line offset" line.long 0xA08 "GFXMMU_LUT833L,GFXMMU LUT entry 833 low" hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA0C "GFXMMU_LUT833H,GFXMMU LUT entry 833 high" hexmask.long.tbyte 0xA0C 4.--21. 1. "LO,Line offset" line.long 0xA10 "GFXMMU_LUT834L,GFXMMU LUT entry 834 low" hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA14 "GFXMMU_LUT834H,GFXMMU LUT entry 834 high" hexmask.long.tbyte 0xA14 4.--21. 1. "LO,Line offset" line.long 0xA18 "GFXMMU_LUT835L,GFXMMU LUT entry 835 low" hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA1C "GFXMMU_LUT835H,GFXMMU LUT entry 835 high" hexmask.long.tbyte 0xA1C 4.--21. 1. "LO,Line offset" line.long 0xA20 "GFXMMU_LUT836L,GFXMMU LUT entry 836 low" hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA24 "GFXMMU_LUT836H,GFXMMU LUT entry 836 high" hexmask.long.tbyte 0xA24 4.--21. 1. "LO,Line offset" line.long 0xA28 "GFXMMU_LUT837L,GFXMMU LUT entry 837 low" hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA2C "GFXMMU_LUT837H,GFXMMU LUT entry 837 high" hexmask.long.tbyte 0xA2C 4.--21. 1. "LO,Line offset" line.long 0xA30 "GFXMMU_LUT838L,GFXMMU LUT entry 838 low" hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA34 "GFXMMU_LUT838H,GFXMMU LUT entry 838 high" hexmask.long.tbyte 0xA34 4.--21. 1. "LO,Line offset" line.long 0xA38 "GFXMMU_LUT839L,GFXMMU LUT entry 839 low" hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA3C "GFXMMU_LUT839H,GFXMMU LUT entry 839 high" hexmask.long.tbyte 0xA3C 4.--21. 1. "LO,Line offset" line.long 0xA40 "GFXMMU_LUT840L,GFXMMU LUT entry 840 low" hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA44 "GFXMMU_LUT840H,GFXMMU LUT entry 840 high" hexmask.long.tbyte 0xA44 4.--21. 1. "LO,Line offset" line.long 0xA48 "GFXMMU_LUT841L,GFXMMU LUT entry 841 low" hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4C "GFXMMU_LUT841H,GFXMMU LUT entry 841 high" hexmask.long.tbyte 0xA4C 4.--21. 1. "LO,Line offset" line.long 0xA50 "GFXMMU_LUT842L,GFXMMU LUT entry 842 low" hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA54 "GFXMMU_LUT842H,GFXMMU LUT entry 842 high" hexmask.long.tbyte 0xA54 4.--21. 1. "LO,Line offset" line.long 0xA58 "GFXMMU_LUT843L,GFXMMU LUT entry 843 low" hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA5C "GFXMMU_LUT843H,GFXMMU LUT entry 843 high" hexmask.long.tbyte 0xA5C 4.--21. 1. "LO,Line offset" line.long 0xA60 "GFXMMU_LUT844L,GFXMMU LUT entry 844 low" hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA64 "GFXMMU_LUT844H,GFXMMU LUT entry 844 high" hexmask.long.tbyte 0xA64 4.--21. 1. "LO,Line offset" line.long 0xA68 "GFXMMU_LUT845L,GFXMMU LUT entry 845 low" hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA6C "GFXMMU_LUT845H,GFXMMU LUT entry 845 high" hexmask.long.tbyte 0xA6C 4.--21. 1. "LO,Line offset" line.long 0xA70 "GFXMMU_LUT846L,GFXMMU LUT entry 846 low" hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA74 "GFXMMU_LUT846H,GFXMMU LUT entry 846 high" hexmask.long.tbyte 0xA74 4.--21. 1. "LO,Line offset" line.long 0xA78 "GFXMMU_LUT847L,GFXMMU LUT entry 847 low" hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA7C "GFXMMU_LUT847H,GFXMMU LUT entry 847 high" hexmask.long.tbyte 0xA7C 4.--21. 1. "LO,Line offset" line.long 0xA80 "GFXMMU_LUT848L,GFXMMU LUT entry 848 low" hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA84 "GFXMMU_LUT848H,GFXMMU LUT entry 848 high" hexmask.long.tbyte 0xA84 4.--21. 1. "LO,Line offset" line.long 0xA88 "GFXMMU_LUT849L,GFXMMU LUT entry 849 low" hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA8C "GFXMMU_LUT849H,GFXMMU LUT entry 849 high" hexmask.long.tbyte 0xA8C 4.--21. 1. "LO,Line offset" line.long 0xA90 "GFXMMU_LUT850L,GFXMMU LUT entry 850 low" hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA94 "GFXMMU_LUT850H,GFXMMU LUT entry 850 high" hexmask.long.tbyte 0xA94 4.--21. 1. "LO,Line offset" line.long 0xA98 "GFXMMU_LUT851L,GFXMMU LUT entry 851 low" hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xA98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA9C "GFXMMU_LUT851H,GFXMMU LUT entry 851 high" hexmask.long.tbyte 0xA9C 4.--21. 1. "LO,Line offset" line.long 0xAA0 "GFXMMU_LUT852L,GFXMMU LUT entry 852 low" hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAA4 "GFXMMU_LUT852H,GFXMMU LUT entry 852 high" hexmask.long.tbyte 0xAA4 4.--21. 1. "LO,Line offset" line.long 0xAA8 "GFXMMU_LUT853L,GFXMMU LUT entry 853 low" hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAAC "GFXMMU_LUT853H,GFXMMU LUT entry 853 high" hexmask.long.tbyte 0xAAC 4.--21. 1. "LO,Line offset" line.long 0xAB0 "GFXMMU_LUT854L,GFXMMU LUT entry 854 low" hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAB4 "GFXMMU_LUT854H,GFXMMU LUT entry 854 high" hexmask.long.tbyte 0xAB4 4.--21. 1. "LO,Line offset" line.long 0xAB8 "GFXMMU_LUT855L,GFXMMU LUT entry 855 low" hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xABC "GFXMMU_LUT855H,GFXMMU LUT entry 855 high" hexmask.long.tbyte 0xABC 4.--21. 1. "LO,Line offset" line.long 0xAC0 "GFXMMU_LUT856L,GFXMMU LUT entry 856 low" hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC4 "GFXMMU_LUT856H,GFXMMU LUT entry 856 high" hexmask.long.tbyte 0xAC4 4.--21. 1. "LO,Line offset" line.long 0xAC8 "GFXMMU_LUT857L,GFXMMU LUT entry 857 low" hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xACC "GFXMMU_LUT857H,GFXMMU LUT entry 857 high" hexmask.long.tbyte 0xACC 4.--21. 1. "LO,Line offset" line.long 0xAD0 "GFXMMU_LUT858L,GFXMMU LUT entry 858 low" hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAD4 "GFXMMU_LUT858H,GFXMMU LUT entry 858 high" hexmask.long.tbyte 0xAD4 4.--21. 1. "LO,Line offset" line.long 0xAD8 "GFXMMU_LUT859L,GFXMMU LUT entry 859 low" hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xADC "GFXMMU_LUT859H,GFXMMU LUT entry 859 high" hexmask.long.tbyte 0xADC 4.--21. 1. "LO,Line offset" line.long 0xAE0 "GFXMMU_LUT860L,GFXMMU LUT entry 860 low" hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAE4 "GFXMMU_LUT860H,GFXMMU LUT entry 860 high" hexmask.long.tbyte 0xAE4 4.--21. 1. "LO,Line offset" line.long 0xAE8 "GFXMMU_LUT861L,GFXMMU LUT entry 861 low" hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAEC "GFXMMU_LUT861H,GFXMMU LUT entry 861 high" hexmask.long.tbyte 0xAEC 4.--21. 1. "LO,Line offset" line.long 0xAF0 "GFXMMU_LUT862L,GFXMMU LUT entry 862 low" hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAF4 "GFXMMU_LUT862H,GFXMMU LUT entry 862 high" hexmask.long.tbyte 0xAF4 4.--21. 1. "LO,Line offset" line.long 0xAF8 "GFXMMU_LUT863L,GFXMMU LUT entry 863 low" hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAFC "GFXMMU_LUT863H,GFXMMU LUT entry 863 high" hexmask.long.tbyte 0xAFC 4.--21. 1. "LO,Line offset" line.long 0xB00 "GFXMMU_LUT864L,GFXMMU LUT entry 864 low" hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB04 "GFXMMU_LUT864H,GFXMMU LUT entry 864 high" hexmask.long.tbyte 0xB04 4.--21. 1. "LO,Line offset" line.long 0xB08 "GFXMMU_LUT865L,GFXMMU LUT entry 865 low" hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB0C "GFXMMU_LUT865H,GFXMMU LUT entry 865 high" hexmask.long.tbyte 0xB0C 4.--21. 1. "LO,Line offset" line.long 0xB10 "GFXMMU_LUT866L,GFXMMU LUT entry 866 low" hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB14 "GFXMMU_LUT866H,GFXMMU LUT entry 866 high" hexmask.long.tbyte 0xB14 4.--21. 1. "LO,Line offset" line.long 0xB18 "GFXMMU_LUT867L,GFXMMU LUT entry 867 low" hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB1C "GFXMMU_LUT867H,GFXMMU LUT entry 867 high" hexmask.long.tbyte 0xB1C 4.--21. 1. "LO,Line offset" line.long 0xB20 "GFXMMU_LUT868L,GFXMMU LUT entry 868 low" hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB24 "GFXMMU_LUT868H,GFXMMU LUT entry 868 high" hexmask.long.tbyte 0xB24 4.--21. 1. "LO,Line offset" line.long 0xB28 "GFXMMU_LUT869L,GFXMMU LUT entry 869 low" hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB2C "GFXMMU_LUT869H,GFXMMU LUT entry 869 high" hexmask.long.tbyte 0xB2C 4.--21. 1. "LO,Line offset" line.long 0xB30 "GFXMMU_LUT870L,GFXMMU LUT entry 870 low" hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB34 "GFXMMU_LUT870H,GFXMMU LUT entry 870 high" hexmask.long.tbyte 0xB34 4.--21. 1. "LO,Line offset" line.long 0xB38 "GFXMMU_LUT871L,GFXMMU LUT entry 871 low" hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB3C "GFXMMU_LUT871H,GFXMMU LUT entry 871 high" hexmask.long.tbyte 0xB3C 4.--21. 1. "LO,Line offset" line.long 0xB40 "GFXMMU_LUT872L,GFXMMU LUT entry 872 low" hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB44 "GFXMMU_LUT872H,GFXMMU LUT entry 872 high" hexmask.long.tbyte 0xB44 4.--21. 1. "LO,Line offset" line.long 0xB48 "GFXMMU_LUT873L,GFXMMU LUT entry 873 low" hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4C "GFXMMU_LUT873H,GFXMMU LUT entry 873 high" hexmask.long.tbyte 0xB4C 4.--21. 1. "LO,Line offset" line.long 0xB50 "GFXMMU_LUT874L,GFXMMU LUT entry 874 low" hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB54 "GFXMMU_LUT874H,GFXMMU LUT entry 874 high" hexmask.long.tbyte 0xB54 4.--21. 1. "LO,Line offset" line.long 0xB58 "GFXMMU_LUT875L,GFXMMU LUT entry 875 low" hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB5C "GFXMMU_LUT875H,GFXMMU LUT entry 875 high" hexmask.long.tbyte 0xB5C 4.--21. 1. "LO,Line offset" line.long 0xB60 "GFXMMU_LUT876L,GFXMMU LUT entry 876 low" hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB64 "GFXMMU_LUT876H,GFXMMU LUT entry 876 high" hexmask.long.tbyte 0xB64 4.--21. 1. "LO,Line offset" line.long 0xB68 "GFXMMU_LUT877L,GFXMMU LUT entry 877 low" hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB6C "GFXMMU_LUT877H,GFXMMU LUT entry 877 high" hexmask.long.tbyte 0xB6C 4.--21. 1. "LO,Line offset" line.long 0xB70 "GFXMMU_LUT878L,GFXMMU LUT entry 878 low" hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB74 "GFXMMU_LUT878H,GFXMMU LUT entry 878 high" hexmask.long.tbyte 0xB74 4.--21. 1. "LO,Line offset" line.long 0xB78 "GFXMMU_LUT879L,GFXMMU LUT entry 879 low" hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB7C "GFXMMU_LUT879H,GFXMMU LUT entry 879 high" hexmask.long.tbyte 0xB7C 4.--21. 1. "LO,Line offset" line.long 0xB80 "GFXMMU_LUT880L,GFXMMU LUT entry 880 low" hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB84 "GFXMMU_LUT880H,GFXMMU LUT entry 880 high" hexmask.long.tbyte 0xB84 4.--21. 1. "LO,Line offset" line.long 0xB88 "GFXMMU_LUT881L,GFXMMU LUT entry 881 low" hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB8C "GFXMMU_LUT881H,GFXMMU LUT entry 881 high" hexmask.long.tbyte 0xB8C 4.--21. 1. "LO,Line offset" line.long 0xB90 "GFXMMU_LUT882L,GFXMMU LUT entry 882 low" hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB94 "GFXMMU_LUT882H,GFXMMU LUT entry 882 high" hexmask.long.tbyte 0xB94 4.--21. 1. "LO,Line offset" line.long 0xB98 "GFXMMU_LUT883L,GFXMMU LUT entry 883 low" hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xB98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB9C "GFXMMU_LUT883H,GFXMMU LUT entry 883 high" hexmask.long.tbyte 0xB9C 4.--21. 1. "LO,Line offset" line.long 0xBA0 "GFXMMU_LUT884L,GFXMMU LUT entry 884 low" hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBA4 "GFXMMU_LUT884H,GFXMMU LUT entry 884 high" hexmask.long.tbyte 0xBA4 4.--21. 1. "LO,Line offset" line.long 0xBA8 "GFXMMU_LUT885L,GFXMMU LUT entry 885 low" hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBAC "GFXMMU_LUT885H,GFXMMU LUT entry 885 high" hexmask.long.tbyte 0xBAC 4.--21. 1. "LO,Line offset" line.long 0xBB0 "GFXMMU_LUT886L,GFXMMU LUT entry 886 low" hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBB4 "GFXMMU_LUT886H,GFXMMU LUT entry 886 high" hexmask.long.tbyte 0xBB4 4.--21. 1. "LO,Line offset" line.long 0xBB8 "GFXMMU_LUT887L,GFXMMU LUT entry 887 low" hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBBC "GFXMMU_LUT887H,GFXMMU LUT entry 887 high" hexmask.long.tbyte 0xBBC 4.--21. 1. "LO,Line offset" line.long 0xBC0 "GFXMMU_LUT888L,GFXMMU LUT entry 888 low" hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC4 "GFXMMU_LUT888H,GFXMMU LUT entry 888 high" hexmask.long.tbyte 0xBC4 4.--21. 1. "LO,Line offset" line.long 0xBC8 "GFXMMU_LUT889L,GFXMMU LUT entry 889 low" hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBCC "GFXMMU_LUT889H,GFXMMU LUT entry 889 high" hexmask.long.tbyte 0xBCC 4.--21. 1. "LO,Line offset" line.long 0xBD0 "GFXMMU_LUT890L,GFXMMU LUT entry 890 low" hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBD4 "GFXMMU_LUT890H,GFXMMU LUT entry 890 high" hexmask.long.tbyte 0xBD4 4.--21. 1. "LO,Line offset" line.long 0xBD8 "GFXMMU_LUT891L,GFXMMU LUT entry 891 low" hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBDC "GFXMMU_LUT891H,GFXMMU LUT entry 891 high" hexmask.long.tbyte 0xBDC 4.--21. 1. "LO,Line offset" line.long 0xBE0 "GFXMMU_LUT892L,GFXMMU LUT entry 892 low" hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBE4 "GFXMMU_LUT892H,GFXMMU LUT entry 892 high" hexmask.long.tbyte 0xBE4 4.--21. 1. "LO,Line offset" line.long 0xBE8 "GFXMMU_LUT893L,GFXMMU LUT entry 893 low" hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBEC "GFXMMU_LUT893H,GFXMMU LUT entry 893 high" hexmask.long.tbyte 0xBEC 4.--21. 1. "LO,Line offset" line.long 0xBF0 "GFXMMU_LUT894L,GFXMMU LUT entry 894 low" hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBF4 "GFXMMU_LUT894H,GFXMMU LUT entry 894 high" hexmask.long.tbyte 0xBF4 4.--21. 1. "LO,Line offset" line.long 0xBF8 "GFXMMU_LUT895L,GFXMMU LUT entry 895 low" hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBFC "GFXMMU_LUT895H,GFXMMU LUT entry 895 high" hexmask.long.tbyte 0xBFC 4.--21. 1. "LO,Line offset" line.long 0xC00 "GFXMMU_LUT896L,GFXMMU LUT entry 896 low" hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC04 "GFXMMU_LUT896H,GFXMMU LUT entry 896 high" hexmask.long.tbyte 0xC04 4.--21. 1. "LO,Line offset" line.long 0xC08 "GFXMMU_LUT897L,GFXMMU LUT entry 897 low" hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC0C "GFXMMU_LUT897H,GFXMMU LUT entry 897 high" hexmask.long.tbyte 0xC0C 4.--21. 1. "LO,Line offset" line.long 0xC10 "GFXMMU_LUT898L,GFXMMU LUT entry 898 low" hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC14 "GFXMMU_LUT898H,GFXMMU LUT entry 898 high" hexmask.long.tbyte 0xC14 4.--21. 1. "LO,Line offset" line.long 0xC18 "GFXMMU_LUT899L,GFXMMU LUT entry 899 low" hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC1C "GFXMMU_LUT899H,GFXMMU LUT entry 899 high" hexmask.long.tbyte 0xC1C 4.--21. 1. "LO,Line offset" line.long 0xC20 "GFXMMU_LUT900L,GFXMMU LUT entry 900 low" hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC24 "GFXMMU_LUT900H,GFXMMU LUT entry 900 high" hexmask.long.tbyte 0xC24 4.--21. 1. "LO,Line offset" line.long 0xC28 "GFXMMU_LUT901L,GFXMMU LUT entry 901 low" hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC2C "GFXMMU_LUT901H,GFXMMU LUT entry 901 high" hexmask.long.tbyte 0xC2C 4.--21. 1. "LO,Line offset" line.long 0xC30 "GFXMMU_LUT902L,GFXMMU LUT entry 902 low" hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC34 "GFXMMU_LUT902H,GFXMMU LUT entry 902 high" hexmask.long.tbyte 0xC34 4.--21. 1. "LO,Line offset" line.long 0xC38 "GFXMMU_LUT903L,GFXMMU LUT entry 903 low" hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC3C "GFXMMU_LUT903H,GFXMMU LUT entry 903 high" hexmask.long.tbyte 0xC3C 4.--21. 1. "LO,Line offset" line.long 0xC40 "GFXMMU_LUT904L,GFXMMU LUT entry 904 low" hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC44 "GFXMMU_LUT904H,GFXMMU LUT entry 904 high" hexmask.long.tbyte 0xC44 4.--21. 1. "LO,Line offset" line.long 0xC48 "GFXMMU_LUT905L,GFXMMU LUT entry 905 low" hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4C "GFXMMU_LUT905H,GFXMMU LUT entry 905 high" hexmask.long.tbyte 0xC4C 4.--21. 1. "LO,Line offset" line.long 0xC50 "GFXMMU_LUT906L,GFXMMU LUT entry 906 low" hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC54 "GFXMMU_LUT906H,GFXMMU LUT entry 906 high" hexmask.long.tbyte 0xC54 4.--21. 1. "LO,Line offset" line.long 0xC58 "GFXMMU_LUT907L,GFXMMU LUT entry 907 low" hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC5C "GFXMMU_LUT907H,GFXMMU LUT entry 907 high" hexmask.long.tbyte 0xC5C 4.--21. 1. "LO,Line offset" line.long 0xC60 "GFXMMU_LUT908L,GFXMMU LUT entry 908 low" hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC64 "GFXMMU_LUT908H,GFXMMU LUT entry 908 high" hexmask.long.tbyte 0xC64 4.--21. 1. "LO,Line offset" line.long 0xC68 "GFXMMU_LUT909L,GFXMMU LUT entry 909 low" hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC6C "GFXMMU_LUT909H,GFXMMU LUT entry 909 high" hexmask.long.tbyte 0xC6C 4.--21. 1. "LO,Line offset" line.long 0xC70 "GFXMMU_LUT910L,GFXMMU LUT entry 910 low" hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC74 "GFXMMU_LUT910H,GFXMMU LUT entry 910 high" hexmask.long.tbyte 0xC74 4.--21. 1. "LO,Line offset" line.long 0xC78 "GFXMMU_LUT911L,GFXMMU LUT entry 911 low" hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC7C "GFXMMU_LUT911H,GFXMMU LUT entry 911 high" hexmask.long.tbyte 0xC7C 4.--21. 1. "LO,Line offset" line.long 0xC80 "GFXMMU_LUT912L,GFXMMU LUT entry 912 low" hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC84 "GFXMMU_LUT912H,GFXMMU LUT entry 912 high" hexmask.long.tbyte 0xC84 4.--21. 1. "LO,Line offset" line.long 0xC88 "GFXMMU_LUT913L,GFXMMU LUT entry 913 low" hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC8C "GFXMMU_LUT913H,GFXMMU LUT entry 913 high" hexmask.long.tbyte 0xC8C 4.--21. 1. "LO,Line offset" line.long 0xC90 "GFXMMU_LUT914L,GFXMMU LUT entry 914 low" hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC94 "GFXMMU_LUT914H,GFXMMU LUT entry 914 high" hexmask.long.tbyte 0xC94 4.--21. 1. "LO,Line offset" line.long 0xC98 "GFXMMU_LUT915L,GFXMMU LUT entry 915 low" hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xC98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC9C "GFXMMU_LUT915H,GFXMMU LUT entry 915 high" hexmask.long.tbyte 0xC9C 4.--21. 1. "LO,Line offset" line.long 0xCA0 "GFXMMU_LUT916L,GFXMMU LUT entry 916 low" hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCA4 "GFXMMU_LUT916H,GFXMMU LUT entry 916 high" hexmask.long.tbyte 0xCA4 4.--21. 1. "LO,Line offset" line.long 0xCA8 "GFXMMU_LUT917L,GFXMMU LUT entry 917 low" hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCAC "GFXMMU_LUT917H,GFXMMU LUT entry 917 high" hexmask.long.tbyte 0xCAC 4.--21. 1. "LO,Line offset" line.long 0xCB0 "GFXMMU_LUT918L,GFXMMU LUT entry 918 low" hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCB4 "GFXMMU_LUT918H,GFXMMU LUT entry 918 high" hexmask.long.tbyte 0xCB4 4.--21. 1. "LO,Line offset" line.long 0xCB8 "GFXMMU_LUT919L,GFXMMU LUT entry 919 low" hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCBC "GFXMMU_LUT919H,GFXMMU LUT entry 919 high" hexmask.long.tbyte 0xCBC 4.--21. 1. "LO,Line offset" line.long 0xCC0 "GFXMMU_LUT920L,GFXMMU LUT entry 920 low" hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC4 "GFXMMU_LUT920H,GFXMMU LUT entry 920 high" hexmask.long.tbyte 0xCC4 4.--21. 1. "LO,Line offset" line.long 0xCC8 "GFXMMU_LUT921L,GFXMMU LUT entry 921 low" hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCCC "GFXMMU_LUT921H,GFXMMU LUT entry 921 high" hexmask.long.tbyte 0xCCC 4.--21. 1. "LO,Line offset" line.long 0xCD0 "GFXMMU_LUT922L,GFXMMU LUT entry 922 low" hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCD4 "GFXMMU_LUT922H,GFXMMU LUT entry 922 high" hexmask.long.tbyte 0xCD4 4.--21. 1. "LO,Line offset" line.long 0xCD8 "GFXMMU_LUT923L,GFXMMU LUT entry 923 low" hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCDC "GFXMMU_LUT923H,GFXMMU LUT entry 923 high" hexmask.long.tbyte 0xCDC 4.--21. 1. "LO,Line offset" line.long 0xCE0 "GFXMMU_LUT924L,GFXMMU LUT entry 924 low" hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCE4 "GFXMMU_LUT924H,GFXMMU LUT entry 924 high" hexmask.long.tbyte 0xCE4 4.--21. 1. "LO,Line offset" line.long 0xCE8 "GFXMMU_LUT925L,GFXMMU LUT entry 925 low" hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCEC "GFXMMU_LUT925H,GFXMMU LUT entry 925 high" hexmask.long.tbyte 0xCEC 4.--21. 1. "LO,Line offset" line.long 0xCF0 "GFXMMU_LUT926L,GFXMMU LUT entry 926 low" hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCF4 "GFXMMU_LUT926H,GFXMMU LUT entry 926 high" hexmask.long.tbyte 0xCF4 4.--21. 1. "LO,Line offset" line.long 0xCF8 "GFXMMU_LUT927L,GFXMMU LUT entry 927 low" hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCFC "GFXMMU_LUT927H,GFXMMU LUT entry 927 high" hexmask.long.tbyte 0xCFC 4.--21. 1. "LO,Line offset" line.long 0xD00 "GFXMMU_LUT928L,GFXMMU LUT entry 928 low" hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD04 "GFXMMU_LUT928H,GFXMMU LUT entry 928 high" hexmask.long.tbyte 0xD04 4.--21. 1. "LO,Line offset" line.long 0xD08 "GFXMMU_LUT929L,GFXMMU LUT entry 929 low" hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD0C "GFXMMU_LUT929H,GFXMMU LUT entry 929 high" hexmask.long.tbyte 0xD0C 4.--21. 1. "LO,Line offset" line.long 0xD10 "GFXMMU_LUT930L,GFXMMU LUT entry 930 low" hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD14 "GFXMMU_LUT930H,GFXMMU LUT entry 930 high" hexmask.long.tbyte 0xD14 4.--21. 1. "LO,Line offset" line.long 0xD18 "GFXMMU_LUT931L,GFXMMU LUT entry 931 low" hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD1C "GFXMMU_LUT931H,GFXMMU LUT entry 931 high" hexmask.long.tbyte 0xD1C 4.--21. 1. "LO,Line offset" line.long 0xD20 "GFXMMU_LUT932L,GFXMMU LUT entry 932 low" hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD24 "GFXMMU_LUT932H,GFXMMU LUT entry 932 high" hexmask.long.tbyte 0xD24 4.--21. 1. "LO,Line offset" line.long 0xD28 "GFXMMU_LUT933L,GFXMMU LUT entry 933 low" hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD2C "GFXMMU_LUT933H,GFXMMU LUT entry 933 high" hexmask.long.tbyte 0xD2C 4.--21. 1. "LO,Line offset" line.long 0xD30 "GFXMMU_LUT934L,GFXMMU LUT entry 934 low" hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD34 "GFXMMU_LUT934H,GFXMMU LUT entry 934 high" hexmask.long.tbyte 0xD34 4.--21. 1. "LO,Line offset" line.long 0xD38 "GFXMMU_LUT935L,GFXMMU LUT entry 935 low" hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD3C "GFXMMU_LUT935H,GFXMMU LUT entry 935 high" hexmask.long.tbyte 0xD3C 4.--21. 1. "LO,Line offset" line.long 0xD40 "GFXMMU_LUT936L,GFXMMU LUT entry 936 low" hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD44 "GFXMMU_LUT936H,GFXMMU LUT entry 936 high" hexmask.long.tbyte 0xD44 4.--21. 1. "LO,Line offset" line.long 0xD48 "GFXMMU_LUT937L,GFXMMU LUT entry 937 low" hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4C "GFXMMU_LUT937H,GFXMMU LUT entry 937 high" hexmask.long.tbyte 0xD4C 4.--21. 1. "LO,Line offset" line.long 0xD50 "GFXMMU_LUT938L,GFXMMU LUT entry 938 low" hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD54 "GFXMMU_LUT938H,GFXMMU LUT entry 938 high" hexmask.long.tbyte 0xD54 4.--21. 1. "LO,Line offset" line.long 0xD58 "GFXMMU_LUT939L,GFXMMU LUT entry 939 low" hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD5C "GFXMMU_LUT939H,GFXMMU LUT entry 939 high" hexmask.long.tbyte 0xD5C 4.--21. 1. "LO,Line offset" line.long 0xD60 "GFXMMU_LUT940L,GFXMMU LUT entry 940 low" hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD64 "GFXMMU_LUT940H,GFXMMU LUT entry 940 high" hexmask.long.tbyte 0xD64 4.--21. 1. "LO,Line offset" line.long 0xD68 "GFXMMU_LUT941L,GFXMMU LUT entry 941 low" hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD6C "GFXMMU_LUT941H,GFXMMU LUT entry 941 high" hexmask.long.tbyte 0xD6C 4.--21. 1. "LO,Line offset" line.long 0xD70 "GFXMMU_LUT942L,GFXMMU LUT entry 942 low" hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD74 "GFXMMU_LUT942H,GFXMMU LUT entry 942 high" hexmask.long.tbyte 0xD74 4.--21. 1. "LO,Line offset" line.long 0xD78 "GFXMMU_LUT943L,GFXMMU LUT entry 943 low" hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD7C "GFXMMU_LUT943H,GFXMMU LUT entry 943 high" hexmask.long.tbyte 0xD7C 4.--21. 1. "LO,Line offset" line.long 0xD80 "GFXMMU_LUT944L,GFXMMU LUT entry 944 low" hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD84 "GFXMMU_LUT944H,GFXMMU LUT entry 944 high" hexmask.long.tbyte 0xD84 4.--21. 1. "LO,Line offset" line.long 0xD88 "GFXMMU_LUT945L,GFXMMU LUT entry 945 low" hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD8C "GFXMMU_LUT945H,GFXMMU LUT entry 945 high" hexmask.long.tbyte 0xD8C 4.--21. 1. "LO,Line offset" line.long 0xD90 "GFXMMU_LUT946L,GFXMMU LUT entry 946 low" hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD94 "GFXMMU_LUT946H,GFXMMU LUT entry 946 high" hexmask.long.tbyte 0xD94 4.--21. 1. "LO,Line offset" line.long 0xD98 "GFXMMU_LUT947L,GFXMMU LUT entry 947 low" hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xD98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD9C "GFXMMU_LUT947H,GFXMMU LUT entry 947 high" hexmask.long.tbyte 0xD9C 4.--21. 1. "LO,Line offset" line.long 0xDA0 "GFXMMU_LUT948L,GFXMMU LUT entry 948 low" hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDA4 "GFXMMU_LUT948H,GFXMMU LUT entry 948 high" hexmask.long.tbyte 0xDA4 4.--21. 1. "LO,Line offset" line.long 0xDA8 "GFXMMU_LUT949L,GFXMMU LUT entry 949 low" hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDAC "GFXMMU_LUT949H,GFXMMU LUT entry 949 high" hexmask.long.tbyte 0xDAC 4.--21. 1. "LO,Line offset" line.long 0xDB0 "GFXMMU_LUT950L,GFXMMU LUT entry 950 low" hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDB4 "GFXMMU_LUT950H,GFXMMU LUT entry 950 high" hexmask.long.tbyte 0xDB4 4.--21. 1. "LO,Line offset" line.long 0xDB8 "GFXMMU_LUT951L,GFXMMU LUT entry 951 low" hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDBC "GFXMMU_LUT951H,GFXMMU LUT entry 951 high" hexmask.long.tbyte 0xDBC 4.--21. 1. "LO,Line offset" line.long 0xDC0 "GFXMMU_LUT952L,GFXMMU LUT entry 952 low" hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC4 "GFXMMU_LUT952H,GFXMMU LUT entry 952 high" hexmask.long.tbyte 0xDC4 4.--21. 1. "LO,Line offset" line.long 0xDC8 "GFXMMU_LUT953L,GFXMMU LUT entry 953 low" hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDCC "GFXMMU_LUT953H,GFXMMU LUT entry 953 high" hexmask.long.tbyte 0xDCC 4.--21. 1. "LO,Line offset" line.long 0xDD0 "GFXMMU_LUT954L,GFXMMU LUT entry 954 low" hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDD4 "GFXMMU_LUT954H,GFXMMU LUT entry 954 high" hexmask.long.tbyte 0xDD4 4.--21. 1. "LO,Line offset" line.long 0xDD8 "GFXMMU_LUT955L,GFXMMU LUT entry 955 low" hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDDC "GFXMMU_LUT955H,GFXMMU LUT entry 955 high" hexmask.long.tbyte 0xDDC 4.--21. 1. "LO,Line offset" line.long 0xDE0 "GFXMMU_LUT956L,GFXMMU LUT entry 956 low" hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDE4 "GFXMMU_LUT956H,GFXMMU LUT entry 956 high" hexmask.long.tbyte 0xDE4 4.--21. 1. "LO,Line offset" line.long 0xDE8 "GFXMMU_LUT957L,GFXMMU LUT entry 957 low" hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDEC "GFXMMU_LUT957H,GFXMMU LUT entry 957 high" hexmask.long.tbyte 0xDEC 4.--21. 1. "LO,Line offset" line.long 0xDF0 "GFXMMU_LUT958L,GFXMMU LUT entry 958 low" hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDF4 "GFXMMU_LUT958H,GFXMMU LUT entry 958 high" hexmask.long.tbyte 0xDF4 4.--21. 1. "LO,Line offset" line.long 0xDF8 "GFXMMU_LUT959L,GFXMMU LUT entry 959 low" hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDFC "GFXMMU_LUT959H,GFXMMU LUT entry 959 high" hexmask.long.tbyte 0xDFC 4.--21. 1. "LO,Line offset" line.long 0xE00 "GFXMMU_LUT960L,GFXMMU LUT entry 960 low" hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE04 "GFXMMU_LUT960H,GFXMMU LUT entry 960 high" hexmask.long.tbyte 0xE04 4.--21. 1. "LO,Line offset" line.long 0xE08 "GFXMMU_LUT961L,GFXMMU LUT entry 961 low" hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE0C "GFXMMU_LUT961H,GFXMMU LUT entry 961 high" hexmask.long.tbyte 0xE0C 4.--21. 1. "LO,Line offset" line.long 0xE10 "GFXMMU_LUT962L,GFXMMU LUT entry 962 low" hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE14 "GFXMMU_LUT962H,GFXMMU LUT entry 962 high" hexmask.long.tbyte 0xE14 4.--21. 1. "LO,Line offset" line.long 0xE18 "GFXMMU_LUT963L,GFXMMU LUT entry 963 low" hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE1C "GFXMMU_LUT963H,GFXMMU LUT entry 963 high" hexmask.long.tbyte 0xE1C 4.--21. 1. "LO,Line offset" line.long 0xE20 "GFXMMU_LUT964L,GFXMMU LUT entry 964 low" hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE24 "GFXMMU_LUT964H,GFXMMU LUT entry 964 high" hexmask.long.tbyte 0xE24 4.--21. 1. "LO,Line offset" line.long 0xE28 "GFXMMU_LUT965L,GFXMMU LUT entry 965 low" hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE2C "GFXMMU_LUT965H,GFXMMU LUT entry 965 high" hexmask.long.tbyte 0xE2C 4.--21. 1. "LO,Line offset" line.long 0xE30 "GFXMMU_LUT966L,GFXMMU LUT entry 966 low" hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE34 "GFXMMU_LUT966H,GFXMMU LUT entry 966 high" hexmask.long.tbyte 0xE34 4.--21. 1. "LO,Line offset" line.long 0xE38 "GFXMMU_LUT967L,GFXMMU LUT entry 967 low" hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE3C "GFXMMU_LUT967H,GFXMMU LUT entry 967 high" hexmask.long.tbyte 0xE3C 4.--21. 1. "LO,Line offset" line.long 0xE40 "GFXMMU_LUT968L,GFXMMU LUT entry 968 low" hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE44 "GFXMMU_LUT968H,GFXMMU LUT entry 968 high" hexmask.long.tbyte 0xE44 4.--21. 1. "LO,Line offset" line.long 0xE48 "GFXMMU_LUT969L,GFXMMU LUT entry 969 low" hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4C "GFXMMU_LUT969H,GFXMMU LUT entry 969 high" hexmask.long.tbyte 0xE4C 4.--21. 1. "LO,Line offset" line.long 0xE50 "GFXMMU_LUT970L,GFXMMU LUT entry 970 low" hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE54 "GFXMMU_LUT970H,GFXMMU LUT entry 970 high" hexmask.long.tbyte 0xE54 4.--21. 1. "LO,Line offset" line.long 0xE58 "GFXMMU_LUT971L,GFXMMU LUT entry 971 low" hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE5C "GFXMMU_LUT971H,GFXMMU LUT entry 971 high" hexmask.long.tbyte 0xE5C 4.--21. 1. "LO,Line offset" line.long 0xE60 "GFXMMU_LUT972L,GFXMMU LUT entry 972 low" hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE64 "GFXMMU_LUT972H,GFXMMU LUT entry 972 high" hexmask.long.tbyte 0xE64 4.--21. 1. "LO,Line offset" line.long 0xE68 "GFXMMU_LUT973L,GFXMMU LUT entry 973 low" hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE6C "GFXMMU_LUT973H,GFXMMU LUT entry 973 high" hexmask.long.tbyte 0xE6C 4.--21. 1. "LO,Line offset" line.long 0xE70 "GFXMMU_LUT974L,GFXMMU LUT entry 974 low" hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE74 "GFXMMU_LUT974H,GFXMMU LUT entry 974 high" hexmask.long.tbyte 0xE74 4.--21. 1. "LO,Line offset" line.long 0xE78 "GFXMMU_LUT975L,GFXMMU LUT entry 975 low" hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE7C "GFXMMU_LUT975H,GFXMMU LUT entry 975 high" hexmask.long.tbyte 0xE7C 4.--21. 1. "LO,Line offset" line.long 0xE80 "GFXMMU_LUT976L,GFXMMU LUT entry 976 low" hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE84 "GFXMMU_LUT976H,GFXMMU LUT entry 976 high" hexmask.long.tbyte 0xE84 4.--21. 1. "LO,Line offset" line.long 0xE88 "GFXMMU_LUT977L,GFXMMU LUT entry 977 low" hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE8C "GFXMMU_LUT977H,GFXMMU LUT entry 977 high" hexmask.long.tbyte 0xE8C 4.--21. 1. "LO,Line offset" line.long 0xE90 "GFXMMU_LUT978L,GFXMMU LUT entry 978 low" hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE94 "GFXMMU_LUT978H,GFXMMU LUT entry 978 high" hexmask.long.tbyte 0xE94 4.--21. 1. "LO,Line offset" line.long 0xE98 "GFXMMU_LUT979L,GFXMMU LUT entry 979 low" hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xE98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE9C "GFXMMU_LUT979H,GFXMMU LUT entry 979 high" hexmask.long.tbyte 0xE9C 4.--21. 1. "LO,Line offset" line.long 0xEA0 "GFXMMU_LUT980L,GFXMMU LUT entry 980 low" hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEA4 "GFXMMU_LUT980H,GFXMMU LUT entry 980 high" hexmask.long.tbyte 0xEA4 4.--21. 1. "LO,Line offset" line.long 0xEA8 "GFXMMU_LUT981L,GFXMMU LUT entry 981 low" hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEAC "GFXMMU_LUT981H,GFXMMU LUT entry 981 high" hexmask.long.tbyte 0xEAC 4.--21. 1. "LO,Line offset" line.long 0xEB0 "GFXMMU_LUT982L,GFXMMU LUT entry 982 low" hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEB4 "GFXMMU_LUT982H,GFXMMU LUT entry 982 high" hexmask.long.tbyte 0xEB4 4.--21. 1. "LO,Line offset" line.long 0xEB8 "GFXMMU_LUT983L,GFXMMU LUT entry 983 low" hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEBC "GFXMMU_LUT983H,GFXMMU LUT entry 983 high" hexmask.long.tbyte 0xEBC 4.--21. 1. "LO,Line offset" line.long 0xEC0 "GFXMMU_LUT984L,GFXMMU LUT entry 984 low" hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC4 "GFXMMU_LUT984H,GFXMMU LUT entry 984 high" hexmask.long.tbyte 0xEC4 4.--21. 1. "LO,Line offset" line.long 0xEC8 "GFXMMU_LUT985L,GFXMMU LUT entry 985 low" hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xECC "GFXMMU_LUT985H,GFXMMU LUT entry 985 high" hexmask.long.tbyte 0xECC 4.--21. 1. "LO,Line offset" line.long 0xED0 "GFXMMU_LUT986L,GFXMMU LUT entry 986 low" hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xED0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xED4 "GFXMMU_LUT986H,GFXMMU LUT entry 986 high" hexmask.long.tbyte 0xED4 4.--21. 1. "LO,Line offset" line.long 0xED8 "GFXMMU_LUT987L,GFXMMU LUT entry 987 low" hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xED8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEDC "GFXMMU_LUT987H,GFXMMU LUT entry 987 high" hexmask.long.tbyte 0xEDC 4.--21. 1. "LO,Line offset" line.long 0xEE0 "GFXMMU_LUT988L,GFXMMU LUT entry 988 low" hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEE4 "GFXMMU_LUT988H,GFXMMU LUT entry 988 high" hexmask.long.tbyte 0xEE4 4.--21. 1. "LO,Line offset" line.long 0xEE8 "GFXMMU_LUT989L,GFXMMU LUT entry 989 low" hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEEC "GFXMMU_LUT989H,GFXMMU LUT entry 989 high" hexmask.long.tbyte 0xEEC 4.--21. 1. "LO,Line offset" line.long 0xEF0 "GFXMMU_LUT990L,GFXMMU LUT entry 990 low" hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEF4 "GFXMMU_LUT990H,GFXMMU LUT entry 990 high" hexmask.long.tbyte 0xEF4 4.--21. 1. "LO,Line offset" line.long 0xEF8 "GFXMMU_LUT991L,GFXMMU LUT entry 991 low" hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEFC "GFXMMU_LUT991H,GFXMMU LUT entry 991 high" hexmask.long.tbyte 0xEFC 4.--21. 1. "LO,Line offset" line.long 0xF00 "GFXMMU_LUT992L,GFXMMU LUT entry 992 low" hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF00 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF04 "GFXMMU_LUT992H,GFXMMU LUT entry 992 high" hexmask.long.tbyte 0xF04 4.--21. 1. "LO,Line offset" line.long 0xF08 "GFXMMU_LUT993L,GFXMMU LUT entry 993 low" hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF08 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF0C "GFXMMU_LUT993H,GFXMMU LUT entry 993 high" hexmask.long.tbyte 0xF0C 4.--21. 1. "LO,Line offset" line.long 0xF10 "GFXMMU_LUT994L,GFXMMU LUT entry 994 low" hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF10 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF14 "GFXMMU_LUT994H,GFXMMU LUT entry 994 high" hexmask.long.tbyte 0xF14 4.--21. 1. "LO,Line offset" line.long 0xF18 "GFXMMU_LUT995L,GFXMMU LUT entry 995 low" hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF18 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF1C "GFXMMU_LUT995H,GFXMMU LUT entry 995 high" hexmask.long.tbyte 0xF1C 4.--21. 1. "LO,Line offset" line.long 0xF20 "GFXMMU_LUT996L,GFXMMU LUT entry 996 low" hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF20 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF24 "GFXMMU_LUT996H,GFXMMU LUT entry 996 high" hexmask.long.tbyte 0xF24 4.--21. 1. "LO,Line offset" line.long 0xF28 "GFXMMU_LUT997L,GFXMMU LUT entry 997 low" hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF28 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF2C "GFXMMU_LUT997H,GFXMMU LUT entry 997 high" hexmask.long.tbyte 0xF2C 4.--21. 1. "LO,Line offset" line.long 0xF30 "GFXMMU_LUT998L,GFXMMU LUT entry 998 low" hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF30 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF34 "GFXMMU_LUT998H,GFXMMU LUT entry 998 high" hexmask.long.tbyte 0xF34 4.--21. 1. "LO,Line offset" line.long 0xF38 "GFXMMU_LUT999L,GFXMMU LUT entry 999 low" hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF38 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF3C "GFXMMU_LUT999H,GFXMMU LUT entry 999 high" hexmask.long.tbyte 0xF3C 4.--21. 1. "LO,Line offset" line.long 0xF40 "GFXMMU_LUT1000L,GFXMMU LUT entry 1000 low" hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF40 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF44 "GFXMMU_LUT1000H,GFXMMU LUT entry 1000 high" hexmask.long.tbyte 0xF44 4.--21. 1. "LO,Line offset" line.long 0xF48 "GFXMMU_LUT1001L,GFXMMU LUT entry 1001 low" hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF48 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4C "GFXMMU_LUT1001H,GFXMMU LUT entry 1001 high" hexmask.long.tbyte 0xF4C 4.--21. 1. "LO,Line offset" line.long 0xF50 "GFXMMU_LUT1002L,GFXMMU LUT entry 1002 low" hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF50 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF54 "GFXMMU_LUT1002H,GFXMMU LUT entry 1002 high" hexmask.long.tbyte 0xF54 4.--21. 1. "LO,Line offset" line.long 0xF58 "GFXMMU_LUT1003L,GFXMMU LUT entry 1003 low" hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF58 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF5C "GFXMMU_LUT1003H,GFXMMU LUT entry 1003 high" hexmask.long.tbyte 0xF5C 4.--21. 1. "LO,Line offset" line.long 0xF60 "GFXMMU_LUT1004L,GFXMMU LUT entry 1004 low" hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF60 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF64 "GFXMMU_LUT1004H,GFXMMU LUT entry 1004 high" hexmask.long.tbyte 0xF64 4.--21. 1. "LO,Line offset" line.long 0xF68 "GFXMMU_LUT1005L,GFXMMU LUT entry 1005 low" hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF68 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF6C "GFXMMU_LUT1005H,GFXMMU LUT entry 1005 high" hexmask.long.tbyte 0xF6C 4.--21. 1. "LO,Line offset" line.long 0xF70 "GFXMMU_LUT1006L,GFXMMU LUT entry 1006 low" hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF70 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF74 "GFXMMU_LUT1006H,GFXMMU LUT entry 1006 high" hexmask.long.tbyte 0xF74 4.--21. 1. "LO,Line offset" line.long 0xF78 "GFXMMU_LUT1007L,GFXMMU LUT entry 1007 low" hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF78 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF7C "GFXMMU_LUT1007H,GFXMMU LUT entry 1007 high" hexmask.long.tbyte 0xF7C 4.--21. 1. "LO,Line offset" line.long 0xF80 "GFXMMU_LUT1008L,GFXMMU LUT entry 1008 low" hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF80 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF84 "GFXMMU_LUT1008H,GFXMMU LUT entry 1008 high" hexmask.long.tbyte 0xF84 4.--21. 1. "LO,Line offset" line.long 0xF88 "GFXMMU_LUT1009L,GFXMMU LUT entry 1009 low" hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF88 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF8C "GFXMMU_LUT1009H,GFXMMU LUT entry 1009 high" hexmask.long.tbyte 0xF8C 4.--21. 1. "LO,Line offset" line.long 0xF90 "GFXMMU_LUT1010L,GFXMMU LUT entry 1010 low" hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF90 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF94 "GFXMMU_LUT1010H,GFXMMU LUT entry 1010 high" hexmask.long.tbyte 0xF94 4.--21. 1. "LO,Line offset" line.long 0xF98 "GFXMMU_LUT1011L,GFXMMU LUT entry 1011 low" hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xF98 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF9C "GFXMMU_LUT1011H,GFXMMU LUT entry 1011 high" hexmask.long.tbyte 0xF9C 4.--21. 1. "LO,Line offset" line.long 0xFA0 "GFXMMU_LUT1012L,GFXMMU LUT entry 1012 low" hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFA4 "GFXMMU_LUT1012H,GFXMMU LUT entry 1012 high" hexmask.long.tbyte 0xFA4 4.--21. 1. "LO,Line offset" line.long 0xFA8 "GFXMMU_LUT1013L,GFXMMU LUT entry 1013 low" hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFAC "GFXMMU_LUT1013H,GFXMMU LUT entry 1013 high" hexmask.long.tbyte 0xFAC 4.--21. 1. "LO,Line offset" line.long 0xFB0 "GFXMMU_LUT1014L,GFXMMU LUT entry 1014 low" hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFB4 "GFXMMU_LUT1014H,GFXMMU LUT entry 1014 high" hexmask.long.tbyte 0xFB4 4.--21. 1. "LO,Line offset" line.long 0xFB8 "GFXMMU_LUT1015L,GFXMMU LUT entry 1015 low" hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFBC "GFXMMU_LUT1015H,GFXMMU LUT entry 1015 high" hexmask.long.tbyte 0xFBC 4.--21. 1. "LO,Line offset" line.long 0xFC0 "GFXMMU_LUT1016L,GFXMMU LUT entry 1016 low" hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC4 "GFXMMU_LUT1016H,GFXMMU LUT entry 1016 high" hexmask.long.tbyte 0xFC4 4.--21. 1. "LO,Line offset" line.long 0xFC8 "GFXMMU_LUT1017L,GFXMMU LUT entry 1017 low" hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFCC "GFXMMU_LUT1017H,GFXMMU LUT entry 1017 high" hexmask.long.tbyte 0xFCC 4.--21. 1. "LO,Line offset" line.long 0xFD0 "GFXMMU_LUT1018L,GFXMMU LUT entry 1018 low" hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFD4 "GFXMMU_LUT1018H,GFXMMU LUT entry 1018 high" hexmask.long.tbyte 0xFD4 4.--21. 1. "LO,Line offset" line.long 0xFD8 "GFXMMU_LUT1019L,GFXMMU LUT entry 1019 low" hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFDC "GFXMMU_LUT1019H,GFXMMU LUT entry 1019 high" hexmask.long.tbyte 0xFDC 4.--21. 1. "LO,Line offset" line.long 0xFE0 "GFXMMU_LUT1020L,GFXMMU LUT entry 1020 low" hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFE4 "GFXMMU_LUT1020H,GFXMMU LUT entry 1020 high" hexmask.long.tbyte 0xFE4 4.--21. 1. "LO,Line offset" line.long 0xFE8 "GFXMMU_LUT1021L,GFXMMU LUT entry 1021 low" hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFEC "GFXMMU_LUT1021H,GFXMMU LUT entry 1021 high" hexmask.long.tbyte 0xFEC 4.--21. 1. "LO,Line offset" line.long 0xFF0 "GFXMMU_LUT1022L,GFXMMU LUT entry 1022 low" hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFF4 "GFXMMU_LUT1022H,GFXMMU LUT entry 1022 high" hexmask.long.tbyte 0xFF4 4.--21. 1. "LO,Line offset" line.long 0xFF8 "GFXMMU_LUT1023L,GFXMMU LUT entry 1023 low" hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last Valid Block" hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First Valid Block" newline bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFFC "GFXMMU_LUT1023H,GFXMMU LUT entry 1023 high" hexmask.long.tbyte 0xFFC 4.--21. 1. "LO,Line offset" tree.end tree.end endif sif (cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "GFXTIM (Graphic Timer)" base ad:0x0 tree "GFXTIM" base ad:0x40016400 group.long 0x0++0xB line.long 0x0 "GFXTIM_CR,GFXTIM configuration register" bitfld.long 0x0 17. "LCCOE,line-clock calibration output enable" "0: line-clock output disabled,1: line-clock output enabled" bitfld.long 0x0 16. "FCCOE,frame-clock calibration output enable" "0: frame-clock output disabled,1: frame-clock output enabled" newline bitfld.long 0x0 8.--9. "SYNCS,synchronization source" "0: gfxtim_hsync[0] and gfxtim_vsync[0] selected,1: gfxtim_hsync[1] and gfxtim_vsync[1] selected,2: gfxtim_hsync[2] and gfxtim_vsync[2] selected,3: gfxtim_hsync[3] and gfxtim_vsync[3] selected" bitfld.long 0x0 4. "TEPOL,tearing--effect polarity" "0: tearing effect active on rising edge,1: tearing effect active on falling edge" newline bitfld.long 0x0 0.--1. "TES,tearing source" "0: TE input pad selected,1: gfxtim_ite selected,2: HSYNC input selected by SYNCS[1:0],3: VSYNC input selected by SYNCS[1:0]" line.long 0x4 "GFXTIM_CGCR,GFXTIM clock generator configuration register" bitfld.long 0x4 28.--30. "FCCHRS,frame- -clock counter hardware reload source" "0: no hardware reload,1: line- -clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 24. "FCCFR,frame clock counter force reload" "0: No effect,1: frame clock counter reload forced" newline bitfld.long 0x4 20.--22. "FCCCS,frame clock counter clock source" "0: frame clock counter disabled,1: line clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 16.--18. "FCS,frame clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" newline bitfld.long 0x4 12.--14. "LCCHRS,line clock counter hardware reload source" "0: no hardware reload,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 8. "LCCFR,line clock counter force reload" "0: no effect,1: line clock counter reload forced" newline bitfld.long 0x4 4. "LCCCS,line clock counter clock source" "0: line clock counter disabled,1: system clock selected" bitfld.long 0x4 0.--2. "LCS,line clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" line.long 0x8 "GFXTIM_TCR,GFXTIM timers configuration register" bitfld.long 0x8 22. "FRFC2R,force relative frame counter 2 reload" "0: no effect,1: relative frame counter 2 reload forced" bitfld.long 0x8 21. "RFC2CM,relative frame counter 2 continuous mode" "0: relative frame counter 2 is one shot.,1: relative frame counter 2 is in continuous mode." newline bitfld.long 0x8 20. "RFC2EN,relative frame counter 2 enable" "0: no effect,1: relative frame counter 2 enabled" bitfld.long 0x8 18. "FRFC1R,force relative frame counter 1 reload" "0: no effect,1: relative frame counter 1 reload forced" newline bitfld.long 0x8 17. "RFC1CM,relative frame counter 1 continuous mode" "0: relative frame counter 1 is one shot.,1: relative frame counter 1 is in continuous mode." bitfld.long 0x8 16. "RFC1EN,relative frame counter 1 enable" "0: no effect,1: relative frame counter enabled" newline bitfld.long 0x8 5. "FALCR,force absolute line counter reset" "0: no effect,1: absolute line counter reset forced" bitfld.long 0x8 4. "ALCEN,absolute line counter enable" "0: no effect,1: absolute line counter enabled" newline bitfld.long 0x8 1. "FAFCR,force absolute frame counter reset" "0: no effect,1: absolute frame counter reset forced" bitfld.long 0x8 0. "AFCEN,absolute frame counter enable" "0: no effect,1: absolute frame counter enabled" wgroup.long 0xC++0x3 line.long 0x0 "GFXTIM_TDR,GFXTIM timers disable register" bitfld.long 0x0 20. "RFC2DIS,relative frame counter 2 disable" "0: no effect,1: relative frame counter 2 disabled" bitfld.long 0x0 16. "RFC1DIS,relative frame counter 1 disable" "0: no effect,1: relative frame counter 1 disabled" newline bitfld.long 0x0 4. "ALCDIS,absolute line counter disable" "0: no effect,1: absolute line counter disabled" bitfld.long 0x0 0. "AFCDIS,absolute frame counter disable" "0: no effect,1: absolute frame counter disabled" group.long 0x10++0x7 line.long 0x0 "GFXTIM_EVCR,GFXTIM events control register" bitfld.long 0x0 3. "EV4EN,event 4 enable" "0: event 4 generation disabled,1: event 4 generation enabled" bitfld.long 0x0 2. "EV3EN,event 3 enable" "0: event 3 generation disabled,1: event 3 generation enabled" newline bitfld.long 0x0 1. "EV2EN,event 2 enable" "0: event 2 generation disabled,1: event 2 generation enabled" bitfld.long 0x0 0. "EV1EN,event 1 enable" "0: event 1 generation disabled,1: event 1 generation enabled" line.long 0x4 "GFXTIM_EVSR,GFXTIM events selection register" bitfld.long 0x4 28.--30. "FES4,frame-event selection 4" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 24.--26. "LES4,line-event selection 4" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 20.--22. "FES3,frame-event selection 3" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 16.--18. "LES3,line-event selection 3" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 12.--14. "FES2,frame-event selection 2" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 8.--10. "LES2,line-event selection 2" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 4.--6. "FES1,frame-event selection 1" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 0.--2. "LES1,line-event selection 1" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" group.long 0x20++0x3 line.long 0x0 "GFXTIM_WDGTCR,GFXTIM watchdog timer configuration register" bitfld.long 0x0 16. "FWDGR,force watchdog reload" "0: no effect,1: graphic watchdog reload forced" hexmask.long.byte 0x0 8.--11. 1. "WDGCS,watchdog clock source" newline bitfld.long 0x0 4.--5. "WDGHRC,watchdog hardware reload configuration" "0: watchdog hardware reload disabled,1: watchdog reloaded a rising edge of gfxtim_wrld,2: watchdog reloaded a falling edge of gfxtim_wrld,3: reserved" rbitfld.long 0x0 2. "WDGS,watchdog status" "0: graphic watchdog disabled,1: graphic watchdog enabled" newline bitfld.long 0x0 1. "WDGDIS,watchdog disable" "0: no effect,1: graphic watchdog disabled" bitfld.long 0x0 0. "WDGEN,watchdog enable" "0: no effect,1: graphic watchdog enabled" rgroup.long 0x30++0x3 line.long 0x0 "GFXTIM_ISR,GFXTIM interrupt status register" bitfld.long 0x0 25. "WDGPF,watchdog pre-alarm flag" "0: no graphic watchdog pre-alarm occurred.,1: a graphic watchdog pre-alarm occurred." bitfld.long 0x0 24. "WDGAF,watchdog alarm flag" "0: no graphic watchdog alarm occurred.,1: a graphic watchdog alarm occurred." newline bitfld.long 0x0 19. "EV4F,event 4 flag" "0: no complex event 4 occurred.,1: a complex event 4 occurred." bitfld.long 0x0 18. "EV3F,event 3 flag" "0: no complex event 3 occurred.,1: a complex event 3 occurred." newline bitfld.long 0x0 17. "EV2F,event 2 flag" "0: no complex event 2 occurred.,1: a complex event 2 occurred." bitfld.long 0x0 16. "EV1F,event 1 flag" "0: No complex event 1 occurred.,1: Complex event 1 occurred." newline bitfld.long 0x0 13. "RFC2RF,relative frame counter 2 reload flag" "0: no reload occurred on relative frame counter 2.,1: a reload on relative frame counter 2 occurred." bitfld.long 0x0 12. "RFC1RF,relative frame counter 1 reload flag" "0: no reload occurred on relative frame counter 1.,1: a reload on relative frame counter 1 occurred." newline bitfld.long 0x0 9. "ALCC2F,absolute line counter compare 2 flag" "0: no match occurred on compare 2 of the absolute..,1: a match on compare 2 of the absolute line.." bitfld.long 0x0 8. "ALCC1F,absolute line counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute line.." newline bitfld.long 0x0 4. "AFCC1F,absolute frame counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute frame.." bitfld.long 0x0 2. "TEF,tearing-effect flag" "0: no tearing effect occurred.,1: a tearing effect occurred." newline bitfld.long 0x0 1. "ALCOF,absolute line counter overflow flag" "0: no overflow occurred on the absolute line counter.,1: a overflow on the absolute line counter occurred." bitfld.long 0x0 0. "AFCOF,absolute frame counter overflow flag" "0: no overflow occurred on the absolute frame..,1: a overflow on the absolute frame counter occurred." wgroup.long 0x34++0x3 line.long 0x0 "GFXTIM_ICR,GFXTIM interrupt clear register" bitfld.long 0x0 25. "CWDGPF,clear watchdog pre-alarm flag" "0: no effect,1: WDGPF cleared" bitfld.long 0x0 24. "CWDGAF,clear watchdog alarm flag" "0: no effect,1: WDGAF cleared" newline bitfld.long 0x0 19. "CEV4F,clear event 4 flag" "0: no effect,1: EV4F cleared" bitfld.long 0x0 18. "CEV3F,clear event 3 flag" "0: no effect,1: EV3F cleared" newline bitfld.long 0x0 17. "CEV2F,clear event 2 flag" "0: no effect,1: EV2F cleared" bitfld.long 0x0 16. "CEV1F,clear event 1 flag" "0: no effect,1: EV1F cleared" newline bitfld.long 0x0 13. "CRFC2RF,clear relative frame counter 2 reload flag" "0: no effect,1: RFC2RF cleared" bitfld.long 0x0 12. "CRFC1RF,clear relative frame counter 1 reload flag" "0: no effect,1: RFC1RF cleared" newline bitfld.long 0x0 9. "CALCC2F,clear absolute line counter compare 2 flag" "0: no effect,1: ALCC2F cleared" bitfld.long 0x0 8. "CALCC1F,clear absolute line counter compare 1 flag" "0: no effect,1: ALCC1F cleared" newline bitfld.long 0x0 4. "CAFCC1F,clear absolute frame counter compare 1 flag" "0: no effect,1: AFCC1F cleared" bitfld.long 0x0 2. "CTEF,clear tearing-effect flag" "0: no effect,1: TEF cleared" newline bitfld.long 0x0 1. "CALCOF,clear absolute line counter overflow flag" "0: no effect,1: ALCOF cleared" bitfld.long 0x0 0. "CAFCOF,clear absolute frame counter overflow flag" "0: no effect,1: AFCOF cleared" group.long 0x38++0x3 line.long 0x0 "GFXTIM_IER,GFXTIM interrupt enable register" bitfld.long 0x0 25. "WDGPIE,watchdog pre-alarm interrupt enable" "0: watchdog pre-alarm interrupt disabled,1: watchdog pre-alarm interrupt enabled" bitfld.long 0x0 24. "WDGAIE,watchdog alarm interrupt enable" "0: watchdog alarm interrupt disabled,1: watchdog alarm interrupt enabled" newline bitfld.long 0x0 19. "EV4IE,event 4 interrupt enable" "0: event 4 interrupt disabled,1: event 4 interrupt enabled" bitfld.long 0x0 18. "EV3IE,event 3 interrupt enable" "0: event 3 interrupt disabled,1: event 3 interrupt enabled" newline bitfld.long 0x0 17. "EV2IE,event 2 interrupt enable" "0: event 2 interrupt disabled,1: event 2 interrupt enabled" bitfld.long 0x0 16. "EV1IE,event 1 interrupt enable" "0: event 1 interrupt disabled,1: event 1 interrupt enabled" newline bitfld.long 0x0 13. "RFC2RIE,relative frame counter 2 reload interrupt enable" "0: relative frame counter 2 reload interrupt disabled,1: relative frame counter 2 reload interrupt enabled" bitfld.long 0x0 12. "RFC1RIE,relative frame counter 1 reload interrupt enable" "0: relative frame counter 1 reload interrupt disabled,1: relative frame counter 1 reload interrupt enabled" newline bitfld.long 0x0 9. "ALCC2IE,absolute line counter compare 2 interrupt enable" "0: absolute line counter compare 2 interrupt disabled,1: absolute line counter compare 2 interrupt enabled" bitfld.long 0x0 8. "ALCC1IE,absolute line counter compare 1 interrupt enable" "0: absolute line counter compare 1 interrupt disabled,1: absolute line counter compare 1 interrupt enabled" newline bitfld.long 0x0 4. "AFCC1IE,absolute frame counter compare 1 interrupt enable" "0: absolute frame counter compare 1 interrupt..,1: absolute frame counter compare 1 interrupt enabled" bitfld.long 0x0 2. "TEIE,tearing-effect interrupt enable" "0: tearing-effect interrupt disabled,1: tearing-effect interrupt enabled" newline bitfld.long 0x0 1. "ALCOIE,absolute line counter overflow interrupt enable" "0: absolute line counter overflow interrupt disabled,1: absolute line counter overflow interrupt enabled" bitfld.long 0x0 0. "AFCOIE,absolute frame counter overflow interrupt enable" "0: absolute frame counter overflow interrupt disabled,1: absolute frame counter overflow interrupt enabled" rgroup.long 0x3C++0x3 line.long 0x0 "GFXTIM_TSR,GFXTIM timers status register" bitfld.long 0x0 20. "RFC2S,relative frame counter 2 status" "0: relative frame counter 2 disabled,1: relative frame counter 2 enabled" bitfld.long 0x0 16. "RFC1S,relative frame counter 1 status" "0: relative frame counter 1 disabled,1: relative frame counter 1 enabled" newline bitfld.long 0x0 4. "ALCS,absolute line counter status" "0: absolute line counter disabled,1: absolute line counter enabled" bitfld.long 0x0 0. "AFCS,absolute frame counter status" "0: absolute frame counter disabled,1: absolute frame counter enabled" group.long 0x40++0x7 line.long 0x0 "GFXTIM_LCCRR,GFXTIM line clock counter reload register" hexmask.long.tbyte 0x0 0.--21. 1. "RELOAD,reload value" line.long 0x4 "GFXTIM_FCCRR,GFXTIM frame clock counter reload register" hexmask.long.word 0x4 0.--11. 1. "RELOAD,reload value" rgroup.long 0x50++0x3 line.long 0x0 "GFXTIM_ATR,GFXTIM absolute time register" hexmask.long.tbyte 0x0 12.--31. 1. "FRAME,fame number" hexmask.long.word 0x0 0.--11. 1. "LINE,line number" group.long 0x54++0x7 line.long 0x0 "GFXTIM_AFCR,GFXTIM absolute frame counter register" hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number" line.long 0x4 "GFXTIM_ALCR,GFXTIM absolute line counter register" hexmask.long.word 0x4 0.--11. 1. "LINE,line number" group.long 0x60++0x3 line.long 0x0 "GFXTIM_AFCC1R,GFXTIM absolute frame counter compare 1 register" hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number" group.long 0x70++0x7 line.long 0x0 "GFXTIM_ALCC1R,GFXTIM absolute line counter compare 1 register" hexmask.long.word 0x0 0.--11. 1. "LINE,line number" line.long 0x4 "GFXTIM_ALCC2R,GFXTIM absolute line counter compare 2 register" hexmask.long.word 0x4 0.--11. 1. "LINE,line number" rgroup.long 0x80++0x3 line.long 0x0 "GFXTIM_RFC1R,GFXTIM relative frame counter 1 register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number" group.long 0x84++0x3 line.long 0x0 "GFXTIM_RFC1RR,GFXTIM relative frame counter 1 reload register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value" rgroup.long 0x88++0x3 line.long 0x0 "GFXTIM_RFC2R,GFXTIM relative frame counter 2 register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number" group.long 0x8C++0x3 line.long 0x0 "GFXTIM_RFC2RR,GFXTIM relative frame counter 2 reload register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value" rgroup.long 0xA0++0x3 line.long 0x0 "GFXTIM_WDGCR,GFXTIM watchdog counter register" hexmask.long.word 0x0 0.--15. 1. "VALUE,value" group.long 0xA4++0x7 line.long 0x0 "GFXTIM_WDGRR,GFXTIM watchdog reload register" hexmask.long.word 0x0 0.--15. 1. "RELOAD,reload value" line.long 0x4 "GFXTIM_WDGPAR,GFXTIM watchdog pre-alarm register" hexmask.long.word 0x4 0.--15. 1. "PREALARM,pre-alarm value" tree.end tree "SEC_GFXTIM" base ad:0x50016400 group.long 0x0++0xB line.long 0x0 "GFXTIM_CR,GFXTIM configuration register" bitfld.long 0x0 17. "LCCOE,line-clock calibration output enable" "0: line-clock output disabled,1: line-clock output enabled" bitfld.long 0x0 16. "FCCOE,frame-clock calibration output enable" "0: frame-clock output disabled,1: frame-clock output enabled" newline bitfld.long 0x0 8.--9. "SYNCS,synchronization source" "0: gfxtim_hsync[0] and gfxtim_vsync[0] selected,1: gfxtim_hsync[1] and gfxtim_vsync[1] selected,2: gfxtim_hsync[2] and gfxtim_vsync[2] selected,3: gfxtim_hsync[3] and gfxtim_vsync[3] selected" bitfld.long 0x0 4. "TEPOL,tearing--effect polarity" "0: tearing effect active on rising edge,1: tearing effect active on falling edge" newline bitfld.long 0x0 0.--1. "TES,tearing source" "0: TE input pad selected,1: gfxtim_ite selected,2: HSYNC input selected by SYNCS[1:0],3: VSYNC input selected by SYNCS[1:0]" line.long 0x4 "GFXTIM_CGCR,GFXTIM clock generator configuration register" bitfld.long 0x4 28.--30. "FCCHRS,frame- -clock counter hardware reload source" "0: no hardware reload,1: line- -clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 24. "FCCFR,frame clock counter force reload" "0: No effect,1: frame clock counter reload forced" newline bitfld.long 0x4 20.--22. "FCCCS,frame clock counter clock source" "0: frame clock counter disabled,1: line clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 16.--18. "FCS,frame clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" newline bitfld.long 0x4 12.--14. "LCCHRS,line clock counter hardware reload source" "0: no hardware reload,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 8. "LCCFR,line clock counter force reload" "0: no effect,1: line clock counter reload forced" newline bitfld.long 0x4 4. "LCCCS,line clock counter clock source" "0: line clock counter disabled,1: system clock selected" bitfld.long 0x4 0.--2. "LCS,line clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" line.long 0x8 "GFXTIM_TCR,GFXTIM timers configuration register" bitfld.long 0x8 22. "FRFC2R,force relative frame counter 2 reload" "0: no effect,1: relative frame counter 2 reload forced" bitfld.long 0x8 21. "RFC2CM,relative frame counter 2 continuous mode" "0: relative frame counter 2 is one shot.,1: relative frame counter 2 is in continuous mode." newline bitfld.long 0x8 20. "RFC2EN,relative frame counter 2 enable" "0: no effect,1: relative frame counter 2 enabled" bitfld.long 0x8 18. "FRFC1R,force relative frame counter 1 reload" "0: no effect,1: relative frame counter 1 reload forced" newline bitfld.long 0x8 17. "RFC1CM,relative frame counter 1 continuous mode" "0: relative frame counter 1 is one shot.,1: relative frame counter 1 is in continuous mode." bitfld.long 0x8 16. "RFC1EN,relative frame counter 1 enable" "0: no effect,1: relative frame counter enabled" newline bitfld.long 0x8 5. "FALCR,force absolute line counter reset" "0: no effect,1: absolute line counter reset forced" bitfld.long 0x8 4. "ALCEN,absolute line counter enable" "0: no effect,1: absolute line counter enabled" newline bitfld.long 0x8 1. "FAFCR,force absolute frame counter reset" "0: no effect,1: absolute frame counter reset forced" bitfld.long 0x8 0. "AFCEN,absolute frame counter enable" "0: no effect,1: absolute frame counter enabled" wgroup.long 0xC++0x3 line.long 0x0 "GFXTIM_TDR,GFXTIM timers disable register" bitfld.long 0x0 20. "RFC2DIS,relative frame counter 2 disable" "0: no effect,1: relative frame counter 2 disabled" bitfld.long 0x0 16. "RFC1DIS,relative frame counter 1 disable" "0: no effect,1: relative frame counter 1 disabled" newline bitfld.long 0x0 4. "ALCDIS,absolute line counter disable" "0: no effect,1: absolute line counter disabled" bitfld.long 0x0 0. "AFCDIS,absolute frame counter disable" "0: no effect,1: absolute frame counter disabled" group.long 0x10++0x7 line.long 0x0 "GFXTIM_EVCR,GFXTIM events control register" bitfld.long 0x0 3. "EV4EN,event 4 enable" "0: event 4 generation disabled,1: event 4 generation enabled" bitfld.long 0x0 2. "EV3EN,event 3 enable" "0: event 3 generation disabled,1: event 3 generation enabled" newline bitfld.long 0x0 1. "EV2EN,event 2 enable" "0: event 2 generation disabled,1: event 2 generation enabled" bitfld.long 0x0 0. "EV1EN,event 1 enable" "0: event 1 generation disabled,1: event 1 generation enabled" line.long 0x4 "GFXTIM_EVSR,GFXTIM events selection register" bitfld.long 0x4 28.--30. "FES4,frame-event selection 4" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 24.--26. "LES4,line-event selection 4" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 20.--22. "FES3,frame-event selection 3" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 16.--18. "LES3,line-event selection 3" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 12.--14. "FES2,frame-event selection 2" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 8.--10. "LES2,line-event selection 2" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 4.--6. "FES1,frame-event selection 1" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 0.--2. "LES1,line-event selection 1" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" group.long 0x20++0x3 line.long 0x0 "GFXTIM_WDGTCR,GFXTIM watchdog timer configuration register" bitfld.long 0x0 16. "FWDGR,force watchdog reload" "0: no effect,1: graphic watchdog reload forced" hexmask.long.byte 0x0 8.--11. 1. "WDGCS,watchdog clock source" newline bitfld.long 0x0 4.--5. "WDGHRC,watchdog hardware reload configuration" "0: watchdog hardware reload disabled,1: watchdog reloaded a rising edge of gfxtim_wrld,2: watchdog reloaded a falling edge of gfxtim_wrld,3: reserved" rbitfld.long 0x0 2. "WDGS,watchdog status" "0: graphic watchdog disabled,1: graphic watchdog enabled" newline bitfld.long 0x0 1. "WDGDIS,watchdog disable" "0: no effect,1: graphic watchdog disabled" bitfld.long 0x0 0. "WDGEN,watchdog enable" "0: no effect,1: graphic watchdog enabled" rgroup.long 0x30++0x3 line.long 0x0 "GFXTIM_ISR,GFXTIM interrupt status register" bitfld.long 0x0 25. "WDGPF,watchdog pre-alarm flag" "0: no graphic watchdog pre-alarm occurred.,1: a graphic watchdog pre-alarm occurred." bitfld.long 0x0 24. "WDGAF,watchdog alarm flag" "0: no graphic watchdog alarm occurred.,1: a graphic watchdog alarm occurred." newline bitfld.long 0x0 19. "EV4F,event 4 flag" "0: no complex event 4 occurred.,1: a complex event 4 occurred." bitfld.long 0x0 18. "EV3F,event 3 flag" "0: no complex event 3 occurred.,1: a complex event 3 occurred." newline bitfld.long 0x0 17. "EV2F,event 2 flag" "0: no complex event 2 occurred.,1: a complex event 2 occurred." bitfld.long 0x0 16. "EV1F,event 1 flag" "0: No complex event 1 occurred.,1: Complex event 1 occurred." newline bitfld.long 0x0 13. "RFC2RF,relative frame counter 2 reload flag" "0: no reload occurred on relative frame counter 2.,1: a reload on relative frame counter 2 occurred." bitfld.long 0x0 12. "RFC1RF,relative frame counter 1 reload flag" "0: no reload occurred on relative frame counter 1.,1: a reload on relative frame counter 1 occurred." newline bitfld.long 0x0 9. "ALCC2F,absolute line counter compare 2 flag" "0: no match occurred on compare 2 of the absolute..,1: a match on compare 2 of the absolute line.." bitfld.long 0x0 8. "ALCC1F,absolute line counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute line.." newline bitfld.long 0x0 4. "AFCC1F,absolute frame counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute frame.." bitfld.long 0x0 2. "TEF,tearing-effect flag" "0: no tearing effect occurred.,1: a tearing effect occurred." newline bitfld.long 0x0 1. "ALCOF,absolute line counter overflow flag" "0: no overflow occurred on the absolute line counter.,1: a overflow on the absolute line counter occurred." bitfld.long 0x0 0. "AFCOF,absolute frame counter overflow flag" "0: no overflow occurred on the absolute frame..,1: a overflow on the absolute frame counter occurred." wgroup.long 0x34++0x3 line.long 0x0 "GFXTIM_ICR,GFXTIM interrupt clear register" bitfld.long 0x0 25. "CWDGPF,clear watchdog pre-alarm flag" "0: no effect,1: WDGPF cleared" bitfld.long 0x0 24. "CWDGAF,clear watchdog alarm flag" "0: no effect,1: WDGAF cleared" newline bitfld.long 0x0 19. "CEV4F,clear event 4 flag" "0: no effect,1: EV4F cleared" bitfld.long 0x0 18. "CEV3F,clear event 3 flag" "0: no effect,1: EV3F cleared" newline bitfld.long 0x0 17. "CEV2F,clear event 2 flag" "0: no effect,1: EV2F cleared" bitfld.long 0x0 16. "CEV1F,clear event 1 flag" "0: no effect,1: EV1F cleared" newline bitfld.long 0x0 13. "CRFC2RF,clear relative frame counter 2 reload flag" "0: no effect,1: RFC2RF cleared" bitfld.long 0x0 12. "CRFC1RF,clear relative frame counter 1 reload flag" "0: no effect,1: RFC1RF cleared" newline bitfld.long 0x0 9. "CALCC2F,clear absolute line counter compare 2 flag" "0: no effect,1: ALCC2F cleared" bitfld.long 0x0 8. "CALCC1F,clear absolute line counter compare 1 flag" "0: no effect,1: ALCC1F cleared" newline bitfld.long 0x0 4. "CAFCC1F,clear absolute frame counter compare 1 flag" "0: no effect,1: AFCC1F cleared" bitfld.long 0x0 2. "CTEF,clear tearing-effect flag" "0: no effect,1: TEF cleared" newline bitfld.long 0x0 1. "CALCOF,clear absolute line counter overflow flag" "0: no effect,1: ALCOF cleared" bitfld.long 0x0 0. "CAFCOF,clear absolute frame counter overflow flag" "0: no effect,1: AFCOF cleared" group.long 0x38++0x3 line.long 0x0 "GFXTIM_IER,GFXTIM interrupt enable register" bitfld.long 0x0 25. "WDGPIE,watchdog pre-alarm interrupt enable" "0: watchdog pre-alarm interrupt disabled,1: watchdog pre-alarm interrupt enabled" bitfld.long 0x0 24. "WDGAIE,watchdog alarm interrupt enable" "0: watchdog alarm interrupt disabled,1: watchdog alarm interrupt enabled" newline bitfld.long 0x0 19. "EV4IE,event 4 interrupt enable" "0: event 4 interrupt disabled,1: event 4 interrupt enabled" bitfld.long 0x0 18. "EV3IE,event 3 interrupt enable" "0: event 3 interrupt disabled,1: event 3 interrupt enabled" newline bitfld.long 0x0 17. "EV2IE,event 2 interrupt enable" "0: event 2 interrupt disabled,1: event 2 interrupt enabled" bitfld.long 0x0 16. "EV1IE,event 1 interrupt enable" "0: event 1 interrupt disabled,1: event 1 interrupt enabled" newline bitfld.long 0x0 13. "RFC2RIE,relative frame counter 2 reload interrupt enable" "0: relative frame counter 2 reload interrupt disabled,1: relative frame counter 2 reload interrupt enabled" bitfld.long 0x0 12. "RFC1RIE,relative frame counter 1 reload interrupt enable" "0: relative frame counter 1 reload interrupt disabled,1: relative frame counter 1 reload interrupt enabled" newline bitfld.long 0x0 9. "ALCC2IE,absolute line counter compare 2 interrupt enable" "0: absolute line counter compare 2 interrupt disabled,1: absolute line counter compare 2 interrupt enabled" bitfld.long 0x0 8. "ALCC1IE,absolute line counter compare 1 interrupt enable" "0: absolute line counter compare 1 interrupt disabled,1: absolute line counter compare 1 interrupt enabled" newline bitfld.long 0x0 4. "AFCC1IE,absolute frame counter compare 1 interrupt enable" "0: absolute frame counter compare 1 interrupt..,1: absolute frame counter compare 1 interrupt enabled" bitfld.long 0x0 2. "TEIE,tearing-effect interrupt enable" "0: tearing-effect interrupt disabled,1: tearing-effect interrupt enabled" newline bitfld.long 0x0 1. "ALCOIE,absolute line counter overflow interrupt enable" "0: absolute line counter overflow interrupt disabled,1: absolute line counter overflow interrupt enabled" bitfld.long 0x0 0. "AFCOIE,absolute frame counter overflow interrupt enable" "0: absolute frame counter overflow interrupt disabled,1: absolute frame counter overflow interrupt enabled" rgroup.long 0x3C++0x3 line.long 0x0 "GFXTIM_TSR,GFXTIM timers status register" bitfld.long 0x0 20. "RFC2S,relative frame counter 2 status" "0: relative frame counter 2 disabled,1: relative frame counter 2 enabled" bitfld.long 0x0 16. "RFC1S,relative frame counter 1 status" "0: relative frame counter 1 disabled,1: relative frame counter 1 enabled" newline bitfld.long 0x0 4. "ALCS,absolute line counter status" "0: absolute line counter disabled,1: absolute line counter enabled" bitfld.long 0x0 0. "AFCS,absolute frame counter status" "0: absolute frame counter disabled,1: absolute frame counter enabled" group.long 0x40++0x7 line.long 0x0 "GFXTIM_LCCRR,GFXTIM line clock counter reload register" hexmask.long.tbyte 0x0 0.--21. 1. "RELOAD,reload value" line.long 0x4 "GFXTIM_FCCRR,GFXTIM frame clock counter reload register" hexmask.long.word 0x4 0.--11. 1. "RELOAD,reload value" rgroup.long 0x50++0x3 line.long 0x0 "GFXTIM_ATR,GFXTIM absolute time register" hexmask.long.tbyte 0x0 12.--31. 1. "FRAME,fame number" hexmask.long.word 0x0 0.--11. 1. "LINE,line number" group.long 0x54++0x7 line.long 0x0 "GFXTIM_AFCR,GFXTIM absolute frame counter register" hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number" line.long 0x4 "GFXTIM_ALCR,GFXTIM absolute line counter register" hexmask.long.word 0x4 0.--11. 1. "LINE,line number" group.long 0x60++0x3 line.long 0x0 "GFXTIM_AFCC1R,GFXTIM absolute frame counter compare 1 register" hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number" group.long 0x70++0x7 line.long 0x0 "GFXTIM_ALCC1R,GFXTIM absolute line counter compare 1 register" hexmask.long.word 0x0 0.--11. 1. "LINE,line number" line.long 0x4 "GFXTIM_ALCC2R,GFXTIM absolute line counter compare 2 register" hexmask.long.word 0x4 0.--11. 1. "LINE,line number" rgroup.long 0x80++0x3 line.long 0x0 "GFXTIM_RFC1R,GFXTIM relative frame counter 1 register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number" group.long 0x84++0x3 line.long 0x0 "GFXTIM_RFC1RR,GFXTIM relative frame counter 1 reload register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value" rgroup.long 0x88++0x3 line.long 0x0 "GFXTIM_RFC2R,GFXTIM relative frame counter 2 register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number" group.long 0x8C++0x3 line.long 0x0 "GFXTIM_RFC2RR,GFXTIM relative frame counter 2 reload register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value" rgroup.long 0xA0++0x3 line.long 0x0 "GFXTIM_WDGCR,GFXTIM watchdog counter register" hexmask.long.word 0x0 0.--15. 1. "VALUE,value" group.long 0xA4++0x7 line.long 0x0 "GFXTIM_WDGRR,GFXTIM watchdog reload register" hexmask.long.word 0x0 0.--15. 1. "RELOAD,reload value" line.long 0x4 "GFXTIM_WDGPAR,GFXTIM watchdog pre-alarm register" hexmask.long.word 0x4 0.--15. 1. "PREALARM,pre-alarm value" tree.end tree.end endif tree "GPDMA (General Purpose Direct Memory Access Controller)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "GPDMA1" base ad:0x40020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x8++0x3 line.long 0x0 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x0 15. "LOCK15,LOCK15" "0,1" bitfld.long 0x0 14. "LOCK14,LOCK14" "0,1" newline bitfld.long 0x0 13. "LOCK13,LOCK13" "0,1" bitfld.long 0x0 12. "LOCK12,LOCK12" "0,1" newline bitfld.long 0x0 11. "LOCK11,LOCK11" "0,1" bitfld.long 0x0 10. "LOCK10,LOCK10" "0,1" newline bitfld.long 0x0 9. "LOCK9,LOCK9" "0,1" bitfld.long 0x0 8. "LOCK8,LOCK8" "0,1" newline bitfld.long 0x0 7. "LOCK7,LOCK7" "0,1" bitfld.long 0x0 6. "LOCK6,LOCK6" "0,1" newline bitfld.long 0x0 5. "LOCK5,LOCK5" "0,1" bitfld.long 0x0 4. "LOCK4,LOCK4" "0,1" newline bitfld.long 0x0 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x0 2. "LOCK2,LOCK2" "0,1" newline bitfld.long 0x0 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x0 0. "LOCK0,LOCK0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" endif group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" newline bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline endif hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" endif line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" newline bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline endif hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" endif line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" newline bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline endif hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" endif line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" newline bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline endif hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" endif line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x0 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x0 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x0 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline endif hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x0 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x0 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x0 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline endif hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x0 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x0 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x0 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline endif hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x0 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x0 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x0 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline endif hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." sif (cpuis("STM32U575*")) group.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" endif sif (cpuis("STM32U575*")) group.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" endif sif (cpuis("STM32U575*")) group.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" endif sif (cpuis("STM32U575*")) group.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" endif sif (cpuis("STM32U575*")) group.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" group.long 0x290++0x3 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" group.long 0x310++0x3 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" group.long 0x390++0x3 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" group.long 0x410++0x3 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" group.long 0x490++0x3 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" group.long 0x510++0x3 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" group.long 0x590++0x3 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" group.long 0x610++0x3 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" group.long 0x690++0x3 line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" group.long 0x710++0x3 line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" group.long 0x790++0x3 line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" group.long 0x810++0x3 line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_GPDMA1" base ad:0x50020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x8++0x3 line.long 0x0 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x0 15. "LOCK15,LOCK15" "0,1" bitfld.long 0x0 14. "LOCK14,LOCK14" "0,1" newline bitfld.long 0x0 13. "LOCK13,LOCK13" "0,1" bitfld.long 0x0 12. "LOCK12,LOCK12" "0,1" newline bitfld.long 0x0 11. "LOCK11,LOCK11" "0,1" bitfld.long 0x0 10. "LOCK10,LOCK10" "0,1" newline bitfld.long 0x0 9. "LOCK9,LOCK9" "0,1" bitfld.long 0x0 8. "LOCK8,LOCK8" "0,1" newline bitfld.long 0x0 7. "LOCK7,LOCK7" "0,1" bitfld.long 0x0 6. "LOCK6,LOCK6" "0,1" newline bitfld.long 0x0 5. "LOCK5,LOCK5" "0,1" bitfld.long 0x0 4. "LOCK4,LOCK4" "0,1" newline bitfld.long 0x0 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x0 2. "LOCK2,LOCK2" "0,1" newline bitfld.long 0x0 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x0 0. "LOCK0,LOCK0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" endif group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" newline bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline endif hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" endif line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" newline bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline endif hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" endif line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" newline bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline endif hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" endif line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" newline bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline endif hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" endif line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" bitfld.long 0x0 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline endif hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." sif (cpuis("STM32U575*")) bitfld.long 0x0 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x0 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x0 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x0 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x0 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x0 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline endif hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x0 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x0 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x0 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline endif hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x0 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x0 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x0 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline endif hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x0 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x0 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x0 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline endif hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" newline bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." sif (cpuis("STM32U575*")) group.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" endif sif (cpuis("STM32U575*")) group.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" endif sif (cpuis("STM32U575*")) group.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" endif sif (cpuis("STM32U575*")) group.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" endif sif (cpuis("STM32U575*")) group.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" group.long 0x290++0x3 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" group.long 0x310++0x3 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" group.long 0x390++0x3 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" group.long 0x410++0x3 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" group.long 0x490++0x3 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" group.long 0x510++0x3 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" group.long 0x590++0x3 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" group.long 0x610++0x3 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" group.long 0x690++0x3 line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" group.long 0x710++0x3 line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" group.long 0x790++0x3 line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif sif (cpuis("STM32U575*")) group.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" group.long 0x810++0x3 line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" endif tree.end endif sif (cpuis("STM32U585*")) tree "GPDMA1" base ad:0x40020000 group.long 0x0++0xB line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,LOCK15" "0,1" bitfld.long 0x8 14. "LOCK14,LOCK14" "0,1" newline bitfld.long 0x8 13. "LOCK13,LOCK13" "0,1" bitfld.long 0x8 12. "LOCK12,LOCK12" "0,1" newline bitfld.long 0x8 11. "LOCK11,LOCK11" "0,1" bitfld.long 0x8 10. "LOCK10,LOCK10" "0,1" newline bitfld.long 0x8 9. "LOCK9,LOCK9" "0,1" bitfld.long 0x8 8. "LOCK8,LOCK8" "0,1" newline bitfld.long 0x8 7. "LOCK7,LOCK7" "0,1" bitfld.long 0x8 6. "LOCK6,LOCK6" "0,1" newline bitfld.long 0x8 5. "LOCK5,LOCK5" "0,1" bitfld.long 0x8 4. "LOCK4,LOCK4" "0,1" newline bitfld.long 0x8 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x8 2. "LOCK2,LOCK2" "0,1" newline bitfld.long 0x8 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x8 0. "LOCK0,LOCK0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,GPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,GPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C0TR2,GPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C0BR1,GPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C1LBAR,GPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,GPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C1TR2,GPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C1BR1,GPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C2LBAR,GPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,GPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C2TR2,GPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C2BR1,GPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C3LBAR,GPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,GPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "GPDMA_C3TR1,GPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C3TR2,GPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C3BR1,GPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C3SAR,GPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C3DAR,GPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x7 line.long 0x0 "GPDMA_C3LLR,GPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C4LBAR,GPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,GPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C4TR2,GPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C4BR1,GPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C4SAR,GPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C4DAR,GPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0x7 line.long 0x0 "GPDMA_C4LLR,GPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C5LBAR,GPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,GPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C5TR2,GPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C5BR1,GPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C5SAR,GPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C5DAR,GPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0x7 line.long 0x0 "GPDMA_C5LLR,GPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C6LBAR,GPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,GPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C6TR2,GPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C6BR1,GPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C6SAR,GPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C6DAR,GPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0x7 line.long 0x0 "GPDMA_C6LLR,GPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C7LBAR,GPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,GPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C7TR2,GPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C7BR1,GPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C7SAR,GPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C7DAR,GPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0x7 line.long 0x0 "GPDMA_C7LLR,GPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C8LBAR,GPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,GPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C8TR2,GPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C8BR1,GPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C8SAR,GPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C8DAR,GPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0x7 line.long 0x0 "GPDMA_C8LLR,GPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C9LBAR,GPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,GPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C9TR2,GPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C9BR1,GPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C9SAR,GPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C9DAR,GPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0x7 line.long 0x0 "GPDMA_C9LLR,GPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C10LBAR,GPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,GPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C10TR2,GPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C10BR1,GPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C10SAR,GPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C10DAR,GPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0x7 line.long 0x0 "GPDMA_C10LLR,GPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C11LBAR,GPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,GPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C11TR2,GPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C11BR1,GPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C11SAR,GPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C11DAR,GPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0x7 line.long 0x0 "GPDMA_C11LLR,GPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C12LBAR,GPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,GPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C12TR2,GPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C12BR1,GPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C12SAR,GPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C12DAR,GPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C12TR3,GPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C12BR2,GPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0x7 line.long 0x0 "GPDMA_C12LLR,GPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C13LBAR,GPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,GPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C13TR2,GPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C13BR1,GPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C13SAR,GPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C13DAR,GPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C13TR3,GPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C13BR2,GPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0x7 line.long 0x0 "GPDMA_C13LLR,GPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C14LBAR,GPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,GPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C14TR2,GPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C14BR1,GPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C14SAR,GPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C14DAR,GPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C14TR3,GPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C14BR2,GPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0x7 line.long 0x0 "GPDMA_C14LLR,GPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C15LBAR,GPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,GPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C15TR2,GPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C15BR1,GPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C15SAR,GPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C15DAR,GPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C15TR3,GPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C15BR2,GPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end tree "SEC_GPDMA1" base ad:0x50020000 group.long 0x0++0xB line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,LOCK15" "0,1" bitfld.long 0x8 14. "LOCK14,LOCK14" "0,1" newline bitfld.long 0x8 13. "LOCK13,LOCK13" "0,1" bitfld.long 0x8 12. "LOCK12,LOCK12" "0,1" newline bitfld.long 0x8 11. "LOCK11,LOCK11" "0,1" bitfld.long 0x8 10. "LOCK10,LOCK10" "0,1" newline bitfld.long 0x8 9. "LOCK9,LOCK9" "0,1" bitfld.long 0x8 8. "LOCK8,LOCK8" "0,1" newline bitfld.long 0x8 7. "LOCK7,LOCK7" "0,1" bitfld.long 0x8 6. "LOCK6,LOCK6" "0,1" newline bitfld.long 0x8 5. "LOCK5,LOCK5" "0,1" bitfld.long 0x8 4. "LOCK4,LOCK4" "0,1" newline bitfld.long 0x8 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x8 2. "LOCK2,LOCK2" "0,1" newline bitfld.long 0x8 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x8 0. "LOCK0,LOCK0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,GPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,GPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C0TR2,GPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C0BR1,GPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C1LBAR,GPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,GPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C1TR2,GPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C1BR1,GPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C2LBAR,GPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,GPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C2TR2,GPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C2BR1,GPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C3LBAR,GPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,GPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "GPDMA_C3TR1,GPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C3TR2,GPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C3BR1,GPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C3SAR,GPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C3DAR,GPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x7 line.long 0x0 "GPDMA_C3LLR,GPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C4LBAR,GPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,GPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C4TR2,GPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C4BR1,GPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C4SAR,GPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C4DAR,GPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0x7 line.long 0x0 "GPDMA_C4LLR,GPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C5LBAR,GPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,GPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C5TR2,GPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C5BR1,GPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C5SAR,GPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C5DAR,GPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0x7 line.long 0x0 "GPDMA_C5LLR,GPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C6LBAR,GPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,GPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C6TR2,GPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C6BR1,GPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C6SAR,GPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C6DAR,GPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0x7 line.long 0x0 "GPDMA_C6LLR,GPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C7LBAR,GPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,GPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C7TR2,GPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C7BR1,GPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C7SAR,GPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C7DAR,GPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0x7 line.long 0x0 "GPDMA_C7LLR,GPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C8LBAR,GPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,GPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C8TR2,GPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C8BR1,GPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C8SAR,GPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C8DAR,GPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0x7 line.long 0x0 "GPDMA_C8LLR,GPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C9LBAR,GPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,GPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C9TR2,GPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C9BR1,GPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C9SAR,GPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C9DAR,GPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0x7 line.long 0x0 "GPDMA_C9LLR,GPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C10LBAR,GPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,GPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C10TR2,GPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C10BR1,GPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C10SAR,GPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C10DAR,GPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0x7 line.long 0x0 "GPDMA_C10LLR,GPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C11LBAR,GPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,GPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C11TR2,GPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C11BR1,GPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C11SAR,GPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C11DAR,GPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0x7 line.long 0x0 "GPDMA_C11LLR,GPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C12LBAR,GPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,GPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C12TR2,GPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C12BR1,GPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C12SAR,GPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C12DAR,GPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C12TR3,GPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C12BR2,GPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0x7 line.long 0x0 "GPDMA_C12LLR,GPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C13LBAR,GPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,GPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C13TR2,GPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C13BR1,GPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C13SAR,GPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C13DAR,GPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C13TR3,GPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C13BR2,GPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0x7 line.long 0x0 "GPDMA_C13LLR,GPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C14LBAR,GPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,GPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C14TR2,GPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C14BR1,GPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C14SAR,GPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C14DAR,GPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C14TR3,GPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C14BR2,GPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0x7 line.long 0x0 "GPDMA_C14LLR,GPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C15LBAR,GPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,GPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width,2: If destination data width < source data width,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C15TR2,GPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." newline bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C15BR1,GPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C15SAR,GPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C15DAR,GPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C15TR3,GPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C15BR2,GPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32U595*")) tree "GPDMA1" base ad:0x40020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end tree "SEC_GPDMA1" base ad:0x50020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end endif sif (cpuis("STM32U599*")) tree "GPDMA1" base ad:0x40020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end tree "SEC_GPDMA1" base ad:0x50020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end endif sif (cpuis("STM32U5A5*")) tree "GPDMA1" base ad:0x40020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end tree "SEC_GPDMA1" base ad:0x50020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end endif sif (cpuis("STM32U5A9*")) tree "GPDMA1" base ad:0x40020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end tree "SEC_GPDMA1" base ad:0x50020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end endif sif (cpuis("STM32U5F*")) tree "GPDMA1" base ad:0x40020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end tree "SEC_GPDMA1" base ad:0x50020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end endif sif (cpuis("STM32U5G*")) tree "GPDMA1" base ad:0x40020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end tree "SEC_GPDMA1" base ad:0x50020000 group.long 0x0++0x7 line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,MIS15" "0,1" bitfld.long 0x0 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x0 13. "MIS13,MIS13" "0,1" bitfld.long 0x0 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x0 11. "MIS11,MIS11" "0,1" bitfld.long 0x0 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x0 9. "MIS9,MIS9" "0,1" bitfld.long 0x0 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x0 7. "MIS7,MIS7" "0,1" bitfld.long 0x0 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x0 5. "MIS5,MIS5" "0,1" bitfld.long 0x0 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,MIS15" "0,1" bitfld.long 0x4 14. "MIS14,MIS14" "0,1" newline bitfld.long 0x4 13. "MIS13,MIS13" "0,1" bitfld.long 0x4 12. "MIS12,MIS12" "0,1" newline bitfld.long 0x4 11. "MIS11,MIS11" "0,1" bitfld.long 0x4 10. "MIS10,MIS10" "0,1" newline bitfld.long 0x4 9. "MIS9,MIS9" "0,1" bitfld.long 0x4 8. "MIS8,MIS8" "0,1" newline bitfld.long 0x4 7. "MIS7,MIS7" "0,1" bitfld.long 0x4 6. "MIS6,MIS6" "0,1" newline bitfld.long 0x4 5. "MIS5,MIS5" "0,1" bitfld.long 0x4 4. "MIS4,MIS4" "0,1" newline bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C0TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C0BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C1TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,TRIGM mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C1BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C2TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "GPDMA_C2BR1,GPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "GPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x7 line.long 0x0 "GPDMA_C3TR1,GPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 30. "DAP,destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is.." "0: port 0,1: port 1" newline bitfld.long 0x0 27. "DHX,destination half-word exchangeIf destination data size is shorter than a word this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each.." "0: no halfword-based exchange within word-,1: the two consecutive" bitfld.long 0x0 26. "DBX,destination byte exchangeIf destination data size is a byte this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word" "0: no byte-based exchange within half-word-,1: the two consecutive" newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the destination data width i.e." bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 14. "SAP,source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: port 0,1: port 1" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1:.." "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0 then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst.." newline bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "GPDMA_C3TR2,GPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x4 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x294++0x3 line.long 0x0 "GPDMA_C4TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode" "0,1,2,3" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x314++0x3 line.long 0x0 "GPDMA_C5TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x394++0x3 line.long 0x0 "GPDMA_C6TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x414++0x3 line.long 0x0 "GPDMA_C7TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x494++0x3 line.long 0x0 "GPDMA_C8TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x514++0x3 line.long 0x0 "GPDMA_C9TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x594++0x3 line.long 0x0 "GPDMA_C10TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x614++0x3 line.long 0x0 "GPDMA_C11TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x694++0x3 line.long 0x0 "GPDMA_C12TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x714++0x3 line.long 0x0 "GPDMA_C13TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x794++0x3 line.long 0x0 "GPDMA_C14TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x814++0x3 line.long 0x0 "GPDMA_C15TR2,GPDMA channel x transfer register 2" bitfld.long 0x0 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x0 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x0 14.--15. "TRIGM,Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring trashing the (possible) memorized hit of the formerly defined LLIn trigger. After.." "0,1,2,3" newline bitfld.long 0x0 11. "BREQ,BREQ" "0,1" bitfld.long 0x0 10. "DREQ,Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else: - 0: the selected hardware request is driven by a source.." "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x0 9. "SWREQ,Software request When GPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" hexmask.long.byte 0x0 0.--6. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." group.long 0x218++0x3 line.long 0x0 "GPDMA_C3BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x298++0x3 line.long 0x0 "GPDMA_C4BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x318++0x3 line.long 0x0 "GPDMA_C5BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x398++0x3 line.long 0x0 "GPDMA_C6BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x418++0x3 line.long 0x0 "GPDMA_C7BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x498++0x3 line.long 0x0 "GPDMA_C8BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x518++0x3 line.long 0x0 "GPDMA_C9BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x598++0x3 line.long 0x0 "GPDMA_C10BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x618++0x3 line.long 0x0 "GPDMA_C11BR1,GPDMA channel x block register 1" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x698++0x3 line.long 0x0 "GPDMA_C12BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x718++0x3 line.long 0x0 "GPDMA_C13BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x798++0x3 line.long 0x0 "GPDMA_C14BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x818++0x3 line.long 0x0 "GPDMA_C15BR1,GPDMA channel x block register 1" bitfld.long 0x0 31. "BRDDEC,BRDDEC" "0,1" bitfld.long 0x0 30. "BRSDEC,BRSDEC" "0,1" newline bitfld.long 0x0 29. "DDEC,DDEC" "0,1" bitfld.long 0x0 28. "SDEC,SDEC" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "BRC,BRC" hexmask.long.word 0x0 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" group.long 0x21C++0x3 line.long 0x0 "GPDMA_C3SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x29C++0x3 line.long 0x0 "GPDMA_C4SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x31C++0x3 line.long 0x0 "GPDMA_C5SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x39C++0x3 line.long 0x0 "GPDMA_C6SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x41C++0x3 line.long 0x0 "GPDMA_C7SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x49C++0x3 line.long 0x0 "GPDMA_C8SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x51C++0x3 line.long 0x0 "GPDMA_C9SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x59C++0x3 line.long 0x0 "GPDMA_C10SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x61C++0x3 line.long 0x0 "GPDMA_C11SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x69C++0x3 line.long 0x0 "GPDMA_C12SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x71C++0x3 line.long 0x0 "GPDMA_C13SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x79C++0x3 line.long 0x0 "GPDMA_C14SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x81C++0x3 line.long 0x0 "GPDMA_C15SAR,GPDMA channel x source address register" hexmask.long 0x0 0.--31. 1. "SA,source address" group.long 0x220++0x3 line.long 0x0 "GPDMA_C3DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x2A0++0x3 line.long 0x0 "GPDMA_C4DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x320++0x3 line.long 0x0 "GPDMA_C5DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x3A0++0x3 line.long 0x0 "GPDMA_C6DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x420++0x3 line.long 0x0 "GPDMA_C7DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x4A0++0x3 line.long 0x0 "GPDMA_C8DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x520++0x3 line.long 0x0 "GPDMA_C9DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x5A0++0x3 line.long 0x0 "GPDMA_C10DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x620++0x3 line.long 0x0 "GPDMA_C11DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x6A0++0x3 line.long 0x0 "GPDMA_C12DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x720++0x3 line.long 0x0 "GPDMA_C13DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x7A0++0x3 line.long 0x0 "GPDMA_C14DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x820++0x3 line.long 0x0 "GPDMA_C15DAR,GPDMA channel x destination address register" hexmask.long 0x0 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "GPDMA_C3LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x2CC++0x3 line.long 0x0 "GPDMA_C4LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x34C++0x3 line.long 0x0 "GPDMA_C5LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x3CC++0x3 line.long 0x0 "GPDMA_C6LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x44C++0x3 line.long 0x0 "GPDMA_C7LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x4CC++0x3 line.long 0x0 "GPDMA_C8LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x54C++0x3 line.long 0x0 "GPDMA_C9LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x5CC++0x3 line.long 0x0 "GPDMA_C10LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x64C++0x3 line.long 0x0 "GPDMA_C11LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x6CC++0x3 line.long 0x0 "GPDMA_C12LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x74C++0x3 line.long 0x0 "GPDMA_C13LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x7CC++0x3 line.long 0x0 "GPDMA_C14LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0 the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no GPDMA_CxBR1 update,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." group.long 0x250++0x3 line.long 0x0 "GPDMA_C4LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x2D0++0x3 line.long 0x0 "GPDMA_C5LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x350++0x3 line.long 0x0 "GPDMA_C6LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x3D0++0x3 line.long 0x0 "GPDMA_C7LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x450++0x3 line.long 0x0 "GPDMA_C8LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x4D0++0x3 line.long 0x0 "GPDMA_C9LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x550++0x3 line.long 0x0 "GPDMA_C10LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x5D0++0x3 line.long 0x0 "GPDMA_C11LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x650++0x3 line.long 0x0 "GPDMA_C12LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x6D0++0x3 line.long 0x0 "GPDMA_C13LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x750++0x3 line.long 0x0 "GPDMA_C14LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" group.long 0x7D0++0x3 line.long 0x0 "GPDMA_C15LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel x flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0,1" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,channel x status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level Number of available write beats in the FIFO in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0] i.e. in units of bytes half-words or words). Note: After having suspended an active transfer the.." bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset" "0,1" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 17. "LAP,linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update.." "0: port 0,1: port 1" newline bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" newline bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x6A4++0x3 line.long 0x0 "GPDMA_C12TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x724++0x3 line.long 0x0 "GPDMA_C13TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x7A4++0x3 line.long 0x0 "GPDMA_C14TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x824++0x3 line.long 0x0 "GPDMA_C15TR3,GPDMA channel x transfer register 3" hexmask.long.word 0x0 16.--28. 1. "DAO,destination address offset increment The destination address pointed by GPDMA_CxDAR is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is.." hexmask.long.word 0x0 0.--12. 1. "SAO,source address offset increment The source address pointed by GPDMA_CxSAR is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the.." group.long 0x6A8++0x3 line.long 0x0 "GPDMA_C12BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x728++0x3 line.long 0x0 "GPDMA_C13BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x7A8++0x3 line.long 0x0 "GPDMA_C14BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." group.long 0x828++0x3 line.long 0x0 "GPDMA_C15BR2,GPDMA channel x block register 2" hexmask.long.word 0x0 16.--31. 1. "BRDAO,Block repeated destination address offset For a channel with 2D addressing capability this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the.." hexmask.long.word 0x0 0.--15. 1. "BRSAO,Block repeated source address offset For a channel with 2D addressing capability this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a.." tree.end endif tree.end tree "GPIO (General Purpose Inputs/Outputs)" base ad:0x0 tree "GPIOA" base ad:0x42020000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end sif (cpuis("STM32U575*")) tree "GPIOF" base ad:0x42021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOF" base ad:0x52021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U575*")) tree "GPIOI" base ad:0x42022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U585*")) tree "GPIOF" base ad:0x42021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOF" base ad:0x52021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U585*")) tree "GPIOI" base ad:0x42022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U595*")) tree "GPIOF" base ad:0x42021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOF" base ad:0x52021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U595*")) tree "GPIOI" base ad:0x42022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOJ" base ad:0x42022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U599*")) tree "GPIOF" base ad:0x42021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOF" base ad:0x52021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOI" base ad:0x52022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U599*")) tree "GPIOI" base ad:0x42022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOJ" base ad:0x42022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5A5*")) tree "GPIOF" base ad:0x42021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOF" base ad:0x52021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOI" base ad:0x52022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5A5*")) tree "GPIOI" base ad:0x42022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOJ" base ad:0x42022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5A9*")) tree "GPIOF" base ad:0x42021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOF" base ad:0x52021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOI" base ad:0x52022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5A9*")) tree "GPIOI" base ad:0x42022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOJ" base ad:0x42022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5F*")) tree "GPIOF" base ad:0x42021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOF" base ad:0x52021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOI" base ad:0x52022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5F*")) tree "GPIOI" base ad:0x42022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOJ" base ad:0x42022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5G*")) tree "GPIOF" base ad:0x42021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOF" base ad:0x52021400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOI" base ad:0x52022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5G*")) tree "GPIOI" base ad:0x42022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOJ" base ad:0x42022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif tree "GPIOB" base ad:0x42020400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOC" base ad:0x42020800 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOD" base ad:0x42020C00 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOE" base ad:0x42021000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOG" base ad:0x42021800 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "GPIOH" base ad:0x42021C00 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOA" base ad:0x52020000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOB" base ad:0x52020400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOC" base ad:0x52020800 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOD" base ad:0x52020C00 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOE" base ad:0x52021000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOG" base ad:0x52021800 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOH" base ad:0x52021C00 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end sif (cpuis("STM32U575*")) tree "SEC_GPIOI" base ad:0x52022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U585*")) tree "SEC_GPIOI" base ad:0x52022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U595*")) tree "SEC_GPIOI" base ad:0x52022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end tree "SEC_GPIOJ" base ad:0x52022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U599*")) tree "SEC_GPIOJ" base ad:0x52022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5A5*")) tree "SEC_GPIOJ" base ad:0x52022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5A9*")) tree "SEC_GPIOJ" base ad:0x52022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5F*")) tree "SEC_GPIOJ" base ad:0x52022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif sif (cpuis("STM32U5G*")) tree "SEC_GPIOJ" base ad:0x52022400 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: Reserved" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,GPIO port configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIO_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIO_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIO_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit" group.long 0x2C++0x7 line.long 0x0 "GPIO_HSLVR,GPIO high-speed low-voltage register" bitfld.long 0x0 15. "HSLV15,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 14. "HSLV14,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 13. "HSLV13,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 12. "HSLV12,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 11. "HSLV11,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 10. "HSLV10,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 9. "HSLV9,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 8. "HSLV8,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 7. "HSLV7,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 6. "HSLV6,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 5. "HSLV5,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 4. "HSLV4,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 3. "HSLV3,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 2. "HSLV2,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" newline bitfld.long 0x0 1. "HSLV1,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" bitfld.long 0x0 0. "HSLV0,Port x high-speed low-voltage configuration" "0: I/O speed optimization disabled,1: I/O speed optimization enabled" line.long 0x4 "GPIO_SECCFGR,GPIO secure configuration register" bitfld.long 0x4 15. "SEC15,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 14. "SEC14,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 13. "SEC13,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 12. "SEC12,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 11. "SEC11,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 10. "SEC10,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 9. "SEC9,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 8. "SEC8,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 7. "SEC7,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 6. "SEC6,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 5. "SEC5,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 4. "SEC4,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 3. "SEC3,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 2. "SEC2,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" newline bitfld.long 0x4 1. "SEC1,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" bitfld.long 0x4 0. "SEC0,I/O pin of Port x secure bit enable y" "0: The I/O pin is non-secure,1: The I/O pin is secure" tree.end endif tree.end tree "GTZC (Global TrustZone Controller)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "GTZC1_MPCBB1" base ad:0x40032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" newline bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" newline bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" newline bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" newline bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" newline bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" newline bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" newline bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" newline bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" newline bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" newline bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" newline bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" newline bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" newline bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" newline bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" newline bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" newline bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" newline bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" newline bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" newline bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x180++0x4F line.long 0x0 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" newline bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" newline bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" newline bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" newline bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" newline bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" newline bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" newline bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" newline bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" newline bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" newline bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" newline bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" newline bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" group.long 0x280++0x4F line.long 0x0 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x10++0x3 line.long 0x0 "MPCBB1_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" newline bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" newline bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" newline bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" newline bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" newline bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" newline bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" newline bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" newline bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" newline bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" newline bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" newline bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" newline bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" endif group.long 0x100++0x7F line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_GTZC1_MPCBB1" base ad:0x50032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" newline bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" newline bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" newline bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" newline bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" newline bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" newline bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" newline bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" newline bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" newline bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" newline bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" newline bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" newline bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" newline bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" newline bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" newline bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" newline bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" newline bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" newline bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" newline bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x180++0x4F line.long 0x0 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" newline bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" newline bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" newline bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" newline bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" newline bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" newline bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" newline bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" newline bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" newline bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" newline bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" newline bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" newline bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" group.long 0x280++0x4F line.long 0x0 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x10++0x3 line.long 0x0 "MPCBB1_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" newline bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" newline bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" newline bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" newline bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" newline bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" newline bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" newline bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" newline bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" newline bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" newline bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" newline bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" newline bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" endif group.long 0x100++0x7F line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "GTZC1_MPCBB2" base ad:0x40033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" newline bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" newline bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" newline bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" newline bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" newline bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" newline bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" newline bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" newline bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" newline bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" newline bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" newline bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" newline bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" newline bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" newline bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" newline bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" newline bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" newline bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" newline bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" newline bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x180++0x4F line.long 0x0 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" newline bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" newline bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" newline bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" newline bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" newline bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" newline bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" newline bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" newline bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" newline bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" newline bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" newline bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" newline bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" group.long 0x280++0x4F line.long 0x0 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x10++0x3 line.long 0x0 "MPCBB2_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" newline bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" newline bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" newline bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" newline bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" newline bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" newline bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" newline bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" newline bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" newline bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" newline bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" newline bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" newline bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" endif group.long 0x100++0x7F line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_GTZC1_MPCBB2" base ad:0x50033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" newline bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" newline bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" newline bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" newline bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" newline bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" newline bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" newline bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" newline bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" newline bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" newline bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" newline bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" newline bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" newline bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" newline bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" newline bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" newline bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" newline bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" newline bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" newline bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x180++0x4F line.long 0x0 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" newline bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" newline bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" newline bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" newline bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" newline bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" newline bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" newline bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" newline bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" newline bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" newline bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" newline bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" newline bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" newline bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" newline bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" newline bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" newline bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" newline bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" newline bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" newline bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" newline bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" newline bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" newline bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" newline bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" group.long 0x280++0x4F line.long 0x0 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" newline bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" newline bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" newline bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" newline bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" newline bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" newline bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" newline bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" newline bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" newline bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" newline bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" newline bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x10++0x3 line.long 0x0 "MPCBB2_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" newline bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" newline bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" newline bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" newline bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" newline bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" newline bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" newline bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" newline bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" newline bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" newline bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" newline bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" newline bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" endif group.long 0x100++0x7F line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "GTZC1_TZIC" base ad:0x40032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" newline bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" newline bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" endif bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" newline bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" endif bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" newline bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" newline bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" endif bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" newline bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" endif bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" newline bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" endif bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" newline bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" newline bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" endif bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" newline bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" newline bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" endif bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" newline sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" endif bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" newline bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" newline bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" endif bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "SEC_GTZC1_TZIC" base ad:0x50032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" newline bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" newline bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" endif bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" newline bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" endif bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" newline bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" newline bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" endif bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" newline bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" endif bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" newline bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" endif bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" newline bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" newline bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" endif bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" newline bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" newline bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" endif bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" newline sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" endif bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" newline bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" newline bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" endif bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "GTZC1_TZSC" base ad:0x40032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" newline bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" newline bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" newline bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" endif newline bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" endif bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" newline bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" newline bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" newline bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" newline bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" endif newline bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" endif bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" newline bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "SEC_GTZC1_TZSC" base ad:0x50032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" newline bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" newline bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" newline bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" endif newline bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" endif bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" newline bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" newline bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" newline bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" newline bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" endif newline bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" endif bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" newline bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U575*")) tree "GTZC1_MPCBB3" base ad:0x40033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB3_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" group.long 0x100++0x7F line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB3" base ad:0x50033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB3_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" group.long 0x100++0x7F line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U575*")) tree "GTZC1_TZIC" base ad:0x40032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" newline bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" newline bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2IE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1IE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMCIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" newline bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGFSIE,illegal access interrupt enable for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1IE,illegal access interrupt enable for ADC1" "0,1" bitfld.long 0x8 7. "DCACHEIE,illegal access interrupt enable for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "ICACHEIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" newline bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" newline bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" newline bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2F,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1F,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMCF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGFSF,illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC1F,illegal access flag for ADC1" "0,1" bitfld.long 0x8 7. "DCACHEF,illegal access flag for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "ICACHEF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" newline bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" newline bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" newline bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2F,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1F,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "CFSMCF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGFSF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC1F,clear the illegal access flag for ADC1" "0,1" bitfld.long 0x8 7. "CDCACHEF,clear the illegal access flag for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "CICACHEF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 3" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" newline bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end tree "SEC_GTZC1_TZIC" base ad:0x50032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" newline bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" newline bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2IE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1IE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMCIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" newline bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGFSIE,illegal access interrupt enable for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1IE,illegal access interrupt enable for ADC1" "0,1" bitfld.long 0x8 7. "DCACHEIE,illegal access interrupt enable for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "ICACHEIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" newline bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" newline bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" newline bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2F,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1F,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMCF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGFSF,illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC1F,illegal access flag for ADC1" "0,1" bitfld.long 0x8 7. "DCACHEF,illegal access flag for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "ICACHEF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" newline bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" newline bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" newline bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2F,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1F,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "CFSMCF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGFSF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC1F,clear the illegal access flag for ADC1" "0,1" bitfld.long 0x8 7. "CDCACHEF,clear the illegal access flag for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "CICACHEF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 3" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" newline bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U575*")) tree "GTZC1_TZSC" base ad:0x40032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" newline bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" newline bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" newline bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" newline bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE_REGSEC,secure access mode for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" newline bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" newline bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" newline bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" newline bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE_REGPRIV,privileged access mode for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0xF line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end tree "SEC_GTZC1_TZSC" base ad:0x50032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" newline bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" newline bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" newline bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" newline bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE_REGSEC,secure access mode for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" newline bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" newline bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" newline bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" newline bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE_REGPRIV,privileged access mode for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0xF line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U575*")) tree "GTZC2_TZIC" base ad:0x46023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4IE,illegal access interrupt enable for ADC4" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4F,illegal access flag for ADC4" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC4F,clear the illegal access flag for ADC4" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U575*")) tree "GTZC2_TZSC" base ad:0x46023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4SEC,secure access mode for ADC4" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4PRIV,privileged access mode for ADC4" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "GTZC1_MPCBB1" base ad:0x40032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB1_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" group.long 0x100++0x7F line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB1" base ad:0x50032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB1_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" group.long 0x100++0x7F line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB2" base ad:0x50033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB2_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" group.long 0x100++0x7F line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB3" base ad:0x50033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB3_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" group.long 0x100++0x7F line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "GTZC1_MPCBB2" base ad:0x40033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB2_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" group.long 0x100++0x7F line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB3" base ad:0x40033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB3_CFGLOCKR1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" group.long 0x100++0x7F line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" group.long 0x200++0x7F line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_TZIC" base ad:0x50032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" newline bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" newline bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2IE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1IE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMCIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" newline bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGFSIE,illegal access interrupt enable for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1IE,illegal access interrupt enable for ADC1" "0,1" bitfld.long 0x8 7. "DCACHEIE,illegal access interrupt enable for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "ICACHEIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" newline bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" newline bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" newline bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2F,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1F,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMCF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGFSF,illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC1F,illegal access flag for ADC1" "0,1" bitfld.long 0x8 7. "DCACHEF,illegal access flag for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "ICACHEF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" newline bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" newline bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" newline bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2F,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1F,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "CFSMCF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGFSF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC1F,clear the illegal access flag for ADC1" "0,1" bitfld.long 0x8 7. "CDCACHEF,clear the illegal access flag for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "CICACHEF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 3" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" newline bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "GTZC1_TZIC" base ad:0x40032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" newline bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" newline bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2IE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1IE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMCIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" newline bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGFSIE,illegal access interrupt enable for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1IE,illegal access interrupt enable for ADC1" "0,1" bitfld.long 0x8 7. "DCACHEIE,illegal access interrupt enable for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "ICACHEIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" newline bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" newline bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" newline bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2F,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1F,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMCF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGFSF,illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC1F,illegal access flag for ADC1" "0,1" bitfld.long 0x8 7. "DCACHEF,illegal access flag for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "ICACHEF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" newline bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" newline bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" newline bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2F,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1F,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "CFSMCF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGFSF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC1F,clear the illegal access flag for ADC1" "0,1" bitfld.long 0x8 7. "CDCACHEF,clear the illegal access flag for DCACHE registers" "0,1" newline bitfld.long 0x8 6. "CICACHEF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 3" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" newline bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" newline bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end tree "SEC_GTZC1_TZSC" base ad:0x50032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" newline bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" newline bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" newline bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" newline bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE_REGSEC,secure access mode for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" newline bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" newline bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" newline bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" newline bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE_REGPRIV,privileged access mode for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0xF line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U585*")) tree "GTZC1_TZSC" base ad:0x40032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" newline bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" newline bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" newline bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" newline bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE_REGSEC,secure access mode for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" newline bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" newline bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" newline bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" newline bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" newline bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE_REGPRIV,privileged access mode for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0xF line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end tree "GTZC2_TZIC" base ad:0x46023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4IE,illegal access interrupt enable for ADC4" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4F,illegal access flag for ADC4" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC4F,clear the illegal access flag for ADC4" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "GTZC2_TZSC" base ad:0x46023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4SEC,secure access mode for ADC4" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4PRIV,privileged access mode for ADC4" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "GTZC1_MPCBB1" base ad:0x40032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB1" base ad:0x50032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB2" base ad:0x50033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB3" base ad:0x50033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB5" base ad:0x50033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "GTZC1_MPCBB2" base ad:0x40033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB3" base ad:0x40033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB5" base ad:0x40033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_TZIC" base ad:0x50032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" newline bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "GTZC1_TZIC" base ad:0x40032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" newline bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" newline bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end tree "SEC_GTZC1_TZSC" base ad:0x50032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" newline bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" newline bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" newline bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" newline bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U595*")) tree "GTZC1_TZSC" base ad:0x40032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" newline bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" newline bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" newline bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" newline bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end tree "GTZC2_TZIC" base ad:0x46023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "GTZC2_TZSC" base ad:0x46023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "GTZC1_MPCBB1" base ad:0x40032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB1" base ad:0x50032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB2" base ad:0x50033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB3" base ad:0x50033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB5" base ad:0x50033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "GTZC1_MPCBB2" base ad:0x40033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB3" base ad:0x40033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB5" base ad:0x40033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_TZIC" base ad:0x50032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 10. "DSIIE,illegal access interrupt enable for DSI" "0,1" bitfld.long 0x4 9. "LTDCIE,illegal access interrupt enable for LTDC" "0,1" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 27. "DCACHE2_REGIE,DCACHE2_REGIE" "0,1" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 25. "GFXMMU_REGIE,GFXMMU_REGIE" "0,1" bitfld.long 0x8 24. "GFXMMUIE,GFXMMUIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 10. "DSIF,illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "LTDCF,illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 27. "DCACHE2_REGF,illegal access flag for DCACHE2 registers" "0,1" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 25. "GFXMMU_REGF,illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "GFXMMUF,illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 10. "CDSIF,clear the illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "CLTDCF,clear the illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 27. "CDCACHE2_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 26. "CHSPI1_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 25. "CGFXMMU_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "CGFXMMUF,clear the illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" newline bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" newline bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "GTZC1_TZIC" base ad:0x40032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 10. "DSIIE,illegal access interrupt enable for DSI" "0,1" bitfld.long 0x4 9. "LTDCIE,illegal access interrupt enable for LTDC" "0,1" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 27. "DCACHE2_REGIE,DCACHE2_REGIE" "0,1" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 25. "GFXMMU_REGIE,GFXMMU_REGIE" "0,1" bitfld.long 0x8 24. "GFXMMUIE,GFXMMUIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 10. "DSIF,illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "LTDCF,illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 27. "DCACHE2_REGF,illegal access flag for DCACHE2 registers" "0,1" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 25. "GFXMMU_REGF,illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "GFXMMUF,illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 10. "CDSIF,clear the illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "CLTDCF,clear the illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 27. "CDCACHE2_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 26. "CHSPI1_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 25. "CGFXMMU_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "CGFXMMUF,clear the illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" newline bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" newline bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end tree "SEC_GTZC1_TZSC" base ad:0x50032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 10. "DSISEC,DSISEC" "0,1" bitfld.long 0x4 9. "LTDCSEC,LTDCSEC" "0,1" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" newline bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGSEC,DCACHE2_REGSEC" "0,1" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 25. "GFXMMU_REGSEC,GFXMMU_REGSEC" "0,1" bitfld.long 0x8 24. "GFXMMUSEC,GFXMMUSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 10. "DSIPRIV,DSIPRIV" "0,1" bitfld.long 0x4 9. "LTDCPRIV,LTDCPRIV" "0,1" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" newline bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGPRIV,DCACHE2_REGPRIV" "0,1" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 25. "GFXMMU_REGPRIV,GFXMMU_REGPRIV" "0,1" bitfld.long 0x8 24. "GFXMMUPRIV,GFXMMUPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U599*")) tree "GTZC1_TZSC" base ad:0x40032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 10. "DSISEC,DSISEC" "0,1" bitfld.long 0x4 9. "LTDCSEC,LTDCSEC" "0,1" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" newline bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGSEC,DCACHE2_REGSEC" "0,1" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 25. "GFXMMU_REGSEC,GFXMMU_REGSEC" "0,1" bitfld.long 0x8 24. "GFXMMUSEC,GFXMMUSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 10. "DSIPRIV,DSIPRIV" "0,1" bitfld.long 0x4 9. "LTDCPRIV,LTDCPRIV" "0,1" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" newline bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGPRIV,DCACHE2_REGPRIV" "0,1" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 25. "GFXMMU_REGPRIV,GFXMMU_REGPRIV" "0,1" bitfld.long 0x8 24. "GFXMMUPRIV,GFXMMUPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end tree "GTZC2_TZIC" base ad:0x46023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "GTZC2_TZSC" base ad:0x46023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "GTZC1_MPCBB1" base ad:0x40032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB1" base ad:0x50032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB2" base ad:0x50033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB3" base ad:0x50033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB5" base ad:0x50033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "GTZC1_MPCBB2" base ad:0x40033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB3" base ad:0x40033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB5" base ad:0x40033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_TZIC" base ad:0x50032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" newline bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" newline bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "GTZC1_TZIC" base ad:0x40032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" newline bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" newline bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" newline bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" newline bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end tree "SEC_GTZC1_TZSC" base ad:0x50032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" newline bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" newline bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" newline bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" newline bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" newline bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" newline bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U5A5*")) tree "GTZC1_TZSC" base ad:0x40032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" newline bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" newline bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" newline bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" newline bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" newline bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" newline bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end tree "GTZC2_TZIC" base ad:0x46023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "GTZC2_TZSC" base ad:0x46023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "GTZC1_MPCBB1" base ad:0x40032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB1" base ad:0x50032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB2" base ad:0x50033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB3" base ad:0x50033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB5" base ad:0x50033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "GTZC1_MPCBB2" base ad:0x40033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB3" base ad:0x40033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB5" base ad:0x40033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_TZIC" base ad:0x50032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 10. "DSIIE,illegal access interrupt enable for DSI" "0,1" bitfld.long 0x4 9. "LTDCIE,illegal access interrupt enable for LTDC" "0,1" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 27. "DCACHE2_REGIE,DCACHE2_REGIE" "0,1" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 25. "GFXMMU_REGIE,GFXMMU_REGIE" "0,1" bitfld.long 0x8 24. "GFXMMUIE,GFXMMUIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" newline bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" newline bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 10. "DSIF,illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "LTDCF,illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 27. "DCACHE2_REGF,illegal access flag for DCACHE2 registers" "0,1" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 25. "GFXMMU_REGF,illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "GFXMMUF,illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" newline bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 10. "CDSIF,clear the illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "CLTDCF,clear the illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 27. "CDCACHE2_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 26. "CHSPI1_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 25. "CGFXMMU_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "CGFXMMUF,clear the illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" newline bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "GTZC1_TZIC" base ad:0x40032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 10. "DSIIE,illegal access interrupt enable for DSI" "0,1" bitfld.long 0x4 9. "LTDCIE,illegal access interrupt enable for LTDC" "0,1" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 27. "DCACHE2_REGIE,DCACHE2_REGIE" "0,1" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 25. "GFXMMU_REGIE,GFXMMU_REGIE" "0,1" bitfld.long 0x8 24. "GFXMMUIE,GFXMMUIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" newline bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" newline bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 10. "DSIF,illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "LTDCF,illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 27. "DCACHE2_REGF,illegal access flag for DCACHE2 registers" "0,1" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 25. "GFXMMU_REGF,illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "GFXMMUF,illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" newline bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 10. "CDSIF,clear the illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "CLTDCF,clear the illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 27. "CDCACHE2_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 26. "CHSPI1_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 25. "CGFXMMU_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "CGFXMMUF,clear the illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" newline bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end tree "SEC_GTZC1_TZSC" base ad:0x50032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 10. "DSISEC,DSISEC" "0,1" bitfld.long 0x4 9. "LTDCSEC,LTDCSEC" "0,1" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" newline bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGSEC,DCACHE2_REGSEC" "0,1" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 25. "GFXMMU_REGSEC,GFXMMU_REGSEC" "0,1" bitfld.long 0x8 24. "GFXMMUSEC,GFXMMUSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" newline bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" newline bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 10. "DSIPRIV,DSIPRIV" "0,1" bitfld.long 0x4 9. "LTDCPRIV,LTDCPRIV" "0,1" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" newline bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGPRIV,DCACHE2_REGPRIV" "0,1" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 25. "GFXMMU_REGPRIV,GFXMMU_REGPRIV" "0,1" bitfld.long 0x8 24. "GFXMMUPRIV,GFXMMUPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" newline bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" newline bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U5A9*")) tree "GTZC1_TZSC" base ad:0x40032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 10. "DSISEC,DSISEC" "0,1" bitfld.long 0x4 9. "LTDCSEC,LTDCSEC" "0,1" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" newline bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGSEC,DCACHE2_REGSEC" "0,1" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 25. "GFXMMU_REGSEC,GFXMMU_REGSEC" "0,1" bitfld.long 0x8 24. "GFXMMUSEC,GFXMMUSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" newline bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" newline bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 10. "DSIPRIV,DSIPRIV" "0,1" bitfld.long 0x4 9. "LTDCPRIV,LTDCPRIV" "0,1" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" newline bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGPRIV,DCACHE2_REGPRIV" "0,1" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 25. "GFXMMU_REGPRIV,GFXMMU_REGPRIV" "0,1" bitfld.long 0x8 24. "GFXMMUPRIV,GFXMMUPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" newline bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" newline bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end tree "GTZC2_TZIC" base ad:0x46023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "GTZC2_TZSC" base ad:0x46023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "GTZC1_MPCBB1" base ad:0x40032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB1" base ad:0x50032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB2" base ad:0x50033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB3" base ad:0x50033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB5" base ad:0x50033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB6" base ad:0x50033C00 group.long 0x0++0x3 line.long 0x0 "MPCBB6_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB6_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB6_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB6_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB6_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB6_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB6_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB6_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB6_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB6_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB6_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB6_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB6_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB6_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB6_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB6_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB6_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB6_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB6_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB6_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB6_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB6_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB6_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB6_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB6_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB6_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB6_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB6_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB6_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB6_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB6_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB6_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB6_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB6_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB6_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB6_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB6_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB6_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB6_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB6_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB6_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB6_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB6_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB6_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB6_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB6_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB6_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB6_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB6_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB6_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB6_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB6_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB6_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB6_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB6_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB6_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB6_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB6_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB6_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB6_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB6_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB6_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB6_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB6_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB6_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB6_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB6_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB6_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB6_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB6_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB6_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB6_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB6_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB6_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB6_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB6_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB6_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB6_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB6_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB6_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB6_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB6_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB6_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB6_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB6_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB6_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB6_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB6_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB6_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB6_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB6_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB6_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB6_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB6_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB6_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB6_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB6_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB6_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB6_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB6_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB6_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB6_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB6_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB6_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB6_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB6_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB6_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "GTZC1_MPCBB2" base ad:0x40033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB3" base ad:0x40033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB5" base ad:0x40033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB6" base ad:0x40033C00 group.long 0x0++0x3 line.long 0x0 "MPCBB6_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB6_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB6_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB6_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB6_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB6_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB6_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB6_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB6_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB6_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB6_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB6_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB6_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB6_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB6_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB6_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB6_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB6_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB6_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB6_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB6_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB6_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB6_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB6_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB6_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB6_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB6_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB6_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB6_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB6_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB6_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB6_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB6_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB6_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB6_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB6_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB6_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB6_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB6_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB6_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB6_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB6_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB6_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB6_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB6_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB6_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB6_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB6_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB6_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB6_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB6_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB6_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB6_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB6_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB6_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB6_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB6_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB6_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB6_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB6_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB6_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB6_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB6_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB6_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB6_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB6_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB6_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB6_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB6_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB6_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB6_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB6_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB6_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB6_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB6_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB6_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB6_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB6_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB6_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB6_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB6_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB6_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB6_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB6_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB6_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB6_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB6_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB6_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB6_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB6_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB6_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB6_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB6_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB6_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB6_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB6_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB6_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB6_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB6_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB6_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB6_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB6_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB6_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB6_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB6_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB6_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB6_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_TZIC" base ad:0x50032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 10. "DSIIE,illegal access interrupt enable for DSI" "0,1" bitfld.long 0x4 9. "LTDCIE,illegal access interrupt enable for LTDC" "0,1" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 27. "DCACHE2_REGIE,DCACHE2_REGIE" "0,1" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 25. "GFXMMU_REGIE,GFXMMU_REGIE" "0,1" bitfld.long 0x8 24. "GFXMMUIE,GFXMMUIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 10. "DSIF,illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "LTDCF,illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 27. "DCACHE2_REGF,illegal access flag for DCACHE2 registers" "0,1" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 25. "GFXMMU_REGF,illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "GFXMMUF,illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 10. "CDSIF,clear the illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "CLTDCF,clear the illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 27. "CDCACHE2_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 26. "CHSPI1_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 25. "CGFXMMU_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "CGFXMMUF,clear the illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" newline bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" newline bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "GTZC1_TZIC" base ad:0x40032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 10. "DSIIE,illegal access interrupt enable for DSI" "0,1" bitfld.long 0x4 9. "LTDCIE,illegal access interrupt enable for LTDC" "0,1" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 27. "DCACHE2_REGIE,DCACHE2_REGIE" "0,1" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 25. "GFXMMU_REGIE,GFXMMU_REGIE" "0,1" bitfld.long 0x8 24. "GFXMMUIE,GFXMMUIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 10. "DSIF,illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "LTDCF,illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 27. "DCACHE2_REGF,illegal access flag for DCACHE2 registers" "0,1" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 25. "GFXMMU_REGF,illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "GFXMMUF,illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" newline bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 10. "CDSIF,clear the illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "CLTDCF,clear the illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 27. "CDCACHE2_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 26. "CHSPI1_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 25. "CGFXMMU_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "CGFXMMUF,clear the illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" newline bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" newline bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" newline bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end tree "SEC_GTZC1_TZSC" base ad:0x50032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 10. "DSISEC,DSISEC" "0,1" bitfld.long 0x4 9. "LTDCSEC,LTDCSEC" "0,1" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" newline bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGSEC,DCACHE2_REGSEC" "0,1" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 25. "GFXMMU_REGSEC,GFXMMU_REGSEC" "0,1" bitfld.long 0x8 24. "GFXMMUSEC,GFXMMUSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 10. "DSIPRIV,DSIPRIV" "0,1" bitfld.long 0x4 9. "LTDCPRIV,LTDCPRIV" "0,1" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" newline bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGPRIV,DCACHE2_REGPRIV" "0,1" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 25. "GFXMMU_REGPRIV,GFXMMU_REGPRIV" "0,1" bitfld.long 0x8 24. "GFXMMUPRIV,GFXMMUPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U5F*")) tree "GTZC1_TZSC" base ad:0x40032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 10. "DSISEC,DSISEC" "0,1" bitfld.long 0x4 9. "LTDCSEC,LTDCSEC" "0,1" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" newline bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGSEC,DCACHE2_REGSEC" "0,1" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 25. "GFXMMU_REGSEC,GFXMMU_REGSEC" "0,1" bitfld.long 0x8 24. "GFXMMUSEC,GFXMMUSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 10. "DSIPRIV,DSIPRIV" "0,1" bitfld.long 0x4 9. "LTDCPRIV,LTDCPRIV" "0,1" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" newline bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGPRIV,DCACHE2_REGPRIV" "0,1" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 25. "GFXMMU_REGPRIV,GFXMMU_REGPRIV" "0,1" bitfld.long 0x8 24. "GFXMMUPRIV,GFXMMUPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" newline bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" newline bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end tree "GTZC2_TZIC" base ad:0x46023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "GTZC2_TZSC" base ad:0x46023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "GTZC1_MPCBB1" base ad:0x40032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB1" base ad:0x50032C00 group.long 0x0++0x3 line.long 0x0 "MPCBB1_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB1_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register 1" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB1_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB1_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB1_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB1_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB1_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB1_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB1_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB1_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB1_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB1_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB1_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB1_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB1_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB1_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB1_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB1_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB1_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB1_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB1_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB1_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB1_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB1_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB1_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB1_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB1_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB1_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB1_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB1_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB1_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB1_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB1_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB1_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB1_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB1_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB1_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB1_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB1_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB1_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB1_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB1_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB1_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB1_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB1_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB1_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB1_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB1_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB1_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB1_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB1_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB1_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB1_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB1_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB1_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB1_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB1_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB1_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB1_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB1_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB1_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB1_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB1_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB1_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB1_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB1_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB1_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB1_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB1_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB1_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB1_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB1_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB1_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB1_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB1_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB1_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB1_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB1_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB1_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB1_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB1_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB1_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB1_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB1_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB1_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB1_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB1_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB1_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB1_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB1_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB1_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB1_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB1_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB1_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB1_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB1_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB1_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB1_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB1_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB1_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB1_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB1_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB1_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB1_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB1_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB1_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB1_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB2" base ad:0x50033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB3" base ad:0x50033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC3 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB5" base ad:0x50033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_MPCBB6" base ad:0x50033C00 group.long 0x0++0x3 line.long 0x0 "MPCBB6_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB6_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB6_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB6_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB6_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB6_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB6_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB6_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB6_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB6_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB6_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB6_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB6_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB6_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB6_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB6_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB6_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB6_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB6_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB6_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB6_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB6_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB6_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB6_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB6_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB6_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB6_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB6_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB6_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB6_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB6_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB6_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB6_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB6_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB6_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB6_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB6_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB6_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB6_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB6_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB6_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB6_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB6_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB6_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB6_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB6_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB6_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB6_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB6_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB6_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB6_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB6_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB6_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB6_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB6_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB6_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB6_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB6_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB6_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB6_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB6_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB6_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB6_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB6_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB6_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB6_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB6_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB6_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB6_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB6_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB6_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB6_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB6_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB6_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB6_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB6_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB6_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB6_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB6_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB6_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB6_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB6_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB6_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB6_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB6_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB6_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB6_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB6_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB6_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB6_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB6_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB6_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB6_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB6_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB6_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB6_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB6_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB6_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB6_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB6_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB6_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB6_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB6_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB6_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB6_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB6_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB6_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "GTZC1_MPCBB2" base ad:0x40033000 group.long 0x0++0x3 line.long 0x0 "MPCBB2_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB2_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB2_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB2_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB2_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB2_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB2_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB2_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB2_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB2_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB2_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB2_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB2_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB2_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB2_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB2_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB2_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB2_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB2_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB2_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB2_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB2_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB2_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB2_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB2_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB2_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB2_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB2_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB2_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB2_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB2_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB2_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB2_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB2_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB2_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB2_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB2_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB2_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB2_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB2_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB2_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB2_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB2_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB2_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB2_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB2_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB2_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB2_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB2_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB2_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB2_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB2_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB2_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB2_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB2_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB2_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB2_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB2_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB2_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB2_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB2_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB2_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB2_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB2_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB2_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB2_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB2_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB2_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB2_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB2_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB2_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB2_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB2_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB2_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB2_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB2_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB2_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB2_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB2_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB2_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB2_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB2_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB2_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB2_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB2_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB2_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB2_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB2_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB2_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB2_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB2_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB2_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB2_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB2_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB2_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB2_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB2_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB2_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB2_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB2_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB2_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB2_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB2_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB2_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB2_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB2_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB2_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB3" base ad:0x40033400 group.long 0x0++0x3 line.long 0x0 "MPCBB3_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB3_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB3_CFGLOCK2,GTZC3 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB3_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB3_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB3_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB3_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB3_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB3_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB3_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB3_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB3_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB3_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB3_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB3_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB3_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB3_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB3_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB3_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB3_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB3_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB3_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB3_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB3_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB3_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB3_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB3_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB3_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB3_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB3_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB3_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB3_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB3_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB3_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB3_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB3_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB3_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB3_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB3_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB3_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB3_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB3_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB3_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB3_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB3_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB3_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB3_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB3_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB3_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB3_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB3_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB3_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB3_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB3_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB3_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB3_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB3_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB3_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB3_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB3_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB3_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB3_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB3_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB3_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB3_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB3_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB3_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB3_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB3_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB3_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB3_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB3_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB3_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB3_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB3_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB3_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB3_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB3_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB3_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB3_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB3_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB3_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB3_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB3_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB3_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB3_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB3_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB3_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB3_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB3_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB3_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB3_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB3_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB3_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB3_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB3_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB3_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB3_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB3_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB3_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB3_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB3_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB3_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB3_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB3_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB3_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB3_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB5" base ad:0x40033800 group.long 0x0++0x3 line.long 0x0 "MPCBB5_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB5_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB5_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB5_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB5_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB5_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB5_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB5_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB5_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB5_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB5_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB5_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB5_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB5_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB5_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB5_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB5_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB5_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB5_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB5_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB5_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB5_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB5_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB5_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB5_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB5_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB5_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB5_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB5_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB5_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB5_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB5_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB5_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB5_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB5_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB5_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB5_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB5_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB5_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB5_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB5_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB5_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB5_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB5_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB5_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB5_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB5_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB5_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB5_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB5_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB5_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB5_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB5_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB5_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB5_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB5_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB5_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB5_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB5_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB5_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB5_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB5_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB5_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB5_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB5_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB5_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB5_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB5_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB5_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB5_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB5_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB5_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB5_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB5_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB5_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB5_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB5_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB5_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB5_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB5_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB5_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB5_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB5_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB5_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB5_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB5_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB5_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB5_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB5_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB5_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB5_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB5_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB5_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB5_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB5_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB5_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB5_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB5_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB5_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB5_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB5_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB5_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB5_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB5_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB5_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB5_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB5_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "GTZC1_MPCBB6" base ad:0x40033C00 group.long 0x0++0x3 line.long 0x0 "MPCBB6_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x7 line.long 0x0 "MPCBB6_CFGLOCK1,GTZC1 SRAMz MPCBB configuration lock register" bitfld.long 0x0 31. "SPLCK31,SPLCK31" "0,1" bitfld.long 0x0 30. "SPLCK30,SPLCK30" "0,1" bitfld.long 0x0 29. "SPLCK29,SPLCK29" "0,1" bitfld.long 0x0 28. "SPLCK28,SPLCK28" "0,1" bitfld.long 0x0 27. "SPLCK27,SPLCK27" "0,1" bitfld.long 0x0 26. "SPLCK26,SPLCK26" "0,1" bitfld.long 0x0 25. "SPLCK25,SPLCK25" "0,1" bitfld.long 0x0 24. "SPLCK24,SPLCK24" "0,1" newline bitfld.long 0x0 23. "SPLCK23,SPLCK23" "0,1" bitfld.long 0x0 22. "SPLCK22,SPLCK22" "0,1" bitfld.long 0x0 21. "SPLCK21,SPLCK21" "0,1" bitfld.long 0x0 20. "SPLCK20,SPLCK20" "0,1" bitfld.long 0x0 19. "SPLCK19,SPLCK19" "0,1" bitfld.long 0x0 18. "SPLCK18,SPLCK18" "0,1" bitfld.long 0x0 17. "SPLCK17,SPLCK17" "0,1" bitfld.long 0x0 16. "SPLCK16,SPLCK16" "0,1" newline bitfld.long 0x0 15. "SPLCK15,SPLCK15" "0,1" bitfld.long 0x0 14. "SPLCK14,SPLCK14" "0,1" bitfld.long 0x0 13. "SPLCK13,SPLCK13" "0,1" bitfld.long 0x0 12. "SPLCK12,SPLCK12" "0,1" bitfld.long 0x0 11. "SPLCK11,SPLCK11" "0,1" bitfld.long 0x0 10. "SPLCK10,SPLCK10" "0,1" bitfld.long 0x0 9. "SPLCK9,SPLCK9" "0,1" bitfld.long 0x0 8. "SPLCK8,SPLCK8" "0,1" newline bitfld.long 0x0 7. "SPLCK7,SPLCK7" "0,1" bitfld.long 0x0 6. "SPLCK6,SPLCK6" "0,1" bitfld.long 0x0 5. "SPLCK5,SPLCK5" "0,1" bitfld.long 0x0 4. "SPLCK4,SPLCK4" "0,1" bitfld.long 0x0 3. "SPLCK3,SPLCK3" "0,1" bitfld.long 0x0 2. "SPLCK2,SPLCK2" "0,1" bitfld.long 0x0 1. "SPLCK1,SPLCK1" "0,1" bitfld.long 0x0 0. "SPLCK0,SPLCK0" "0,1" line.long 0x4 "MPCBB6_CFGLOCK2,GTZC1 SRAMz MPCBB configuration lock register 2" bitfld.long 0x4 19. "SPLCK51,SPLCK51" "0,1" bitfld.long 0x4 18. "SPLCK50,SPLCK50" "0,1" bitfld.long 0x4 17. "SPLCK49,SPLCK49" "0,1" bitfld.long 0x4 16. "SPLCK48,SPLCK48" "0,1" bitfld.long 0x4 15. "SPLCK47,SPLCK47" "0,1" bitfld.long 0x4 14. "SPLCK46,SPLCK46" "0,1" bitfld.long 0x4 13. "SPLCK45,SPLCK45" "0,1" bitfld.long 0x4 12. "SPLCK44,SPLCK44" "0,1" newline bitfld.long 0x4 11. "SPLCK43,SPLCK43" "0,1" bitfld.long 0x4 10. "SPLCK42,SPLCK42" "0,1" bitfld.long 0x4 9. "SPLCK41,SPLCK41" "0,1" bitfld.long 0x4 8. "SPLCK40,SPLCK40" "0,1" bitfld.long 0x4 7. "SPLCK39,SPLCK39" "0,1" bitfld.long 0x4 6. "SPLCK38,SPLCK38" "0,1" bitfld.long 0x4 5. "SPLCK37,SPLCK37" "0,1" bitfld.long 0x4 4. "SPLCK36,SPLCK36" "0,1" newline bitfld.long 0x4 3. "SPLCK35,SPLCK35" "0,1" bitfld.long 0x4 2. "SPLCK34,SPLCK34" "0,1" bitfld.long 0x4 1. "SPLCK33,SPLCK33" "0,1" bitfld.long 0x4 0. "SPLCK32,SPLCK32" "0,1" group.long 0x100++0xCF line.long 0x0 "MPCBB6_SECCFGR0,MPCBBx security configuration for super-block x register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "MPCBB6_SECCFGR1,MPCBBx security configuration for super-block x register" bitfld.long 0x4 31. "SEC31,SEC31" "0,1" bitfld.long 0x4 30. "SEC30,SEC30" "0,1" bitfld.long 0x4 29. "SEC29,SEC29" "0,1" bitfld.long 0x4 28. "SEC28,SEC28" "0,1" bitfld.long 0x4 27. "SEC27,SEC27" "0,1" bitfld.long 0x4 26. "SEC26,SEC26" "0,1" bitfld.long 0x4 25. "SEC25,SEC25" "0,1" bitfld.long 0x4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4 23. "SEC23,SEC23" "0,1" bitfld.long 0x4 22. "SEC22,SEC22" "0,1" bitfld.long 0x4 21. "SEC21,SEC21" "0,1" bitfld.long 0x4 20. "SEC20,SEC20" "0,1" bitfld.long 0x4 19. "SEC19,SEC19" "0,1" bitfld.long 0x4 18. "SEC18,SEC18" "0,1" bitfld.long 0x4 17. "SEC17,SEC17" "0,1" bitfld.long 0x4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4 15. "SEC15,SEC15" "0,1" bitfld.long 0x4 14. "SEC14,SEC14" "0,1" bitfld.long 0x4 13. "SEC13,SEC13" "0,1" bitfld.long 0x4 12. "SEC12,SEC12" "0,1" bitfld.long 0x4 11. "SEC11,SEC11" "0,1" bitfld.long 0x4 10. "SEC10,SEC10" "0,1" bitfld.long 0x4 9. "SEC9,SEC9" "0,1" bitfld.long 0x4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4 7. "SEC7,SEC7" "0,1" bitfld.long 0x4 6. "SEC6,SEC6" "0,1" bitfld.long 0x4 5. "SEC5,SEC5" "0,1" bitfld.long 0x4 4. "SEC4,SEC4" "0,1" bitfld.long 0x4 3. "SEC3,SEC3" "0,1" bitfld.long 0x4 2. "SEC2,SEC2" "0,1" bitfld.long 0x4 1. "SEC1,SEC1" "0,1" bitfld.long 0x4 0. "SEC0,SEC0" "0,1" line.long 0x8 "MPCBB6_SECCFGR2,MPCBBx security configuration for super-block x register" bitfld.long 0x8 31. "SEC31,SEC31" "0,1" bitfld.long 0x8 30. "SEC30,SEC30" "0,1" bitfld.long 0x8 29. "SEC29,SEC29" "0,1" bitfld.long 0x8 28. "SEC28,SEC28" "0,1" bitfld.long 0x8 27. "SEC27,SEC27" "0,1" bitfld.long 0x8 26. "SEC26,SEC26" "0,1" bitfld.long 0x8 25. "SEC25,SEC25" "0,1" bitfld.long 0x8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8 23. "SEC23,SEC23" "0,1" bitfld.long 0x8 22. "SEC22,SEC22" "0,1" bitfld.long 0x8 21. "SEC21,SEC21" "0,1" bitfld.long 0x8 20. "SEC20,SEC20" "0,1" bitfld.long 0x8 19. "SEC19,SEC19" "0,1" bitfld.long 0x8 18. "SEC18,SEC18" "0,1" bitfld.long 0x8 17. "SEC17,SEC17" "0,1" bitfld.long 0x8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8 15. "SEC15,SEC15" "0,1" bitfld.long 0x8 14. "SEC14,SEC14" "0,1" bitfld.long 0x8 13. "SEC13,SEC13" "0,1" bitfld.long 0x8 12. "SEC12,SEC12" "0,1" bitfld.long 0x8 11. "SEC11,SEC11" "0,1" bitfld.long 0x8 10. "SEC10,SEC10" "0,1" bitfld.long 0x8 9. "SEC9,SEC9" "0,1" bitfld.long 0x8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8 7. "SEC7,SEC7" "0,1" bitfld.long 0x8 6. "SEC6,SEC6" "0,1" bitfld.long 0x8 5. "SEC5,SEC5" "0,1" bitfld.long 0x8 4. "SEC4,SEC4" "0,1" bitfld.long 0x8 3. "SEC3,SEC3" "0,1" bitfld.long 0x8 2. "SEC2,SEC2" "0,1" bitfld.long 0x8 1. "SEC1,SEC1" "0,1" bitfld.long 0x8 0. "SEC0,SEC0" "0,1" line.long 0xC "MPCBB6_SECCFGR3,MPCBBx security configuration for super-block x register" bitfld.long 0xC 31. "SEC31,SEC31" "0,1" bitfld.long 0xC 30. "SEC30,SEC30" "0,1" bitfld.long 0xC 29. "SEC29,SEC29" "0,1" bitfld.long 0xC 28. "SEC28,SEC28" "0,1" bitfld.long 0xC 27. "SEC27,SEC27" "0,1" bitfld.long 0xC 26. "SEC26,SEC26" "0,1" bitfld.long 0xC 25. "SEC25,SEC25" "0,1" bitfld.long 0xC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC 23. "SEC23,SEC23" "0,1" bitfld.long 0xC 22. "SEC22,SEC22" "0,1" bitfld.long 0xC 21. "SEC21,SEC21" "0,1" bitfld.long 0xC 20. "SEC20,SEC20" "0,1" bitfld.long 0xC 19. "SEC19,SEC19" "0,1" bitfld.long 0xC 18. "SEC18,SEC18" "0,1" bitfld.long 0xC 17. "SEC17,SEC17" "0,1" bitfld.long 0xC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC 15. "SEC15,SEC15" "0,1" bitfld.long 0xC 14. "SEC14,SEC14" "0,1" bitfld.long 0xC 13. "SEC13,SEC13" "0,1" bitfld.long 0xC 12. "SEC12,SEC12" "0,1" bitfld.long 0xC 11. "SEC11,SEC11" "0,1" bitfld.long 0xC 10. "SEC10,SEC10" "0,1" bitfld.long 0xC 9. "SEC9,SEC9" "0,1" bitfld.long 0xC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC 7. "SEC7,SEC7" "0,1" bitfld.long 0xC 6. "SEC6,SEC6" "0,1" bitfld.long 0xC 5. "SEC5,SEC5" "0,1" bitfld.long 0xC 4. "SEC4,SEC4" "0,1" bitfld.long 0xC 3. "SEC3,SEC3" "0,1" bitfld.long 0xC 2. "SEC2,SEC2" "0,1" bitfld.long 0xC 1. "SEC1,SEC1" "0,1" bitfld.long 0xC 0. "SEC0,SEC0" "0,1" line.long 0x10 "MPCBB6_SECCFGR4,MPCBBx security configuration for super-block x register" bitfld.long 0x10 31. "SEC31,SEC31" "0,1" bitfld.long 0x10 30. "SEC30,SEC30" "0,1" bitfld.long 0x10 29. "SEC29,SEC29" "0,1" bitfld.long 0x10 28. "SEC28,SEC28" "0,1" bitfld.long 0x10 27. "SEC27,SEC27" "0,1" bitfld.long 0x10 26. "SEC26,SEC26" "0,1" bitfld.long 0x10 25. "SEC25,SEC25" "0,1" bitfld.long 0x10 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x10 23. "SEC23,SEC23" "0,1" bitfld.long 0x10 22. "SEC22,SEC22" "0,1" bitfld.long 0x10 21. "SEC21,SEC21" "0,1" bitfld.long 0x10 20. "SEC20,SEC20" "0,1" bitfld.long 0x10 19. "SEC19,SEC19" "0,1" bitfld.long 0x10 18. "SEC18,SEC18" "0,1" bitfld.long 0x10 17. "SEC17,SEC17" "0,1" bitfld.long 0x10 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x10 15. "SEC15,SEC15" "0,1" bitfld.long 0x10 14. "SEC14,SEC14" "0,1" bitfld.long 0x10 13. "SEC13,SEC13" "0,1" bitfld.long 0x10 12. "SEC12,SEC12" "0,1" bitfld.long 0x10 11. "SEC11,SEC11" "0,1" bitfld.long 0x10 10. "SEC10,SEC10" "0,1" bitfld.long 0x10 9. "SEC9,SEC9" "0,1" bitfld.long 0x10 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x10 7. "SEC7,SEC7" "0,1" bitfld.long 0x10 6. "SEC6,SEC6" "0,1" bitfld.long 0x10 5. "SEC5,SEC5" "0,1" bitfld.long 0x10 4. "SEC4,SEC4" "0,1" bitfld.long 0x10 3. "SEC3,SEC3" "0,1" bitfld.long 0x10 2. "SEC2,SEC2" "0,1" bitfld.long 0x10 1. "SEC1,SEC1" "0,1" bitfld.long 0x10 0. "SEC0,SEC0" "0,1" line.long 0x14 "MPCBB6_SECCFGR5,MPCBBx security configuration for super-block x register" bitfld.long 0x14 31. "SEC31,SEC31" "0,1" bitfld.long 0x14 30. "SEC30,SEC30" "0,1" bitfld.long 0x14 29. "SEC29,SEC29" "0,1" bitfld.long 0x14 28. "SEC28,SEC28" "0,1" bitfld.long 0x14 27. "SEC27,SEC27" "0,1" bitfld.long 0x14 26. "SEC26,SEC26" "0,1" bitfld.long 0x14 25. "SEC25,SEC25" "0,1" bitfld.long 0x14 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x14 23. "SEC23,SEC23" "0,1" bitfld.long 0x14 22. "SEC22,SEC22" "0,1" bitfld.long 0x14 21. "SEC21,SEC21" "0,1" bitfld.long 0x14 20. "SEC20,SEC20" "0,1" bitfld.long 0x14 19. "SEC19,SEC19" "0,1" bitfld.long 0x14 18. "SEC18,SEC18" "0,1" bitfld.long 0x14 17. "SEC17,SEC17" "0,1" bitfld.long 0x14 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x14 15. "SEC15,SEC15" "0,1" bitfld.long 0x14 14. "SEC14,SEC14" "0,1" bitfld.long 0x14 13. "SEC13,SEC13" "0,1" bitfld.long 0x14 12. "SEC12,SEC12" "0,1" bitfld.long 0x14 11. "SEC11,SEC11" "0,1" bitfld.long 0x14 10. "SEC10,SEC10" "0,1" bitfld.long 0x14 9. "SEC9,SEC9" "0,1" bitfld.long 0x14 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x14 7. "SEC7,SEC7" "0,1" bitfld.long 0x14 6. "SEC6,SEC6" "0,1" bitfld.long 0x14 5. "SEC5,SEC5" "0,1" bitfld.long 0x14 4. "SEC4,SEC4" "0,1" bitfld.long 0x14 3. "SEC3,SEC3" "0,1" bitfld.long 0x14 2. "SEC2,SEC2" "0,1" bitfld.long 0x14 1. "SEC1,SEC1" "0,1" bitfld.long 0x14 0. "SEC0,SEC0" "0,1" line.long 0x18 "MPCBB6_SECCFGR6,MPCBBx security configuration for super-block x register" bitfld.long 0x18 31. "SEC31,SEC31" "0,1" bitfld.long 0x18 30. "SEC30,SEC30" "0,1" bitfld.long 0x18 29. "SEC29,SEC29" "0,1" bitfld.long 0x18 28. "SEC28,SEC28" "0,1" bitfld.long 0x18 27. "SEC27,SEC27" "0,1" bitfld.long 0x18 26. "SEC26,SEC26" "0,1" bitfld.long 0x18 25. "SEC25,SEC25" "0,1" bitfld.long 0x18 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x18 23. "SEC23,SEC23" "0,1" bitfld.long 0x18 22. "SEC22,SEC22" "0,1" bitfld.long 0x18 21. "SEC21,SEC21" "0,1" bitfld.long 0x18 20. "SEC20,SEC20" "0,1" bitfld.long 0x18 19. "SEC19,SEC19" "0,1" bitfld.long 0x18 18. "SEC18,SEC18" "0,1" bitfld.long 0x18 17. "SEC17,SEC17" "0,1" bitfld.long 0x18 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x18 15. "SEC15,SEC15" "0,1" bitfld.long 0x18 14. "SEC14,SEC14" "0,1" bitfld.long 0x18 13. "SEC13,SEC13" "0,1" bitfld.long 0x18 12. "SEC12,SEC12" "0,1" bitfld.long 0x18 11. "SEC11,SEC11" "0,1" bitfld.long 0x18 10. "SEC10,SEC10" "0,1" bitfld.long 0x18 9. "SEC9,SEC9" "0,1" bitfld.long 0x18 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x18 7. "SEC7,SEC7" "0,1" bitfld.long 0x18 6. "SEC6,SEC6" "0,1" bitfld.long 0x18 5. "SEC5,SEC5" "0,1" bitfld.long 0x18 4. "SEC4,SEC4" "0,1" bitfld.long 0x18 3. "SEC3,SEC3" "0,1" bitfld.long 0x18 2. "SEC2,SEC2" "0,1" bitfld.long 0x18 1. "SEC1,SEC1" "0,1" bitfld.long 0x18 0. "SEC0,SEC0" "0,1" line.long 0x1C "MPCBB6_SECCFGR7,MPCBBx security configuration for super-block x register" bitfld.long 0x1C 31. "SEC31,SEC31" "0,1" bitfld.long 0x1C 30. "SEC30,SEC30" "0,1" bitfld.long 0x1C 29. "SEC29,SEC29" "0,1" bitfld.long 0x1C 28. "SEC28,SEC28" "0,1" bitfld.long 0x1C 27. "SEC27,SEC27" "0,1" bitfld.long 0x1C 26. "SEC26,SEC26" "0,1" bitfld.long 0x1C 25. "SEC25,SEC25" "0,1" bitfld.long 0x1C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x1C 23. "SEC23,SEC23" "0,1" bitfld.long 0x1C 22. "SEC22,SEC22" "0,1" bitfld.long 0x1C 21. "SEC21,SEC21" "0,1" bitfld.long 0x1C 20. "SEC20,SEC20" "0,1" bitfld.long 0x1C 19. "SEC19,SEC19" "0,1" bitfld.long 0x1C 18. "SEC18,SEC18" "0,1" bitfld.long 0x1C 17. "SEC17,SEC17" "0,1" bitfld.long 0x1C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x1C 15. "SEC15,SEC15" "0,1" bitfld.long 0x1C 14. "SEC14,SEC14" "0,1" bitfld.long 0x1C 13. "SEC13,SEC13" "0,1" bitfld.long 0x1C 12. "SEC12,SEC12" "0,1" bitfld.long 0x1C 11. "SEC11,SEC11" "0,1" bitfld.long 0x1C 10. "SEC10,SEC10" "0,1" bitfld.long 0x1C 9. "SEC9,SEC9" "0,1" bitfld.long 0x1C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x1C 7. "SEC7,SEC7" "0,1" bitfld.long 0x1C 6. "SEC6,SEC6" "0,1" bitfld.long 0x1C 5. "SEC5,SEC5" "0,1" bitfld.long 0x1C 4. "SEC4,SEC4" "0,1" bitfld.long 0x1C 3. "SEC3,SEC3" "0,1" bitfld.long 0x1C 2. "SEC2,SEC2" "0,1" bitfld.long 0x1C 1. "SEC1,SEC1" "0,1" bitfld.long 0x1C 0. "SEC0,SEC0" "0,1" line.long 0x20 "MPCBB6_SECCFGR8,MPCBBx security configuration for super-block x register" bitfld.long 0x20 31. "SEC31,SEC31" "0,1" bitfld.long 0x20 30. "SEC30,SEC30" "0,1" bitfld.long 0x20 29. "SEC29,SEC29" "0,1" bitfld.long 0x20 28. "SEC28,SEC28" "0,1" bitfld.long 0x20 27. "SEC27,SEC27" "0,1" bitfld.long 0x20 26. "SEC26,SEC26" "0,1" bitfld.long 0x20 25. "SEC25,SEC25" "0,1" bitfld.long 0x20 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x20 23. "SEC23,SEC23" "0,1" bitfld.long 0x20 22. "SEC22,SEC22" "0,1" bitfld.long 0x20 21. "SEC21,SEC21" "0,1" bitfld.long 0x20 20. "SEC20,SEC20" "0,1" bitfld.long 0x20 19. "SEC19,SEC19" "0,1" bitfld.long 0x20 18. "SEC18,SEC18" "0,1" bitfld.long 0x20 17. "SEC17,SEC17" "0,1" bitfld.long 0x20 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x20 15. "SEC15,SEC15" "0,1" bitfld.long 0x20 14. "SEC14,SEC14" "0,1" bitfld.long 0x20 13. "SEC13,SEC13" "0,1" bitfld.long 0x20 12. "SEC12,SEC12" "0,1" bitfld.long 0x20 11. "SEC11,SEC11" "0,1" bitfld.long 0x20 10. "SEC10,SEC10" "0,1" bitfld.long 0x20 9. "SEC9,SEC9" "0,1" bitfld.long 0x20 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x20 7. "SEC7,SEC7" "0,1" bitfld.long 0x20 6. "SEC6,SEC6" "0,1" bitfld.long 0x20 5. "SEC5,SEC5" "0,1" bitfld.long 0x20 4. "SEC4,SEC4" "0,1" bitfld.long 0x20 3. "SEC3,SEC3" "0,1" bitfld.long 0x20 2. "SEC2,SEC2" "0,1" bitfld.long 0x20 1. "SEC1,SEC1" "0,1" bitfld.long 0x20 0. "SEC0,SEC0" "0,1" line.long 0x24 "MPCBB6_SECCFGR9,MPCBBx security configuration for super-block x register" bitfld.long 0x24 31. "SEC31,SEC31" "0,1" bitfld.long 0x24 30. "SEC30,SEC30" "0,1" bitfld.long 0x24 29. "SEC29,SEC29" "0,1" bitfld.long 0x24 28. "SEC28,SEC28" "0,1" bitfld.long 0x24 27. "SEC27,SEC27" "0,1" bitfld.long 0x24 26. "SEC26,SEC26" "0,1" bitfld.long 0x24 25. "SEC25,SEC25" "0,1" bitfld.long 0x24 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x24 23. "SEC23,SEC23" "0,1" bitfld.long 0x24 22. "SEC22,SEC22" "0,1" bitfld.long 0x24 21. "SEC21,SEC21" "0,1" bitfld.long 0x24 20. "SEC20,SEC20" "0,1" bitfld.long 0x24 19. "SEC19,SEC19" "0,1" bitfld.long 0x24 18. "SEC18,SEC18" "0,1" bitfld.long 0x24 17. "SEC17,SEC17" "0,1" bitfld.long 0x24 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x24 15. "SEC15,SEC15" "0,1" bitfld.long 0x24 14. "SEC14,SEC14" "0,1" bitfld.long 0x24 13. "SEC13,SEC13" "0,1" bitfld.long 0x24 12. "SEC12,SEC12" "0,1" bitfld.long 0x24 11. "SEC11,SEC11" "0,1" bitfld.long 0x24 10. "SEC10,SEC10" "0,1" bitfld.long 0x24 9. "SEC9,SEC9" "0,1" bitfld.long 0x24 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x24 7. "SEC7,SEC7" "0,1" bitfld.long 0x24 6. "SEC6,SEC6" "0,1" bitfld.long 0x24 5. "SEC5,SEC5" "0,1" bitfld.long 0x24 4. "SEC4,SEC4" "0,1" bitfld.long 0x24 3. "SEC3,SEC3" "0,1" bitfld.long 0x24 2. "SEC2,SEC2" "0,1" bitfld.long 0x24 1. "SEC1,SEC1" "0,1" bitfld.long 0x24 0. "SEC0,SEC0" "0,1" line.long 0x28 "MPCBB6_SECCFGR10,MPCBBx security configuration for super-block x register" bitfld.long 0x28 31. "SEC31,SEC31" "0,1" bitfld.long 0x28 30. "SEC30,SEC30" "0,1" bitfld.long 0x28 29. "SEC29,SEC29" "0,1" bitfld.long 0x28 28. "SEC28,SEC28" "0,1" bitfld.long 0x28 27. "SEC27,SEC27" "0,1" bitfld.long 0x28 26. "SEC26,SEC26" "0,1" bitfld.long 0x28 25. "SEC25,SEC25" "0,1" bitfld.long 0x28 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x28 23. "SEC23,SEC23" "0,1" bitfld.long 0x28 22. "SEC22,SEC22" "0,1" bitfld.long 0x28 21. "SEC21,SEC21" "0,1" bitfld.long 0x28 20. "SEC20,SEC20" "0,1" bitfld.long 0x28 19. "SEC19,SEC19" "0,1" bitfld.long 0x28 18. "SEC18,SEC18" "0,1" bitfld.long 0x28 17. "SEC17,SEC17" "0,1" bitfld.long 0x28 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x28 15. "SEC15,SEC15" "0,1" bitfld.long 0x28 14. "SEC14,SEC14" "0,1" bitfld.long 0x28 13. "SEC13,SEC13" "0,1" bitfld.long 0x28 12. "SEC12,SEC12" "0,1" bitfld.long 0x28 11. "SEC11,SEC11" "0,1" bitfld.long 0x28 10. "SEC10,SEC10" "0,1" bitfld.long 0x28 9. "SEC9,SEC9" "0,1" bitfld.long 0x28 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x28 7. "SEC7,SEC7" "0,1" bitfld.long 0x28 6. "SEC6,SEC6" "0,1" bitfld.long 0x28 5. "SEC5,SEC5" "0,1" bitfld.long 0x28 4. "SEC4,SEC4" "0,1" bitfld.long 0x28 3. "SEC3,SEC3" "0,1" bitfld.long 0x28 2. "SEC2,SEC2" "0,1" bitfld.long 0x28 1. "SEC1,SEC1" "0,1" bitfld.long 0x28 0. "SEC0,SEC0" "0,1" line.long 0x2C "MPCBB6_SECCFGR11,MPCBBx security configuration for super-block x register" bitfld.long 0x2C 31. "SEC31,SEC31" "0,1" bitfld.long 0x2C 30. "SEC30,SEC30" "0,1" bitfld.long 0x2C 29. "SEC29,SEC29" "0,1" bitfld.long 0x2C 28. "SEC28,SEC28" "0,1" bitfld.long 0x2C 27. "SEC27,SEC27" "0,1" bitfld.long 0x2C 26. "SEC26,SEC26" "0,1" bitfld.long 0x2C 25. "SEC25,SEC25" "0,1" bitfld.long 0x2C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x2C 23. "SEC23,SEC23" "0,1" bitfld.long 0x2C 22. "SEC22,SEC22" "0,1" bitfld.long 0x2C 21. "SEC21,SEC21" "0,1" bitfld.long 0x2C 20. "SEC20,SEC20" "0,1" bitfld.long 0x2C 19. "SEC19,SEC19" "0,1" bitfld.long 0x2C 18. "SEC18,SEC18" "0,1" bitfld.long 0x2C 17. "SEC17,SEC17" "0,1" bitfld.long 0x2C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x2C 15. "SEC15,SEC15" "0,1" bitfld.long 0x2C 14. "SEC14,SEC14" "0,1" bitfld.long 0x2C 13. "SEC13,SEC13" "0,1" bitfld.long 0x2C 12. "SEC12,SEC12" "0,1" bitfld.long 0x2C 11. "SEC11,SEC11" "0,1" bitfld.long 0x2C 10. "SEC10,SEC10" "0,1" bitfld.long 0x2C 9. "SEC9,SEC9" "0,1" bitfld.long 0x2C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x2C 7. "SEC7,SEC7" "0,1" bitfld.long 0x2C 6. "SEC6,SEC6" "0,1" bitfld.long 0x2C 5. "SEC5,SEC5" "0,1" bitfld.long 0x2C 4. "SEC4,SEC4" "0,1" bitfld.long 0x2C 3. "SEC3,SEC3" "0,1" bitfld.long 0x2C 2. "SEC2,SEC2" "0,1" bitfld.long 0x2C 1. "SEC1,SEC1" "0,1" bitfld.long 0x2C 0. "SEC0,SEC0" "0,1" line.long 0x30 "MPCBB6_SECCFGR12,MPCBBx security configuration for super-block x register" bitfld.long 0x30 31. "SEC31,SEC31" "0,1" bitfld.long 0x30 30. "SEC30,SEC30" "0,1" bitfld.long 0x30 29. "SEC29,SEC29" "0,1" bitfld.long 0x30 28. "SEC28,SEC28" "0,1" bitfld.long 0x30 27. "SEC27,SEC27" "0,1" bitfld.long 0x30 26. "SEC26,SEC26" "0,1" bitfld.long 0x30 25. "SEC25,SEC25" "0,1" bitfld.long 0x30 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x30 23. "SEC23,SEC23" "0,1" bitfld.long 0x30 22. "SEC22,SEC22" "0,1" bitfld.long 0x30 21. "SEC21,SEC21" "0,1" bitfld.long 0x30 20. "SEC20,SEC20" "0,1" bitfld.long 0x30 19. "SEC19,SEC19" "0,1" bitfld.long 0x30 18. "SEC18,SEC18" "0,1" bitfld.long 0x30 17. "SEC17,SEC17" "0,1" bitfld.long 0x30 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x30 15. "SEC15,SEC15" "0,1" bitfld.long 0x30 14. "SEC14,SEC14" "0,1" bitfld.long 0x30 13. "SEC13,SEC13" "0,1" bitfld.long 0x30 12. "SEC12,SEC12" "0,1" bitfld.long 0x30 11. "SEC11,SEC11" "0,1" bitfld.long 0x30 10. "SEC10,SEC10" "0,1" bitfld.long 0x30 9. "SEC9,SEC9" "0,1" bitfld.long 0x30 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x30 7. "SEC7,SEC7" "0,1" bitfld.long 0x30 6. "SEC6,SEC6" "0,1" bitfld.long 0x30 5. "SEC5,SEC5" "0,1" bitfld.long 0x30 4. "SEC4,SEC4" "0,1" bitfld.long 0x30 3. "SEC3,SEC3" "0,1" bitfld.long 0x30 2. "SEC2,SEC2" "0,1" bitfld.long 0x30 1. "SEC1,SEC1" "0,1" bitfld.long 0x30 0. "SEC0,SEC0" "0,1" line.long 0x34 "MPCBB6_SECCFGR13,MPCBBx security configuration for super-block x register" bitfld.long 0x34 31. "SEC31,SEC31" "0,1" bitfld.long 0x34 30. "SEC30,SEC30" "0,1" bitfld.long 0x34 29. "SEC29,SEC29" "0,1" bitfld.long 0x34 28. "SEC28,SEC28" "0,1" bitfld.long 0x34 27. "SEC27,SEC27" "0,1" bitfld.long 0x34 26. "SEC26,SEC26" "0,1" bitfld.long 0x34 25. "SEC25,SEC25" "0,1" bitfld.long 0x34 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x34 23. "SEC23,SEC23" "0,1" bitfld.long 0x34 22. "SEC22,SEC22" "0,1" bitfld.long 0x34 21. "SEC21,SEC21" "0,1" bitfld.long 0x34 20. "SEC20,SEC20" "0,1" bitfld.long 0x34 19. "SEC19,SEC19" "0,1" bitfld.long 0x34 18. "SEC18,SEC18" "0,1" bitfld.long 0x34 17. "SEC17,SEC17" "0,1" bitfld.long 0x34 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x34 15. "SEC15,SEC15" "0,1" bitfld.long 0x34 14. "SEC14,SEC14" "0,1" bitfld.long 0x34 13. "SEC13,SEC13" "0,1" bitfld.long 0x34 12. "SEC12,SEC12" "0,1" bitfld.long 0x34 11. "SEC11,SEC11" "0,1" bitfld.long 0x34 10. "SEC10,SEC10" "0,1" bitfld.long 0x34 9. "SEC9,SEC9" "0,1" bitfld.long 0x34 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x34 7. "SEC7,SEC7" "0,1" bitfld.long 0x34 6. "SEC6,SEC6" "0,1" bitfld.long 0x34 5. "SEC5,SEC5" "0,1" bitfld.long 0x34 4. "SEC4,SEC4" "0,1" bitfld.long 0x34 3. "SEC3,SEC3" "0,1" bitfld.long 0x34 2. "SEC2,SEC2" "0,1" bitfld.long 0x34 1. "SEC1,SEC1" "0,1" bitfld.long 0x34 0. "SEC0,SEC0" "0,1" line.long 0x38 "MPCBB6_SECCFGR14,MPCBBx security configuration for super-block x register" bitfld.long 0x38 31. "SEC31,SEC31" "0,1" bitfld.long 0x38 30. "SEC30,SEC30" "0,1" bitfld.long 0x38 29. "SEC29,SEC29" "0,1" bitfld.long 0x38 28. "SEC28,SEC28" "0,1" bitfld.long 0x38 27. "SEC27,SEC27" "0,1" bitfld.long 0x38 26. "SEC26,SEC26" "0,1" bitfld.long 0x38 25. "SEC25,SEC25" "0,1" bitfld.long 0x38 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x38 23. "SEC23,SEC23" "0,1" bitfld.long 0x38 22. "SEC22,SEC22" "0,1" bitfld.long 0x38 21. "SEC21,SEC21" "0,1" bitfld.long 0x38 20. "SEC20,SEC20" "0,1" bitfld.long 0x38 19. "SEC19,SEC19" "0,1" bitfld.long 0x38 18. "SEC18,SEC18" "0,1" bitfld.long 0x38 17. "SEC17,SEC17" "0,1" bitfld.long 0x38 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x38 15. "SEC15,SEC15" "0,1" bitfld.long 0x38 14. "SEC14,SEC14" "0,1" bitfld.long 0x38 13. "SEC13,SEC13" "0,1" bitfld.long 0x38 12. "SEC12,SEC12" "0,1" bitfld.long 0x38 11. "SEC11,SEC11" "0,1" bitfld.long 0x38 10. "SEC10,SEC10" "0,1" bitfld.long 0x38 9. "SEC9,SEC9" "0,1" bitfld.long 0x38 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x38 7. "SEC7,SEC7" "0,1" bitfld.long 0x38 6. "SEC6,SEC6" "0,1" bitfld.long 0x38 5. "SEC5,SEC5" "0,1" bitfld.long 0x38 4. "SEC4,SEC4" "0,1" bitfld.long 0x38 3. "SEC3,SEC3" "0,1" bitfld.long 0x38 2. "SEC2,SEC2" "0,1" bitfld.long 0x38 1. "SEC1,SEC1" "0,1" bitfld.long 0x38 0. "SEC0,SEC0" "0,1" line.long 0x3C "MPCBB6_SECCFGR15,MPCBBx security configuration for super-block x register" bitfld.long 0x3C 31. "SEC31,SEC31" "0,1" bitfld.long 0x3C 30. "SEC30,SEC30" "0,1" bitfld.long 0x3C 29. "SEC29,SEC29" "0,1" bitfld.long 0x3C 28. "SEC28,SEC28" "0,1" bitfld.long 0x3C 27. "SEC27,SEC27" "0,1" bitfld.long 0x3C 26. "SEC26,SEC26" "0,1" bitfld.long 0x3C 25. "SEC25,SEC25" "0,1" bitfld.long 0x3C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x3C 23. "SEC23,SEC23" "0,1" bitfld.long 0x3C 22. "SEC22,SEC22" "0,1" bitfld.long 0x3C 21. "SEC21,SEC21" "0,1" bitfld.long 0x3C 20. "SEC20,SEC20" "0,1" bitfld.long 0x3C 19. "SEC19,SEC19" "0,1" bitfld.long 0x3C 18. "SEC18,SEC18" "0,1" bitfld.long 0x3C 17. "SEC17,SEC17" "0,1" bitfld.long 0x3C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x3C 15. "SEC15,SEC15" "0,1" bitfld.long 0x3C 14. "SEC14,SEC14" "0,1" bitfld.long 0x3C 13. "SEC13,SEC13" "0,1" bitfld.long 0x3C 12. "SEC12,SEC12" "0,1" bitfld.long 0x3C 11. "SEC11,SEC11" "0,1" bitfld.long 0x3C 10. "SEC10,SEC10" "0,1" bitfld.long 0x3C 9. "SEC9,SEC9" "0,1" bitfld.long 0x3C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x3C 7. "SEC7,SEC7" "0,1" bitfld.long 0x3C 6. "SEC6,SEC6" "0,1" bitfld.long 0x3C 5. "SEC5,SEC5" "0,1" bitfld.long 0x3C 4. "SEC4,SEC4" "0,1" bitfld.long 0x3C 3. "SEC3,SEC3" "0,1" bitfld.long 0x3C 2. "SEC2,SEC2" "0,1" bitfld.long 0x3C 1. "SEC1,SEC1" "0,1" bitfld.long 0x3C 0. "SEC0,SEC0" "0,1" line.long 0x40 "MPCBB6_SECCFGR16,MPCBBx security configuration for super-block x register" bitfld.long 0x40 31. "SEC31,SEC31" "0,1" bitfld.long 0x40 30. "SEC30,SEC30" "0,1" bitfld.long 0x40 29. "SEC29,SEC29" "0,1" bitfld.long 0x40 28. "SEC28,SEC28" "0,1" bitfld.long 0x40 27. "SEC27,SEC27" "0,1" bitfld.long 0x40 26. "SEC26,SEC26" "0,1" bitfld.long 0x40 25. "SEC25,SEC25" "0,1" bitfld.long 0x40 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x40 23. "SEC23,SEC23" "0,1" bitfld.long 0x40 22. "SEC22,SEC22" "0,1" bitfld.long 0x40 21. "SEC21,SEC21" "0,1" bitfld.long 0x40 20. "SEC20,SEC20" "0,1" bitfld.long 0x40 19. "SEC19,SEC19" "0,1" bitfld.long 0x40 18. "SEC18,SEC18" "0,1" bitfld.long 0x40 17. "SEC17,SEC17" "0,1" bitfld.long 0x40 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x40 15. "SEC15,SEC15" "0,1" bitfld.long 0x40 14. "SEC14,SEC14" "0,1" bitfld.long 0x40 13. "SEC13,SEC13" "0,1" bitfld.long 0x40 12. "SEC12,SEC12" "0,1" bitfld.long 0x40 11. "SEC11,SEC11" "0,1" bitfld.long 0x40 10. "SEC10,SEC10" "0,1" bitfld.long 0x40 9. "SEC9,SEC9" "0,1" bitfld.long 0x40 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x40 7. "SEC7,SEC7" "0,1" bitfld.long 0x40 6. "SEC6,SEC6" "0,1" bitfld.long 0x40 5. "SEC5,SEC5" "0,1" bitfld.long 0x40 4. "SEC4,SEC4" "0,1" bitfld.long 0x40 3. "SEC3,SEC3" "0,1" bitfld.long 0x40 2. "SEC2,SEC2" "0,1" bitfld.long 0x40 1. "SEC1,SEC1" "0,1" bitfld.long 0x40 0. "SEC0,SEC0" "0,1" line.long 0x44 "MPCBB6_SECCFGR17,MPCBBx security configuration for super-block x register" bitfld.long 0x44 31. "SEC31,SEC31" "0,1" bitfld.long 0x44 30. "SEC30,SEC30" "0,1" bitfld.long 0x44 29. "SEC29,SEC29" "0,1" bitfld.long 0x44 28. "SEC28,SEC28" "0,1" bitfld.long 0x44 27. "SEC27,SEC27" "0,1" bitfld.long 0x44 26. "SEC26,SEC26" "0,1" bitfld.long 0x44 25. "SEC25,SEC25" "0,1" bitfld.long 0x44 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x44 23. "SEC23,SEC23" "0,1" bitfld.long 0x44 22. "SEC22,SEC22" "0,1" bitfld.long 0x44 21. "SEC21,SEC21" "0,1" bitfld.long 0x44 20. "SEC20,SEC20" "0,1" bitfld.long 0x44 19. "SEC19,SEC19" "0,1" bitfld.long 0x44 18. "SEC18,SEC18" "0,1" bitfld.long 0x44 17. "SEC17,SEC17" "0,1" bitfld.long 0x44 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x44 15. "SEC15,SEC15" "0,1" bitfld.long 0x44 14. "SEC14,SEC14" "0,1" bitfld.long 0x44 13. "SEC13,SEC13" "0,1" bitfld.long 0x44 12. "SEC12,SEC12" "0,1" bitfld.long 0x44 11. "SEC11,SEC11" "0,1" bitfld.long 0x44 10. "SEC10,SEC10" "0,1" bitfld.long 0x44 9. "SEC9,SEC9" "0,1" bitfld.long 0x44 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x44 7. "SEC7,SEC7" "0,1" bitfld.long 0x44 6. "SEC6,SEC6" "0,1" bitfld.long 0x44 5. "SEC5,SEC5" "0,1" bitfld.long 0x44 4. "SEC4,SEC4" "0,1" bitfld.long 0x44 3. "SEC3,SEC3" "0,1" bitfld.long 0x44 2. "SEC2,SEC2" "0,1" bitfld.long 0x44 1. "SEC1,SEC1" "0,1" bitfld.long 0x44 0. "SEC0,SEC0" "0,1" line.long 0x48 "MPCBB6_SECCFGR18,MPCBBx security configuration for super-block x register" bitfld.long 0x48 31. "SEC31,SEC31" "0,1" bitfld.long 0x48 30. "SEC30,SEC30" "0,1" bitfld.long 0x48 29. "SEC29,SEC29" "0,1" bitfld.long 0x48 28. "SEC28,SEC28" "0,1" bitfld.long 0x48 27. "SEC27,SEC27" "0,1" bitfld.long 0x48 26. "SEC26,SEC26" "0,1" bitfld.long 0x48 25. "SEC25,SEC25" "0,1" bitfld.long 0x48 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x48 23. "SEC23,SEC23" "0,1" bitfld.long 0x48 22. "SEC22,SEC22" "0,1" bitfld.long 0x48 21. "SEC21,SEC21" "0,1" bitfld.long 0x48 20. "SEC20,SEC20" "0,1" bitfld.long 0x48 19. "SEC19,SEC19" "0,1" bitfld.long 0x48 18. "SEC18,SEC18" "0,1" bitfld.long 0x48 17. "SEC17,SEC17" "0,1" bitfld.long 0x48 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x48 15. "SEC15,SEC15" "0,1" bitfld.long 0x48 14. "SEC14,SEC14" "0,1" bitfld.long 0x48 13. "SEC13,SEC13" "0,1" bitfld.long 0x48 12. "SEC12,SEC12" "0,1" bitfld.long 0x48 11. "SEC11,SEC11" "0,1" bitfld.long 0x48 10. "SEC10,SEC10" "0,1" bitfld.long 0x48 9. "SEC9,SEC9" "0,1" bitfld.long 0x48 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x48 7. "SEC7,SEC7" "0,1" bitfld.long 0x48 6. "SEC6,SEC6" "0,1" bitfld.long 0x48 5. "SEC5,SEC5" "0,1" bitfld.long 0x48 4. "SEC4,SEC4" "0,1" bitfld.long 0x48 3. "SEC3,SEC3" "0,1" bitfld.long 0x48 2. "SEC2,SEC2" "0,1" bitfld.long 0x48 1. "SEC1,SEC1" "0,1" bitfld.long 0x48 0. "SEC0,SEC0" "0,1" line.long 0x4C "MPCBB6_SECCFGR19,MPCBBx security configuration for super-block x register" bitfld.long 0x4C 31. "SEC31,SEC31" "0,1" bitfld.long 0x4C 30. "SEC30,SEC30" "0,1" bitfld.long 0x4C 29. "SEC29,SEC29" "0,1" bitfld.long 0x4C 28. "SEC28,SEC28" "0,1" bitfld.long 0x4C 27. "SEC27,SEC27" "0,1" bitfld.long 0x4C 26. "SEC26,SEC26" "0,1" bitfld.long 0x4C 25. "SEC25,SEC25" "0,1" bitfld.long 0x4C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x4C 23. "SEC23,SEC23" "0,1" bitfld.long 0x4C 22. "SEC22,SEC22" "0,1" bitfld.long 0x4C 21. "SEC21,SEC21" "0,1" bitfld.long 0x4C 20. "SEC20,SEC20" "0,1" bitfld.long 0x4C 19. "SEC19,SEC19" "0,1" bitfld.long 0x4C 18. "SEC18,SEC18" "0,1" bitfld.long 0x4C 17. "SEC17,SEC17" "0,1" bitfld.long 0x4C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x4C 15. "SEC15,SEC15" "0,1" bitfld.long 0x4C 14. "SEC14,SEC14" "0,1" bitfld.long 0x4C 13. "SEC13,SEC13" "0,1" bitfld.long 0x4C 12. "SEC12,SEC12" "0,1" bitfld.long 0x4C 11. "SEC11,SEC11" "0,1" bitfld.long 0x4C 10. "SEC10,SEC10" "0,1" bitfld.long 0x4C 9. "SEC9,SEC9" "0,1" bitfld.long 0x4C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x4C 7. "SEC7,SEC7" "0,1" bitfld.long 0x4C 6. "SEC6,SEC6" "0,1" bitfld.long 0x4C 5. "SEC5,SEC5" "0,1" bitfld.long 0x4C 4. "SEC4,SEC4" "0,1" bitfld.long 0x4C 3. "SEC3,SEC3" "0,1" bitfld.long 0x4C 2. "SEC2,SEC2" "0,1" bitfld.long 0x4C 1. "SEC1,SEC1" "0,1" bitfld.long 0x4C 0. "SEC0,SEC0" "0,1" line.long 0x50 "MPCBB6_SECCFGR20,MPCBBx security configuration for super-block x register" bitfld.long 0x50 31. "SEC31,SEC31" "0,1" bitfld.long 0x50 30. "SEC30,SEC30" "0,1" bitfld.long 0x50 29. "SEC29,SEC29" "0,1" bitfld.long 0x50 28. "SEC28,SEC28" "0,1" bitfld.long 0x50 27. "SEC27,SEC27" "0,1" bitfld.long 0x50 26. "SEC26,SEC26" "0,1" bitfld.long 0x50 25. "SEC25,SEC25" "0,1" bitfld.long 0x50 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x50 23. "SEC23,SEC23" "0,1" bitfld.long 0x50 22. "SEC22,SEC22" "0,1" bitfld.long 0x50 21. "SEC21,SEC21" "0,1" bitfld.long 0x50 20. "SEC20,SEC20" "0,1" bitfld.long 0x50 19. "SEC19,SEC19" "0,1" bitfld.long 0x50 18. "SEC18,SEC18" "0,1" bitfld.long 0x50 17. "SEC17,SEC17" "0,1" bitfld.long 0x50 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x50 15. "SEC15,SEC15" "0,1" bitfld.long 0x50 14. "SEC14,SEC14" "0,1" bitfld.long 0x50 13. "SEC13,SEC13" "0,1" bitfld.long 0x50 12. "SEC12,SEC12" "0,1" bitfld.long 0x50 11. "SEC11,SEC11" "0,1" bitfld.long 0x50 10. "SEC10,SEC10" "0,1" bitfld.long 0x50 9. "SEC9,SEC9" "0,1" bitfld.long 0x50 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x50 7. "SEC7,SEC7" "0,1" bitfld.long 0x50 6. "SEC6,SEC6" "0,1" bitfld.long 0x50 5. "SEC5,SEC5" "0,1" bitfld.long 0x50 4. "SEC4,SEC4" "0,1" bitfld.long 0x50 3. "SEC3,SEC3" "0,1" bitfld.long 0x50 2. "SEC2,SEC2" "0,1" bitfld.long 0x50 1. "SEC1,SEC1" "0,1" bitfld.long 0x50 0. "SEC0,SEC0" "0,1" line.long 0x54 "MPCBB6_SECCFGR21,MPCBBx security configuration for super-block x register" bitfld.long 0x54 31. "SEC31,SEC31" "0,1" bitfld.long 0x54 30. "SEC30,SEC30" "0,1" bitfld.long 0x54 29. "SEC29,SEC29" "0,1" bitfld.long 0x54 28. "SEC28,SEC28" "0,1" bitfld.long 0x54 27. "SEC27,SEC27" "0,1" bitfld.long 0x54 26. "SEC26,SEC26" "0,1" bitfld.long 0x54 25. "SEC25,SEC25" "0,1" bitfld.long 0x54 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x54 23. "SEC23,SEC23" "0,1" bitfld.long 0x54 22. "SEC22,SEC22" "0,1" bitfld.long 0x54 21. "SEC21,SEC21" "0,1" bitfld.long 0x54 20. "SEC20,SEC20" "0,1" bitfld.long 0x54 19. "SEC19,SEC19" "0,1" bitfld.long 0x54 18. "SEC18,SEC18" "0,1" bitfld.long 0x54 17. "SEC17,SEC17" "0,1" bitfld.long 0x54 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x54 15. "SEC15,SEC15" "0,1" bitfld.long 0x54 14. "SEC14,SEC14" "0,1" bitfld.long 0x54 13. "SEC13,SEC13" "0,1" bitfld.long 0x54 12. "SEC12,SEC12" "0,1" bitfld.long 0x54 11. "SEC11,SEC11" "0,1" bitfld.long 0x54 10. "SEC10,SEC10" "0,1" bitfld.long 0x54 9. "SEC9,SEC9" "0,1" bitfld.long 0x54 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x54 7. "SEC7,SEC7" "0,1" bitfld.long 0x54 6. "SEC6,SEC6" "0,1" bitfld.long 0x54 5. "SEC5,SEC5" "0,1" bitfld.long 0x54 4. "SEC4,SEC4" "0,1" bitfld.long 0x54 3. "SEC3,SEC3" "0,1" bitfld.long 0x54 2. "SEC2,SEC2" "0,1" bitfld.long 0x54 1. "SEC1,SEC1" "0,1" bitfld.long 0x54 0. "SEC0,SEC0" "0,1" line.long 0x58 "MPCBB6_SECCFGR22,MPCBBx security configuration for super-block x register" bitfld.long 0x58 31. "SEC31,SEC31" "0,1" bitfld.long 0x58 30. "SEC30,SEC30" "0,1" bitfld.long 0x58 29. "SEC29,SEC29" "0,1" bitfld.long 0x58 28. "SEC28,SEC28" "0,1" bitfld.long 0x58 27. "SEC27,SEC27" "0,1" bitfld.long 0x58 26. "SEC26,SEC26" "0,1" bitfld.long 0x58 25. "SEC25,SEC25" "0,1" bitfld.long 0x58 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x58 23. "SEC23,SEC23" "0,1" bitfld.long 0x58 22. "SEC22,SEC22" "0,1" bitfld.long 0x58 21. "SEC21,SEC21" "0,1" bitfld.long 0x58 20. "SEC20,SEC20" "0,1" bitfld.long 0x58 19. "SEC19,SEC19" "0,1" bitfld.long 0x58 18. "SEC18,SEC18" "0,1" bitfld.long 0x58 17. "SEC17,SEC17" "0,1" bitfld.long 0x58 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x58 15. "SEC15,SEC15" "0,1" bitfld.long 0x58 14. "SEC14,SEC14" "0,1" bitfld.long 0x58 13. "SEC13,SEC13" "0,1" bitfld.long 0x58 12. "SEC12,SEC12" "0,1" bitfld.long 0x58 11. "SEC11,SEC11" "0,1" bitfld.long 0x58 10. "SEC10,SEC10" "0,1" bitfld.long 0x58 9. "SEC9,SEC9" "0,1" bitfld.long 0x58 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x58 7. "SEC7,SEC7" "0,1" bitfld.long 0x58 6. "SEC6,SEC6" "0,1" bitfld.long 0x58 5. "SEC5,SEC5" "0,1" bitfld.long 0x58 4. "SEC4,SEC4" "0,1" bitfld.long 0x58 3. "SEC3,SEC3" "0,1" bitfld.long 0x58 2. "SEC2,SEC2" "0,1" bitfld.long 0x58 1. "SEC1,SEC1" "0,1" bitfld.long 0x58 0. "SEC0,SEC0" "0,1" line.long 0x5C "MPCBB6_SECCFGR23,MPCBBx security configuration for super-block x register" bitfld.long 0x5C 31. "SEC31,SEC31" "0,1" bitfld.long 0x5C 30. "SEC30,SEC30" "0,1" bitfld.long 0x5C 29. "SEC29,SEC29" "0,1" bitfld.long 0x5C 28. "SEC28,SEC28" "0,1" bitfld.long 0x5C 27. "SEC27,SEC27" "0,1" bitfld.long 0x5C 26. "SEC26,SEC26" "0,1" bitfld.long 0x5C 25. "SEC25,SEC25" "0,1" bitfld.long 0x5C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x5C 23. "SEC23,SEC23" "0,1" bitfld.long 0x5C 22. "SEC22,SEC22" "0,1" bitfld.long 0x5C 21. "SEC21,SEC21" "0,1" bitfld.long 0x5C 20. "SEC20,SEC20" "0,1" bitfld.long 0x5C 19. "SEC19,SEC19" "0,1" bitfld.long 0x5C 18. "SEC18,SEC18" "0,1" bitfld.long 0x5C 17. "SEC17,SEC17" "0,1" bitfld.long 0x5C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x5C 15. "SEC15,SEC15" "0,1" bitfld.long 0x5C 14. "SEC14,SEC14" "0,1" bitfld.long 0x5C 13. "SEC13,SEC13" "0,1" bitfld.long 0x5C 12. "SEC12,SEC12" "0,1" bitfld.long 0x5C 11. "SEC11,SEC11" "0,1" bitfld.long 0x5C 10. "SEC10,SEC10" "0,1" bitfld.long 0x5C 9. "SEC9,SEC9" "0,1" bitfld.long 0x5C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x5C 7. "SEC7,SEC7" "0,1" bitfld.long 0x5C 6. "SEC6,SEC6" "0,1" bitfld.long 0x5C 5. "SEC5,SEC5" "0,1" bitfld.long 0x5C 4. "SEC4,SEC4" "0,1" bitfld.long 0x5C 3. "SEC3,SEC3" "0,1" bitfld.long 0x5C 2. "SEC2,SEC2" "0,1" bitfld.long 0x5C 1. "SEC1,SEC1" "0,1" bitfld.long 0x5C 0. "SEC0,SEC0" "0,1" line.long 0x60 "MPCBB6_SECCFGR24,MPCBBx security configuration for super-block x register" bitfld.long 0x60 31. "SEC31,SEC31" "0,1" bitfld.long 0x60 30. "SEC30,SEC30" "0,1" bitfld.long 0x60 29. "SEC29,SEC29" "0,1" bitfld.long 0x60 28. "SEC28,SEC28" "0,1" bitfld.long 0x60 27. "SEC27,SEC27" "0,1" bitfld.long 0x60 26. "SEC26,SEC26" "0,1" bitfld.long 0x60 25. "SEC25,SEC25" "0,1" bitfld.long 0x60 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x60 23. "SEC23,SEC23" "0,1" bitfld.long 0x60 22. "SEC22,SEC22" "0,1" bitfld.long 0x60 21. "SEC21,SEC21" "0,1" bitfld.long 0x60 20. "SEC20,SEC20" "0,1" bitfld.long 0x60 19. "SEC19,SEC19" "0,1" bitfld.long 0x60 18. "SEC18,SEC18" "0,1" bitfld.long 0x60 17. "SEC17,SEC17" "0,1" bitfld.long 0x60 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x60 15. "SEC15,SEC15" "0,1" bitfld.long 0x60 14. "SEC14,SEC14" "0,1" bitfld.long 0x60 13. "SEC13,SEC13" "0,1" bitfld.long 0x60 12. "SEC12,SEC12" "0,1" bitfld.long 0x60 11. "SEC11,SEC11" "0,1" bitfld.long 0x60 10. "SEC10,SEC10" "0,1" bitfld.long 0x60 9. "SEC9,SEC9" "0,1" bitfld.long 0x60 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x60 7. "SEC7,SEC7" "0,1" bitfld.long 0x60 6. "SEC6,SEC6" "0,1" bitfld.long 0x60 5. "SEC5,SEC5" "0,1" bitfld.long 0x60 4. "SEC4,SEC4" "0,1" bitfld.long 0x60 3. "SEC3,SEC3" "0,1" bitfld.long 0x60 2. "SEC2,SEC2" "0,1" bitfld.long 0x60 1. "SEC1,SEC1" "0,1" bitfld.long 0x60 0. "SEC0,SEC0" "0,1" line.long 0x64 "MPCBB6_SECCFGR25,MPCBBx security configuration for super-block x register" bitfld.long 0x64 31. "SEC31,SEC31" "0,1" bitfld.long 0x64 30. "SEC30,SEC30" "0,1" bitfld.long 0x64 29. "SEC29,SEC29" "0,1" bitfld.long 0x64 28. "SEC28,SEC28" "0,1" bitfld.long 0x64 27. "SEC27,SEC27" "0,1" bitfld.long 0x64 26. "SEC26,SEC26" "0,1" bitfld.long 0x64 25. "SEC25,SEC25" "0,1" bitfld.long 0x64 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x64 23. "SEC23,SEC23" "0,1" bitfld.long 0x64 22. "SEC22,SEC22" "0,1" bitfld.long 0x64 21. "SEC21,SEC21" "0,1" bitfld.long 0x64 20. "SEC20,SEC20" "0,1" bitfld.long 0x64 19. "SEC19,SEC19" "0,1" bitfld.long 0x64 18. "SEC18,SEC18" "0,1" bitfld.long 0x64 17. "SEC17,SEC17" "0,1" bitfld.long 0x64 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x64 15. "SEC15,SEC15" "0,1" bitfld.long 0x64 14. "SEC14,SEC14" "0,1" bitfld.long 0x64 13. "SEC13,SEC13" "0,1" bitfld.long 0x64 12. "SEC12,SEC12" "0,1" bitfld.long 0x64 11. "SEC11,SEC11" "0,1" bitfld.long 0x64 10. "SEC10,SEC10" "0,1" bitfld.long 0x64 9. "SEC9,SEC9" "0,1" bitfld.long 0x64 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x64 7. "SEC7,SEC7" "0,1" bitfld.long 0x64 6. "SEC6,SEC6" "0,1" bitfld.long 0x64 5. "SEC5,SEC5" "0,1" bitfld.long 0x64 4. "SEC4,SEC4" "0,1" bitfld.long 0x64 3. "SEC3,SEC3" "0,1" bitfld.long 0x64 2. "SEC2,SEC2" "0,1" bitfld.long 0x64 1. "SEC1,SEC1" "0,1" bitfld.long 0x64 0. "SEC0,SEC0" "0,1" line.long 0x68 "MPCBB6_SECCFGR26,MPCBBx security configuration for super-block x register" bitfld.long 0x68 31. "SEC31,SEC31" "0,1" bitfld.long 0x68 30. "SEC30,SEC30" "0,1" bitfld.long 0x68 29. "SEC29,SEC29" "0,1" bitfld.long 0x68 28. "SEC28,SEC28" "0,1" bitfld.long 0x68 27. "SEC27,SEC27" "0,1" bitfld.long 0x68 26. "SEC26,SEC26" "0,1" bitfld.long 0x68 25. "SEC25,SEC25" "0,1" bitfld.long 0x68 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x68 23. "SEC23,SEC23" "0,1" bitfld.long 0x68 22. "SEC22,SEC22" "0,1" bitfld.long 0x68 21. "SEC21,SEC21" "0,1" bitfld.long 0x68 20. "SEC20,SEC20" "0,1" bitfld.long 0x68 19. "SEC19,SEC19" "0,1" bitfld.long 0x68 18. "SEC18,SEC18" "0,1" bitfld.long 0x68 17. "SEC17,SEC17" "0,1" bitfld.long 0x68 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x68 15. "SEC15,SEC15" "0,1" bitfld.long 0x68 14. "SEC14,SEC14" "0,1" bitfld.long 0x68 13. "SEC13,SEC13" "0,1" bitfld.long 0x68 12. "SEC12,SEC12" "0,1" bitfld.long 0x68 11. "SEC11,SEC11" "0,1" bitfld.long 0x68 10. "SEC10,SEC10" "0,1" bitfld.long 0x68 9. "SEC9,SEC9" "0,1" bitfld.long 0x68 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x68 7. "SEC7,SEC7" "0,1" bitfld.long 0x68 6. "SEC6,SEC6" "0,1" bitfld.long 0x68 5. "SEC5,SEC5" "0,1" bitfld.long 0x68 4. "SEC4,SEC4" "0,1" bitfld.long 0x68 3. "SEC3,SEC3" "0,1" bitfld.long 0x68 2. "SEC2,SEC2" "0,1" bitfld.long 0x68 1. "SEC1,SEC1" "0,1" bitfld.long 0x68 0. "SEC0,SEC0" "0,1" line.long 0x6C "MPCBB6_SECCFGR27,MPCBBx security configuration for super-block x register" bitfld.long 0x6C 31. "SEC31,SEC31" "0,1" bitfld.long 0x6C 30. "SEC30,SEC30" "0,1" bitfld.long 0x6C 29. "SEC29,SEC29" "0,1" bitfld.long 0x6C 28. "SEC28,SEC28" "0,1" bitfld.long 0x6C 27. "SEC27,SEC27" "0,1" bitfld.long 0x6C 26. "SEC26,SEC26" "0,1" bitfld.long 0x6C 25. "SEC25,SEC25" "0,1" bitfld.long 0x6C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x6C 23. "SEC23,SEC23" "0,1" bitfld.long 0x6C 22. "SEC22,SEC22" "0,1" bitfld.long 0x6C 21. "SEC21,SEC21" "0,1" bitfld.long 0x6C 20. "SEC20,SEC20" "0,1" bitfld.long 0x6C 19. "SEC19,SEC19" "0,1" bitfld.long 0x6C 18. "SEC18,SEC18" "0,1" bitfld.long 0x6C 17. "SEC17,SEC17" "0,1" bitfld.long 0x6C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x6C 15. "SEC15,SEC15" "0,1" bitfld.long 0x6C 14. "SEC14,SEC14" "0,1" bitfld.long 0x6C 13. "SEC13,SEC13" "0,1" bitfld.long 0x6C 12. "SEC12,SEC12" "0,1" bitfld.long 0x6C 11. "SEC11,SEC11" "0,1" bitfld.long 0x6C 10. "SEC10,SEC10" "0,1" bitfld.long 0x6C 9. "SEC9,SEC9" "0,1" bitfld.long 0x6C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x6C 7. "SEC7,SEC7" "0,1" bitfld.long 0x6C 6. "SEC6,SEC6" "0,1" bitfld.long 0x6C 5. "SEC5,SEC5" "0,1" bitfld.long 0x6C 4. "SEC4,SEC4" "0,1" bitfld.long 0x6C 3. "SEC3,SEC3" "0,1" bitfld.long 0x6C 2. "SEC2,SEC2" "0,1" bitfld.long 0x6C 1. "SEC1,SEC1" "0,1" bitfld.long 0x6C 0. "SEC0,SEC0" "0,1" line.long 0x70 "MPCBB6_SECCFGR28,MPCBBx security configuration for super-block x register" bitfld.long 0x70 31. "SEC31,SEC31" "0,1" bitfld.long 0x70 30. "SEC30,SEC30" "0,1" bitfld.long 0x70 29. "SEC29,SEC29" "0,1" bitfld.long 0x70 28. "SEC28,SEC28" "0,1" bitfld.long 0x70 27. "SEC27,SEC27" "0,1" bitfld.long 0x70 26. "SEC26,SEC26" "0,1" bitfld.long 0x70 25. "SEC25,SEC25" "0,1" bitfld.long 0x70 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x70 23. "SEC23,SEC23" "0,1" bitfld.long 0x70 22. "SEC22,SEC22" "0,1" bitfld.long 0x70 21. "SEC21,SEC21" "0,1" bitfld.long 0x70 20. "SEC20,SEC20" "0,1" bitfld.long 0x70 19. "SEC19,SEC19" "0,1" bitfld.long 0x70 18. "SEC18,SEC18" "0,1" bitfld.long 0x70 17. "SEC17,SEC17" "0,1" bitfld.long 0x70 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x70 15. "SEC15,SEC15" "0,1" bitfld.long 0x70 14. "SEC14,SEC14" "0,1" bitfld.long 0x70 13. "SEC13,SEC13" "0,1" bitfld.long 0x70 12. "SEC12,SEC12" "0,1" bitfld.long 0x70 11. "SEC11,SEC11" "0,1" bitfld.long 0x70 10. "SEC10,SEC10" "0,1" bitfld.long 0x70 9. "SEC9,SEC9" "0,1" bitfld.long 0x70 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x70 7. "SEC7,SEC7" "0,1" bitfld.long 0x70 6. "SEC6,SEC6" "0,1" bitfld.long 0x70 5. "SEC5,SEC5" "0,1" bitfld.long 0x70 4. "SEC4,SEC4" "0,1" bitfld.long 0x70 3. "SEC3,SEC3" "0,1" bitfld.long 0x70 2. "SEC2,SEC2" "0,1" bitfld.long 0x70 1. "SEC1,SEC1" "0,1" bitfld.long 0x70 0. "SEC0,SEC0" "0,1" line.long 0x74 "MPCBB6_SECCFGR29,MPCBBx security configuration for super-block x register" bitfld.long 0x74 31. "SEC31,SEC31" "0,1" bitfld.long 0x74 30. "SEC30,SEC30" "0,1" bitfld.long 0x74 29. "SEC29,SEC29" "0,1" bitfld.long 0x74 28. "SEC28,SEC28" "0,1" bitfld.long 0x74 27. "SEC27,SEC27" "0,1" bitfld.long 0x74 26. "SEC26,SEC26" "0,1" bitfld.long 0x74 25. "SEC25,SEC25" "0,1" bitfld.long 0x74 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x74 23. "SEC23,SEC23" "0,1" bitfld.long 0x74 22. "SEC22,SEC22" "0,1" bitfld.long 0x74 21. "SEC21,SEC21" "0,1" bitfld.long 0x74 20. "SEC20,SEC20" "0,1" bitfld.long 0x74 19. "SEC19,SEC19" "0,1" bitfld.long 0x74 18. "SEC18,SEC18" "0,1" bitfld.long 0x74 17. "SEC17,SEC17" "0,1" bitfld.long 0x74 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x74 15. "SEC15,SEC15" "0,1" bitfld.long 0x74 14. "SEC14,SEC14" "0,1" bitfld.long 0x74 13. "SEC13,SEC13" "0,1" bitfld.long 0x74 12. "SEC12,SEC12" "0,1" bitfld.long 0x74 11. "SEC11,SEC11" "0,1" bitfld.long 0x74 10. "SEC10,SEC10" "0,1" bitfld.long 0x74 9. "SEC9,SEC9" "0,1" bitfld.long 0x74 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x74 7. "SEC7,SEC7" "0,1" bitfld.long 0x74 6. "SEC6,SEC6" "0,1" bitfld.long 0x74 5. "SEC5,SEC5" "0,1" bitfld.long 0x74 4. "SEC4,SEC4" "0,1" bitfld.long 0x74 3. "SEC3,SEC3" "0,1" bitfld.long 0x74 2. "SEC2,SEC2" "0,1" bitfld.long 0x74 1. "SEC1,SEC1" "0,1" bitfld.long 0x74 0. "SEC0,SEC0" "0,1" line.long 0x78 "MPCBB6_SECCFGR30,MPCBBx security configuration for super-block x register" bitfld.long 0x78 31. "SEC31,SEC31" "0,1" bitfld.long 0x78 30. "SEC30,SEC30" "0,1" bitfld.long 0x78 29. "SEC29,SEC29" "0,1" bitfld.long 0x78 28. "SEC28,SEC28" "0,1" bitfld.long 0x78 27. "SEC27,SEC27" "0,1" bitfld.long 0x78 26. "SEC26,SEC26" "0,1" bitfld.long 0x78 25. "SEC25,SEC25" "0,1" bitfld.long 0x78 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x78 23. "SEC23,SEC23" "0,1" bitfld.long 0x78 22. "SEC22,SEC22" "0,1" bitfld.long 0x78 21. "SEC21,SEC21" "0,1" bitfld.long 0x78 20. "SEC20,SEC20" "0,1" bitfld.long 0x78 19. "SEC19,SEC19" "0,1" bitfld.long 0x78 18. "SEC18,SEC18" "0,1" bitfld.long 0x78 17. "SEC17,SEC17" "0,1" bitfld.long 0x78 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x78 15. "SEC15,SEC15" "0,1" bitfld.long 0x78 14. "SEC14,SEC14" "0,1" bitfld.long 0x78 13. "SEC13,SEC13" "0,1" bitfld.long 0x78 12. "SEC12,SEC12" "0,1" bitfld.long 0x78 11. "SEC11,SEC11" "0,1" bitfld.long 0x78 10. "SEC10,SEC10" "0,1" bitfld.long 0x78 9. "SEC9,SEC9" "0,1" bitfld.long 0x78 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x78 7. "SEC7,SEC7" "0,1" bitfld.long 0x78 6. "SEC6,SEC6" "0,1" bitfld.long 0x78 5. "SEC5,SEC5" "0,1" bitfld.long 0x78 4. "SEC4,SEC4" "0,1" bitfld.long 0x78 3. "SEC3,SEC3" "0,1" bitfld.long 0x78 2. "SEC2,SEC2" "0,1" bitfld.long 0x78 1. "SEC1,SEC1" "0,1" bitfld.long 0x78 0. "SEC0,SEC0" "0,1" line.long 0x7C "MPCBB6_SECCFGR31,MPCBBx security configuration for super-block x register" bitfld.long 0x7C 31. "SEC31,SEC31" "0,1" bitfld.long 0x7C 30. "SEC30,SEC30" "0,1" bitfld.long 0x7C 29. "SEC29,SEC29" "0,1" bitfld.long 0x7C 28. "SEC28,SEC28" "0,1" bitfld.long 0x7C 27. "SEC27,SEC27" "0,1" bitfld.long 0x7C 26. "SEC26,SEC26" "0,1" bitfld.long 0x7C 25. "SEC25,SEC25" "0,1" bitfld.long 0x7C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x7C 23. "SEC23,SEC23" "0,1" bitfld.long 0x7C 22. "SEC22,SEC22" "0,1" bitfld.long 0x7C 21. "SEC21,SEC21" "0,1" bitfld.long 0x7C 20. "SEC20,SEC20" "0,1" bitfld.long 0x7C 19. "SEC19,SEC19" "0,1" bitfld.long 0x7C 18. "SEC18,SEC18" "0,1" bitfld.long 0x7C 17. "SEC17,SEC17" "0,1" bitfld.long 0x7C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x7C 15. "SEC15,SEC15" "0,1" bitfld.long 0x7C 14. "SEC14,SEC14" "0,1" bitfld.long 0x7C 13. "SEC13,SEC13" "0,1" bitfld.long 0x7C 12. "SEC12,SEC12" "0,1" bitfld.long 0x7C 11. "SEC11,SEC11" "0,1" bitfld.long 0x7C 10. "SEC10,SEC10" "0,1" bitfld.long 0x7C 9. "SEC9,SEC9" "0,1" bitfld.long 0x7C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x7C 7. "SEC7,SEC7" "0,1" bitfld.long 0x7C 6. "SEC6,SEC6" "0,1" bitfld.long 0x7C 5. "SEC5,SEC5" "0,1" bitfld.long 0x7C 4. "SEC4,SEC4" "0,1" bitfld.long 0x7C 3. "SEC3,SEC3" "0,1" bitfld.long 0x7C 2. "SEC2,SEC2" "0,1" bitfld.long 0x7C 1. "SEC1,SEC1" "0,1" bitfld.long 0x7C 0. "SEC0,SEC0" "0,1" line.long 0x80 "MPCBB6_SECCFGR32,MPCBBx security configuration for super-block x register" bitfld.long 0x80 31. "SEC31,SEC31" "0,1" bitfld.long 0x80 30. "SEC30,SEC30" "0,1" bitfld.long 0x80 29. "SEC29,SEC29" "0,1" bitfld.long 0x80 28. "SEC28,SEC28" "0,1" bitfld.long 0x80 27. "SEC27,SEC27" "0,1" bitfld.long 0x80 26. "SEC26,SEC26" "0,1" bitfld.long 0x80 25. "SEC25,SEC25" "0,1" bitfld.long 0x80 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x80 23. "SEC23,SEC23" "0,1" bitfld.long 0x80 22. "SEC22,SEC22" "0,1" bitfld.long 0x80 21. "SEC21,SEC21" "0,1" bitfld.long 0x80 20. "SEC20,SEC20" "0,1" bitfld.long 0x80 19. "SEC19,SEC19" "0,1" bitfld.long 0x80 18. "SEC18,SEC18" "0,1" bitfld.long 0x80 17. "SEC17,SEC17" "0,1" bitfld.long 0x80 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x80 15. "SEC15,SEC15" "0,1" bitfld.long 0x80 14. "SEC14,SEC14" "0,1" bitfld.long 0x80 13. "SEC13,SEC13" "0,1" bitfld.long 0x80 12. "SEC12,SEC12" "0,1" bitfld.long 0x80 11. "SEC11,SEC11" "0,1" bitfld.long 0x80 10. "SEC10,SEC10" "0,1" bitfld.long 0x80 9. "SEC9,SEC9" "0,1" bitfld.long 0x80 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x80 7. "SEC7,SEC7" "0,1" bitfld.long 0x80 6. "SEC6,SEC6" "0,1" bitfld.long 0x80 5. "SEC5,SEC5" "0,1" bitfld.long 0x80 4. "SEC4,SEC4" "0,1" bitfld.long 0x80 3. "SEC3,SEC3" "0,1" bitfld.long 0x80 2. "SEC2,SEC2" "0,1" bitfld.long 0x80 1. "SEC1,SEC1" "0,1" bitfld.long 0x80 0. "SEC0,SEC0" "0,1" line.long 0x84 "MPCBB6_SECCFGR33,MPCBBx security configuration for super-block x register" bitfld.long 0x84 31. "SEC31,SEC31" "0,1" bitfld.long 0x84 30. "SEC30,SEC30" "0,1" bitfld.long 0x84 29. "SEC29,SEC29" "0,1" bitfld.long 0x84 28. "SEC28,SEC28" "0,1" bitfld.long 0x84 27. "SEC27,SEC27" "0,1" bitfld.long 0x84 26. "SEC26,SEC26" "0,1" bitfld.long 0x84 25. "SEC25,SEC25" "0,1" bitfld.long 0x84 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x84 23. "SEC23,SEC23" "0,1" bitfld.long 0x84 22. "SEC22,SEC22" "0,1" bitfld.long 0x84 21. "SEC21,SEC21" "0,1" bitfld.long 0x84 20. "SEC20,SEC20" "0,1" bitfld.long 0x84 19. "SEC19,SEC19" "0,1" bitfld.long 0x84 18. "SEC18,SEC18" "0,1" bitfld.long 0x84 17. "SEC17,SEC17" "0,1" bitfld.long 0x84 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x84 15. "SEC15,SEC15" "0,1" bitfld.long 0x84 14. "SEC14,SEC14" "0,1" bitfld.long 0x84 13. "SEC13,SEC13" "0,1" bitfld.long 0x84 12. "SEC12,SEC12" "0,1" bitfld.long 0x84 11. "SEC11,SEC11" "0,1" bitfld.long 0x84 10. "SEC10,SEC10" "0,1" bitfld.long 0x84 9. "SEC9,SEC9" "0,1" bitfld.long 0x84 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x84 7. "SEC7,SEC7" "0,1" bitfld.long 0x84 6. "SEC6,SEC6" "0,1" bitfld.long 0x84 5. "SEC5,SEC5" "0,1" bitfld.long 0x84 4. "SEC4,SEC4" "0,1" bitfld.long 0x84 3. "SEC3,SEC3" "0,1" bitfld.long 0x84 2. "SEC2,SEC2" "0,1" bitfld.long 0x84 1. "SEC1,SEC1" "0,1" bitfld.long 0x84 0. "SEC0,SEC0" "0,1" line.long 0x88 "MPCBB6_SECCFGR34,MPCBBx security configuration for super-block x register" bitfld.long 0x88 31. "SEC31,SEC31" "0,1" bitfld.long 0x88 30. "SEC30,SEC30" "0,1" bitfld.long 0x88 29. "SEC29,SEC29" "0,1" bitfld.long 0x88 28. "SEC28,SEC28" "0,1" bitfld.long 0x88 27. "SEC27,SEC27" "0,1" bitfld.long 0x88 26. "SEC26,SEC26" "0,1" bitfld.long 0x88 25. "SEC25,SEC25" "0,1" bitfld.long 0x88 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x88 23. "SEC23,SEC23" "0,1" bitfld.long 0x88 22. "SEC22,SEC22" "0,1" bitfld.long 0x88 21. "SEC21,SEC21" "0,1" bitfld.long 0x88 20. "SEC20,SEC20" "0,1" bitfld.long 0x88 19. "SEC19,SEC19" "0,1" bitfld.long 0x88 18. "SEC18,SEC18" "0,1" bitfld.long 0x88 17. "SEC17,SEC17" "0,1" bitfld.long 0x88 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x88 15. "SEC15,SEC15" "0,1" bitfld.long 0x88 14. "SEC14,SEC14" "0,1" bitfld.long 0x88 13. "SEC13,SEC13" "0,1" bitfld.long 0x88 12. "SEC12,SEC12" "0,1" bitfld.long 0x88 11. "SEC11,SEC11" "0,1" bitfld.long 0x88 10. "SEC10,SEC10" "0,1" bitfld.long 0x88 9. "SEC9,SEC9" "0,1" bitfld.long 0x88 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x88 7. "SEC7,SEC7" "0,1" bitfld.long 0x88 6. "SEC6,SEC6" "0,1" bitfld.long 0x88 5. "SEC5,SEC5" "0,1" bitfld.long 0x88 4. "SEC4,SEC4" "0,1" bitfld.long 0x88 3. "SEC3,SEC3" "0,1" bitfld.long 0x88 2. "SEC2,SEC2" "0,1" bitfld.long 0x88 1. "SEC1,SEC1" "0,1" bitfld.long 0x88 0. "SEC0,SEC0" "0,1" line.long 0x8C "MPCBB6_SECCFGR35,MPCBBx security configuration for super-block x register" bitfld.long 0x8C 31. "SEC31,SEC31" "0,1" bitfld.long 0x8C 30. "SEC30,SEC30" "0,1" bitfld.long 0x8C 29. "SEC29,SEC29" "0,1" bitfld.long 0x8C 28. "SEC28,SEC28" "0,1" bitfld.long 0x8C 27. "SEC27,SEC27" "0,1" bitfld.long 0x8C 26. "SEC26,SEC26" "0,1" bitfld.long 0x8C 25. "SEC25,SEC25" "0,1" bitfld.long 0x8C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x8C 23. "SEC23,SEC23" "0,1" bitfld.long 0x8C 22. "SEC22,SEC22" "0,1" bitfld.long 0x8C 21. "SEC21,SEC21" "0,1" bitfld.long 0x8C 20. "SEC20,SEC20" "0,1" bitfld.long 0x8C 19. "SEC19,SEC19" "0,1" bitfld.long 0x8C 18. "SEC18,SEC18" "0,1" bitfld.long 0x8C 17. "SEC17,SEC17" "0,1" bitfld.long 0x8C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x8C 15. "SEC15,SEC15" "0,1" bitfld.long 0x8C 14. "SEC14,SEC14" "0,1" bitfld.long 0x8C 13. "SEC13,SEC13" "0,1" bitfld.long 0x8C 12. "SEC12,SEC12" "0,1" bitfld.long 0x8C 11. "SEC11,SEC11" "0,1" bitfld.long 0x8C 10. "SEC10,SEC10" "0,1" bitfld.long 0x8C 9. "SEC9,SEC9" "0,1" bitfld.long 0x8C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x8C 7. "SEC7,SEC7" "0,1" bitfld.long 0x8C 6. "SEC6,SEC6" "0,1" bitfld.long 0x8C 5. "SEC5,SEC5" "0,1" bitfld.long 0x8C 4. "SEC4,SEC4" "0,1" bitfld.long 0x8C 3. "SEC3,SEC3" "0,1" bitfld.long 0x8C 2. "SEC2,SEC2" "0,1" bitfld.long 0x8C 1. "SEC1,SEC1" "0,1" bitfld.long 0x8C 0. "SEC0,SEC0" "0,1" line.long 0x90 "MPCBB6_SECCFGR36,MPCBBx security configuration for super-block x register" bitfld.long 0x90 31. "SEC31,SEC31" "0,1" bitfld.long 0x90 30. "SEC30,SEC30" "0,1" bitfld.long 0x90 29. "SEC29,SEC29" "0,1" bitfld.long 0x90 28. "SEC28,SEC28" "0,1" bitfld.long 0x90 27. "SEC27,SEC27" "0,1" bitfld.long 0x90 26. "SEC26,SEC26" "0,1" bitfld.long 0x90 25. "SEC25,SEC25" "0,1" bitfld.long 0x90 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x90 23. "SEC23,SEC23" "0,1" bitfld.long 0x90 22. "SEC22,SEC22" "0,1" bitfld.long 0x90 21. "SEC21,SEC21" "0,1" bitfld.long 0x90 20. "SEC20,SEC20" "0,1" bitfld.long 0x90 19. "SEC19,SEC19" "0,1" bitfld.long 0x90 18. "SEC18,SEC18" "0,1" bitfld.long 0x90 17. "SEC17,SEC17" "0,1" bitfld.long 0x90 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x90 15. "SEC15,SEC15" "0,1" bitfld.long 0x90 14. "SEC14,SEC14" "0,1" bitfld.long 0x90 13. "SEC13,SEC13" "0,1" bitfld.long 0x90 12. "SEC12,SEC12" "0,1" bitfld.long 0x90 11. "SEC11,SEC11" "0,1" bitfld.long 0x90 10. "SEC10,SEC10" "0,1" bitfld.long 0x90 9. "SEC9,SEC9" "0,1" bitfld.long 0x90 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x90 7. "SEC7,SEC7" "0,1" bitfld.long 0x90 6. "SEC6,SEC6" "0,1" bitfld.long 0x90 5. "SEC5,SEC5" "0,1" bitfld.long 0x90 4. "SEC4,SEC4" "0,1" bitfld.long 0x90 3. "SEC3,SEC3" "0,1" bitfld.long 0x90 2. "SEC2,SEC2" "0,1" bitfld.long 0x90 1. "SEC1,SEC1" "0,1" bitfld.long 0x90 0. "SEC0,SEC0" "0,1" line.long 0x94 "MPCBB6_SECCFGR37,MPCBBx security configuration for super-block x register" bitfld.long 0x94 31. "SEC31,SEC31" "0,1" bitfld.long 0x94 30. "SEC30,SEC30" "0,1" bitfld.long 0x94 29. "SEC29,SEC29" "0,1" bitfld.long 0x94 28. "SEC28,SEC28" "0,1" bitfld.long 0x94 27. "SEC27,SEC27" "0,1" bitfld.long 0x94 26. "SEC26,SEC26" "0,1" bitfld.long 0x94 25. "SEC25,SEC25" "0,1" bitfld.long 0x94 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x94 23. "SEC23,SEC23" "0,1" bitfld.long 0x94 22. "SEC22,SEC22" "0,1" bitfld.long 0x94 21. "SEC21,SEC21" "0,1" bitfld.long 0x94 20. "SEC20,SEC20" "0,1" bitfld.long 0x94 19. "SEC19,SEC19" "0,1" bitfld.long 0x94 18. "SEC18,SEC18" "0,1" bitfld.long 0x94 17. "SEC17,SEC17" "0,1" bitfld.long 0x94 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x94 15. "SEC15,SEC15" "0,1" bitfld.long 0x94 14. "SEC14,SEC14" "0,1" bitfld.long 0x94 13. "SEC13,SEC13" "0,1" bitfld.long 0x94 12. "SEC12,SEC12" "0,1" bitfld.long 0x94 11. "SEC11,SEC11" "0,1" bitfld.long 0x94 10. "SEC10,SEC10" "0,1" bitfld.long 0x94 9. "SEC9,SEC9" "0,1" bitfld.long 0x94 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x94 7. "SEC7,SEC7" "0,1" bitfld.long 0x94 6. "SEC6,SEC6" "0,1" bitfld.long 0x94 5. "SEC5,SEC5" "0,1" bitfld.long 0x94 4. "SEC4,SEC4" "0,1" bitfld.long 0x94 3. "SEC3,SEC3" "0,1" bitfld.long 0x94 2. "SEC2,SEC2" "0,1" bitfld.long 0x94 1. "SEC1,SEC1" "0,1" bitfld.long 0x94 0. "SEC0,SEC0" "0,1" line.long 0x98 "MPCBB6_SECCFGR38,MPCBBx security configuration for super-block x register" bitfld.long 0x98 31. "SEC31,SEC31" "0,1" bitfld.long 0x98 30. "SEC30,SEC30" "0,1" bitfld.long 0x98 29. "SEC29,SEC29" "0,1" bitfld.long 0x98 28. "SEC28,SEC28" "0,1" bitfld.long 0x98 27. "SEC27,SEC27" "0,1" bitfld.long 0x98 26. "SEC26,SEC26" "0,1" bitfld.long 0x98 25. "SEC25,SEC25" "0,1" bitfld.long 0x98 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x98 23. "SEC23,SEC23" "0,1" bitfld.long 0x98 22. "SEC22,SEC22" "0,1" bitfld.long 0x98 21. "SEC21,SEC21" "0,1" bitfld.long 0x98 20. "SEC20,SEC20" "0,1" bitfld.long 0x98 19. "SEC19,SEC19" "0,1" bitfld.long 0x98 18. "SEC18,SEC18" "0,1" bitfld.long 0x98 17. "SEC17,SEC17" "0,1" bitfld.long 0x98 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x98 15. "SEC15,SEC15" "0,1" bitfld.long 0x98 14. "SEC14,SEC14" "0,1" bitfld.long 0x98 13. "SEC13,SEC13" "0,1" bitfld.long 0x98 12. "SEC12,SEC12" "0,1" bitfld.long 0x98 11. "SEC11,SEC11" "0,1" bitfld.long 0x98 10. "SEC10,SEC10" "0,1" bitfld.long 0x98 9. "SEC9,SEC9" "0,1" bitfld.long 0x98 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x98 7. "SEC7,SEC7" "0,1" bitfld.long 0x98 6. "SEC6,SEC6" "0,1" bitfld.long 0x98 5. "SEC5,SEC5" "0,1" bitfld.long 0x98 4. "SEC4,SEC4" "0,1" bitfld.long 0x98 3. "SEC3,SEC3" "0,1" bitfld.long 0x98 2. "SEC2,SEC2" "0,1" bitfld.long 0x98 1. "SEC1,SEC1" "0,1" bitfld.long 0x98 0. "SEC0,SEC0" "0,1" line.long 0x9C "MPCBB6_SECCFGR39,MPCBBx security configuration for super-block x register" bitfld.long 0x9C 31. "SEC31,SEC31" "0,1" bitfld.long 0x9C 30. "SEC30,SEC30" "0,1" bitfld.long 0x9C 29. "SEC29,SEC29" "0,1" bitfld.long 0x9C 28. "SEC28,SEC28" "0,1" bitfld.long 0x9C 27. "SEC27,SEC27" "0,1" bitfld.long 0x9C 26. "SEC26,SEC26" "0,1" bitfld.long 0x9C 25. "SEC25,SEC25" "0,1" bitfld.long 0x9C 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x9C 23. "SEC23,SEC23" "0,1" bitfld.long 0x9C 22. "SEC22,SEC22" "0,1" bitfld.long 0x9C 21. "SEC21,SEC21" "0,1" bitfld.long 0x9C 20. "SEC20,SEC20" "0,1" bitfld.long 0x9C 19. "SEC19,SEC19" "0,1" bitfld.long 0x9C 18. "SEC18,SEC18" "0,1" bitfld.long 0x9C 17. "SEC17,SEC17" "0,1" bitfld.long 0x9C 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x9C 15. "SEC15,SEC15" "0,1" bitfld.long 0x9C 14. "SEC14,SEC14" "0,1" bitfld.long 0x9C 13. "SEC13,SEC13" "0,1" bitfld.long 0x9C 12. "SEC12,SEC12" "0,1" bitfld.long 0x9C 11. "SEC11,SEC11" "0,1" bitfld.long 0x9C 10. "SEC10,SEC10" "0,1" bitfld.long 0x9C 9. "SEC9,SEC9" "0,1" bitfld.long 0x9C 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x9C 7. "SEC7,SEC7" "0,1" bitfld.long 0x9C 6. "SEC6,SEC6" "0,1" bitfld.long 0x9C 5. "SEC5,SEC5" "0,1" bitfld.long 0x9C 4. "SEC4,SEC4" "0,1" bitfld.long 0x9C 3. "SEC3,SEC3" "0,1" bitfld.long 0x9C 2. "SEC2,SEC2" "0,1" bitfld.long 0x9C 1. "SEC1,SEC1" "0,1" bitfld.long 0x9C 0. "SEC0,SEC0" "0,1" line.long 0xA0 "MPCBB6_SECCFGR40,MPCBBx security configuration for super-block x register" bitfld.long 0xA0 31. "SEC31,SEC31" "0,1" bitfld.long 0xA0 30. "SEC30,SEC30" "0,1" bitfld.long 0xA0 29. "SEC29,SEC29" "0,1" bitfld.long 0xA0 28. "SEC28,SEC28" "0,1" bitfld.long 0xA0 27. "SEC27,SEC27" "0,1" bitfld.long 0xA0 26. "SEC26,SEC26" "0,1" bitfld.long 0xA0 25. "SEC25,SEC25" "0,1" bitfld.long 0xA0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA0 23. "SEC23,SEC23" "0,1" bitfld.long 0xA0 22. "SEC22,SEC22" "0,1" bitfld.long 0xA0 21. "SEC21,SEC21" "0,1" bitfld.long 0xA0 20. "SEC20,SEC20" "0,1" bitfld.long 0xA0 19. "SEC19,SEC19" "0,1" bitfld.long 0xA0 18. "SEC18,SEC18" "0,1" bitfld.long 0xA0 17. "SEC17,SEC17" "0,1" bitfld.long 0xA0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA0 15. "SEC15,SEC15" "0,1" bitfld.long 0xA0 14. "SEC14,SEC14" "0,1" bitfld.long 0xA0 13. "SEC13,SEC13" "0,1" bitfld.long 0xA0 12. "SEC12,SEC12" "0,1" bitfld.long 0xA0 11. "SEC11,SEC11" "0,1" bitfld.long 0xA0 10. "SEC10,SEC10" "0,1" bitfld.long 0xA0 9. "SEC9,SEC9" "0,1" bitfld.long 0xA0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA0 7. "SEC7,SEC7" "0,1" bitfld.long 0xA0 6. "SEC6,SEC6" "0,1" bitfld.long 0xA0 5. "SEC5,SEC5" "0,1" bitfld.long 0xA0 4. "SEC4,SEC4" "0,1" bitfld.long 0xA0 3. "SEC3,SEC3" "0,1" bitfld.long 0xA0 2. "SEC2,SEC2" "0,1" bitfld.long 0xA0 1. "SEC1,SEC1" "0,1" bitfld.long 0xA0 0. "SEC0,SEC0" "0,1" line.long 0xA4 "MPCBB6_SECCFGR41,MPCBBx security configuration for super-block x register" bitfld.long 0xA4 31. "SEC31,SEC31" "0,1" bitfld.long 0xA4 30. "SEC30,SEC30" "0,1" bitfld.long 0xA4 29. "SEC29,SEC29" "0,1" bitfld.long 0xA4 28. "SEC28,SEC28" "0,1" bitfld.long 0xA4 27. "SEC27,SEC27" "0,1" bitfld.long 0xA4 26. "SEC26,SEC26" "0,1" bitfld.long 0xA4 25. "SEC25,SEC25" "0,1" bitfld.long 0xA4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA4 23. "SEC23,SEC23" "0,1" bitfld.long 0xA4 22. "SEC22,SEC22" "0,1" bitfld.long 0xA4 21. "SEC21,SEC21" "0,1" bitfld.long 0xA4 20. "SEC20,SEC20" "0,1" bitfld.long 0xA4 19. "SEC19,SEC19" "0,1" bitfld.long 0xA4 18. "SEC18,SEC18" "0,1" bitfld.long 0xA4 17. "SEC17,SEC17" "0,1" bitfld.long 0xA4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA4 15. "SEC15,SEC15" "0,1" bitfld.long 0xA4 14. "SEC14,SEC14" "0,1" bitfld.long 0xA4 13. "SEC13,SEC13" "0,1" bitfld.long 0xA4 12. "SEC12,SEC12" "0,1" bitfld.long 0xA4 11. "SEC11,SEC11" "0,1" bitfld.long 0xA4 10. "SEC10,SEC10" "0,1" bitfld.long 0xA4 9. "SEC9,SEC9" "0,1" bitfld.long 0xA4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA4 7. "SEC7,SEC7" "0,1" bitfld.long 0xA4 6. "SEC6,SEC6" "0,1" bitfld.long 0xA4 5. "SEC5,SEC5" "0,1" bitfld.long 0xA4 4. "SEC4,SEC4" "0,1" bitfld.long 0xA4 3. "SEC3,SEC3" "0,1" bitfld.long 0xA4 2. "SEC2,SEC2" "0,1" bitfld.long 0xA4 1. "SEC1,SEC1" "0,1" bitfld.long 0xA4 0. "SEC0,SEC0" "0,1" line.long 0xA8 "MPCBB6_SECCFGR42,MPCBBx security configuration for super-block x register" bitfld.long 0xA8 31. "SEC31,SEC31" "0,1" bitfld.long 0xA8 30. "SEC30,SEC30" "0,1" bitfld.long 0xA8 29. "SEC29,SEC29" "0,1" bitfld.long 0xA8 28. "SEC28,SEC28" "0,1" bitfld.long 0xA8 27. "SEC27,SEC27" "0,1" bitfld.long 0xA8 26. "SEC26,SEC26" "0,1" bitfld.long 0xA8 25. "SEC25,SEC25" "0,1" bitfld.long 0xA8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xA8 23. "SEC23,SEC23" "0,1" bitfld.long 0xA8 22. "SEC22,SEC22" "0,1" bitfld.long 0xA8 21. "SEC21,SEC21" "0,1" bitfld.long 0xA8 20. "SEC20,SEC20" "0,1" bitfld.long 0xA8 19. "SEC19,SEC19" "0,1" bitfld.long 0xA8 18. "SEC18,SEC18" "0,1" bitfld.long 0xA8 17. "SEC17,SEC17" "0,1" bitfld.long 0xA8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xA8 15. "SEC15,SEC15" "0,1" bitfld.long 0xA8 14. "SEC14,SEC14" "0,1" bitfld.long 0xA8 13. "SEC13,SEC13" "0,1" bitfld.long 0xA8 12. "SEC12,SEC12" "0,1" bitfld.long 0xA8 11. "SEC11,SEC11" "0,1" bitfld.long 0xA8 10. "SEC10,SEC10" "0,1" bitfld.long 0xA8 9. "SEC9,SEC9" "0,1" bitfld.long 0xA8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xA8 7. "SEC7,SEC7" "0,1" bitfld.long 0xA8 6. "SEC6,SEC6" "0,1" bitfld.long 0xA8 5. "SEC5,SEC5" "0,1" bitfld.long 0xA8 4. "SEC4,SEC4" "0,1" bitfld.long 0xA8 3. "SEC3,SEC3" "0,1" bitfld.long 0xA8 2. "SEC2,SEC2" "0,1" bitfld.long 0xA8 1. "SEC1,SEC1" "0,1" bitfld.long 0xA8 0. "SEC0,SEC0" "0,1" line.long 0xAC "MPCBB6_SECCFGR43,MPCBBx security configuration for super-block x register" bitfld.long 0xAC 31. "SEC31,SEC31" "0,1" bitfld.long 0xAC 30. "SEC30,SEC30" "0,1" bitfld.long 0xAC 29. "SEC29,SEC29" "0,1" bitfld.long 0xAC 28. "SEC28,SEC28" "0,1" bitfld.long 0xAC 27. "SEC27,SEC27" "0,1" bitfld.long 0xAC 26. "SEC26,SEC26" "0,1" bitfld.long 0xAC 25. "SEC25,SEC25" "0,1" bitfld.long 0xAC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xAC 23. "SEC23,SEC23" "0,1" bitfld.long 0xAC 22. "SEC22,SEC22" "0,1" bitfld.long 0xAC 21. "SEC21,SEC21" "0,1" bitfld.long 0xAC 20. "SEC20,SEC20" "0,1" bitfld.long 0xAC 19. "SEC19,SEC19" "0,1" bitfld.long 0xAC 18. "SEC18,SEC18" "0,1" bitfld.long 0xAC 17. "SEC17,SEC17" "0,1" bitfld.long 0xAC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xAC 15. "SEC15,SEC15" "0,1" bitfld.long 0xAC 14. "SEC14,SEC14" "0,1" bitfld.long 0xAC 13. "SEC13,SEC13" "0,1" bitfld.long 0xAC 12. "SEC12,SEC12" "0,1" bitfld.long 0xAC 11. "SEC11,SEC11" "0,1" bitfld.long 0xAC 10. "SEC10,SEC10" "0,1" bitfld.long 0xAC 9. "SEC9,SEC9" "0,1" bitfld.long 0xAC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xAC 7. "SEC7,SEC7" "0,1" bitfld.long 0xAC 6. "SEC6,SEC6" "0,1" bitfld.long 0xAC 5. "SEC5,SEC5" "0,1" bitfld.long 0xAC 4. "SEC4,SEC4" "0,1" bitfld.long 0xAC 3. "SEC3,SEC3" "0,1" bitfld.long 0xAC 2. "SEC2,SEC2" "0,1" bitfld.long 0xAC 1. "SEC1,SEC1" "0,1" bitfld.long 0xAC 0. "SEC0,SEC0" "0,1" line.long 0xB0 "MPCBB6_SECCFGR44,MPCBBx security configuration for super-block x register" bitfld.long 0xB0 31. "SEC31,SEC31" "0,1" bitfld.long 0xB0 30. "SEC30,SEC30" "0,1" bitfld.long 0xB0 29. "SEC29,SEC29" "0,1" bitfld.long 0xB0 28. "SEC28,SEC28" "0,1" bitfld.long 0xB0 27. "SEC27,SEC27" "0,1" bitfld.long 0xB0 26. "SEC26,SEC26" "0,1" bitfld.long 0xB0 25. "SEC25,SEC25" "0,1" bitfld.long 0xB0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB0 23. "SEC23,SEC23" "0,1" bitfld.long 0xB0 22. "SEC22,SEC22" "0,1" bitfld.long 0xB0 21. "SEC21,SEC21" "0,1" bitfld.long 0xB0 20. "SEC20,SEC20" "0,1" bitfld.long 0xB0 19. "SEC19,SEC19" "0,1" bitfld.long 0xB0 18. "SEC18,SEC18" "0,1" bitfld.long 0xB0 17. "SEC17,SEC17" "0,1" bitfld.long 0xB0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB0 15. "SEC15,SEC15" "0,1" bitfld.long 0xB0 14. "SEC14,SEC14" "0,1" bitfld.long 0xB0 13. "SEC13,SEC13" "0,1" bitfld.long 0xB0 12. "SEC12,SEC12" "0,1" bitfld.long 0xB0 11. "SEC11,SEC11" "0,1" bitfld.long 0xB0 10. "SEC10,SEC10" "0,1" bitfld.long 0xB0 9. "SEC9,SEC9" "0,1" bitfld.long 0xB0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB0 7. "SEC7,SEC7" "0,1" bitfld.long 0xB0 6. "SEC6,SEC6" "0,1" bitfld.long 0xB0 5. "SEC5,SEC5" "0,1" bitfld.long 0xB0 4. "SEC4,SEC4" "0,1" bitfld.long 0xB0 3. "SEC3,SEC3" "0,1" bitfld.long 0xB0 2. "SEC2,SEC2" "0,1" bitfld.long 0xB0 1. "SEC1,SEC1" "0,1" bitfld.long 0xB0 0. "SEC0,SEC0" "0,1" line.long 0xB4 "MPCBB6_SECCFGR45,MPCBBx security configuration for super-block x register" bitfld.long 0xB4 31. "SEC31,SEC31" "0,1" bitfld.long 0xB4 30. "SEC30,SEC30" "0,1" bitfld.long 0xB4 29. "SEC29,SEC29" "0,1" bitfld.long 0xB4 28. "SEC28,SEC28" "0,1" bitfld.long 0xB4 27. "SEC27,SEC27" "0,1" bitfld.long 0xB4 26. "SEC26,SEC26" "0,1" bitfld.long 0xB4 25. "SEC25,SEC25" "0,1" bitfld.long 0xB4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB4 23. "SEC23,SEC23" "0,1" bitfld.long 0xB4 22. "SEC22,SEC22" "0,1" bitfld.long 0xB4 21. "SEC21,SEC21" "0,1" bitfld.long 0xB4 20. "SEC20,SEC20" "0,1" bitfld.long 0xB4 19. "SEC19,SEC19" "0,1" bitfld.long 0xB4 18. "SEC18,SEC18" "0,1" bitfld.long 0xB4 17. "SEC17,SEC17" "0,1" bitfld.long 0xB4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB4 15. "SEC15,SEC15" "0,1" bitfld.long 0xB4 14. "SEC14,SEC14" "0,1" bitfld.long 0xB4 13. "SEC13,SEC13" "0,1" bitfld.long 0xB4 12. "SEC12,SEC12" "0,1" bitfld.long 0xB4 11. "SEC11,SEC11" "0,1" bitfld.long 0xB4 10. "SEC10,SEC10" "0,1" bitfld.long 0xB4 9. "SEC9,SEC9" "0,1" bitfld.long 0xB4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB4 7. "SEC7,SEC7" "0,1" bitfld.long 0xB4 6. "SEC6,SEC6" "0,1" bitfld.long 0xB4 5. "SEC5,SEC5" "0,1" bitfld.long 0xB4 4. "SEC4,SEC4" "0,1" bitfld.long 0xB4 3. "SEC3,SEC3" "0,1" bitfld.long 0xB4 2. "SEC2,SEC2" "0,1" bitfld.long 0xB4 1. "SEC1,SEC1" "0,1" bitfld.long 0xB4 0. "SEC0,SEC0" "0,1" line.long 0xB8 "MPCBB6_SECCFGR46,MPCBBx security configuration for super-block x register" bitfld.long 0xB8 31. "SEC31,SEC31" "0,1" bitfld.long 0xB8 30. "SEC30,SEC30" "0,1" bitfld.long 0xB8 29. "SEC29,SEC29" "0,1" bitfld.long 0xB8 28. "SEC28,SEC28" "0,1" bitfld.long 0xB8 27. "SEC27,SEC27" "0,1" bitfld.long 0xB8 26. "SEC26,SEC26" "0,1" bitfld.long 0xB8 25. "SEC25,SEC25" "0,1" bitfld.long 0xB8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xB8 23. "SEC23,SEC23" "0,1" bitfld.long 0xB8 22. "SEC22,SEC22" "0,1" bitfld.long 0xB8 21. "SEC21,SEC21" "0,1" bitfld.long 0xB8 20. "SEC20,SEC20" "0,1" bitfld.long 0xB8 19. "SEC19,SEC19" "0,1" bitfld.long 0xB8 18. "SEC18,SEC18" "0,1" bitfld.long 0xB8 17. "SEC17,SEC17" "0,1" bitfld.long 0xB8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xB8 15. "SEC15,SEC15" "0,1" bitfld.long 0xB8 14. "SEC14,SEC14" "0,1" bitfld.long 0xB8 13. "SEC13,SEC13" "0,1" bitfld.long 0xB8 12. "SEC12,SEC12" "0,1" bitfld.long 0xB8 11. "SEC11,SEC11" "0,1" bitfld.long 0xB8 10. "SEC10,SEC10" "0,1" bitfld.long 0xB8 9. "SEC9,SEC9" "0,1" bitfld.long 0xB8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xB8 7. "SEC7,SEC7" "0,1" bitfld.long 0xB8 6. "SEC6,SEC6" "0,1" bitfld.long 0xB8 5. "SEC5,SEC5" "0,1" bitfld.long 0xB8 4. "SEC4,SEC4" "0,1" bitfld.long 0xB8 3. "SEC3,SEC3" "0,1" bitfld.long 0xB8 2. "SEC2,SEC2" "0,1" bitfld.long 0xB8 1. "SEC1,SEC1" "0,1" bitfld.long 0xB8 0. "SEC0,SEC0" "0,1" line.long 0xBC "MPCBB6_SECCFGR47,MPCBBx security configuration for super-block x register" bitfld.long 0xBC 31. "SEC31,SEC31" "0,1" bitfld.long 0xBC 30. "SEC30,SEC30" "0,1" bitfld.long 0xBC 29. "SEC29,SEC29" "0,1" bitfld.long 0xBC 28. "SEC28,SEC28" "0,1" bitfld.long 0xBC 27. "SEC27,SEC27" "0,1" bitfld.long 0xBC 26. "SEC26,SEC26" "0,1" bitfld.long 0xBC 25. "SEC25,SEC25" "0,1" bitfld.long 0xBC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xBC 23. "SEC23,SEC23" "0,1" bitfld.long 0xBC 22. "SEC22,SEC22" "0,1" bitfld.long 0xBC 21. "SEC21,SEC21" "0,1" bitfld.long 0xBC 20. "SEC20,SEC20" "0,1" bitfld.long 0xBC 19. "SEC19,SEC19" "0,1" bitfld.long 0xBC 18. "SEC18,SEC18" "0,1" bitfld.long 0xBC 17. "SEC17,SEC17" "0,1" bitfld.long 0xBC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xBC 15. "SEC15,SEC15" "0,1" bitfld.long 0xBC 14. "SEC14,SEC14" "0,1" bitfld.long 0xBC 13. "SEC13,SEC13" "0,1" bitfld.long 0xBC 12. "SEC12,SEC12" "0,1" bitfld.long 0xBC 11. "SEC11,SEC11" "0,1" bitfld.long 0xBC 10. "SEC10,SEC10" "0,1" bitfld.long 0xBC 9. "SEC9,SEC9" "0,1" bitfld.long 0xBC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xBC 7. "SEC7,SEC7" "0,1" bitfld.long 0xBC 6. "SEC6,SEC6" "0,1" bitfld.long 0xBC 5. "SEC5,SEC5" "0,1" bitfld.long 0xBC 4. "SEC4,SEC4" "0,1" bitfld.long 0xBC 3. "SEC3,SEC3" "0,1" bitfld.long 0xBC 2. "SEC2,SEC2" "0,1" bitfld.long 0xBC 1. "SEC1,SEC1" "0,1" bitfld.long 0xBC 0. "SEC0,SEC0" "0,1" line.long 0xC0 "MPCBB6_SECCFGR48,MPCBBx security configuration for super-block x register" bitfld.long 0xC0 31. "SEC31,SEC31" "0,1" bitfld.long 0xC0 30. "SEC30,SEC30" "0,1" bitfld.long 0xC0 29. "SEC29,SEC29" "0,1" bitfld.long 0xC0 28. "SEC28,SEC28" "0,1" bitfld.long 0xC0 27. "SEC27,SEC27" "0,1" bitfld.long 0xC0 26. "SEC26,SEC26" "0,1" bitfld.long 0xC0 25. "SEC25,SEC25" "0,1" bitfld.long 0xC0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC0 23. "SEC23,SEC23" "0,1" bitfld.long 0xC0 22. "SEC22,SEC22" "0,1" bitfld.long 0xC0 21. "SEC21,SEC21" "0,1" bitfld.long 0xC0 20. "SEC20,SEC20" "0,1" bitfld.long 0xC0 19. "SEC19,SEC19" "0,1" bitfld.long 0xC0 18. "SEC18,SEC18" "0,1" bitfld.long 0xC0 17. "SEC17,SEC17" "0,1" bitfld.long 0xC0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC0 15. "SEC15,SEC15" "0,1" bitfld.long 0xC0 14. "SEC14,SEC14" "0,1" bitfld.long 0xC0 13. "SEC13,SEC13" "0,1" bitfld.long 0xC0 12. "SEC12,SEC12" "0,1" bitfld.long 0xC0 11. "SEC11,SEC11" "0,1" bitfld.long 0xC0 10. "SEC10,SEC10" "0,1" bitfld.long 0xC0 9. "SEC9,SEC9" "0,1" bitfld.long 0xC0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC0 7. "SEC7,SEC7" "0,1" bitfld.long 0xC0 6. "SEC6,SEC6" "0,1" bitfld.long 0xC0 5. "SEC5,SEC5" "0,1" bitfld.long 0xC0 4. "SEC4,SEC4" "0,1" bitfld.long 0xC0 3. "SEC3,SEC3" "0,1" bitfld.long 0xC0 2. "SEC2,SEC2" "0,1" bitfld.long 0xC0 1. "SEC1,SEC1" "0,1" bitfld.long 0xC0 0. "SEC0,SEC0" "0,1" line.long 0xC4 "MPCBB6_SECCFGR49,MPCBBx security configuration for super-block x register" bitfld.long 0xC4 31. "SEC31,SEC31" "0,1" bitfld.long 0xC4 30. "SEC30,SEC30" "0,1" bitfld.long 0xC4 29. "SEC29,SEC29" "0,1" bitfld.long 0xC4 28. "SEC28,SEC28" "0,1" bitfld.long 0xC4 27. "SEC27,SEC27" "0,1" bitfld.long 0xC4 26. "SEC26,SEC26" "0,1" bitfld.long 0xC4 25. "SEC25,SEC25" "0,1" bitfld.long 0xC4 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC4 23. "SEC23,SEC23" "0,1" bitfld.long 0xC4 22. "SEC22,SEC22" "0,1" bitfld.long 0xC4 21. "SEC21,SEC21" "0,1" bitfld.long 0xC4 20. "SEC20,SEC20" "0,1" bitfld.long 0xC4 19. "SEC19,SEC19" "0,1" bitfld.long 0xC4 18. "SEC18,SEC18" "0,1" bitfld.long 0xC4 17. "SEC17,SEC17" "0,1" bitfld.long 0xC4 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC4 15. "SEC15,SEC15" "0,1" bitfld.long 0xC4 14. "SEC14,SEC14" "0,1" bitfld.long 0xC4 13. "SEC13,SEC13" "0,1" bitfld.long 0xC4 12. "SEC12,SEC12" "0,1" bitfld.long 0xC4 11. "SEC11,SEC11" "0,1" bitfld.long 0xC4 10. "SEC10,SEC10" "0,1" bitfld.long 0xC4 9. "SEC9,SEC9" "0,1" bitfld.long 0xC4 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC4 7. "SEC7,SEC7" "0,1" bitfld.long 0xC4 6. "SEC6,SEC6" "0,1" bitfld.long 0xC4 5. "SEC5,SEC5" "0,1" bitfld.long 0xC4 4. "SEC4,SEC4" "0,1" bitfld.long 0xC4 3. "SEC3,SEC3" "0,1" bitfld.long 0xC4 2. "SEC2,SEC2" "0,1" bitfld.long 0xC4 1. "SEC1,SEC1" "0,1" bitfld.long 0xC4 0. "SEC0,SEC0" "0,1" line.long 0xC8 "MPCBB6_SECCFGR50,MPCBBx security configuration for super-block x register" bitfld.long 0xC8 31. "SEC31,SEC31" "0,1" bitfld.long 0xC8 30. "SEC30,SEC30" "0,1" bitfld.long 0xC8 29. "SEC29,SEC29" "0,1" bitfld.long 0xC8 28. "SEC28,SEC28" "0,1" bitfld.long 0xC8 27. "SEC27,SEC27" "0,1" bitfld.long 0xC8 26. "SEC26,SEC26" "0,1" bitfld.long 0xC8 25. "SEC25,SEC25" "0,1" bitfld.long 0xC8 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xC8 23. "SEC23,SEC23" "0,1" bitfld.long 0xC8 22. "SEC22,SEC22" "0,1" bitfld.long 0xC8 21. "SEC21,SEC21" "0,1" bitfld.long 0xC8 20. "SEC20,SEC20" "0,1" bitfld.long 0xC8 19. "SEC19,SEC19" "0,1" bitfld.long 0xC8 18. "SEC18,SEC18" "0,1" bitfld.long 0xC8 17. "SEC17,SEC17" "0,1" bitfld.long 0xC8 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xC8 15. "SEC15,SEC15" "0,1" bitfld.long 0xC8 14. "SEC14,SEC14" "0,1" bitfld.long 0xC8 13. "SEC13,SEC13" "0,1" bitfld.long 0xC8 12. "SEC12,SEC12" "0,1" bitfld.long 0xC8 11. "SEC11,SEC11" "0,1" bitfld.long 0xC8 10. "SEC10,SEC10" "0,1" bitfld.long 0xC8 9. "SEC9,SEC9" "0,1" bitfld.long 0xC8 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xC8 7. "SEC7,SEC7" "0,1" bitfld.long 0xC8 6. "SEC6,SEC6" "0,1" bitfld.long 0xC8 5. "SEC5,SEC5" "0,1" bitfld.long 0xC8 4. "SEC4,SEC4" "0,1" bitfld.long 0xC8 3. "SEC3,SEC3" "0,1" bitfld.long 0xC8 2. "SEC2,SEC2" "0,1" bitfld.long 0xC8 1. "SEC1,SEC1" "0,1" bitfld.long 0xC8 0. "SEC0,SEC0" "0,1" line.long 0xCC "MPCBB6_SECCFGR51,MPCBBx security configuration for super-block x register" bitfld.long 0xCC 31. "SEC31,SEC31" "0,1" bitfld.long 0xCC 30. "SEC30,SEC30" "0,1" bitfld.long 0xCC 29. "SEC29,SEC29" "0,1" bitfld.long 0xCC 28. "SEC28,SEC28" "0,1" bitfld.long 0xCC 27. "SEC27,SEC27" "0,1" bitfld.long 0xCC 26. "SEC26,SEC26" "0,1" bitfld.long 0xCC 25. "SEC25,SEC25" "0,1" bitfld.long 0xCC 24. "SEC24,SEC24" "0,1" newline bitfld.long 0xCC 23. "SEC23,SEC23" "0,1" bitfld.long 0xCC 22. "SEC22,SEC22" "0,1" bitfld.long 0xCC 21. "SEC21,SEC21" "0,1" bitfld.long 0xCC 20. "SEC20,SEC20" "0,1" bitfld.long 0xCC 19. "SEC19,SEC19" "0,1" bitfld.long 0xCC 18. "SEC18,SEC18" "0,1" bitfld.long 0xCC 17. "SEC17,SEC17" "0,1" bitfld.long 0xCC 16. "SEC16,SEC16" "0,1" newline bitfld.long 0xCC 15. "SEC15,SEC15" "0,1" bitfld.long 0xCC 14. "SEC14,SEC14" "0,1" bitfld.long 0xCC 13. "SEC13,SEC13" "0,1" bitfld.long 0xCC 12. "SEC12,SEC12" "0,1" bitfld.long 0xCC 11. "SEC11,SEC11" "0,1" bitfld.long 0xCC 10. "SEC10,SEC10" "0,1" bitfld.long 0xCC 9. "SEC9,SEC9" "0,1" bitfld.long 0xCC 8. "SEC8,SEC8" "0,1" newline bitfld.long 0xCC 7. "SEC7,SEC7" "0,1" bitfld.long 0xCC 6. "SEC6,SEC6" "0,1" bitfld.long 0xCC 5. "SEC5,SEC5" "0,1" bitfld.long 0xCC 4. "SEC4,SEC4" "0,1" bitfld.long 0xCC 3. "SEC3,SEC3" "0,1" bitfld.long 0xCC 2. "SEC2,SEC2" "0,1" bitfld.long 0xCC 1. "SEC1,SEC1" "0,1" bitfld.long 0xCC 0. "SEC0,SEC0" "0,1" group.long 0x200++0xCF line.long 0x0 "MPCBB6_PRIVCFGR0,MPCBB privileged configuration for super-block x register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" line.long 0x4 "MPCBB6_PRIVCFGR1,MPCBB privileged configuration for super-block x register" bitfld.long 0x4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "MPCBB6_PRIVCFGR2,MPCBB privileged configuration for super-block x register" bitfld.long 0x8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8 0. "PRIV0,PRIV0" "0,1" line.long 0xC "MPCBB6_PRIVCFGR3,MPCBB privileged configuration for super-block x register" bitfld.long 0xC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC 0. "PRIV0,PRIV0" "0,1" line.long 0x10 "MPCBB6_PRIVCFGR4,MPCBB privileged configuration for super-block x register" bitfld.long 0x10 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x10 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x10 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x10 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x10 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x10 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x10 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x10 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x10 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x10 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x10 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x10 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x10 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x10 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x10 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x10 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x10 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x10 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x10 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x10 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x10 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x10 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x10 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x10 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x10 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x10 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x10 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x10 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x10 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x10 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x10 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x10 0. "PRIV0,PRIV0" "0,1" line.long 0x14 "MPCBB6_PRIVCFGR5,MPCBB privileged configuration for super-block x register" bitfld.long 0x14 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x14 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x14 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x14 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x14 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x14 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x14 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x14 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x14 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x14 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x14 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x14 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x14 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x14 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x14 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x14 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x14 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x14 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x14 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x14 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x14 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x14 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x14 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x14 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x14 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x14 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x14 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x14 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x14 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x14 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x14 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x14 0. "PRIV0,PRIV0" "0,1" line.long 0x18 "MPCBB6_PRIVCFGR6,MPCBB privileged configuration for super-block x register" bitfld.long 0x18 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x18 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x18 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x18 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x18 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x18 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x18 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x18 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x18 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x18 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x18 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x18 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x18 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x18 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x18 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x18 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x18 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x18 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x18 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x18 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x18 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x18 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x18 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x18 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x18 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x18 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x18 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x18 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x18 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x18 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x18 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x18 0. "PRIV0,PRIV0" "0,1" line.long 0x1C "MPCBB6_PRIVCFGR7,MPCBB privileged configuration for super-block x register" bitfld.long 0x1C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x1C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x1C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x1C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x1C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x1C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x1C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x1C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x1C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x1C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x1C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x1C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x1C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x1C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x1C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x1C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x1C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x1C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x1C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x1C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x1C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x1C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x1C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x1C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x1C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x1C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x1C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x1C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x1C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x1C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x1C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x1C 0. "PRIV0,PRIV0" "0,1" line.long 0x20 "MPCBB6_PRIVCFGR8,MPCBB privileged configuration for super-block x register" bitfld.long 0x20 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x20 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x20 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x20 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x20 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x20 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x20 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x20 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x20 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x20 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x20 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x20 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x20 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x20 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x20 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x20 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x20 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x20 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x20 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x20 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x20 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x20 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x20 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x20 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x20 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x20 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x20 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x20 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x20 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x20 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x20 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x20 0. "PRIV0,PRIV0" "0,1" line.long 0x24 "MPCBB6_PRIVCFGR9,MPCBB privileged configuration for super-block x register" bitfld.long 0x24 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x24 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x24 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x24 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x24 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x24 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x24 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x24 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x24 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x24 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x24 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x24 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x24 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x24 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x24 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x24 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x24 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x24 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x24 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x24 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x24 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x24 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x24 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x24 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x24 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x24 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x24 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x24 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x24 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x24 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x24 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x24 0. "PRIV0,PRIV0" "0,1" line.long 0x28 "MPCBB6_PRIVCFGR10,MPCBB privileged configuration for super-block x register" bitfld.long 0x28 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x28 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x28 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x28 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x28 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x28 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x28 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x28 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x28 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x28 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x28 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x28 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x28 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x28 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x28 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x28 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x28 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x28 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x28 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x28 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x28 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x28 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x28 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x28 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x28 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x28 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x28 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x28 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x28 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x28 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x28 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x28 0. "PRIV0,PRIV0" "0,1" line.long 0x2C "MPCBB6_PRIVCFGR11,MPCBB privileged configuration for super-block x register" bitfld.long 0x2C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x2C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x2C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x2C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x2C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x2C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x2C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x2C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x2C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x2C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x2C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x2C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x2C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x2C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x2C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x2C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x2C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x2C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x2C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x2C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x2C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x2C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x2C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x2C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x2C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x2C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x2C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x2C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x2C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x2C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x2C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x2C 0. "PRIV0,PRIV0" "0,1" line.long 0x30 "MPCBB6_PRIVCFGR12,MPCBB privileged configuration for super-block x register" bitfld.long 0x30 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x30 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x30 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x30 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x30 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x30 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x30 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x30 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x30 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x30 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x30 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x30 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x30 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x30 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x30 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x30 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x30 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x30 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x30 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x30 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x30 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x30 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x30 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x30 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x30 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x30 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x30 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x30 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x30 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x30 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x30 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x30 0. "PRIV0,PRIV0" "0,1" line.long 0x34 "MPCBB6_PRIVCFGR13,MPCBB privileged configuration for super-block x register" bitfld.long 0x34 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x34 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x34 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x34 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x34 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x34 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x34 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x34 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x34 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x34 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x34 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x34 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x34 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x34 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x34 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x34 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x34 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x34 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x34 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x34 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x34 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x34 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x34 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x34 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x34 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x34 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x34 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x34 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x34 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x34 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x34 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x34 0. "PRIV0,PRIV0" "0,1" line.long 0x38 "MPCBB6_PRIVCFGR14,MPCBB privileged configuration for super-block x register" bitfld.long 0x38 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x38 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x38 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x38 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x38 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x38 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x38 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x38 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x38 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x38 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x38 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x38 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x38 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x38 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x38 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x38 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x38 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x38 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x38 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x38 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x38 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x38 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x38 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x38 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x38 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x38 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x38 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x38 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x38 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x38 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x38 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x38 0. "PRIV0,PRIV0" "0,1" line.long 0x3C "MPCBB6_PRIVCFGR15,MPCBB privileged configuration for super-block x register" bitfld.long 0x3C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x3C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x3C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x3C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x3C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x3C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x3C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x3C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x3C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x3C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x3C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x3C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x3C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x3C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x3C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x3C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x3C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x3C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x3C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x3C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x3C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x3C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x3C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x3C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x3C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x3C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x3C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x3C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x3C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x3C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x3C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x3C 0. "PRIV0,PRIV0" "0,1" line.long 0x40 "MPCBB6_PRIVCFGR16,MPCBB privileged configuration for super-block x register" bitfld.long 0x40 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x40 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x40 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x40 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x40 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x40 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x40 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x40 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x40 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x40 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x40 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x40 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x40 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x40 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x40 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x40 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x40 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x40 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x40 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x40 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x40 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x40 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x40 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x40 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x40 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x40 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x40 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x40 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x40 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x40 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x40 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x40 0. "PRIV0,PRIV0" "0,1" line.long 0x44 "MPCBB6_PRIVCFGR17,MPCBB privileged configuration for super-block x register" bitfld.long 0x44 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x44 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x44 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x44 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x44 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x44 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x44 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x44 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x44 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x44 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x44 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x44 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x44 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x44 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x44 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x44 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x44 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x44 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x44 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x44 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x44 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x44 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x44 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x44 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x44 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x44 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x44 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x44 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x44 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x44 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x44 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x44 0. "PRIV0,PRIV0" "0,1" line.long 0x48 "MPCBB6_PRIVCFGR18,MPCBB privileged configuration for super-block x register" bitfld.long 0x48 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x48 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x48 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x48 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x48 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x48 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x48 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x48 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x48 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x48 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x48 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x48 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x48 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x48 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x48 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x48 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x48 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x48 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x48 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x48 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x48 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x48 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x48 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x48 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x48 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x48 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x48 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x48 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x48 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x48 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x48 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x48 0. "PRIV0,PRIV0" "0,1" line.long 0x4C "MPCBB6_PRIVCFGR19,MPCBB privileged configuration for super-block x register" bitfld.long 0x4C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x4C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x4C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x4C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x4C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x4C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x4C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x4C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x4C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x4C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x4C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x4C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x4C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x4C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x4C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x4C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x4C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x4C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x4C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x4C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x4C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x4C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x4C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x4C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x4C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x4C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x4C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x4C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x4C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x4C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4C 0. "PRIV0,PRIV0" "0,1" line.long 0x50 "MPCBB6_PRIVCFGR20,MPCBB privileged configuration for super-block x register" bitfld.long 0x50 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x50 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x50 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x50 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x50 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x50 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x50 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x50 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x50 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x50 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x50 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x50 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x50 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x50 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x50 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x50 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x50 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x50 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x50 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x50 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x50 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x50 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x50 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x50 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x50 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x50 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x50 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x50 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x50 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x50 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x50 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x50 0. "PRIV0,PRIV0" "0,1" line.long 0x54 "MPCBB6_PRIVCFGR21,MPCBB privileged configuration for super-block x register" bitfld.long 0x54 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x54 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x54 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x54 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x54 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x54 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x54 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x54 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x54 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x54 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x54 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x54 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x54 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x54 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x54 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x54 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x54 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x54 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x54 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x54 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x54 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x54 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x54 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x54 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x54 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x54 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x54 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x54 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x54 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x54 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x54 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x54 0. "PRIV0,PRIV0" "0,1" line.long 0x58 "MPCBB6_PRIVCFGR22,MPCBB privileged configuration for super-block x register" bitfld.long 0x58 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x58 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x58 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x58 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x58 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x58 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x58 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x58 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x58 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x58 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x58 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x58 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x58 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x58 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x58 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x58 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x58 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x58 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x58 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x58 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x58 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x58 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x58 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x58 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x58 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x58 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x58 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x58 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x58 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x58 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x58 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x58 0. "PRIV0,PRIV0" "0,1" line.long 0x5C "MPCBB6_PRIVCFGR23,MPCBB privileged configuration for super-block x register" bitfld.long 0x5C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x5C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x5C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x5C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x5C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x5C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x5C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x5C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x5C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x5C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x5C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x5C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x5C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x5C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x5C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x5C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x5C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x5C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x5C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x5C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x5C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x5C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x5C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x5C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x5C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x5C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x5C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x5C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x5C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x5C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x5C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x5C 0. "PRIV0,PRIV0" "0,1" line.long 0x60 "MPCBB6_PRIVCFGR24,MPCBB privileged configuration for super-block x register" bitfld.long 0x60 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x60 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x60 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x60 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x60 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x60 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x60 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x60 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x60 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x60 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x60 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x60 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x60 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x60 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x60 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x60 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x60 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x60 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x60 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x60 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x60 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x60 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x60 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x60 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x60 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x60 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x60 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x60 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x60 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x60 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x60 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x60 0. "PRIV0,PRIV0" "0,1" line.long 0x64 "MPCBB6_PRIVCFGR25,MPCBB privileged configuration for super-block x register" bitfld.long 0x64 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x64 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x64 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x64 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x64 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x64 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x64 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x64 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x64 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x64 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x64 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x64 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x64 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x64 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x64 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x64 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x64 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x64 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x64 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x64 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x64 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x64 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x64 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x64 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x64 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x64 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x64 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x64 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x64 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x64 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x64 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x64 0. "PRIV0,PRIV0" "0,1" line.long 0x68 "MPCBB6_PRIVCFGR26,MPCBB privileged configuration for super-block x register" bitfld.long 0x68 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x68 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x68 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x68 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x68 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x68 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x68 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x68 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x68 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x68 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x68 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x68 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x68 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x68 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x68 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x68 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x68 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x68 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x68 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x68 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x68 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x68 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x68 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x68 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x68 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x68 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x68 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x68 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x68 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x68 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x68 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x68 0. "PRIV0,PRIV0" "0,1" line.long 0x6C "MPCBB6_PRIVCFGR27,MPCBB privileged configuration for super-block x register" bitfld.long 0x6C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x6C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x6C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x6C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x6C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x6C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x6C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x6C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x6C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x6C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x6C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x6C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x6C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x6C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x6C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x6C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x6C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x6C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x6C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x6C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x6C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x6C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x6C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x6C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x6C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x6C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x6C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x6C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x6C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x6C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x6C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x6C 0. "PRIV0,PRIV0" "0,1" line.long 0x70 "MPCBB6_PRIVCFGR28,MPCBB privileged configuration for super-block x register" bitfld.long 0x70 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x70 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x70 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x70 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x70 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x70 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x70 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x70 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x70 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x70 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x70 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x70 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x70 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x70 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x70 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x70 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x70 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x70 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x70 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x70 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x70 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x70 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x70 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x70 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x70 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x70 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x70 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x70 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x70 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x70 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x70 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x70 0. "PRIV0,PRIV0" "0,1" line.long 0x74 "MPCBB6_PRIVCFGR29,MPCBB privileged configuration for super-block x register" bitfld.long 0x74 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x74 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x74 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x74 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x74 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x74 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x74 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x74 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x74 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x74 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x74 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x74 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x74 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x74 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x74 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x74 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x74 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x74 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x74 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x74 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x74 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x74 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x74 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x74 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x74 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x74 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x74 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x74 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x74 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x74 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x74 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x74 0. "PRIV0,PRIV0" "0,1" line.long 0x78 "MPCBB6_PRIVCFGR30,MPCBB privileged configuration for super-block x register" bitfld.long 0x78 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x78 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x78 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x78 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x78 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x78 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x78 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x78 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x78 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x78 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x78 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x78 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x78 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x78 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x78 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x78 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x78 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x78 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x78 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x78 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x78 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x78 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x78 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x78 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x78 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x78 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x78 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x78 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x78 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x78 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x78 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x78 0. "PRIV0,PRIV0" "0,1" line.long 0x7C "MPCBB6_PRIVCFGR31,MPCBB privileged configuration for super-block x register" bitfld.long 0x7C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x7C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x7C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x7C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x7C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x7C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x7C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x7C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x7C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x7C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x7C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x7C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x7C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x7C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x7C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x7C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x7C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x7C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x7C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x7C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x7C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x7C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x7C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x7C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x7C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x7C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x7C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x7C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x7C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x7C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x7C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x7C 0. "PRIV0,PRIV0" "0,1" line.long 0x80 "MPCBB6_PRIVCFGR32,MPCBB privileged configuration for super-block x register" bitfld.long 0x80 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x80 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x80 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x80 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x80 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x80 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x80 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x80 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x80 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x80 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x80 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x80 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x80 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x80 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x80 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x80 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x80 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x80 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x80 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x80 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x80 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x80 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x80 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x80 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x80 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x80 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x80 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x80 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x80 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x80 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x80 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x80 0. "PRIV0,PRIV0" "0,1" line.long 0x84 "MPCBB6_PRIVCFGR33,MPCBB privileged configuration for super-block x register" bitfld.long 0x84 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x84 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x84 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x84 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x84 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x84 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x84 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x84 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x84 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x84 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x84 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x84 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x84 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x84 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x84 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x84 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x84 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x84 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x84 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x84 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x84 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x84 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x84 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x84 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x84 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x84 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x84 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x84 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x84 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x84 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x84 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x84 0. "PRIV0,PRIV0" "0,1" line.long 0x88 "MPCBB6_PRIVCFGR34,MPCBB privileged configuration for super-block x register" bitfld.long 0x88 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x88 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x88 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x88 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x88 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x88 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x88 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x88 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x88 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x88 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x88 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x88 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x88 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x88 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x88 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x88 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x88 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x88 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x88 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x88 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x88 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x88 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x88 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x88 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x88 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x88 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x88 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x88 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x88 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x88 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x88 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x88 0. "PRIV0,PRIV0" "0,1" line.long 0x8C "MPCBB6_PRIVCFGR35,MPCBB privileged configuration for super-block x register" bitfld.long 0x8C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x8C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x8C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x8C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x8C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x8C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x8C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x8C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x8C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x8C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x8C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x8C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x8C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x8C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x8C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x8C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x8C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x8C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x8C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x8C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x8C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x8C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x8C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x8C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x8C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x8C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x8C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x8C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x8C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x8C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x8C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x8C 0. "PRIV0,PRIV0" "0,1" line.long 0x90 "MPCBB6_PRIVCFGR36,MPCBB privileged configuration for super-block x register" bitfld.long 0x90 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x90 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x90 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x90 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x90 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x90 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x90 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x90 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x90 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x90 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x90 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x90 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x90 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x90 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x90 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x90 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x90 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x90 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x90 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x90 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x90 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x90 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x90 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x90 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x90 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x90 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x90 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x90 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x90 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x90 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x90 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x90 0. "PRIV0,PRIV0" "0,1" line.long 0x94 "MPCBB6_PRIVCFGR37,MPCBB privileged configuration for super-block x register" bitfld.long 0x94 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x94 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x94 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x94 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x94 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x94 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x94 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x94 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x94 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x94 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x94 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x94 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x94 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x94 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x94 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x94 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x94 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x94 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x94 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x94 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x94 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x94 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x94 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x94 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x94 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x94 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x94 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x94 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x94 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x94 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x94 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x94 0. "PRIV0,PRIV0" "0,1" line.long 0x98 "MPCBB6_PRIVCFGR38,MPCBB privileged configuration for super-block x register" bitfld.long 0x98 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x98 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x98 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x98 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x98 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x98 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x98 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x98 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x98 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x98 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x98 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x98 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x98 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x98 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x98 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x98 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x98 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x98 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x98 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x98 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x98 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x98 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x98 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x98 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x98 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x98 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x98 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x98 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x98 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x98 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x98 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x98 0. "PRIV0,PRIV0" "0,1" line.long 0x9C "MPCBB6_PRIVCFGR39,MPCBB privileged configuration for super-block x register" bitfld.long 0x9C 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x9C 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x9C 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x9C 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x9C 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x9C 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x9C 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x9C 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x9C 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x9C 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x9C 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x9C 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x9C 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x9C 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x9C 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x9C 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x9C 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x9C 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x9C 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x9C 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x9C 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x9C 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x9C 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x9C 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x9C 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x9C 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x9C 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x9C 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x9C 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x9C 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x9C 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x9C 0. "PRIV0,PRIV0" "0,1" line.long 0xA0 "MPCBB6_PRIVCFGR40,MPCBB privileged configuration for super-block x register" bitfld.long 0xA0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA0 0. "PRIV0,PRIV0" "0,1" line.long 0xA4 "MPCBB6_PRIVCFGR41,MPCBB privileged configuration for super-block x register" bitfld.long 0xA4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA4 0. "PRIV0,PRIV0" "0,1" line.long 0xA8 "MPCBB6_PRIVCFGR42,MPCBB privileged configuration for super-block x register" bitfld.long 0xA8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xA8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xA8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xA8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xA8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xA8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xA8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xA8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xA8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xA8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xA8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xA8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xA8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xA8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xA8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xA8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xA8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xA8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xA8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xA8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xA8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xA8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xA8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xA8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xA8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xA8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xA8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xA8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xA8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xA8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xA8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xA8 0. "PRIV0,PRIV0" "0,1" line.long 0xAC "MPCBB6_PRIVCFGR43,MPCBB privileged configuration for super-block x register" bitfld.long 0xAC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xAC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xAC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xAC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xAC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xAC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xAC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xAC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xAC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xAC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xAC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xAC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xAC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xAC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xAC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xAC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xAC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xAC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xAC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xAC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xAC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xAC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xAC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xAC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xAC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xAC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xAC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xAC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xAC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xAC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xAC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xAC 0. "PRIV0,PRIV0" "0,1" line.long 0xB0 "MPCBB6_PRIVCFGR44,MPCBB privileged configuration for super-block x register" bitfld.long 0xB0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB0 0. "PRIV0,PRIV0" "0,1" line.long 0xB4 "MPCBB6_PRIVCFGR45,MPCBB privileged configuration for super-block x register" bitfld.long 0xB4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB4 0. "PRIV0,PRIV0" "0,1" line.long 0xB8 "MPCBB6_PRIVCFGR46,MPCBB privileged configuration for super-block x register" bitfld.long 0xB8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xB8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xB8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xB8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xB8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xB8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xB8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xB8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xB8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xB8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xB8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xB8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xB8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xB8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xB8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xB8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xB8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xB8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xB8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xB8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xB8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xB8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xB8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xB8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xB8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xB8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xB8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xB8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xB8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xB8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xB8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xB8 0. "PRIV0,PRIV0" "0,1" line.long 0xBC "MPCBB6_PRIVCFGR47,MPCBB privileged configuration for super-block x register" bitfld.long 0xBC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xBC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xBC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xBC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xBC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xBC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xBC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xBC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xBC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xBC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xBC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xBC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xBC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xBC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xBC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xBC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xBC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xBC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xBC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xBC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xBC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xBC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xBC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xBC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xBC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xBC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xBC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xBC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xBC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xBC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xBC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xBC 0. "PRIV0,PRIV0" "0,1" line.long 0xC0 "MPCBB6_PRIVCFGR48,MPCBB privileged configuration for super-block x register" bitfld.long 0xC0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC0 0. "PRIV0,PRIV0" "0,1" line.long 0xC4 "MPCBB6_PRIVCFGR49,MPCBB privileged configuration for super-block x register" bitfld.long 0xC4 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC4 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC4 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC4 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC4 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC4 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC4 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC4 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC4 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC4 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC4 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC4 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC4 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC4 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC4 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC4 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC4 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC4 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC4 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC4 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC4 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC4 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC4 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC4 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC4 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC4 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC4 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC4 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC4 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC4 0. "PRIV0,PRIV0" "0,1" line.long 0xC8 "MPCBB6_PRIVCFGR50,MPCBB privileged configuration for super-block x register" bitfld.long 0xC8 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xC8 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xC8 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xC8 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xC8 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xC8 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xC8 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xC8 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xC8 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xC8 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xC8 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xC8 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xC8 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xC8 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xC8 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xC8 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xC8 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xC8 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xC8 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xC8 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xC8 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xC8 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xC8 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xC8 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xC8 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xC8 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xC8 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xC8 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xC8 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xC8 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xC8 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xC8 0. "PRIV0,PRIV0" "0,1" line.long 0xCC "MPCBB6_PRIVCFGR51,MPCBB privileged configuration for super-block x register" bitfld.long 0xCC 31. "PRIV31,PRIV31" "0,1" bitfld.long 0xCC 30. "PRIV30,PRIV30" "0,1" bitfld.long 0xCC 29. "PRIV29,PRIV29" "0,1" bitfld.long 0xCC 28. "PRIV28,PRIV28" "0,1" bitfld.long 0xCC 27. "PRIV27,PRIV27" "0,1" bitfld.long 0xCC 26. "PRIV26,PRIV26" "0,1" bitfld.long 0xCC 25. "PRIV25,PRIV25" "0,1" bitfld.long 0xCC 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0xCC 23. "PRIV23,PRIV23" "0,1" bitfld.long 0xCC 22. "PRIV22,PRIV22" "0,1" bitfld.long 0xCC 21. "PRIV21,PRIV21" "0,1" bitfld.long 0xCC 20. "PRIV20,PRIV20" "0,1" bitfld.long 0xCC 19. "PRIV19,PRIV19" "0,1" bitfld.long 0xCC 18. "PRIV18,PRIV18" "0,1" bitfld.long 0xCC 17. "PRIV17,PRIV17" "0,1" bitfld.long 0xCC 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0xCC 15. "PRIV15,PRIV15" "0,1" bitfld.long 0xCC 14. "PRIV14,PRIV14" "0,1" bitfld.long 0xCC 13. "PRIV13,PRIV13" "0,1" bitfld.long 0xCC 12. "PRIV12,PRIV12" "0,1" bitfld.long 0xCC 11. "PRIV11,PRIV11" "0,1" bitfld.long 0xCC 10. "PRIV10,PRIV10" "0,1" bitfld.long 0xCC 9. "PRIV9,PRIV9" "0,1" bitfld.long 0xCC 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0xCC 7. "PRIV7,PRIV7" "0,1" bitfld.long 0xCC 6. "PRIV6,PRIV6" "0,1" bitfld.long 0xCC 5. "PRIV5,PRIV5" "0,1" bitfld.long 0xCC 4. "PRIV4,PRIV4" "0,1" bitfld.long 0xCC 3. "PRIV3,PRIV3" "0,1" bitfld.long 0xCC 2. "PRIV2,PRIV2" "0,1" bitfld.long 0xCC 1. "PRIV1,PRIV1" "0,1" bitfld.long 0xCC 0. "PRIV0,PRIV0" "0,1" tree.end tree "SEC_GTZC1_TZIC" base ad:0x50032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 10. "DSIIE,illegal access interrupt enable for DSI" "0,1" bitfld.long 0x4 9. "LTDCIE,illegal access interrupt enable for LTDC" "0,1" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 27. "DCACHE2_REGIE,DCACHE2_REGIE" "0,1" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 25. "GFXMMU_REGIE,GFXMMU_REGIE" "0,1" bitfld.long 0x8 24. "GFXMMUIE,GFXMMUIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" newline bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" newline bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 10. "DSIF,illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "LTDCF,illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 27. "DCACHE2_REGF,illegal access flag for DCACHE2 registers" "0,1" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 25. "GFXMMU_REGF,illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "GFXMMUF,illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" newline bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 10. "CDSIF,clear the illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "CLTDCF,clear the illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 27. "CDCACHE2_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 26. "CHSPI1_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 25. "CGFXMMU_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "CGFXMMUF,clear the illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" newline bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "GTZC1_TZIC" base ad:0x40032800 group.long 0x0++0xF line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 23. "I2C6IE,illegal access interrupt enable for I2C6" "0,1" bitfld.long 0x0 22. "I2C5IE,illegal access interrupt enable for I2C5" "0,1" bitfld.long 0x0 21. "USART6IE,illegal access interrupt enable for USART6" "0,1" bitfld.long 0x0 19. "UCPD1IE,illegal access interrupt enable for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1IE,illegal access interrupt enable for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2IE,illegal access interrupt enable for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4IE,illegal access interrupt enable for I2C4" "0,1" bitfld.long 0x0 15. "CRSIE,illegal access interrupt enable for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2IE,illegal access interrupt enable for I2C2" "0,1" bitfld.long 0x0 13. "I2C1IE,illegal access interrupt enable for I2C1" "0,1" bitfld.long 0x0 12. "UART5IE,illegal access interrupt enable for UART5" "0,1" bitfld.long 0x0 11. "USART4IE,illegal access interrupt enable for UART4" "0,1" bitfld.long 0x0 10. "USART3IE,illegal access interrupt enable for USART3" "0,1" bitfld.long 0x0 9. "USART2IE,illegal access interrupt enable for USART2" "0,1" bitfld.long 0x0 8. "SPI2IE,SPI2IE" "0,1" bitfld.long 0x0 7. "IWDGIE,IWDGIE" "0,1" newline bitfld.long 0x0 6. "WWDGIE,WWDGIE" "0,1" bitfld.long 0x0 5. "TIM7IE,TIM7IE" "0,1" bitfld.long 0x0 4. "TIM6IE,TIM6IE" "0,1" bitfld.long 0x0 3. "TIM5IE,TIM5IE" "0,1" bitfld.long 0x0 2. "TIM4IE,TIM4IE" "0,1" bitfld.long 0x0 1. "TIM3IE,TIM3IE" "0,1" bitfld.long 0x0 0. "TIM2IE,TIM2IE" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 10. "DSIIE,illegal access interrupt enable for DSI" "0,1" bitfld.long 0x4 9. "LTDCIE,illegal access interrupt enable for LTDC" "0,1" bitfld.long 0x4 8. "SAI2IE,illegal access interrupt enable for SAI2" "0,1" bitfld.long 0x4 7. "SAI1IE,illegal access interrupt enable for SAI1" "0,1" bitfld.long 0x4 6. "TIM17IE,illegal access interrupt enable for TIM7" "0,1" bitfld.long 0x4 5. "TIM16IE,illegal access interrupt enable for TIM6" "0,1" bitfld.long 0x4 4. "TIM15IE,illegal access interrupt enable for TIM5" "0,1" bitfld.long 0x4 3. "USART1IE,illegal access interrupt enable for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8IE,illegal access interrupt enable for TIM8" "0,1" bitfld.long 0x4 1. "SPI1IE,illegal access interrupt enable for SPI1" "0,1" bitfld.long 0x4 0. "TIM1IE,illegal access interrupt enable for TIM1" "0,1" line.long 0x8 "IER3,TZIC interrupt enable register 3" bitfld.long 0x8 27. "DCACHE2_REGIE,DCACHE2_REGIE" "0,1" bitfld.long 0x8 26. "HSPI1_REGIE,HSPI1_REGIE" "0,1" bitfld.long 0x8 25. "GFXMMU_REGIE,GFXMMU_REGIE" "0,1" bitfld.long 0x8 24. "GFXMMUIE,GFXMMUIE" "0,1" bitfld.long 0x8 23. "GPU2DIE,GPU2DIE" "0,1" bitfld.long 0x8 22. "RAMCFGIE,illegal access interrupt enable for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGIE,illegal access interrupt enable for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGIE,illegal access interrupt enable for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGIE,illegal access interrupt enable for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2IE,illegal access interrupt enable for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1IE,illegal access interrupt enable for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMIE,illegal access interrupt enable for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESIE,illegal access interrupt enable for SAES" "0,1" bitfld.long 0x8 14. "PKAIE,illegal access interrupt enable for PKA" "0,1" bitfld.long 0x8 13. "RNGIE,illegal access interrupt enable for RNG" "0,1" bitfld.long 0x8 12. "HASHIE,illegal access interrupt enable for HASH" "0,1" newline bitfld.long 0x8 11. "AESIE,illegal access interrupt enable for AES" "0,1" bitfld.long 0x8 10. "OTGIE,illegal access interrupt enable for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIIE,illegal access interrupt enable for DCMI" "0,1" bitfld.long 0x8 8. "ADC1I2E,illegal access interrupt enable for ADC1 or ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGIE,illegal access interrupt enable for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGIE,illegal access interrupt enable for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DIE,illegal access interrupt enable for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCIE,illegal access interrupt enable for TSC" "0,1" newline bitfld.long 0x8 3. "CRCIE,illegal access interrupt enable for CRC" "0,1" bitfld.long 0x8 2. "FMACIE,illegal access interrupt enable for FMAC" "0,1" bitfld.long 0x8 1. "CORDICIE,illegal access interrupt enable for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1IE,illegal access interrupt enable for MDF1" "0,1" line.long 0xC "IER4,TZIC interrupt enable register 4" bitfld.long 0xC 31. "MPCBB5_REGIE,illegal access interrupt enable for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5IE,illegal access interrupt enable for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGIE,illegal access interrupt enable for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3IE,illegal access interrupt enable for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGIE,illegal access interrupt enable for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2IE,illegal access interrupt enable for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGIE,illegal access interrupt enable for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1IE,illegal access interrupt enable for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMIE,illegal access interrupt enable for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMIE,illegal access interrupt enable for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMIE,illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMIE,illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMIE,illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1IE,illegal access interrupt enable for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1IE,illegal access interrupt enable for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2IE,illegal access interrupt enable for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1IE,illegal access interrupt enable for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHIE,illegal access interrupt enable for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGIE,illegal access interrupt enable for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1IE,illegal access interrupt enable for GPDMA1" "0,1" rgroup.long 0x10++0xF line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 23. "I2C6F,illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "I2C5F,illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "USART6F,illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "UCPD1F,illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1F,illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2F,illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "I2C4F,illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CRSF,illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "I2C2F,illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "I2C1F,illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "UART5F,illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "UART4F,illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "USART3F,illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "USART2F,illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "SPI2F,illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "IWDGF,illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "WWDGF,illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "TIM7F,illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "TIM6F,illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "TIM5F,illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "TIM4F,illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "TIM3F,illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "TIM2F,illegal access flag for TIM2" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 10. "DSIF,illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "LTDCF,illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "SAI2F,illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "SAI1F,illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "TIM17F,illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "TIM16F,illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "TIM15F,illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "USART1F,illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "TIM8F,illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "SPI1F,illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "TIM1F,illegal access flag for TIM1" "0,1" line.long 0x8 "SR3,TZIC status register 3" bitfld.long 0x8 27. "DCACHE2_REGF,illegal access flag for DCACHE2 registers" "0,1" bitfld.long 0x8 26. "HSPI1_REGF,illegal access flag for HSPI1 registers" "0,1" bitfld.long 0x8 25. "GFXMMU_REGF,illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "GFXMMUF,illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "GPU2DF,illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "RAMCFGF,illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "OCTOSPI2_REGF,illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGF,illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "FSMC_REGF,illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2F,illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1F,illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMF,illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "SAESF,illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "PKAF,illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "RNGF,illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "HASHF,illegal access flag for HASH" "0,1" newline bitfld.long 0x8 11. "AESF,illegal access flag for AES" "0,1" bitfld.long 0x8 10. "OTGF,illegal access flag for OTG_FS or OTG_HS" "0,1" bitfld.long 0x8 9. "DCMIF,illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "ADC12F,illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "DCACHE1_REGF,illegal access flag for DCACHE registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGF,illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DF,illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCF,illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CRCF,illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "FMACF,illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CORDICF,illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1F,illegal access flag for MDF1" "0,1" line.long 0xC "SR4,TZIC status register 4" bitfld.long 0xC 31. "MPCBB5_REGF,illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "SRAM5F,illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "MPCBB3_REGF,illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "SRAM3F,illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "MPCBB2_REGF,illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "SRAM2F,illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "MPCBB1_REGF,illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "SRAM1F,illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "HSPI1_MEMF,illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "OCTOSPI2_MEMF,illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "BKPSRAMF,illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "FSMC_MEMF,illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)" "0,1" bitfld.long 0xC 16. "OCTOSPI1_MEMF,illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "TZIC1F,illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "TZSC1F,illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "OTFDEC2F,illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "OTFDEC1F,illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "FLASHF,illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "FLASH_REGF,illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "GPDMA1F,illegal access flag for GPDMA1" "0,1" wgroup.long 0x20++0xF line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 23. "CI2C6F,clear the illegal access flag for I2C6" "0,1" bitfld.long 0x0 22. "CI2C5F,clear the illegal access flag for I2C5" "0,1" bitfld.long 0x0 21. "CUSART6F,clear the illegal access flag for USART6" "0,1" bitfld.long 0x0 19. "CUCPD1F,clear the illegal access flag for UCPD1" "0,1" bitfld.long 0x0 18. "CFDCAN1F,clear the illegal access flag for FDCAN1" "0,1" bitfld.long 0x0 17. "CLPTIM2F,clear the illegal access flag for LPTIM2" "0,1" bitfld.long 0x0 16. "CI2C4F,clear the illegal access flag for I2C4" "0,1" bitfld.long 0x0 15. "CCRSF,clear the illegal access flag for CRS" "0,1" newline bitfld.long 0x0 14. "CI2C2F,clear the illegal access flag for I2C2" "0,1" bitfld.long 0x0 13. "CI2C1F,clear the illegal access flag for I2C1" "0,1" bitfld.long 0x0 12. "CUART5F,clear the illegal access flag for UART5" "0,1" bitfld.long 0x0 11. "CUART4F,clear the illegal access flag for UART4" "0,1" bitfld.long 0x0 10. "CUSART3F,clear the illegal access flag for USART3" "0,1" bitfld.long 0x0 9. "CUSART2F,clear the illegal access flag for USART2" "0,1" bitfld.long 0x0 8. "CSPI2F,clear the illegal access flag for SPI2" "0,1" bitfld.long 0x0 7. "CIWDGF,clear the illegal access flag for IWDG" "0,1" newline bitfld.long 0x0 6. "CWWDGF,clear the illegal access flag for WWDG" "0,1" bitfld.long 0x0 5. "CTIM7F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x0 4. "CTIM6F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x0 3. "CTIM5F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x0 2. "CTIM4F,clear the illegal access flag for TIM4" "0,1" bitfld.long 0x0 1. "CTIM3F,clear the illegal access flag for TIM3" "0,1" bitfld.long 0x0 0. "CTIM2F,clear the illegal access flag for TIM2" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 10. "CDSIF,clear the illegal access flag for DSI" "0,1" bitfld.long 0x4 9. "CLTDCF,clear the illegal access flag for LTDC" "0,1" bitfld.long 0x4 8. "CSAI2F,clear the illegal access flag for SAI2" "0,1" bitfld.long 0x4 7. "CSAI1F,clear the illegal access flag for SAI1" "0,1" bitfld.long 0x4 6. "CTIM17F,clear the illegal access flag for TIM7" "0,1" bitfld.long 0x4 5. "CTIM16F,clear the illegal access flag for TIM6" "0,1" bitfld.long 0x4 4. "CTIM15F,clear the illegal access flag for TIM5" "0,1" bitfld.long 0x4 3. "CUSART1F,clear the illegal access flag for USART1" "0,1" newline bitfld.long 0x4 2. "CTIM8F,clear the illegal access flag for TIM8" "0,1" bitfld.long 0x4 1. "CSPI1F,clear the illegal access flag for SPI1" "0,1" bitfld.long 0x4 0. "CTIM1F,clear the illegal access flag for TIM1" "0,1" line.long 0x8 "FCR3,TZIC flag clear register 3" bitfld.long 0x8 27. "CDCACHE2_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 26. "CHSPI1_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 25. "CGFXMMU_REGF,clear the illegal access flag for GFXMMU registers" "0,1" bitfld.long 0x8 24. "CGFXMMUF,clear the illegal access flag for GFXMMU" "0,1" bitfld.long 0x8 23. "CGPU2DF,clear the illegal access flag for GPU2D" "0,1" bitfld.long 0x8 22. "CRAMCFGF,clear the illegal access flag for RAMCFG" "0,1" bitfld.long 0x8 21. "COCTOSPI2_REGF,clear the illegal access flag for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "COCTOSPI1_REGF,clear the illegal access flag for OCTOSPI1 registers" "0,1" newline bitfld.long 0x8 19. "CFSMC_REGF,clear the illegal access flag for FSMC registers" "0,1" bitfld.long 0x8 18. "CSDMMC2F,clear the illegal access flag for SDMMC1" "0,1" bitfld.long 0x8 17. "CSDMMC1F,clear the illegal access flag for SDMMC2" "0,1" bitfld.long 0x8 16. "COCTOSPIMF,clear the illegal access flag for OCTOSPIM" "0,1" bitfld.long 0x8 15. "CSAESF,clear the illegal access flag for SAES" "0,1" bitfld.long 0x8 14. "CPKAF,clear the illegal access flag for PKA" "0,1" bitfld.long 0x8 13. "CRNGF,clear the illegal access flag for RNG" "0,1" bitfld.long 0x8 12. "CHASHF,clear the illegal access flag for HASH" "0,1" newline bitfld.long 0x8 11. "CAESF,clear the illegal access flag for AES" "0,1" bitfld.long 0x8 10. "COTGF,clear the illegal access flag for OTG_FS" "0,1" bitfld.long 0x8 9. "CDCMIF,clear the illegal access flag for DCMI" "0,1" bitfld.long 0x8 8. "CADC12F,clear the illegal access flag for ADC1 and ADC2" "0,1" bitfld.long 0x8 7. "CDCACHE1_REGF,clear the illegal access flag for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "CICACHE_REGF,clear the illegal access flag for ICACHE registers" "0,1" bitfld.long 0x8 5. "CDMA2DF,clear the illegal access flag for register of DMA2D" "0,1" bitfld.long 0x8 4. "CTSCF,clear the illegal access flag for TSC" "0,1" newline bitfld.long 0x8 3. "CCRCF,clear the illegal access flag for CRC" "0,1" bitfld.long 0x8 2. "CFMACF,clear the illegal access flag for FMAC" "0,1" bitfld.long 0x8 1. "CCORDICF,clear the illegal access flag for CORDIC" "0,1" bitfld.long 0x8 0. "CMDF1F,clear the illegal access flag for MDF1" "0,1" line.long 0xC "FCR4,TZIC flag clear register 4" bitfld.long 0xC 31. "CMPCBB5_REGF,clear the illegal access flag for MPCBB5 registers" "0,1" bitfld.long 0xC 30. "CSRAM5F,clear the illegal access flag for SRAM5" "0,1" bitfld.long 0xC 29. "CMPCBB3_REGF,clear the illegal access flag for MPCBB3 registers" "0,1" bitfld.long 0xC 28. "CSRAM3F,clear the illegal access flag for SRAM3" "0,1" bitfld.long 0xC 27. "CMPCBB2_REGF,clear the illegal access flag for MPCBB2 registers" "0,1" bitfld.long 0xC 26. "CSRAM2F,clear the illegal access flag for SRAM2" "0,1" bitfld.long 0xC 25. "CMPCBB1_REGF,clear the illegal access flag for MPCBB1 registers" "0,1" bitfld.long 0xC 24. "CSRAM1F,clear the illegal access flag for SRAM1" "0,1" newline bitfld.long 0xC 20. "CHSPI1_MEMF,clear the illegal access flag for HSPI1 memory bank" "0,1" bitfld.long 0xC 19. "COCTOSPI2_MEMF,clear the illegal access flag for OCTOSPI2 memory bank" "0,1" bitfld.long 0xC 18. "CBKPSRAMF,clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank" "0,1" bitfld.long 0xC 17. "CFSMC_MEMF,clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3" "0,1" bitfld.long 0xC 16. "COCTOSPI1_MEMF,clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank" "0,1" bitfld.long 0xC 15. "CTZIC1F,clear the illegal access flag for GTZC1 TZIC registers" "0,1" bitfld.long 0xC 14. "CTZSC1F,clear the illegal access flag for GTZC1 TZSC registers" "0,1" bitfld.long 0xC 4. "COTFDEC2F,clear the illegal access flag for OTFDEC2" "0,1" newline bitfld.long 0xC 3. "COTFDEC1F,clear the illegal access flag for OTFDEC1" "0,1" bitfld.long 0xC 2. "CFLASHF,clear the illegal access flag for FLASH memory" "0,1" bitfld.long 0xC 1. "CFLASH_REGF,clear the illegal access flag for FLASH registers" "0,1" bitfld.long 0xC 0. "CGPDMA1F,clear the illegal access flag for GPDMA1" "0,1" tree.end tree "SEC_GTZC1_TZSC" base ad:0x50032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 10. "DSISEC,DSISEC" "0,1" bitfld.long 0x4 9. "LTDCSEC,LTDCSEC" "0,1" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" newline bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGSEC,DCACHE2_REGSEC" "0,1" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 25. "GFXMMU_REGSEC,GFXMMU_REGSEC" "0,1" bitfld.long 0x8 24. "GFXMMUSEC,GFXMMUSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" newline bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" newline bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 10. "DSIPRIV,DSIPRIV" "0,1" bitfld.long 0x4 9. "LTDCPRIV,LTDCPRIV" "0,1" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" newline bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGPRIV,DCACHE2_REGPRIV" "0,1" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 25. "GFXMMU_REGPRIV,GFXMMU_REGPRIV" "0,1" bitfld.long 0x8 24. "GFXMMUPRIV,GFXMMUPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" newline bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" newline bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end endif sif (cpuis("STM32U5G*")) tree "GTZC1_TZSC" base ad:0x40032400 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0xB line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 23. "I2C6SEC,I2C6SEC" "0,1" bitfld.long 0x0 22. "I2C5SEC,I2C5SEC" "0,1" bitfld.long 0x0 21. "USART6SEC,USART6SEC" "0,1" bitfld.long 0x0 19. "UCPD1SEC,secure access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1SEC,secure access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2SEC,secure access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4SEC,secure access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSSEC,secure access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2SEC,secure access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1SEC,secure access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5SEC,secure access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4SEC,secure access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3SEC,secure access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2SEC,secure access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2SEC,secure access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGSEC,secure access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGSEC,secure access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7SEC,secure access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6SEC,secure access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5SEC,secure access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4SEC,secure access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3SEC,secure access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2SEC,secure access mode for TIM2" "0,1" line.long 0x4 "TZSC_SECCFGR2,TZSC secure configuration register 2" bitfld.long 0x4 10. "DSISEC,DSISEC" "0,1" bitfld.long 0x4 9. "LTDCSEC,LTDCSEC" "0,1" bitfld.long 0x4 8. "SAI2SEC,secure access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1SEC,secure access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17SEC,secure access mode for TIM7" "0,1" bitfld.long 0x4 5. "TIM16SEC,secure access mode for TIM6" "0,1" newline bitfld.long 0x4 4. "TIM15SEC,secure access mode for TIM5" "0,1" bitfld.long 0x4 3. "USART1SEC,secure access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8SEC,secure access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1SEC,secure access mode for SPI1" "0,1" bitfld.long 0x4 0. "TIM1SEC,secure access mode for TIM1" "0,1" line.long 0x8 "TZSC_SECCFGR3,TZSC secure configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGSEC,DCACHE2_REGSEC" "0,1" bitfld.long 0x8 26. "HSPI1_REGSEC,HSPI1_REGSEC" "0,1" bitfld.long 0x8 25. "GFXMMU_REGSEC,GFXMMU_REGSEC" "0,1" bitfld.long 0x8 24. "GFXMMUSEC,GFXMMUSEC" "0,1" bitfld.long 0x8 23. "GPU2DSEC,GPU2DSEC" "0,1" bitfld.long 0x8 22. "RAMCFGSEC,secure access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGSEC,secure access mode for OCTOSPI2 registers" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGSEC,secure access mode for OCTOSPI1 registers" "0,1" bitfld.long 0x8 19. "FSMC_REGSEC,secure access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2SEC,secure access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1SEC,secure access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMSEC,secure access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESSEC,secure access mode for SAES" "0,1" bitfld.long 0x8 14. "PKASEC,secure access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGSEC,secure access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHSEC,secure access mode for HASH" "0,1" bitfld.long 0x8 11. "AESSEC,secure access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSSEC,secure access mode for OTG_FS" "0,1" newline bitfld.long 0x8 9. "DCMISEC,secure access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1SEC,secure access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGSEC,secure access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGSEC,secure access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DSEC,secure access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCSEC,secure access mode for TSC" "0,1" newline bitfld.long 0x8 3. "CRCSEC,secure access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACSEC,secure access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICSEC,secure access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1SEC,secure access mode for MDF1" "0,1" group.long 0x20++0xB line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 23. "I2C6PRIV,I2C6PRIV" "0,1" bitfld.long 0x0 22. "I2C5PRIV,I2C5PRIV" "0,1" bitfld.long 0x0 21. "USART6PRIV,USART6PRIV" "0,1" bitfld.long 0x0 19. "UCPD1PRIV,privileged access mode for UCPD1" "0,1" bitfld.long 0x0 18. "FDCAN1PRIV,privileged access mode for FDCAN1" "0,1" bitfld.long 0x0 17. "LPTIM2PRIV,privileged access mode for LPTIM2" "0,1" newline bitfld.long 0x0 16. "I2C4PRIV,privileged access mode for I2C4" "0,1" bitfld.long 0x0 15. "CRSPRIV,privileged access mode for CRS" "0,1" bitfld.long 0x0 14. "I2C2PRIV,privileged access mode for I2C2" "0,1" bitfld.long 0x0 13. "I2C1PRIV,privileged access mode for I2C1" "0,1" bitfld.long 0x0 12. "UART5PRIV,privileged access mode for UART5" "0,1" bitfld.long 0x0 11. "UART4PRIV,privileged access mode for UART4" "0,1" newline bitfld.long 0x0 10. "USART3PRIV,privileged access mode for USART3" "0,1" bitfld.long 0x0 9. "USART2PRIV,privileged access mode for USART2" "0,1" bitfld.long 0x0 8. "SPI2PRIV,privileged access mode for SPI2" "0,1" bitfld.long 0x0 7. "IWDGPRIV,privileged access mode for IWDG" "0,1" bitfld.long 0x0 6. "WWDGPRIV,privileged access mode for WWDG" "0,1" bitfld.long 0x0 5. "TIM7PRIV,privileged access mode for TIM7" "0,1" newline bitfld.long 0x0 4. "TIM6PRIV,privileged access mode for TIM6" "0,1" bitfld.long 0x0 3. "TIM5PRIV,privileged access mode for TIM5" "0,1" bitfld.long 0x0 2. "TIM4PRIV,privileged access mode for TIM4" "0,1" bitfld.long 0x0 1. "TIM3PRIV,privileged access mode for TIM3" "0,1" bitfld.long 0x0 0. "TIM2PRIV,privileged access mode for TIM2" "0,1" line.long 0x4 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2" bitfld.long 0x4 10. "DSIPRIV,DSIPRIV" "0,1" bitfld.long 0x4 9. "LTDCPRIV,LTDCPRIV" "0,1" bitfld.long 0x4 8. "SAI2PRIV,privileged access mode for SAI2" "0,1" bitfld.long 0x4 7. "SAI1PRIV,privileged access mode for SAI1" "0,1" bitfld.long 0x4 6. "TIM17PRIV,privileged access mode for TIM17" "0,1" bitfld.long 0x4 5. "TIM16PRIV,privileged access mode for TIM16" "0,1" newline bitfld.long 0x4 4. "TIM15PRIV,privileged access mode for TIM15" "0,1" bitfld.long 0x4 3. "USART1PRIV,privileged access mode for USART1" "0,1" bitfld.long 0x4 2. "TIM8PRIV,privileged access mode for TIM8" "0,1" bitfld.long 0x4 1. "SPI1PRIV,privileged access mode for SPI1PRIV" "0,1" bitfld.long 0x4 0. "TIM1PRIV,privileged access mode for TIM1" "0,1" line.long 0x8 "TZSC_PRIVCFGR3,TZSC privilege configuration register 3" bitfld.long 0x8 27. "DCACHE2_REGPRIV,DCACHE2_REGPRIV" "0,1" bitfld.long 0x8 26. "HSPI1_REGPRIV,HSPI1_REGPRIV" "0,1" bitfld.long 0x8 25. "GFXMMU_REGPRIV,GFXMMU_REGPRIV" "0,1" bitfld.long 0x8 24. "GFXMMUPRIV,GFXMMUPRIV" "0,1" bitfld.long 0x8 23. "GPU2DPRIV,GPU2DPRIV" "0,1" bitfld.long 0x8 22. "RAMCFGPRIV,privileged access mode for RAMCFG" "0,1" newline bitfld.long 0x8 21. "OCTOSPI2_REGPRIV,privileged access mode for OCTOSPI2" "0,1" bitfld.long 0x8 20. "OCTOSPI1_REGPRIV,privileged access mode for OCTOSPI1" "0,1" bitfld.long 0x8 19. "FSMC_REGPRIV,privileged access mode for FSMC registers" "0,1" bitfld.long 0x8 18. "SDMMC2PRIV,privileged access mode for SDMMC1" "0,1" bitfld.long 0x8 17. "SDMMC1PRIV,privileged access mode for SDMMC2" "0,1" bitfld.long 0x8 16. "OCTOSPIMPRIV,privileged access mode for OCTOSPIM" "0,1" newline bitfld.long 0x8 15. "SAESPRIV,privileged access mode for SAES" "0,1" bitfld.long 0x8 14. "PKAPRIV,privileged access mode for PKA" "0,1" bitfld.long 0x8 13. "RNGPRIV,privileged access mode for RNG" "0,1" bitfld.long 0x8 12. "HASHPRIV,privileged access mode for HASH" "0,1" bitfld.long 0x8 11. "AESPRIV,privileged access mode for AES" "0,1" bitfld.long 0x8 10. "OTGFSPRIV,privileged access mode for OTG_FS" "0,1" newline bitfld.long 0x8 9. "DCMIPRIV,privileged access mode for DCMI" "0,1" bitfld.long 0x8 8. "ADC1PRIV,privileged access mode for ADC1" "0,1" bitfld.long 0x8 7. "DCACHE1_REGPRIV,privileged access mode for DCACHE1 registers" "0,1" bitfld.long 0x8 6. "ICACHE_REGPRIV,privileged access mode for ICACHE registers" "0,1" bitfld.long 0x8 5. "DMA2DPRIV,privileged access mode for register of DMA2D" "0,1" bitfld.long 0x8 4. "TSCPRIV,privileged access mode for TSC" "0,1" newline bitfld.long 0x8 3. "CRCPRIV,privileged access mode for CRC" "0,1" bitfld.long 0x8 2. "FMACPRIV,privileged access mode for FMAC" "0,1" bitfld.long 0x8 1. "CORDICPRIV,privileged access mode for CORDIC" "0,1" bitfld.long 0x8 0. "MDF1PRIV,privileged access mode for MDF1" "0,1" group.long 0x40++0x27 line.long 0x0 "TZSC_MPCWM1ACFGR,TZSC memory 1 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM1AR,TZSC memory 1 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM1BCFGR,TZSC memory 1 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM1BR,TZSC memory 1 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM2ACFGR,TZSC memory 2 sub-region A watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM2AR,TZSC memory 2 sub-region A watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM2BCFGR,TZSC memory 2 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM2BR,TZSC memory 2 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x20 "TZSC_MPCWM3ACFGR,TZSC memory 3 sub-region A watermark configuration register" bitfld.long 0x20 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x20 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x20 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x20 0. "SREN,Sub-region enable" "0,1" line.long 0x24 "TZSC_MPCWM3AR,TZSC memory 3 sub-region A watermark register" hexmask.long.word 0x24 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x24 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x70++0x7 line.long 0x0 "TZSC_MPCWM4ACFGR,TZSC memory 4 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM4AR,TZSC memory 4 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" group.long 0x80++0x1F line.long 0x0 "TZSC_MPCWM5ACFGR,TZSC memory 5 sub-region A watermark configuration register" bitfld.long 0x0 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x0 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x0 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x0 0. "SREN,Sub-region enable" "0,1" line.long 0x4 "TZSC_MPCWM5AR,TZSC memory 5 sub-region A watermark register" hexmask.long.word 0x4 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x4 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x8 "TZSC_MPCWM5BCFGR,TZSC memory 5 sub-region B watermark configuration register" bitfld.long 0x8 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x8 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x8 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x8 0. "SREN,Sub-region enable" "0,1" line.long 0xC "TZSC_MPCWM5BR,TZSC memory 5 sub-region B watermark register" hexmask.long.word 0xC 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0xC 0.--10. 1. "SUBB_START,Start of sub-region A" line.long 0x10 "TZSC_MPCWM6ACFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x10 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x10 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x10 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x10 0. "SREN,Sub-region enable" "0,1" line.long 0x14 "TZSC_MPCWM6AR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x14 16.--27. 1. "SUBA_LENGTH,Length of sub-region A" hexmask.long.word 0x14 0.--10. 1. "SUBA_START,Start of sub-region A" line.long 0x18 "TZSC_MPCWM6BCFGR,TZSC memory 6 sub-region B watermark configuration register" bitfld.long 0x18 9. "PRIV,Privileged sub-region" "0,1" bitfld.long 0x18 8. "SEC,Secure sub-region" "0,1" bitfld.long 0x18 1. "SRLOCK,Sub-region lock" "0,1" bitfld.long 0x18 0. "SREN,Sub-region enable" "0,1" line.long 0x1C "TZSC_MPCWM6BR,TZSC memory 6 sub-region B watermark register" hexmask.long.word 0x1C 16.--27. 1. "SUBB_LENGTH,Length of sub-region A" hexmask.long.word 0x1C 0.--10. 1. "SUBB_START,Start of sub-region A" tree.end tree "GTZC2_TZIC" base ad:0x46023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "GTZC2_TZSC" base ad:0x46023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif tree "GTZC2_MPCBB4" base ad:0x46023800 group.long 0x0++0x3 line.long 0x0 "MPCBB4_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB4_CFGLOCK,GTZC2 SRAM4 MPCBB configuration lock register" bitfld.long 0x0 0. "SPLCK0,Security/privilege configuration lock for super-block 0" "0,1" group.long 0x100++0x3 line.long 0x0 "MPCBB4_SECCFGR0,MPCBB security configuration for super-block 0 register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" group.long 0x200++0x3 line.long 0x0 "MPCBB4_PRIVCFGR0,MPCBB privileged configuration for super-block 0 register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" tree.end sif (cpuis("STM32U575*")) tree "SEC_GTZC2_TZIC" base ad:0x56023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4IE,illegal access interrupt enable for ADC4" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4F,illegal access flag for ADC4" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC4F,clear the illegal access flag for ADC4" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U575*")) tree "SEC_GTZC2_TZSC" base ad:0x56023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4SEC,secure access mode for ADC4" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4PRIV,privileged access mode for ADC4" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "SEC_GTZC2_TZIC" base ad:0x56023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4IE,illegal access interrupt enable for ADC4" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4F,illegal access flag for ADC4" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC4F,clear the illegal access flag for ADC4" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "SEC_GTZC2_TZSC" base ad:0x56023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4SEC,secure access mode for ADC4" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC4PRIV,privileged access mode for ADC4" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "SEC_GTZC2_TZIC" base ad:0x56023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "SEC_GTZC2_TZSC" base ad:0x56023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "SEC_GTZC2_TZIC" base ad:0x56023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "SEC_GTZC2_TZSC" base ad:0x56023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "SEC_GTZC2_TZIC" base ad:0x56023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "SEC_GTZC2_TZSC" base ad:0x56023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "SEC_GTZC2_TZIC" base ad:0x56023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "SEC_GTZC2_TZSC" base ad:0x56023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "SEC_GTZC2_TZIC" base ad:0x56023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "SEC_GTZC2_TZSC" base ad:0x56023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "SEC_GTZC2_TZIC" base ad:0x56023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "SEC_GTZC2_TZSC" base ad:0x56023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif tree "SEC_GTZC2_MPCBB4" base ad:0x56023800 group.long 0x0++0x3 line.long 0x0 "MPCBB4_CR,MPCBB control register" bitfld.long 0x0 31. "SRWILADIS,secure read/write illegal access disable" "0,1" bitfld.long 0x0 30. "INVSECSTATE,SRAMx clocks security state" "0,1" bitfld.long 0x0 0. "GLOCK,lock the control register of the MPCBB until next reset" "0,1" group.long 0x10++0x3 line.long 0x0 "MPCBB4_CFGLOCK,GTZC2 SRAM4 MPCBB configuration lock register" bitfld.long 0x0 0. "SPLCK0,Security/privilege configuration lock for super-block 0" "0,1" group.long 0x100++0x3 line.long 0x0 "MPCBB4_SECCFGR0,MPCBB security configuration for super-block 0 register" bitfld.long 0x0 31. "SEC31,SEC31" "0,1" bitfld.long 0x0 30. "SEC30,SEC30" "0,1" bitfld.long 0x0 29. "SEC29,SEC29" "0,1" bitfld.long 0x0 28. "SEC28,SEC28" "0,1" bitfld.long 0x0 27. "SEC27,SEC27" "0,1" bitfld.long 0x0 26. "SEC26,SEC26" "0,1" bitfld.long 0x0 25. "SEC25,SEC25" "0,1" bitfld.long 0x0 24. "SEC24,SEC24" "0,1" newline bitfld.long 0x0 23. "SEC23,SEC23" "0,1" bitfld.long 0x0 22. "SEC22,SEC22" "0,1" bitfld.long 0x0 21. "SEC21,SEC21" "0,1" bitfld.long 0x0 20. "SEC20,SEC20" "0,1" bitfld.long 0x0 19. "SEC19,SEC19" "0,1" bitfld.long 0x0 18. "SEC18,SEC18" "0,1" bitfld.long 0x0 17. "SEC17,SEC17" "0,1" bitfld.long 0x0 16. "SEC16,SEC16" "0,1" newline bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" bitfld.long 0x0 8. "SEC8,SEC8" "0,1" newline bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" group.long 0x200++0x3 line.long 0x0 "MPCBB4_PRIVCFGR0,MPCBB privileged configuration for super-block 0 register" bitfld.long 0x0 31. "PRIV31,PRIV31" "0,1" bitfld.long 0x0 30. "PRIV30,PRIV30" "0,1" bitfld.long 0x0 29. "PRIV29,PRIV29" "0,1" bitfld.long 0x0 28. "PRIV28,PRIV28" "0,1" bitfld.long 0x0 27. "PRIV27,PRIV27" "0,1" bitfld.long 0x0 26. "PRIV26,PRIV26" "0,1" bitfld.long 0x0 25. "PRIV25,PRIV25" "0,1" bitfld.long 0x0 24. "PRIV24,PRIV24" "0,1" newline bitfld.long 0x0 23. "PRIV23,PRIV23" "0,1" bitfld.long 0x0 22. "PRIV22,PRIV22" "0,1" bitfld.long 0x0 21. "PRIV21,PRIV21" "0,1" bitfld.long 0x0 20. "PRIV20,PRIV20" "0,1" bitfld.long 0x0 19. "PRIV19,PRIV19" "0,1" bitfld.long 0x0 18. "PRIV18,PRIV18" "0,1" bitfld.long 0x0 17. "PRIV17,PRIV17" "0,1" bitfld.long 0x0 16. "PRIV16,PRIV16" "0,1" newline bitfld.long 0x0 15. "PRIV15,PRIV15" "0,1" bitfld.long 0x0 14. "PRIV14,PRIV14" "0,1" bitfld.long 0x0 13. "PRIV13,PRIV13" "0,1" bitfld.long 0x0 12. "PRIV12,PRIV12" "0,1" bitfld.long 0x0 11. "PRIV11,PRIV11" "0,1" bitfld.long 0x0 10. "PRIV10,PRIV10" "0,1" bitfld.long 0x0 9. "PRIV9,PRIV9" "0,1" bitfld.long 0x0 8. "PRIV8,PRIV8" "0,1" newline bitfld.long 0x0 7. "PRIV7,PRIV7" "0,1" bitfld.long 0x0 6. "PRIV6,PRIV6" "0,1" bitfld.long 0x0 5. "PRIV5,PRIV5" "0,1" bitfld.long 0x0 4. "PRIV4,PRIV4" "0,1" bitfld.long 0x0 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x0 2. "PRIV2,PRIV2" "0,1" bitfld.long 0x0 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x0 0. "PRIV0,PRIV0" "0,1" tree.end sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "GTZC2_TZIC" base ad:0x46023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" endif bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" endif bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "SEC_GTZC2_TZIC" base ad:0x56023400 group.long 0x0++0x7 line.long 0x0 "IER1,TZIC interrupt enable register 1" bitfld.long 0x0 12. "ADF1IE,illegal access interrupt enable for ADF1" "0,1" bitfld.long 0x0 11. "DAC1IE,illegal access interrupt enable for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFIE,illegal access interrupt enable for VREFBUF" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x0 8. "ADC2IE,illegal access interrupt enable for ADC2" "0,1" endif bitfld.long 0x0 7. "COMPIE,illegal access interrupt enable for COMP" "0,1" bitfld.long 0x0 6. "OPAMPIE,illegal access interrupt enable for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4IE,illegal access interrupt enable for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3IE,illegal access interrupt enable for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1IE,illegal access interrupt enable for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3IE,illegal access interrupt enable for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1IE,illegal access interrupt enable for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3IE,illegal access interrupt enable for SPI3" "0,1" line.long 0x4 "IER2,TZIC interrupt enable register 2" bitfld.long 0x4 25. "MPCBB4_REGIE,illegal access interrupt enable for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4IE,illegal access interrupt enable for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2IE,illegal access interrupt enable for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2IE,illegal access interrupt enable for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIIE,illegal access interrupt enable for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1IE,illegal access interrupt enable for LPDMA" "0,1" bitfld.long 0x4 4. "RCCIE,illegal access interrupt enable for RCC" "0,1" bitfld.long 0x4 3. "PWRIE,illegal access interrupt enable for PWR" "0,1" bitfld.long 0x4 2. "TAMPIE,illegal access interrupt enable for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCIE,illegal access interrupt enable for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGIE,illegal access interrupt enable for SYSCFG" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SR1,TZIC status register 1" bitfld.long 0x0 12. "ADF1F,illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "DAC1F,illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFF,illegal access flag for VREFBUF" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x0 8. "ADC2F,illegal access flag for ADC2" "0,1" endif bitfld.long 0x0 7. "COMPF,illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "OPAMPF,illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4F,illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3F,illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1F,illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3F,illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1F,illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3F,illegal access flag for SPI3" "0,1" line.long 0x4 "SR2,TZIC status register 2" bitfld.long 0x4 25. "MPCBB4_REGF,illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "SRAM4F,illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "TZIC2F,illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "TZSC2F,illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "EXTIF,illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "LPDMA1F,illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "RCCF,illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "PWRF,illegal access flag for PWRUSART1F" "0,1" bitfld.long 0x4 2. "TAMPF,illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "RTCF,illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "SYSCFGF,illegal access flag for SYSCFG" "0,1" wgroup.long 0x20++0x7 line.long 0x0 "FCR1,TZIC flag clear register 1" bitfld.long 0x0 12. "CADF1F,clear the illegal access flag for ADF1" "0,1" bitfld.long 0x0 11. "CDAC1F,clear the illegal access flag for DAC1" "0,1" bitfld.long 0x0 9. "CVREFBUFF,clear the illegal access flag for VREFBUF" "0,1" bitfld.long 0x0 8. "CADC2F,clear the illegal access flag for ADC2" "0,1" bitfld.long 0x0 7. "CCOMPF,clear the illegal access flag for COMP" "0,1" bitfld.long 0x0 6. "COPAMPF,clear the illegal access flag for OPAMP" "0,1" bitfld.long 0x0 5. "CLPTIM4F,clear the illegal access flag for LPTIM4" "0,1" bitfld.long 0x0 4. "CLPTIM3F,clear the illegal access flag for LPTIM3" "0,1" bitfld.long 0x0 3. "CLPTIM1F,clear the illegal access flag for LPTIM1" "0,1" newline bitfld.long 0x0 2. "CI2C3F,clear the illegal access flag for I2C3" "0,1" bitfld.long 0x0 1. "CLPUART1F,clear the illegal access flag for LPUART1" "0,1" bitfld.long 0x0 0. "CSPI3F,clear the illegal access flag for SPI3" "0,1" line.long 0x4 "FCR2,TZIC flag clear register 2" bitfld.long 0x4 25. "CMPCBB4_REGF,clear the illegal access flag for MPCBB4 registers" "0,1" bitfld.long 0x4 24. "CSRAM4F,clear the illegal access flag for SRAM4" "0,1" bitfld.long 0x4 15. "CTZIC2F,clear the illegal access flag for GTZC2 TZIC registers" "0,1" bitfld.long 0x4 14. "CTZSC2F,clear the illegal access flag for GTZC2 TZSC registers" "0,1" bitfld.long 0x4 6. "CEXTIF,clear the illegal access flag for EXTI" "0,1" bitfld.long 0x4 5. "CLPDMA1F,clear the illegal access flag for LPDMA" "0,1" bitfld.long 0x4 4. "CRCCF,clear the illegal access flag for RCC" "0,1" bitfld.long 0x4 3. "CPWRF,clear the illegal access flag for PWR" "0,1" bitfld.long 0x4 2. "CTAMPF,clear the illegal access flag for TAMP" "0,1" newline bitfld.long 0x4 1. "CRTCF,clear the illegal access flag for RTC" "0,1" bitfld.long 0x4 0. "CSYSCFGF,clear the illegal access flag for SYSCFG" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "GTZC2_TZSC" base ad:0x46023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" endif bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" endif bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "SEC_GTZC2_TZSC" base ad:0x56023000 group.long 0x0++0x3 line.long 0x0 "TZSC_CR,TZSC control register" bitfld.long 0x0 0. "LCK,lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx" "0,1" group.long 0x10++0x3 line.long 0x0 "TZSC_SECCFGR1,TZSC secure configuration register 1" bitfld.long 0x0 12. "ADF1SEC,secure access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1SEC,secure access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFSEC,secure access mode for VREFBUF" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x0 8. "ADC2SEC,secure access mode for ADC2" "0,1" endif bitfld.long 0x0 7. "COMPSEC,secure access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPSEC,secure access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4SEC,secure access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3SEC,secure access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1SEC,secure access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3SEC,secure access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1SEC,secure access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3SEC,secure access mode for SPI3" "0,1" group.long 0x20++0x3 line.long 0x0 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1" bitfld.long 0x0 12. "ADF1PRIV,privileged access mode for ADF1" "0,1" bitfld.long 0x0 11. "DAC1PRIV,privileged access mode for DAC1" "0,1" bitfld.long 0x0 9. "VREFBUFPRIV,privileged access mode for VREFBUF" "0,1" sif (cpuis("STM32U545*")) bitfld.long 0x0 8. "ADC2PRIV,privileged access mode for ADC2" "0,1" endif bitfld.long 0x0 7. "COMPPRIV,privileged access mode for COMP" "0,1" bitfld.long 0x0 6. "OPAMPPRIV,privileged access mode for OPAMP" "0,1" bitfld.long 0x0 5. "LPTIM4PRIV,privileged access mode for LPTIM4" "0,1" bitfld.long 0x0 4. "LPTIM3PRIV,privileged access mode for LPTIM3" "0,1" bitfld.long 0x0 3. "LPTIM1PRIV,privileged access mode for LPTIM1" "0,1" newline bitfld.long 0x0 2. "I2C3PRIV,privileged access mode for I2C3" "0,1" bitfld.long 0x0 1. "LPUART1PRIV,privileged access mode for LPUART1" "0,1" bitfld.long 0x0 0. "SPI3PRIV,privileged access mode for SPI3" "0,1" tree.end endif tree.end tree "HASH (HASH Hardware Accelerator)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "HASH" base ad:0x420C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "CS0,CS0" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "CSR0,CSR0" endif line.long 0x4 "CSR1,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x4 0.--31. 1. "CS1,CS1" endif sif (cpuis("STM32U575*")) hexmask.long 0x4 0.--31. 1. "CSR1,CSR1" endif line.long 0x8 "CSR2,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x8 0.--31. 1. "CS2,CS2" endif sif (cpuis("STM32U575*")) hexmask.long 0x8 0.--31. 1. "CSR2,CSR2" endif line.long 0xC "CSR3,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC 0.--31. 1. "CS3,CS3" endif sif (cpuis("STM32U575*")) hexmask.long 0xC 0.--31. 1. "CSR3,CSR3" endif line.long 0x10 "CSR4,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x10 0.--31. 1. "CS4,CS4" endif sif (cpuis("STM32U575*")) hexmask.long 0x10 0.--31. 1. "CSR4,CSR4" endif line.long 0x14 "CSR5,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x14 0.--31. 1. "CS5,CS5" endif sif (cpuis("STM32U575*")) hexmask.long 0x14 0.--31. 1. "CSR5,CSR5" endif line.long 0x18 "CSR6,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x18 0.--31. 1. "CS6,CS6" endif sif (cpuis("STM32U575*")) hexmask.long 0x18 0.--31. 1. "CSR6,CSR6" endif line.long 0x1C "CSR7,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x1C 0.--31. 1. "CS7,CS7" endif sif (cpuis("STM32U575*")) hexmask.long 0x1C 0.--31. 1. "CSR7,CSR7" endif line.long 0x20 "CSR8,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x20 0.--31. 1. "CS8,CS8" endif sif (cpuis("STM32U575*")) hexmask.long 0x20 0.--31. 1. "CSR8,CSR8" endif line.long 0x24 "CSR9,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x24 0.--31. 1. "CS9,CS9" endif sif (cpuis("STM32U575*")) hexmask.long 0x24 0.--31. 1. "CSR9,CSR9" endif line.long 0x28 "CSR10,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x28 0.--31. 1. "CS10,CS10" endif sif (cpuis("STM32U575*")) hexmask.long 0x28 0.--31. 1. "CSR10,CSR10" endif line.long 0x2C "CSR11,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x2C 0.--31. 1. "CS11,CS11" endif sif (cpuis("STM32U575*")) hexmask.long 0x2C 0.--31. 1. "CSR11,CSR11" endif line.long 0x30 "CSR12,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x30 0.--31. 1. "CS12,CS12" endif sif (cpuis("STM32U575*")) hexmask.long 0x30 0.--31. 1. "CSR12,CSR12" endif line.long 0x34 "CSR13,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x34 0.--31. 1. "CS13,CS13" endif sif (cpuis("STM32U575*")) hexmask.long 0x34 0.--31. 1. "CSR13,CSR13" endif line.long 0x38 "CSR14,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x38 0.--31. 1. "CS14,CS14" endif sif (cpuis("STM32U575*")) hexmask.long 0x38 0.--31. 1. "CSR14,CSR14" endif line.long 0x3C "CSR15,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x3C 0.--31. 1. "CS15,CS15" endif sif (cpuis("STM32U575*")) hexmask.long 0x3C 0.--31. 1. "CSR15,CSR15" endif line.long 0x40 "CSR16,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x40 0.--31. 1. "CS16,CS16" endif sif (cpuis("STM32U575*")) hexmask.long 0x40 0.--31. 1. "CSR16,CSR16" endif line.long 0x44 "CSR17,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x44 0.--31. 1. "CS17,CS17" endif sif (cpuis("STM32U575*")) hexmask.long 0x44 0.--31. 1. "CSR17,CSR17" endif line.long 0x48 "CSR18,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x48 0.--31. 1. "CS18,CS18" endif sif (cpuis("STM32U575*")) hexmask.long 0x48 0.--31. 1. "CSR18,CSR18" endif line.long 0x4C "CSR19,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x4C 0.--31. 1. "CS19,CS19" endif sif (cpuis("STM32U575*")) hexmask.long 0x4C 0.--31. 1. "CSR19,CSR19" endif line.long 0x50 "CSR20,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x50 0.--31. 1. "CS20,CS20" endif sif (cpuis("STM32U575*")) hexmask.long 0x50 0.--31. 1. "CSR20,CSR20" endif line.long 0x54 "CSR21,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x54 0.--31. 1. "CS21,CS21" endif sif (cpuis("STM32U575*")) hexmask.long 0x54 0.--31. 1. "CSR21,CSR21" endif line.long 0x58 "CSR22,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x58 0.--31. 1. "CS22,CS22" endif sif (cpuis("STM32U575*")) hexmask.long 0x58 0.--31. 1. "CSR22,CSR22" endif line.long 0x5C "CSR23,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x5C 0.--31. 1. "CS23,CS23" endif sif (cpuis("STM32U575*")) hexmask.long 0x5C 0.--31. 1. "CSR23,CSR23" endif line.long 0x60 "CSR24,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x60 0.--31. 1. "CS24,CS24" endif sif (cpuis("STM32U575*")) hexmask.long 0x60 0.--31. 1. "CSR24,CSR24" endif line.long 0x64 "CSR25,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x64 0.--31. 1. "CS25,CS25" endif sif (cpuis("STM32U575*")) hexmask.long 0x64 0.--31. 1. "CSR25,CSR25" endif line.long 0x68 "CSR26,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x68 0.--31. 1. "CS26,CS26" endif sif (cpuis("STM32U575*")) hexmask.long 0x68 0.--31. 1. "CSR26,CSR26" endif line.long 0x6C "CSR27,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x6C 0.--31. 1. "CS27,CS27" endif sif (cpuis("STM32U575*")) hexmask.long 0x6C 0.--31. 1. "CSR27,CSR27" endif line.long 0x70 "CSR28,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x70 0.--31. 1. "CS28,CS28" endif sif (cpuis("STM32U575*")) hexmask.long 0x70 0.--31. 1. "CSR28,CSR28" endif line.long 0x74 "CSR29,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x74 0.--31. 1. "CS29,CS29" endif sif (cpuis("STM32U575*")) hexmask.long 0x74 0.--31. 1. "CSR29,CSR29" endif line.long 0x78 "CSR30,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x78 0.--31. 1. "CS30,CS30" endif sif (cpuis("STM32U575*")) hexmask.long 0x78 0.--31. 1. "CSR30,CSR30" endif line.long 0x7C "CSR31,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x7C 0.--31. 1. "CS31,CS31" endif sif (cpuis("STM32U575*")) hexmask.long 0x7C 0.--31. 1. "CSR31,CSR31" endif line.long 0x80 "CSR32,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x80 0.--31. 1. "CS32,CS32" endif sif (cpuis("STM32U575*")) hexmask.long 0x80 0.--31. 1. "CSR32,CSR32" endif line.long 0x84 "CSR33,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x84 0.--31. 1. "CS33,CS33" endif sif (cpuis("STM32U575*")) hexmask.long 0x84 0.--31. 1. "CSR33,CSR33" endif line.long 0x88 "CSR34,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x88 0.--31. 1. "CS34,CS34" endif sif (cpuis("STM32U575*")) hexmask.long 0x88 0.--31. 1. "CSR34,CSR34" endif line.long 0x8C "CSR35,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x8C 0.--31. 1. "CS35,CS35" endif sif (cpuis("STM32U575*")) hexmask.long 0x8C 0.--31. 1. "CSR35,CSR35" endif line.long 0x90 "CSR36,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x90 0.--31. 1. "CS36,CS36" endif sif (cpuis("STM32U575*")) hexmask.long 0x90 0.--31. 1. "CSR36,CSR36" endif line.long 0x94 "CSR37,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x94 0.--31. 1. "CS37,CS37" endif sif (cpuis("STM32U575*")) hexmask.long 0x94 0.--31. 1. "CSR37,CSR37" endif line.long 0x98 "CSR38,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x98 0.--31. 1. "CS38,CS38" endif sif (cpuis("STM32U575*")) hexmask.long 0x98 0.--31. 1. "CSR38,CSR38" endif line.long 0x9C "CSR39,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x9C 0.--31. 1. "CS39,CS39" endif sif (cpuis("STM32U575*")) hexmask.long 0x9C 0.--31. 1. "CSR39,CSR39" endif line.long 0xA0 "CSR40,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xA0 0.--31. 1. "CS40,CS40" endif sif (cpuis("STM32U575*")) hexmask.long 0xA0 0.--31. 1. "CSR40,CSR40" endif line.long 0xA4 "CSR41,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xA4 0.--31. 1. "CS41,CS41" endif sif (cpuis("STM32U575*")) hexmask.long 0xA4 0.--31. 1. "CSR41,CSR41" endif line.long 0xA8 "CSR42,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xA8 0.--31. 1. "CS42,CS42" endif sif (cpuis("STM32U575*")) hexmask.long 0xA8 0.--31. 1. "CSR42,CSR42" endif line.long 0xAC "CSR43,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xAC 0.--31. 1. "CS43,CS43" endif sif (cpuis("STM32U575*")) hexmask.long 0xAC 0.--31. 1. "CSR43,CSR43" endif line.long 0xB0 "CSR44,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xB0 0.--31. 1. "CS44,CS44" endif sif (cpuis("STM32U575*")) hexmask.long 0xB0 0.--31. 1. "CSR44,CSR44" endif line.long 0xB4 "CSR45,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xB4 0.--31. 1. "CS45,CS45" endif sif (cpuis("STM32U575*")) hexmask.long 0xB4 0.--31. 1. "CSR45,CSR45" endif line.long 0xB8 "CSR46,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xB8 0.--31. 1. "CS46,CS46" endif sif (cpuis("STM32U575*")) hexmask.long 0xB8 0.--31. 1. "CSR46,CSR46" endif line.long 0xBC "CSR47,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xBC 0.--31. 1. "CS47,CS47" endif sif (cpuis("STM32U575*")) hexmask.long 0xBC 0.--31. 1. "CSR47,CSR47" endif line.long 0xC0 "CSR48,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC0 0.--31. 1. "CS48,CS48" endif sif (cpuis("STM32U575*")) hexmask.long 0xC0 0.--31. 1. "CSR48,CSR48" endif line.long 0xC4 "CSR49,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC4 0.--31. 1. "CS49,CS49" endif sif (cpuis("STM32U575*")) hexmask.long 0xC4 0.--31. 1. "CSR49,CSR49" endif line.long 0xC8 "CSR50,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC8 0.--31. 1. "CS50,CS50" endif sif (cpuis("STM32U575*")) hexmask.long 0xC8 0.--31. 1. "CSR50,CSR50" endif line.long 0xCC "CSR51,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xCC 0.--31. 1. "CS51,CS51" endif sif (cpuis("STM32U575*")) hexmask.long 0xCC 0.--31. 1. "CSR51,CSR51" endif line.long 0xD0 "CSR52,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xD0 0.--31. 1. "CS52,CS52" endif sif (cpuis("STM32U575*")) hexmask.long 0xD0 0.--31. 1. "CSR52,CSR52" endif line.long 0xD4 "CSR53,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xD4 0.--31. 1. "CS53,CS53" endif sif (cpuis("STM32U575*")) hexmask.long 0xD4 0.--31. 1. "CSR53,CSR53" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_HASH" base ad:0x520C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "CS0,CS0" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "CSR0,CSR0" endif line.long 0x4 "CSR1,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x4 0.--31. 1. "CS1,CS1" endif sif (cpuis("STM32U575*")) hexmask.long 0x4 0.--31. 1. "CSR1,CSR1" endif line.long 0x8 "CSR2,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x8 0.--31. 1. "CS2,CS2" endif sif (cpuis("STM32U575*")) hexmask.long 0x8 0.--31. 1. "CSR2,CSR2" endif line.long 0xC "CSR3,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC 0.--31. 1. "CS3,CS3" endif sif (cpuis("STM32U575*")) hexmask.long 0xC 0.--31. 1. "CSR3,CSR3" endif line.long 0x10 "CSR4,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x10 0.--31. 1. "CS4,CS4" endif sif (cpuis("STM32U575*")) hexmask.long 0x10 0.--31. 1. "CSR4,CSR4" endif line.long 0x14 "CSR5,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x14 0.--31. 1. "CS5,CS5" endif sif (cpuis("STM32U575*")) hexmask.long 0x14 0.--31. 1. "CSR5,CSR5" endif line.long 0x18 "CSR6,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x18 0.--31. 1. "CS6,CS6" endif sif (cpuis("STM32U575*")) hexmask.long 0x18 0.--31. 1. "CSR6,CSR6" endif line.long 0x1C "CSR7,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x1C 0.--31. 1. "CS7,CS7" endif sif (cpuis("STM32U575*")) hexmask.long 0x1C 0.--31. 1. "CSR7,CSR7" endif line.long 0x20 "CSR8,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x20 0.--31. 1. "CS8,CS8" endif sif (cpuis("STM32U575*")) hexmask.long 0x20 0.--31. 1. "CSR8,CSR8" endif line.long 0x24 "CSR9,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x24 0.--31. 1. "CS9,CS9" endif sif (cpuis("STM32U575*")) hexmask.long 0x24 0.--31. 1. "CSR9,CSR9" endif line.long 0x28 "CSR10,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x28 0.--31. 1. "CS10,CS10" endif sif (cpuis("STM32U575*")) hexmask.long 0x28 0.--31. 1. "CSR10,CSR10" endif line.long 0x2C "CSR11,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x2C 0.--31. 1. "CS11,CS11" endif sif (cpuis("STM32U575*")) hexmask.long 0x2C 0.--31. 1. "CSR11,CSR11" endif line.long 0x30 "CSR12,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x30 0.--31. 1. "CS12,CS12" endif sif (cpuis("STM32U575*")) hexmask.long 0x30 0.--31. 1. "CSR12,CSR12" endif line.long 0x34 "CSR13,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x34 0.--31. 1. "CS13,CS13" endif sif (cpuis("STM32U575*")) hexmask.long 0x34 0.--31. 1. "CSR13,CSR13" endif line.long 0x38 "CSR14,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x38 0.--31. 1. "CS14,CS14" endif sif (cpuis("STM32U575*")) hexmask.long 0x38 0.--31. 1. "CSR14,CSR14" endif line.long 0x3C "CSR15,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x3C 0.--31. 1. "CS15,CS15" endif sif (cpuis("STM32U575*")) hexmask.long 0x3C 0.--31. 1. "CSR15,CSR15" endif line.long 0x40 "CSR16,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x40 0.--31. 1. "CS16,CS16" endif sif (cpuis("STM32U575*")) hexmask.long 0x40 0.--31. 1. "CSR16,CSR16" endif line.long 0x44 "CSR17,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x44 0.--31. 1. "CS17,CS17" endif sif (cpuis("STM32U575*")) hexmask.long 0x44 0.--31. 1. "CSR17,CSR17" endif line.long 0x48 "CSR18,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x48 0.--31. 1. "CS18,CS18" endif sif (cpuis("STM32U575*")) hexmask.long 0x48 0.--31. 1. "CSR18,CSR18" endif line.long 0x4C "CSR19,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x4C 0.--31. 1. "CS19,CS19" endif sif (cpuis("STM32U575*")) hexmask.long 0x4C 0.--31. 1. "CSR19,CSR19" endif line.long 0x50 "CSR20,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x50 0.--31. 1. "CS20,CS20" endif sif (cpuis("STM32U575*")) hexmask.long 0x50 0.--31. 1. "CSR20,CSR20" endif line.long 0x54 "CSR21,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x54 0.--31. 1. "CS21,CS21" endif sif (cpuis("STM32U575*")) hexmask.long 0x54 0.--31. 1. "CSR21,CSR21" endif line.long 0x58 "CSR22,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x58 0.--31. 1. "CS22,CS22" endif sif (cpuis("STM32U575*")) hexmask.long 0x58 0.--31. 1. "CSR22,CSR22" endif line.long 0x5C "CSR23,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x5C 0.--31. 1. "CS23,CS23" endif sif (cpuis("STM32U575*")) hexmask.long 0x5C 0.--31. 1. "CSR23,CSR23" endif line.long 0x60 "CSR24,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x60 0.--31. 1. "CS24,CS24" endif sif (cpuis("STM32U575*")) hexmask.long 0x60 0.--31. 1. "CSR24,CSR24" endif line.long 0x64 "CSR25,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x64 0.--31. 1. "CS25,CS25" endif sif (cpuis("STM32U575*")) hexmask.long 0x64 0.--31. 1. "CSR25,CSR25" endif line.long 0x68 "CSR26,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x68 0.--31. 1. "CS26,CS26" endif sif (cpuis("STM32U575*")) hexmask.long 0x68 0.--31. 1. "CSR26,CSR26" endif line.long 0x6C "CSR27,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x6C 0.--31. 1. "CS27,CS27" endif sif (cpuis("STM32U575*")) hexmask.long 0x6C 0.--31. 1. "CSR27,CSR27" endif line.long 0x70 "CSR28,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x70 0.--31. 1. "CS28,CS28" endif sif (cpuis("STM32U575*")) hexmask.long 0x70 0.--31. 1. "CSR28,CSR28" endif line.long 0x74 "CSR29,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x74 0.--31. 1. "CS29,CS29" endif sif (cpuis("STM32U575*")) hexmask.long 0x74 0.--31. 1. "CSR29,CSR29" endif line.long 0x78 "CSR30,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x78 0.--31. 1. "CS30,CS30" endif sif (cpuis("STM32U575*")) hexmask.long 0x78 0.--31. 1. "CSR30,CSR30" endif line.long 0x7C "CSR31,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x7C 0.--31. 1. "CS31,CS31" endif sif (cpuis("STM32U575*")) hexmask.long 0x7C 0.--31. 1. "CSR31,CSR31" endif line.long 0x80 "CSR32,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x80 0.--31. 1. "CS32,CS32" endif sif (cpuis("STM32U575*")) hexmask.long 0x80 0.--31. 1. "CSR32,CSR32" endif line.long 0x84 "CSR33,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x84 0.--31. 1. "CS33,CS33" endif sif (cpuis("STM32U575*")) hexmask.long 0x84 0.--31. 1. "CSR33,CSR33" endif line.long 0x88 "CSR34,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x88 0.--31. 1. "CS34,CS34" endif sif (cpuis("STM32U575*")) hexmask.long 0x88 0.--31. 1. "CSR34,CSR34" endif line.long 0x8C "CSR35,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x8C 0.--31. 1. "CS35,CS35" endif sif (cpuis("STM32U575*")) hexmask.long 0x8C 0.--31. 1. "CSR35,CSR35" endif line.long 0x90 "CSR36,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x90 0.--31. 1. "CS36,CS36" endif sif (cpuis("STM32U575*")) hexmask.long 0x90 0.--31. 1. "CSR36,CSR36" endif line.long 0x94 "CSR37,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x94 0.--31. 1. "CS37,CS37" endif sif (cpuis("STM32U575*")) hexmask.long 0x94 0.--31. 1. "CSR37,CSR37" endif line.long 0x98 "CSR38,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x98 0.--31. 1. "CS38,CS38" endif sif (cpuis("STM32U575*")) hexmask.long 0x98 0.--31. 1. "CSR38,CSR38" endif line.long 0x9C "CSR39,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0x9C 0.--31. 1. "CS39,CS39" endif sif (cpuis("STM32U575*")) hexmask.long 0x9C 0.--31. 1. "CSR39,CSR39" endif line.long 0xA0 "CSR40,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xA0 0.--31. 1. "CS40,CS40" endif sif (cpuis("STM32U575*")) hexmask.long 0xA0 0.--31. 1. "CSR40,CSR40" endif line.long 0xA4 "CSR41,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xA4 0.--31. 1. "CS41,CS41" endif sif (cpuis("STM32U575*")) hexmask.long 0xA4 0.--31. 1. "CSR41,CSR41" endif line.long 0xA8 "CSR42,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xA8 0.--31. 1. "CS42,CS42" endif sif (cpuis("STM32U575*")) hexmask.long 0xA8 0.--31. 1. "CSR42,CSR42" endif line.long 0xAC "CSR43,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xAC 0.--31. 1. "CS43,CS43" endif sif (cpuis("STM32U575*")) hexmask.long 0xAC 0.--31. 1. "CSR43,CSR43" endif line.long 0xB0 "CSR44,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xB0 0.--31. 1. "CS44,CS44" endif sif (cpuis("STM32U575*")) hexmask.long 0xB0 0.--31. 1. "CSR44,CSR44" endif line.long 0xB4 "CSR45,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xB4 0.--31. 1. "CS45,CS45" endif sif (cpuis("STM32U575*")) hexmask.long 0xB4 0.--31. 1. "CSR45,CSR45" endif line.long 0xB8 "CSR46,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xB8 0.--31. 1. "CS46,CS46" endif sif (cpuis("STM32U575*")) hexmask.long 0xB8 0.--31. 1. "CSR46,CSR46" endif line.long 0xBC "CSR47,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xBC 0.--31. 1. "CS47,CS47" endif sif (cpuis("STM32U575*")) hexmask.long 0xBC 0.--31. 1. "CSR47,CSR47" endif line.long 0xC0 "CSR48,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC0 0.--31. 1. "CS48,CS48" endif sif (cpuis("STM32U575*")) hexmask.long 0xC0 0.--31. 1. "CSR48,CSR48" endif line.long 0xC4 "CSR49,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC4 0.--31. 1. "CS49,CS49" endif sif (cpuis("STM32U575*")) hexmask.long 0xC4 0.--31. 1. "CSR49,CSR49" endif line.long 0xC8 "CSR50,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xC8 0.--31. 1. "CS50,CS50" endif sif (cpuis("STM32U575*")) hexmask.long 0xC8 0.--31. 1. "CSR50,CSR50" endif line.long 0xCC "CSR51,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xCC 0.--31. 1. "CS51,CS51" endif sif (cpuis("STM32U575*")) hexmask.long 0xCC 0.--31. 1. "CSR51,CSR51" endif line.long 0xD0 "CSR52,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xD0 0.--31. 1. "CS52,CS52" endif sif (cpuis("STM32U575*")) hexmask.long 0xD0 0.--31. 1. "CSR52,CSR52" endif line.long 0xD4 "CSR53,context swap registers" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long 0xD4 0.--31. 1. "CS53,CS53" endif sif (cpuis("STM32U575*")) hexmask.long 0xD4 0.--31. 1. "CSR53,CSR53" endif tree.end endif sif (cpuis("STM32U585*")) tree "HASH" base ad:0x420C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CSR0,CSR0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CSR1,CSR1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CSR2,CSR2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CSR3,CSR3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CSR4,CSR4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CSR5,CSR5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CSR6,CSR6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CSR7,CSR7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CSR8,CSR8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CSR9,CSR9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CSR10,CSR10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CSR11,CSR11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CSR12,CSR12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CSR13,CSR13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CSR14,CSR14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CSR15,CSR15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CSR16,CSR16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CSR17,CSR17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CSR18,CSR18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CSR19,CSR19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CSR20,CSR20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CSR21,CSR21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CSR22,CSR22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CSR23,CSR23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CSR24,CSR24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CSR25,CSR25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CSR26,CSR26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CSR27,CSR27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CSR28,CSR28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CSR29,CSR29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CSR30,CSR30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CSR31,CSR31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CSR32,CSR32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CSR33,CSR33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CSR34,CSR34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CSR35,CSR35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CSR36,CSR36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CSR37,CSR37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CSR38,CSR38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CSR39,CSR39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CSR40,CSR40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CSR41,CSR41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CSR42,CSR42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CSR43,CSR43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CSR44,CSR44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CSR45,CSR45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CSR46,CSR46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CSR47,CSR47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CSR48,CSR48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CSR49,CSR49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CSR50,CSR50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CSR51,CSR51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CSR52,CSR52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CSR53,CSR53" tree.end tree "SEC_HASH" base ad:0x520C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CSR0,CSR0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CSR1,CSR1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CSR2,CSR2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CSR3,CSR3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CSR4,CSR4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CSR5,CSR5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CSR6,CSR6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CSR7,CSR7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CSR8,CSR8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CSR9,CSR9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CSR10,CSR10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CSR11,CSR11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CSR12,CSR12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CSR13,CSR13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CSR14,CSR14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CSR15,CSR15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CSR16,CSR16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CSR17,CSR17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CSR18,CSR18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CSR19,CSR19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CSR20,CSR20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CSR21,CSR21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CSR22,CSR22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CSR23,CSR23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CSR24,CSR24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CSR25,CSR25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CSR26,CSR26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CSR27,CSR27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CSR28,CSR28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CSR29,CSR29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CSR30,CSR30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CSR31,CSR31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CSR32,CSR32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CSR33,CSR33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CSR34,CSR34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CSR35,CSR35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CSR36,CSR36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CSR37,CSR37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CSR38,CSR38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CSR39,CSR39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CSR40,CSR40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CSR41,CSR41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CSR42,CSR42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CSR43,CSR43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CSR44,CSR44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CSR45,CSR45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CSR46,CSR46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CSR47,CSR47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CSR48,CSR48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CSR49,CSR49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CSR50,CSR50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CSR51,CSR51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CSR52,CSR52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CSR53,CSR53" tree.end endif sif (cpuis("STM32U595*")) tree "HASH" base ad:0x420C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end tree "SEC_HASH" base ad:0x520C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end endif sif (cpuis("STM32U599*")) tree "HASH" base ad:0x420C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end tree "SEC_HASH" base ad:0x520C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end endif sif (cpuis("STM32U5A5*")) tree "HASH" base ad:0x420C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end tree "SEC_HASH" base ad:0x520C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end endif sif (cpuis("STM32U5A9*")) tree "HASH" base ad:0x420C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end tree "SEC_HASH" base ad:0x520C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end endif sif (cpuis("STM32U5F*")) tree "HASH" base ad:0x420C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end tree "SEC_HASH" base ad:0x520C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end endif sif (cpuis("STM32U5G*")) tree "HASH" base ad:0x420C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end tree "SEC_HASH" base ad:0x520C0400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 17.--18. "ALGO,Algorithm selection" "0,1,2,3" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "STR,start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word of the message" rgroup.long 0xC++0x13 line.long 0x0 "HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" rgroup.long 0x310++0x1F line.long 0x0 "HR0,digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest register 4" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HR5,supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HR6,supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HR7,supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,H7" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0,1" line.long 0x4 "SR,status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" tree.end endif tree.end sif (cpuis("STM32U599*")||cpuis("STM32U5A9*")||cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "HSPI (Hexadeca-SPI Interface)" base ad:0x0 tree "HSPI1" base ad:0x420D3400 group.long 0x0++0x3 line.long 0x0 "HSPI_CR,HSPI control register" bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO11:8],3: data exchanged over IO[15:12]" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: Indirect-write mode,1: Indirect-read mode,2: Automatic-polling mode,3: Memory-mapped mode" newline bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.." bitfld.long 0x0 22. "APMS,Automatic-polling mode stop" "0: Automatic-polling mode is stopped only by abort..,1: Automatic-polling mode stops as soon as there is.." newline bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level" newline bitfld.long 0x0 7. "FSEL,Memory select" "0,1" bitfld.long 0x0 6. "DMM,Dual-memory mode" "0: Dual-quad mode disabled,1: Dual-quad mode enabled" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: Timeout counter is disabled and thus the..,1: Timeout counter is enabled and thus the.." bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for Indirect mode,1: DMA enabled for Indirect mode" newline bitfld.long 0x0 1. "ABORT,Abort request" "0: No abort requested,1: Abort requested" bitfld.long 0x0 0. "EN,Enable" "0: HSPI disabled,1: HSPI enabled" group.long 0x8++0xF line.long 0x0 "HSPI_DCR1,HSPI device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" newline hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0: The internal sampling clock (called feedback..,1: The delay block is bypassed so the internal.." newline bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)." bitfld.long 0x0 0. "CKMODE,Mode 0/Mode 3" "0: CLK must stay low while nCS is high (chip-select..,1: CLK must stay high while nCS is high.." line.long 0x4 "HSPI_DCR2,HSPI device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: Wrapped reads are not supported by the memory.,?,2: External memory supports wrap size of 16 bytes.,3: External memory supports wrap size of 32 bytes.,4: External memory supports wrap size of 64 bytes.,5: External memory supports wrap size of 128 bytes.,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "HSPI_DCR3,HSPI device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "HSPI_DCR4,HSPI device configuration register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "HSPI_SR," hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "HSPI_FCR," bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "HSPI_DLR,HSPI data length register" hexmask.long 0x0 0.--31. 1. "DL,[31: 0]: Data length" group.long 0x48++0x3 line.long 0x0 "HSPI_AR," hexmask.long 0x0 0.--31. 1. "ADDRESS,Address" group.long 0x50++0x3 line.long 0x0 "HSPI_DR," hexmask.long 0x0 0.--31. 1. "DATA,[31: 0]: Data" group.long 0x80++0x3 line.long 0x0 "HSPI_PSMKR,HSPI polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "HSPI_PSMAR,HSPI polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,[31: 0]: Status match" group.long 0x90++0x3 line.long 0x0 "HSPI_PIR,HSPI polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,[15: 0]: Polling interval" group.long 0x100++0x3 line.long 0x0 "HSPI_CCR,HSPI communication configuration register" bitfld.long 0x0 31. "SIOO,Send instruction only once mode" "0: Send instruction on every transaction,1: Send instruction only for the first command" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" newline bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: No data,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,5: data on 16 lines,?,?" newline bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" newline bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: No alternate bytes,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,?,?,?,?" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" newline bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: No address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" newline bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" newline bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "HSPI_TCR,HSPI timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: No shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: No delay hold,1: 1/4 cycle hold" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "HSPI_IR,HSPI instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x120++0x3 line.long 0x0 "HSPI_ABR,HSPI alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,[31: 0]: Alternate bytes" group.long 0x130++0x3 line.long 0x0 "HSPI_LPTR,HSPI low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,[15: 0]: Timeout period" group.long 0x140++0x3 line.long 0x0 "HSPI_WPCCR,HSPI wrap communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: No data,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,?,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: No alternate bytes,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,5: Alternate bytes on 16 lines,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: No address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "HSPI_WPTCR,HSPI wrap timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: No shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: No quarter cycle delay,1: Quarter cycle delay inserted" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "HSPI_WPIR,HSPI wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,[31: 0]: Instruction" group.long 0x160++0x3 line.long 0x0 "HSPI_WPABR,HSPI wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,[31: 0]: Alternate bytes" group.long 0x180++0x3 line.long 0x0 "HSPI_WCCR,HSPI write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: No data,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,5: Data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: No alternate bytes,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: No address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "HSPI_WTCR,HSPI write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "HSPI_WIR,HSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "HSPI_WABR,HSPI write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,[31: 0]: Alternate bytes" group.long 0x200++0x3 line.long 0x0 "HSPI_HLCR,HSPI HyperBus latency configuration register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,[7: 0]: Access time" newline bitfld.long 0x0 1. "WZL,Write zero latency" "0: Latency on write accesses,1: No latency on write accesses" bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency" rgroup.long 0x210++0x3 line.long 0x0 "HSPI_CALFCR,HSPI full-cycle calibration configuration" bitfld.long 0x0 31. "CALMAX,Max value" "0,1" hexmask.long.byte 0x0 16.--20. 1. "COARSE,[4: 0]: Coarse calibration" newline hexmask.long.byte 0x0 0.--6. 1. "FINE,[6: 0]: Fine calibration" group.long 0x218++0x3 line.long 0x0 "HSPI_CALMR,HSPI DLL master calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,[4: 0]: Coarse calibration" hexmask.long.byte 0x0 0.--6. 1. "FINE,[6: 0]: Fine calibration" group.long 0x220++0x3 line.long 0x0 "HSPI_CALSOR,HSPI DLL slave output calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,[4: 0]: Coarse calibration" hexmask.long.byte 0x0 0.--6. 1. "FINE,[6: 0]: Fine calibration" group.long 0x228++0x3 line.long 0x0 "HSPI_CALSIR,HSPI DLL slave input calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,[4: 0]: Coarse calibration" hexmask.long.byte 0x0 0.--6. 1. "FINE,[6: 0]: Fine calibration" tree.end tree "SEC_HSPI1" base ad:0x520D3400 group.long 0x0++0x3 line.long 0x0 "HSPI_CR,HSPI control register" bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO11:8],3: data exchanged over IO[15:12]" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: Indirect-write mode,1: Indirect-read mode,2: Automatic-polling mode,3: Memory-mapped mode" newline bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.." bitfld.long 0x0 22. "APMS,Automatic-polling mode stop" "0: Automatic-polling mode is stopped only by abort..,1: Automatic-polling mode stops as soon as there is.." newline bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level" newline bitfld.long 0x0 7. "FSEL,Memory select" "0,1" bitfld.long 0x0 6. "DMM,Dual-memory mode" "0: Dual-quad mode disabled,1: Dual-quad mode enabled" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: Timeout counter is disabled and thus the..,1: Timeout counter is enabled and thus the.." bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for Indirect mode,1: DMA enabled for Indirect mode" newline bitfld.long 0x0 1. "ABORT,Abort request" "0: No abort requested,1: Abort requested" bitfld.long 0x0 0. "EN,Enable" "0: HSPI disabled,1: HSPI enabled" group.long 0x8++0xF line.long 0x0 "HSPI_DCR1,HSPI device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" newline hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0: The internal sampling clock (called feedback..,1: The delay block is bypassed so the internal.." newline bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)." bitfld.long 0x0 0. "CKMODE,Mode 0/Mode 3" "0: CLK must stay low while nCS is high (chip-select..,1: CLK must stay high while nCS is high.." line.long 0x4 "HSPI_DCR2,HSPI device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: Wrapped reads are not supported by the memory.,?,2: External memory supports wrap size of 16 bytes.,3: External memory supports wrap size of 32 bytes.,4: External memory supports wrap size of 64 bytes.,5: External memory supports wrap size of 128 bytes.,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "HSPI_DCR3,HSPI device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "HSPI_DCR4,HSPI device configuration register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "HSPI_SR," hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "HSPI_FCR," bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "HSPI_DLR,HSPI data length register" hexmask.long 0x0 0.--31. 1. "DL,[31: 0]: Data length" group.long 0x48++0x3 line.long 0x0 "HSPI_AR," hexmask.long 0x0 0.--31. 1. "ADDRESS,Address" group.long 0x50++0x3 line.long 0x0 "HSPI_DR," hexmask.long 0x0 0.--31. 1. "DATA,[31: 0]: Data" group.long 0x80++0x3 line.long 0x0 "HSPI_PSMKR,HSPI polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "HSPI_PSMAR,HSPI polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,[31: 0]: Status match" group.long 0x90++0x3 line.long 0x0 "HSPI_PIR,HSPI polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,[15: 0]: Polling interval" group.long 0x100++0x3 line.long 0x0 "HSPI_CCR,HSPI communication configuration register" bitfld.long 0x0 31. "SIOO,Send instruction only once mode" "0: Send instruction on every transaction,1: Send instruction only for the first command" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" newline bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: No data,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,5: data on 16 lines,?,?" newline bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" newline bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: No alternate bytes,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,?,?,?,?" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" newline bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: No address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" newline bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" newline bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "HSPI_TCR,HSPI timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: No shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: No delay hold,1: 1/4 cycle hold" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "HSPI_IR,HSPI instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x120++0x3 line.long 0x0 "HSPI_ABR,HSPI alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,[31: 0]: Alternate bytes" group.long 0x130++0x3 line.long 0x0 "HSPI_LPTR,HSPI low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,[15: 0]: Timeout period" group.long 0x140++0x3 line.long 0x0 "HSPI_WPCCR,HSPI wrap communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: No data,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,?,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: No alternate bytes,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,5: Alternate bytes on 16 lines,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: No address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "HSPI_WPTCR,HSPI wrap timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: No shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: No quarter cycle delay,1: Quarter cycle delay inserted" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "HSPI_WPIR,HSPI wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,[31: 0]: Instruction" group.long 0x160++0x3 line.long 0x0 "HSPI_WPABR,HSPI wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,[31: 0]: Alternate bytes" group.long 0x180++0x3 line.long 0x0 "HSPI_WCCR,HSPI write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: No data,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,5: Data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: No alternate bytes,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: No address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "HSPI_WTCR,HSPI write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "HSPI_WIR,HSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "HSPI_WABR,HSPI write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,[31: 0]: Alternate bytes" group.long 0x200++0x3 line.long 0x0 "HSPI_HLCR,HSPI HyperBus latency configuration register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,[7: 0]: Access time" newline bitfld.long 0x0 1. "WZL,Write zero latency" "0: Latency on write accesses,1: No latency on write accesses" bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency" rgroup.long 0x210++0x3 line.long 0x0 "HSPI_CALFCR,HSPI full-cycle calibration configuration" bitfld.long 0x0 31. "CALMAX,Max value" "0,1" hexmask.long.byte 0x0 16.--20. 1. "COARSE,[4: 0]: Coarse calibration" newline hexmask.long.byte 0x0 0.--6. 1. "FINE,[6: 0]: Fine calibration" group.long 0x218++0x3 line.long 0x0 "HSPI_CALMR,HSPI DLL master calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,[4: 0]: Coarse calibration" hexmask.long.byte 0x0 0.--6. 1. "FINE,[6: 0]: Fine calibration" group.long 0x220++0x3 line.long 0x0 "HSPI_CALSOR,HSPI DLL slave output calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,[4: 0]: Coarse calibration" hexmask.long.byte 0x0 0.--6. 1. "FINE,[6: 0]: Fine calibration" group.long 0x228++0x3 line.long 0x0 "HSPI_CALSIR,HSPI DLL slave input calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,[4: 0]: Coarse calibration" hexmask.long.byte 0x0 0.--6. 1. "FINE,[6: 0]: Fine calibration" tree.end tree.end endif tree "I2C (Inter-Integrated Circuit Interface)" base ad:0x0 tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end sif (cpuis("STM32U595*")) tree "I2C5" base ad:0x40009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "I2C6" base ad:0x40009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "I2C5" base ad:0x40009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "I2C6" base ad:0x40009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "I2C5" base ad:0x40009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "I2C6" base ad:0x40009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "I2C5" base ad:0x40009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "I2C6" base ad:0x40009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "I2C5" base ad:0x40009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "I2C6" base ad:0x40009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "I2C5" base ad:0x40009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "I2C6" base ad:0x40009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "I2C3" base ad:0x46002800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "SEC_I2C1" base ad:0x50005400 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "SEC_I2C2" base ad:0x50005800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end sif (cpuis("STM32U595*")) tree "SEC_I2C5" base ad:0x50009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "SEC_I2C6" base ad:0x50009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "SEC_I2C5" base ad:0x50009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "SEC_I2C6" base ad:0x50009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "SEC_I2C5" base ad:0x50009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "SEC_I2C6" base ad:0x50009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "SEC_I2C5" base ad:0x50009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "SEC_I2C6" base ad:0x50009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "SEC_I2C5" base ad:0x50009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "SEC_I2C6" base ad:0x50009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "SEC_I2C5" base ad:0x50009800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "SEC_I2C6" base ad:0x50009C00 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end endif tree "I2C4" base ad:0x40008400 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "SEC_I2C3" base ad:0x56002800 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree "SEC_I2C4" base ad:0x50008400 group.long 0x0++0x1B line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0,1" bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0,1" bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0,1" bitfld.long 0x0 23. "PECEN,PEC enable" "0,1" bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" newline bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable" "0,1" line.long 0x4 "CR2,Control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1" bitfld.long 0x4 13. "START,Start generation" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master" line.long 0x8 "OAR1,Own address register 1" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address" line.long 0xC "OAR2,Own address register 2" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "TIMINGR,Timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master" line.long 0x14 "TIMEOUTR,Status register 1" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A" line.long 0x18 "ISR,Interrupt and Status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1" bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking" line.long 0x4 "RXDR,Receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x7 line.long 0x0 "TXDR,Transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" line.long 0x4 "I2C_AUTOCR,I2C Autonomous mode control register" bitfld.long 0x4 21. "TRIGEN,Trigger enable" "0,1" bitfld.long 0x4 20. "TRIGPOL,Trigger polarity" "0,1" hexmask.long.byte 0x4 16.--19. 1. "TRIGSEL,Trigger selection" bitfld.long 0x4 7. "TCRDMAEN,DMA request enable on Transfer Complete Reload event" "0,1" bitfld.long 0x4 6. "TCDMAEN,DMA request enable on Transfer Complete event" "0,1" tree.end tree.end tree "ICACHE (Instruction Cache)" base ad:0x0 tree "ICACHE" base ad:0x40030400 group.long 0x0++0x3 line.long 0x0 "ICACHE_CR,ICACHE control register" bitfld.long 0x0 19. "MISSMRST,MISSMRST" "0,1" bitfld.long 0x0 18. "HITMRST,HITMRST" "0,1" bitfld.long 0x0 17. "MISSMEN,MISSMEN" "0,1" bitfld.long 0x0 16. "HITMEN,HITMEN" "0,1" bitfld.long 0x0 2. "WAYSEL,WAYSEL" "0,1" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ICACHE_SR,ICACHE status register" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "ICACHE_IER,ICACHE interrupt enable" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "ICACHE_FCR,ICACHE flag clear register" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "ICACHE_HMONR,ICACHE hit monitor register" hexmask.long 0x0 0.--31. 1. "HITMON,HITMON" line.long 0x4 "ICACHE_MMONR,ICACHE miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MISSMON,MISSMON" group.long 0x20++0xF line.long 0x0 "ICACHE_CRR0,ICACHE region configuration" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 28. "MSTSEL,MSTSEL" "0,1" hexmask.long.word 0x0 16.--26. 1. "REMAPADDR,REMAPADDR" bitfld.long 0x0 15. "REN,REN" "0,1" bitfld.long 0x0 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "BASEADDR,BASEADDR" line.long 0x4 "ICACHE_CRR1,ICACHE region configuration" bitfld.long 0x4 31. "HBURST,HBURST" "0,1" bitfld.long 0x4 28. "MSTSEL,MSTSEL" "0,1" hexmask.long.word 0x4 16.--26. 1. "REMAPADDR,REMAPADDR" bitfld.long 0x4 15. "REN,REN" "0,1" bitfld.long 0x4 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "BASEADDR,BASEADDR" line.long 0x8 "ICACHE_CRR2,ICACHE region configuration" bitfld.long 0x8 31. "HBURST,HBURST" "0,1" bitfld.long 0x8 28. "MSTSEL,MSTSEL" "0,1" hexmask.long.word 0x8 16.--26. 1. "REMAPADDR,REMAPADDR" bitfld.long 0x8 15. "REN,REN" "0,1" bitfld.long 0x8 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--7. 1. "BASEADDR,BASEADDR" line.long 0xC "ICACHE_CRR3,ICACHE region configuration" bitfld.long 0xC 31. "HBURST,HBURST" "0,1" bitfld.long 0xC 28. "MSTSEL,MSTSEL" "0,1" hexmask.long.word 0xC 16.--26. 1. "REMAPADDR,REMAPADDR" bitfld.long 0xC 15. "REN,REN" "0,1" bitfld.long 0xC 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--7. 1. "BASEADDR,BASEADDR" tree.end tree "SEC_ICACHE" base ad:0x50030400 group.long 0x0++0x3 line.long 0x0 "ICACHE_CR,ICACHE control register" bitfld.long 0x0 19. "MISSMRST,MISSMRST" "0,1" bitfld.long 0x0 18. "HITMRST,HITMRST" "0,1" bitfld.long 0x0 17. "MISSMEN,MISSMEN" "0,1" bitfld.long 0x0 16. "HITMEN,HITMEN" "0,1" bitfld.long 0x0 2. "WAYSEL,WAYSEL" "0,1" bitfld.long 0x0 1. "CACHEINV,CACHEINV" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ICACHE_SR,ICACHE status register" bitfld.long 0x0 2. "ERRF,ERRF" "0,1" bitfld.long 0x0 1. "BSYENDF,BSYENDF" "0,1" bitfld.long 0x0 0. "BUSYF,BUSYF" "0,1" group.long 0x8++0x3 line.long 0x0 "ICACHE_IER,ICACHE interrupt enable" bitfld.long 0x0 2. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 1. "BSYENDIE,BSYENDIE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "ICACHE_FCR,ICACHE flag clear register" bitfld.long 0x0 2. "CERRF,CERRF" "0,1" bitfld.long 0x0 1. "CBSYENDF,CBSYENDF" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "ICACHE_HMONR,ICACHE hit monitor register" hexmask.long 0x0 0.--31. 1. "HITMON,HITMON" line.long 0x4 "ICACHE_MMONR,ICACHE miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MISSMON,MISSMON" group.long 0x20++0xF line.long 0x0 "ICACHE_CRR0,ICACHE region configuration" bitfld.long 0x0 31. "HBURST,HBURST" "0,1" bitfld.long 0x0 28. "MSTSEL,MSTSEL" "0,1" hexmask.long.word 0x0 16.--26. 1. "REMAPADDR,REMAPADDR" bitfld.long 0x0 15. "REN,REN" "0,1" bitfld.long 0x0 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "BASEADDR,BASEADDR" line.long 0x4 "ICACHE_CRR1,ICACHE region configuration" bitfld.long 0x4 31. "HBURST,HBURST" "0,1" bitfld.long 0x4 28. "MSTSEL,MSTSEL" "0,1" hexmask.long.word 0x4 16.--26. 1. "REMAPADDR,REMAPADDR" bitfld.long 0x4 15. "REN,REN" "0,1" bitfld.long 0x4 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "BASEADDR,BASEADDR" line.long 0x8 "ICACHE_CRR2,ICACHE region configuration" bitfld.long 0x8 31. "HBURST,HBURST" "0,1" bitfld.long 0x8 28. "MSTSEL,MSTSEL" "0,1" hexmask.long.word 0x8 16.--26. 1. "REMAPADDR,REMAPADDR" bitfld.long 0x8 15. "REN,REN" "0,1" bitfld.long 0x8 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--7. 1. "BASEADDR,BASEADDR" line.long 0xC "ICACHE_CRR3,ICACHE region configuration" bitfld.long 0xC 31. "HBURST,HBURST" "0,1" bitfld.long 0xC 28. "MSTSEL,MSTSEL" "0,1" hexmask.long.word 0xC 16.--26. 1. "REMAPADDR,REMAPADDR" bitfld.long 0xC 15. "REN,REN" "0,1" bitfld.long 0xC 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--7. 1. "BASEADDR,BASEADDR" tree.end tree.end tree "IWDG (Independent Watchdog)" base ad:0x0 tree "IWDG" base ad:0x40003000 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" hexmask.long.byte 0x0 0.--3. 1. "PR,Prescaler divider" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 14. "EWIF,Watchdog Early interrupt flag" "0,1" bitfld.long 0x0 3. "EWU,Watchdog interrupt comparator value update" "0,1" bitfld.long 0x0 2. "WVU,Watchdog counter window value" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value" "0,1" group.long 0x10++0x7 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window" line.long 0x4 "EWCR,IWDG early wakeup interrupt register" bitfld.long 0x4 15. "EWIE,Watchdog early interrupt enable" "0,1" bitfld.long 0x4 14. "EWIC,Watchdog early interrupt acknowledge" "0,1" hexmask.long.word 0x4 0.--11. 1. "EWIT,Watchdog counter window value" tree.end tree "SEC_IWDG" base ad:0x50003000 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" hexmask.long.byte 0x0 0.--3. 1. "PR,Prescaler divider" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 14. "EWIF,Watchdog Early interrupt flag" "0,1" bitfld.long 0x0 3. "EWU,Watchdog interrupt comparator value update" "0,1" bitfld.long 0x0 2. "WVU,Watchdog counter window value" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value" "0,1" group.long 0x10++0x7 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window" line.long 0x4 "EWCR,IWDG early wakeup interrupt register" bitfld.long 0x4 15. "EWIE,Watchdog early interrupt enable" "0,1" bitfld.long 0x4 14. "EWIC,Watchdog early interrupt acknowledge" "0,1" hexmask.long.word 0x4 0.--11. 1. "EWIT,Watchdog counter window value" tree.end tree.end sif (cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "JPEG (JPEG Codec)" base ad:0x0 tree "JPEG" base ad:0x4002A000 wgroup.long 0x0++0x3 line.long 0x0 "JPEG_CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start" "0: Stop/abort,1: Start" group.long 0x4++0x1B line.long 0x0 "JPEG_CONFR1,JPEG codec configuration register 1" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size" bitfld.long 0x0 8. "HDR,Header processing" "0: Disable,1: Enable" newline bitfld.long 0x0 6.--7. "NS,Number of components for scan" "0,1,2,3" bitfld.long 0x0 4.--5. "COLSPACE,Color space" "0: Grayscale (1 quantization table),1: YUV (2 quantization tables),2: RGB (3 quantization tables),3: CMYK (4 quantization tables)" newline bitfld.long 0x0 3. "DE,Codec operation as coder or decoder" "0: Code,1: Decode" bitfld.long 0x0 0.--1. "NF,Number of color components" "0: Grayscale (1 color component),1: - (2 color components),2: YUV or RGB (3 color components),3: CMYK (4 color components)" line.long 0x4 "JPEG_CONFR2,JPEG codec configuration register 2" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCUs" line.long 0x8 "JPEG_CONFR3,JPEG codec configuration register 3" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size" line.long 0xC "JPEG_CONFR4,JPEG codec configuration register 4" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of blocks" bitfld.long 0xC 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0xC 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0xC 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x10 "JPEG_CONFR5,JPEG codec configuration register 5" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of blocks" bitfld.long 0x10 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x10 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x10 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x14 "JPEG_CONFR6,JPEG codec configuration register 6" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of blocks" bitfld.long 0x14 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x14 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x14 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x18 "JPEG_CONFR7,JPEG codec configuration register 7" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of blocks" bitfld.long 0x18 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x18 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x18 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" group.long 0x30++0x3 line.long 0x0 "JPEG_CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO flush" "0: No effect,1: Output FIFO is flushed" bitfld.long 0x0 13. "IFF,Input FIFO flush" "0: No effect,1: Input FIFO is flushed" newline bitfld.long 0x0 12. "ODMAEN,Output DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "IDMAEN,Input DMA enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "HPDIE,Header parsing done interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 5. "EOCIE,End of conversion interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO not empty interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 3. "OFTIE,Output FIFO threshold interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO not full interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 1. "IFTIE,Input FIFO threshold interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "JCEN,JPEG core enable" "0: Disabled (internal registers are reset).,1: Enabled (internal registers are accessible)." rgroup.long 0x34++0x3 line.long 0x0 "JPEG_SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec operation flag" "0: Not in progress,1: In progress" bitfld.long 0x0 6. "HPDF,Header parsing done flag" "0: Not completed,1: Completed" newline bitfld.long 0x0 5. "EOCF,End of conversion flag" "0: Not completed,1: Completed" bitfld.long 0x0 4. "OFNEF,Output FIFO not empty flag" "0: Empty (data not available),1: Not empty (data available)" newline bitfld.long 0x0 3. "OFTF,Output FIFO threshold flag" "0: Below threshold,1: At or above threshold" bitfld.long 0x0 2. "IFNFF,Input FIFO not full flag" "0: Full,1: Not full" newline bitfld.long 0x0 1. "IFTF,Input FIFO threshold flag" "0: At or above threshold,1: Below threshold." group.long 0x38++0x3 line.long 0x0 "JPEG_CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear header parsing done flag" "0: No effect,1: Clear" bitfld.long 0x0 5. "CEOCF,Clear end of conversion flag" "0: No effect,1: Clear" wgroup.long 0x40++0x3 line.long 0x0 "JPEG_DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input FIFO" rgroup.long 0x44++0x3 line.long 0x0 "JPEG_DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data output FIFO" group.long 0x50++0x4AB line.long 0x0 "JPEG_QMEM0_0,JPEG quantization memory 0" hexmask.long.byte 0x0 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x0 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x0 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x0 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x4 "JPEG_QMEM0_1,JPEG quantization memory 0" hexmask.long.byte 0x4 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x4 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x4 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x4 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x8 "JPEG_QMEM0_2,JPEG quantization memory 0" hexmask.long.byte 0x8 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x8 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x8 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x8 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0xC "JPEG_QMEM0_3,JPEG quantization memory 0" hexmask.long.byte 0xC 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0xC 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0xC 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0xC 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x10 "JPEG_QMEM0_4,JPEG quantization memory 0" hexmask.long.byte 0x10 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x10 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x10 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x10 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x14 "JPEG_QMEM0_5,JPEG quantization memory 0" hexmask.long.byte 0x14 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x14 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x14 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x14 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x18 "JPEG_QMEM0_6,JPEG quantization memory 0" hexmask.long.byte 0x18 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x18 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x18 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x18 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x1C "JPEG_QMEM0_7,JPEG quantization memory 0" hexmask.long.byte 0x1C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x1C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x1C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x1C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0x20 "JPEG_QMEM0_8,JPEG quantization memory 0" hexmask.long.byte 0x20 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0x20 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0x20 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0x20 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0x24 "JPEG_QMEM0_9,JPEG quantization memory 0" hexmask.long.byte 0x24 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0x24 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0x24 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0x24 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0x28 "JPEG_QMEM0_10,JPEG quantization memory 0" hexmask.long.byte 0x28 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0x28 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0x28 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0x28 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0x2C "JPEG_QMEM0_11,JPEG quantization memory 0" hexmask.long.byte 0x2C 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0x2C 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0x2C 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0x2C 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0x30 "JPEG_QMEM0_12,JPEG quantization memory 0" hexmask.long.byte 0x30 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0x30 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0x30 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0x30 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0x34 "JPEG_QMEM0_13,JPEG quantization memory 0" hexmask.long.byte 0x34 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0x34 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0x34 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0x34 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0x38 "JPEG_QMEM0_14,JPEG quantization memory 0" hexmask.long.byte 0x38 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0x38 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0x38 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0x38 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0x3C "JPEG_QMEM0_15,JPEG quantization memory 0" hexmask.long.byte 0x3C 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0x3C 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0x3C 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0x3C 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x40 "JPEG_QMEM1_0,JPEG quantization memory 1" hexmask.long.byte 0x40 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x40 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x40 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x40 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x44 "JPEG_QMEM1_1,JPEG quantization memory 1" hexmask.long.byte 0x44 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x44 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x44 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x44 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x48 "JPEG_QMEM1_2,JPEG quantization memory 1" hexmask.long.byte 0x48 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x48 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x48 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x48 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0x4C "JPEG_QMEM1_3,JPEG quantization memory 1" hexmask.long.byte 0x4C 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0x4C 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0x4C 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0x4C 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x50 "JPEG_QMEM1_4,JPEG quantization memory 1" hexmask.long.byte 0x50 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x50 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x50 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x50 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x54 "JPEG_QMEM1_5,JPEG quantization memory 1" hexmask.long.byte 0x54 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x54 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x54 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x54 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x58 "JPEG_QMEM1_6,JPEG quantization memory 1" hexmask.long.byte 0x58 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x58 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x58 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x58 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x5C "JPEG_QMEM1_7,JPEG quantization memory 1" hexmask.long.byte 0x5C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x5C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x5C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x5C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0x60 "JPEG_QMEM1_8,JPEG quantization memory 1" hexmask.long.byte 0x60 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0x60 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0x60 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0x60 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0x64 "JPEG_QMEM1_9,JPEG quantization memory 1" hexmask.long.byte 0x64 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0x64 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0x64 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0x64 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0x68 "JPEG_QMEM1_10,JPEG quantization memory 1" hexmask.long.byte 0x68 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0x68 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0x68 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0x68 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0x6C "JPEG_QMEM1_11,JPEG quantization memory 1" hexmask.long.byte 0x6C 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0x6C 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0x6C 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0x6C 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0x70 "JPEG_QMEM1_12,JPEG quantization memory 1" hexmask.long.byte 0x70 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0x70 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0x70 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0x70 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0x74 "JPEG_QMEM1_13,JPEG quantization memory 1" hexmask.long.byte 0x74 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0x74 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0x74 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0x74 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0x78 "JPEG_QMEM1_14,JPEG quantization memory 1" hexmask.long.byte 0x78 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0x78 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0x78 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0x78 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0x7C "JPEG_QMEM1_15,JPEG quantization memory 1" hexmask.long.byte 0x7C 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0x7C 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0x7C 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0x7C 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x80 "JPEG_QMEM2_0,JPEG quantization memory 2" hexmask.long.byte 0x80 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x80 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x80 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x80 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x84 "JPEG_QMEM2_1,JPEG quantization memory 2" hexmask.long.byte 0x84 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x84 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x84 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x84 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x88 "JPEG_QMEM2_2,JPEG quantization memory 2" hexmask.long.byte 0x88 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x88 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x88 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x88 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0x8C "JPEG_QMEM2_3,JPEG quantization memory 2" hexmask.long.byte 0x8C 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0x8C 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0x8C 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0x8C 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x90 "JPEG_QMEM2_4,JPEG quantization memory 2" hexmask.long.byte 0x90 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x90 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x90 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x90 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x94 "JPEG_QMEM2_5,JPEG quantization memory 2" hexmask.long.byte 0x94 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x94 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x94 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x94 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x98 "JPEG_QMEM2_6,JPEG quantization memory 2" hexmask.long.byte 0x98 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x98 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x98 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x98 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x9C "JPEG_QMEM2_7,JPEG quantization memory 2" hexmask.long.byte 0x9C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x9C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x9C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x9C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0xA0 "JPEG_QMEM2_8,JPEG quantization memory 2" hexmask.long.byte 0xA0 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0xA0 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0xA0 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0xA0 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0xA4 "JPEG_QMEM2_9,JPEG quantization memory 2" hexmask.long.byte 0xA4 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0xA4 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0xA4 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0xA4 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0xA8 "JPEG_QMEM2_10,JPEG quantization memory 2" hexmask.long.byte 0xA8 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0xA8 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0xA8 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0xA8 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0xAC "JPEG_QMEM2_11,JPEG quantization memory 2" hexmask.long.byte 0xAC 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0xAC 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0xAC 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0xAC 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0xB0 "JPEG_QMEM2_12,JPEG quantization memory 2" hexmask.long.byte 0xB0 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0xB0 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0xB0 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0xB0 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0xB4 "JPEG_QMEM2_13,JPEG quantization memory 2" hexmask.long.byte 0xB4 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0xB4 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0xB4 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0xB4 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0xB8 "JPEG_QMEM2_14,JPEG quantization memory 2" hexmask.long.byte 0xB8 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0xB8 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0xB8 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0xB8 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0xBC "JPEG_QMEM2_15,JPEG quantization memory 2" hexmask.long.byte 0xBC 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0xBC 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0xBC 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0xBC 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0xC0 "JPEG_QMEM3_0,JPEG quantization memory 3" hexmask.long.byte 0xC0 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0xC0 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0xC0 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0xC0 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0xC4 "JPEG_QMEM3_1,JPEG quantization memory 3" hexmask.long.byte 0xC4 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0xC4 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0xC4 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0xC4 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0xC8 "JPEG_QMEM3_2,JPEG quantization memory 3" hexmask.long.byte 0xC8 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0xC8 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0xC8 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0xC8 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0xCC "JPEG_QMEM3_3,JPEG quantization memory 3" hexmask.long.byte 0xCC 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0xCC 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0xCC 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0xCC 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0xD0 "JPEG_QMEM3_4,JPEG quantization memory 3" hexmask.long.byte 0xD0 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0xD0 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0xD0 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0xD0 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0xD4 "JPEG_QMEM3_5,JPEG quantization memory 3" hexmask.long.byte 0xD4 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0xD4 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0xD4 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0xD4 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0xD8 "JPEG_QMEM3_6,JPEG quantization memory 3" hexmask.long.byte 0xD8 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0xD8 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0xD8 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0xD8 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0xDC "JPEG_QMEM3_7,JPEG quantization memory 3" hexmask.long.byte 0xDC 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0xDC 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0xDC 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0xDC 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0xE0 "JPEG_QMEM3_8,JPEG quantization memory 3" hexmask.long.byte 0xE0 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0xE0 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0xE0 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0xE0 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0xE4 "JPEG_QMEM3_9,JPEG quantization memory 3" hexmask.long.byte 0xE4 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0xE4 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0xE4 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0xE4 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0xE8 "JPEG_QMEM3_10,JPEG quantization memory 3" hexmask.long.byte 0xE8 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0xE8 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0xE8 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0xE8 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0xEC "JPEG_QMEM3_11,JPEG quantization memory 3" hexmask.long.byte 0xEC 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0xEC 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0xEC 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0xEC 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0xF0 "JPEG_QMEM3_12,JPEG quantization memory 3" hexmask.long.byte 0xF0 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0xF0 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0xF0 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0xF0 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0xF4 "JPEG_QMEM3_13,JPEG quantization memory 3" hexmask.long.byte 0xF4 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0xF4 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0xF4 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0xF4 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0xF8 "JPEG_QMEM3_14,JPEG quantization memory 3" hexmask.long.byte 0xF8 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0xF8 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0xF8 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0xF8 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0xFC "JPEG_QMEM3_15,JPEG quantization memory 3" hexmask.long.byte 0xFC 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0xFC 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0xFC 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0xFC 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x100 "JPEG_HUFFMIN0_0,JPEG Huffman min" hexmask.long 0x100 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x104 "JPEG_HUFFMIN0_1,JPEG Huffman min" hexmask.long 0x104 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x108 "JPEG_HUFFMIN0_2,JPEG Huffman min" hexmask.long 0x108 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x10C "JPEG_HUFFMIN0_3,JPEG Huffman min 0 [alternate]" hexmask.long.byte 0x10C 0.--3. 1. "DATA0,Minimum Huffman value" line.long 0x110 "JPEG_HUFFMIN1_0,JPEG Huffman min" hexmask.long 0x110 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x114 "JPEG_HUFFMIN1_1,JPEG Huffman min" hexmask.long 0x114 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x118 "JPEG_HUFFMIN1_2,JPEG Huffman min" hexmask.long 0x118 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x11C "JPEG_HUFFMIN1_3,JPEG Huffman min 1 [alternate]" hexmask.long.byte 0x11C 0.--3. 1. "DATA1,Minimum Huffman value" line.long 0x120 "JPEG_HUFFMIN2_0,JPEG Huffman min" hexmask.long 0x120 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x124 "JPEG_HUFFMIN2_1,JPEG Huffman min" hexmask.long 0x124 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x128 "JPEG_HUFFMIN2_2,JPEG Huffman min" hexmask.long 0x128 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x12C "JPEG_HUFFMIN2_3,JPEG Huffman min 2 [alternate]" hexmask.long.byte 0x12C 0.--3. 1. "DATA2,Minimum Huffman value" line.long 0x130 "JPEG_HUFFMIN3_0,JPEG Huffman min" hexmask.long 0x130 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x134 "JPEG_HUFFMIN3_1,JPEG Huffman min" hexmask.long 0x134 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x138 "JPEG_HUFFMIN3_2,JPEG Huffman min" hexmask.long 0x138 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x13C "JPEG_HUFFMIN3_3,JPEG Huffman min 3 [alternate]" hexmask.long.byte 0x13C 0.--3. 1. "DATA3,Minimum Huffman value" line.long 0x140 "JPEG_HUFFBASE0,JPEG Huffman base" hexmask.long.word 0x140 16.--24. 1. "DATA1,Data 1" hexmask.long.word 0x140 0.--8. 1. "DATA0,Data 0" line.long 0x144 "JPEG_HUFFBASE1,JPEG Huffman base" hexmask.long.word 0x144 16.--24. 1. "DATA3,Data 3" hexmask.long.word 0x144 0.--8. 1. "DATA2,Data 2" line.long 0x148 "JPEG_HUFFBASE2,JPEG Huffman base" hexmask.long.word 0x148 16.--24. 1. "DATA5,Data 5" hexmask.long.word 0x148 0.--8. 1. "DATA4,Data 4" line.long 0x14C "JPEG_HUFFBASE3,JPEG Huffman base" hexmask.long.word 0x14C 16.--24. 1. "DATA7,Data 7" hexmask.long.word 0x14C 0.--8. 1. "DATA6,Data 6" line.long 0x150 "JPEG_HUFFBASE4,JPEG Huffman base" hexmask.long.word 0x150 16.--24. 1. "DATA9,Data 9" hexmask.long.word 0x150 0.--8. 1. "DATA8,Data 8" line.long 0x154 "JPEG_HUFFBASE5,JPEG Huffman base" hexmask.long.word 0x154 16.--24. 1. "DATA11,Data 11" hexmask.long.word 0x154 0.--8. 1. "DATA10,Data 10" line.long 0x158 "JPEG_HUFFBASE6,JPEG Huffman base" hexmask.long.word 0x158 16.--24. 1. "DATA13,Data 13" hexmask.long.word 0x158 0.--8. 1. "DATA12,Data 12" line.long 0x15C "JPEG_HUFFBASE7,JPEG Huffman base" hexmask.long.word 0x15C 16.--24. 1. "DATA15,Data 15" hexmask.long.word 0x15C 0.--8. 1. "DATA14,Data 14" line.long 0x160 "JPEG_HUFFBASE8,JPEG Huffman base" hexmask.long.word 0x160 16.--24. 1. "DATA17,Data 17" hexmask.long.word 0x160 0.--8. 1. "DATA16,Data 16" line.long 0x164 "JPEG_HUFFBASE9,JPEG Huffman base" hexmask.long.word 0x164 16.--24. 1. "DATA19,Data 19" hexmask.long.word 0x164 0.--8. 1. "DATA18,Data 18" line.long 0x168 "JPEG_HUFFBASE10,JPEG Huffman base" hexmask.long.word 0x168 16.--24. 1. "DATA21,Data 21" hexmask.long.word 0x168 0.--8. 1. "DATA20,Data 20" line.long 0x16C "JPEG_HUFFBASE11,JPEG Huffman base" hexmask.long.word 0x16C 16.--24. 1. "DATA23,Data 23" hexmask.long.word 0x16C 0.--8. 1. "DATA22,Data 22" line.long 0x170 "JPEG_HUFFBASE12,JPEG Huffman base" hexmask.long.word 0x170 16.--24. 1. "DATA25,Data 25" hexmask.long.word 0x170 0.--8. 1. "DATA24,Data 24" line.long 0x174 "JPEG_HUFFBASE13,JPEG Huffman base" hexmask.long.word 0x174 16.--24. 1. "DATA27,Data 27" hexmask.long.word 0x174 0.--8. 1. "DATA26,Data 26" line.long 0x178 "JPEG_HUFFBASE14,JPEG Huffman base" hexmask.long.word 0x178 16.--24. 1. "DATA29,Data 29" hexmask.long.word 0x178 0.--8. 1. "DATA28,Data 28" line.long 0x17C "JPEG_HUFFBASE15,JPEG Huffman base" hexmask.long.word 0x17C 16.--24. 1. "DATA31,Data 31" hexmask.long.word 0x17C 0.--8. 1. "DATA30,Data 30" line.long 0x180 "JPEG_HUFFBASE16,JPEG Huffman base" hexmask.long.word 0x180 16.--24. 1. "DATA33,Data 33" hexmask.long.word 0x180 0.--8. 1. "DATA32,Data 32" line.long 0x184 "JPEG_HUFFBASE17,JPEG Huffman base" hexmask.long.word 0x184 16.--24. 1. "DATA35,Data 35" hexmask.long.word 0x184 0.--8. 1. "DATA34,Data 34" line.long 0x188 "JPEG_HUFFBASE18,JPEG Huffman base" hexmask.long.word 0x188 16.--24. 1. "DATA37,Data 37" hexmask.long.word 0x188 0.--8. 1. "DATA36,Data 36" line.long 0x18C "JPEG_HUFFBASE19,JPEG Huffman base" hexmask.long.word 0x18C 16.--24. 1. "DATA39,Data 39" hexmask.long.word 0x18C 0.--8. 1. "DATA38,Data 38" line.long 0x190 "JPEG_HUFFBASE20,JPEG Huffman base" hexmask.long.word 0x190 16.--24. 1. "DATA41,Data 41" hexmask.long.word 0x190 0.--8. 1. "DATA40,Data 40" line.long 0x194 "JPEG_HUFFBASE21,JPEG Huffman base" hexmask.long.word 0x194 16.--24. 1. "DATA43,Data 43" hexmask.long.word 0x194 0.--8. 1. "DATA42,Data 42" line.long 0x198 "JPEG_HUFFBASE22,JPEG Huffman base" hexmask.long.word 0x198 16.--24. 1. "DATA45,Data 45" hexmask.long.word 0x198 0.--8. 1. "DATA44,Data 44" line.long 0x19C "JPEG_HUFFBASE23,JPEG Huffman base" hexmask.long.word 0x19C 16.--24. 1. "DATA47,Data 47" hexmask.long.word 0x19C 0.--8. 1. "DATA46,Data 46" line.long 0x1A0 "JPEG_HUFFBASE24,JPEG Huffman base" hexmask.long.word 0x1A0 16.--24. 1. "DATA49,Data 49" hexmask.long.word 0x1A0 0.--8. 1. "DATA48,Data 48" line.long 0x1A4 "JPEG_HUFFBASE25,JPEG Huffman base" hexmask.long.word 0x1A4 16.--24. 1. "DATA51,Data 51" hexmask.long.word 0x1A4 0.--8. 1. "DATA50,Data 50" line.long 0x1A8 "JPEG_HUFFBASE26,JPEG Huffman base" hexmask.long.word 0x1A8 16.--24. 1. "DATA53,Data 53" hexmask.long.word 0x1A8 0.--8. 1. "DATA52,Data 52" line.long 0x1AC "JPEG_HUFFBASE27,JPEG Huffman base" hexmask.long.word 0x1AC 16.--24. 1. "DATA55,Data 55" hexmask.long.word 0x1AC 0.--8. 1. "DATA54,Data 54" line.long 0x1B0 "JPEG_HUFFBASE28,JPEG Huffman base" hexmask.long.word 0x1B0 16.--24. 1. "DATA57,Data 57" hexmask.long.word 0x1B0 0.--8. 1. "DATA56,Data 56" line.long 0x1B4 "JPEG_HUFFBASE29,JPEG Huffman base" hexmask.long.word 0x1B4 16.--24. 1. "DATA59,Data 59" hexmask.long.word 0x1B4 0.--8. 1. "DATA58,Data 58" line.long 0x1B8 "JPEG_HUFFBASE30,JPEG Huffman base" hexmask.long.word 0x1B8 16.--24. 1. "DATA61,Data 61" hexmask.long.word 0x1B8 0.--8. 1. "DATA60,Data 60" line.long 0x1BC "JPEG_HUFFBASE31,JPEG Huffman base" hexmask.long.word 0x1BC 16.--24. 1. "DATA63,Data 63" hexmask.long.word 0x1BC 0.--8. 1. "DATA62,Data 62" line.long 0x1C0 "JPEG_HUFFSYMB0,JPEG Huffman symbol" hexmask.long.byte 0x1C0 24.--31. 1. "DATA3,Data 3" hexmask.long.byte 0x1C0 16.--23. 1. "DATA2,Data 2" newline hexmask.long.byte 0x1C0 8.--15. 1. "DATA1,Data 1" hexmask.long.byte 0x1C0 0.--7. 1. "DATA0,Data 0" line.long 0x1C4 "JPEG_HUFFSYMB1,JPEG Huffman symbol" hexmask.long.byte 0x1C4 24.--31. 1. "DATA7,Data 7" hexmask.long.byte 0x1C4 16.--23. 1. "DATA6,Data 6" newline hexmask.long.byte 0x1C4 8.--15. 1. "DATA5,Data 5" hexmask.long.byte 0x1C4 0.--7. 1. "DATA4,Data 4" line.long 0x1C8 "JPEG_HUFFSYMB2,JPEG Huffman symbol" hexmask.long.byte 0x1C8 24.--31. 1. "DATA11,Data 11" hexmask.long.byte 0x1C8 16.--23. 1. "DATA10,Data 10" newline hexmask.long.byte 0x1C8 8.--15. 1. "DATA9,Data 9" hexmask.long.byte 0x1C8 0.--7. 1. "DATA8,Data 8" line.long 0x1CC "JPEG_HUFFSYMB3,JPEG Huffman symbol" hexmask.long.byte 0x1CC 24.--31. 1. "DATA15,Data 15" hexmask.long.byte 0x1CC 16.--23. 1. "DATA14,Data 14" newline hexmask.long.byte 0x1CC 8.--15. 1. "DATA13,Data 13" hexmask.long.byte 0x1CC 0.--7. 1. "DATA12,Data 12" line.long 0x1D0 "JPEG_HUFFSYMB4,JPEG Huffman symbol" hexmask.long.byte 0x1D0 24.--31. 1. "DATA19,Data 19" hexmask.long.byte 0x1D0 16.--23. 1. "DATA18,Data 18" newline hexmask.long.byte 0x1D0 8.--15. 1. "DATA17,Data 17" hexmask.long.byte 0x1D0 0.--7. 1. "DATA16,Data 16" line.long 0x1D4 "JPEG_HUFFSYMB5,JPEG Huffman symbol" hexmask.long.byte 0x1D4 24.--31. 1. "DATA23,Data 23" hexmask.long.byte 0x1D4 16.--23. 1. "DATA22,Data 22" newline hexmask.long.byte 0x1D4 8.--15. 1. "DATA21,Data 21" hexmask.long.byte 0x1D4 0.--7. 1. "DATA20,Data 20" line.long 0x1D8 "JPEG_HUFFSYMB6,JPEG Huffman symbol" hexmask.long.byte 0x1D8 24.--31. 1. "DATA27,Data 27" hexmask.long.byte 0x1D8 16.--23. 1. "DATA26,Data 26" newline hexmask.long.byte 0x1D8 8.--15. 1. "DATA25,Data 25" hexmask.long.byte 0x1D8 0.--7. 1. "DATA24,Data 24" line.long 0x1DC "JPEG_HUFFSYMB7,JPEG Huffman symbol" hexmask.long.byte 0x1DC 24.--31. 1. "DATA31,Data 31" hexmask.long.byte 0x1DC 16.--23. 1. "DATA30,Data 30" newline hexmask.long.byte 0x1DC 8.--15. 1. "DATA29,Data 29" hexmask.long.byte 0x1DC 0.--7. 1. "DATA28,Data 28" line.long 0x1E0 "JPEG_HUFFSYMB8,JPEG Huffman symbol" hexmask.long.byte 0x1E0 24.--31. 1. "DATA35,Data 35" hexmask.long.byte 0x1E0 16.--23. 1. "DATA34,Data 34" newline hexmask.long.byte 0x1E0 8.--15. 1. "DATA33,Data 33" hexmask.long.byte 0x1E0 0.--7. 1. "DATA32,Data 32" line.long 0x1E4 "JPEG_HUFFSYMB9,JPEG Huffman symbol" hexmask.long.byte 0x1E4 24.--31. 1. "DATA39,Data 39" hexmask.long.byte 0x1E4 16.--23. 1. "DATA38,Data 38" newline hexmask.long.byte 0x1E4 8.--15. 1. "DATA37,Data 37" hexmask.long.byte 0x1E4 0.--7. 1. "DATA36,Data 36" line.long 0x1E8 "JPEG_HUFFSYMB10,JPEG Huffman symbol" hexmask.long.byte 0x1E8 24.--31. 1. "DATA43,Data 43" hexmask.long.byte 0x1E8 16.--23. 1. "DATA42,Data 42" newline hexmask.long.byte 0x1E8 8.--15. 1. "DATA41,Data 41" hexmask.long.byte 0x1E8 0.--7. 1. "DATA40,Data 40" line.long 0x1EC "JPEG_HUFFSYMB11,JPEG Huffman symbol" hexmask.long.byte 0x1EC 24.--31. 1. "DATA47,Data 47" hexmask.long.byte 0x1EC 16.--23. 1. "DATA46,Data 46" newline hexmask.long.byte 0x1EC 8.--15. 1. "DATA45,Data 45" hexmask.long.byte 0x1EC 0.--7. 1. "DATA44,Data 44" line.long 0x1F0 "JPEG_HUFFSYMB12,JPEG Huffman symbol" hexmask.long.byte 0x1F0 24.--31. 1. "DATA51,Data 51" hexmask.long.byte 0x1F0 16.--23. 1. "DATA50,Data 50" newline hexmask.long.byte 0x1F0 8.--15. 1. "DATA49,Data 49" hexmask.long.byte 0x1F0 0.--7. 1. "DATA48,Data 48" line.long 0x1F4 "JPEG_HUFFSYMB13,JPEG Huffman symbol" hexmask.long.byte 0x1F4 24.--31. 1. "DATA55,Data 55" hexmask.long.byte 0x1F4 16.--23. 1. "DATA54,Data 54" newline hexmask.long.byte 0x1F4 8.--15. 1. "DATA53,Data 53" hexmask.long.byte 0x1F4 0.--7. 1. "DATA52,Data 52" line.long 0x1F8 "JPEG_HUFFSYMB14,JPEG Huffman symbol" hexmask.long.byte 0x1F8 24.--31. 1. "DATA59,Data 59" hexmask.long.byte 0x1F8 16.--23. 1. "DATA58,Data 58" newline hexmask.long.byte 0x1F8 8.--15. 1. "DATA57,Data 57" hexmask.long.byte 0x1F8 0.--7. 1. "DATA56,Data 56" line.long 0x1FC "JPEG_HUFFSYMB15,JPEG Huffman symbol" hexmask.long.byte 0x1FC 24.--31. 1. "DATA63,Data 63" hexmask.long.byte 0x1FC 16.--23. 1. "DATA62,Data 62" newline hexmask.long.byte 0x1FC 8.--15. 1. "DATA61,Data 61" hexmask.long.byte 0x1FC 0.--7. 1. "DATA60,Data 60" line.long 0x200 "JPEG_HUFFSYMB16,JPEG Huffman symbol" hexmask.long.byte 0x200 24.--31. 1. "DATA67,Data 67" hexmask.long.byte 0x200 16.--23. 1. "DATA66,Data 66" newline hexmask.long.byte 0x200 8.--15. 1. "DATA65,Data 65" hexmask.long.byte 0x200 0.--7. 1. "DATA64,Data 64" line.long 0x204 "JPEG_HUFFSYMB17,JPEG Huffman symbol" hexmask.long.byte 0x204 24.--31. 1. "DATA71,Data 71" hexmask.long.byte 0x204 16.--23. 1. "DATA70,Data 70" newline hexmask.long.byte 0x204 8.--15. 1. "DATA69,Data 69" hexmask.long.byte 0x204 0.--7. 1. "DATA68,Data 68" line.long 0x208 "JPEG_HUFFSYMB18,JPEG Huffman symbol" hexmask.long.byte 0x208 24.--31. 1. "DATA75,Data 75" hexmask.long.byte 0x208 16.--23. 1. "DATA74,Data 74" newline hexmask.long.byte 0x208 8.--15. 1. "DATA73,Data 73" hexmask.long.byte 0x208 0.--7. 1. "DATA72,Data 72" line.long 0x20C "JPEG_HUFFSYMB19,JPEG Huffman symbol" hexmask.long.byte 0x20C 24.--31. 1. "DATA79,Data 79" hexmask.long.byte 0x20C 16.--23. 1. "DATA78,Data 78" newline hexmask.long.byte 0x20C 8.--15. 1. "DATA77,Data 77" hexmask.long.byte 0x20C 0.--7. 1. "DATA76,Data 76" line.long 0x210 "JPEG_HUFFSYMB20,JPEG Huffman symbol" hexmask.long.byte 0x210 24.--31. 1. "DATA83,Data 83" hexmask.long.byte 0x210 16.--23. 1. "DATA82,Data 82" newline hexmask.long.byte 0x210 8.--15. 1. "DATA81,Data 81" hexmask.long.byte 0x210 0.--7. 1. "DATA80,Data 80" line.long 0x214 "JPEG_HUFFSYMB21,JPEG Huffman symbol" hexmask.long.byte 0x214 24.--31. 1. "DATA87,Data 87" hexmask.long.byte 0x214 16.--23. 1. "DATA86,Data 86" newline hexmask.long.byte 0x214 8.--15. 1. "DATA85,Data 85" hexmask.long.byte 0x214 0.--7. 1. "DATA84,Data 84" line.long 0x218 "JPEG_HUFFSYMB22,JPEG Huffman symbol" hexmask.long.byte 0x218 24.--31. 1. "DATA91,Data 91" hexmask.long.byte 0x218 16.--23. 1. "DATA90,Data 90" newline hexmask.long.byte 0x218 8.--15. 1. "DATA89,Data 89" hexmask.long.byte 0x218 0.--7. 1. "DATA88,Data 88" line.long 0x21C "JPEG_HUFFSYMB23,JPEG Huffman symbol" hexmask.long.byte 0x21C 24.--31. 1. "DATA95,Data 95" hexmask.long.byte 0x21C 16.--23. 1. "DATA94,Data 94" newline hexmask.long.byte 0x21C 8.--15. 1. "DATA93,Data 93" hexmask.long.byte 0x21C 0.--7. 1. "DATA92,Data 92" line.long 0x220 "JPEG_HUFFSYMB24,JPEG Huffman symbol" hexmask.long.byte 0x220 24.--31. 1. "DATA99,Data 99" hexmask.long.byte 0x220 16.--23. 1. "DATA98,Data 98" newline hexmask.long.byte 0x220 8.--15. 1. "DATA97,Data 97" hexmask.long.byte 0x220 0.--7. 1. "DATA96,Data 96" line.long 0x224 "JPEG_HUFFSYMB25,JPEG Huffman symbol" hexmask.long.byte 0x224 24.--31. 1. "DATA103,Data 103" hexmask.long.byte 0x224 16.--23. 1. "DATA102,Data 102" newline hexmask.long.byte 0x224 8.--15. 1. "DATA101,Data 101" hexmask.long.byte 0x224 0.--7. 1. "DATA100,Data 100" line.long 0x228 "JPEG_HUFFSYMB26,JPEG Huffman symbol" hexmask.long.byte 0x228 24.--31. 1. "DATA107,Data 107" hexmask.long.byte 0x228 16.--23. 1. "DATA106,Data 106" newline hexmask.long.byte 0x228 8.--15. 1. "DATA105,Data 105" hexmask.long.byte 0x228 0.--7. 1. "DATA104,Data 104" line.long 0x22C "JPEG_HUFFSYMB27,JPEG Huffman symbol" hexmask.long.byte 0x22C 24.--31. 1. "DATA111,Data 111" hexmask.long.byte 0x22C 16.--23. 1. "DATA110,Data 110" newline hexmask.long.byte 0x22C 8.--15. 1. "DATA109,Data 109" hexmask.long.byte 0x22C 0.--7. 1. "DATA108,Data 108" line.long 0x230 "JPEG_HUFFSYMB28,JPEG Huffman symbol" hexmask.long.byte 0x230 24.--31. 1. "DATA115,Data 115" hexmask.long.byte 0x230 16.--23. 1. "DATA114,Data 114" newline hexmask.long.byte 0x230 8.--15. 1. "DATA113,Data 113" hexmask.long.byte 0x230 0.--7. 1. "DATA112,Data 112" line.long 0x234 "JPEG_HUFFSYMB29,JPEG Huffman symbol" hexmask.long.byte 0x234 24.--31. 1. "DATA119,Data 119" hexmask.long.byte 0x234 16.--23. 1. "DATA118,Data 118" newline hexmask.long.byte 0x234 8.--15. 1. "DATA117,Data 117" hexmask.long.byte 0x234 0.--7. 1. "DATA116,Data 116" line.long 0x238 "JPEG_HUFFSYMB30,JPEG Huffman symbol" hexmask.long.byte 0x238 24.--31. 1. "DATA123,Data 123" hexmask.long.byte 0x238 16.--23. 1. "DATA122,Data 122" newline hexmask.long.byte 0x238 8.--15. 1. "DATA121,Data 121" hexmask.long.byte 0x238 0.--7. 1. "DATA120,Data 120" line.long 0x23C "JPEG_HUFFSYMB31,JPEG Huffman symbol" hexmask.long.byte 0x23C 24.--31. 1. "DATA127,Data 127" hexmask.long.byte 0x23C 16.--23. 1. "DATA126,Data 126" newline hexmask.long.byte 0x23C 8.--15. 1. "DATA125,Data 125" hexmask.long.byte 0x23C 0.--7. 1. "DATA124,Data 124" line.long 0x240 "JPEG_HUFFSYMB32,JPEG Huffman symbol" hexmask.long.byte 0x240 24.--31. 1. "DATA131,Data 131" hexmask.long.byte 0x240 16.--23. 1. "DATA130,Data 130" newline hexmask.long.byte 0x240 8.--15. 1. "DATA129,Data 129" hexmask.long.byte 0x240 0.--7. 1. "DATA128,Data 128" line.long 0x244 "JPEG_HUFFSYMB33,JPEG Huffman symbol" hexmask.long.byte 0x244 24.--31. 1. "DATA135,Data 135" hexmask.long.byte 0x244 16.--23. 1. "DATA134,Data 134" newline hexmask.long.byte 0x244 8.--15. 1. "DATA133,Data 133" hexmask.long.byte 0x244 0.--7. 1. "DATA132,Data 132" line.long 0x248 "JPEG_HUFFSYMB34,JPEG Huffman symbol" hexmask.long.byte 0x248 24.--31. 1. "DATA139,Data 139" hexmask.long.byte 0x248 16.--23. 1. "DATA138,Data 138" newline hexmask.long.byte 0x248 8.--15. 1. "DATA137,Data 137" hexmask.long.byte 0x248 0.--7. 1. "DATA136,Data 136" line.long 0x24C "JPEG_HUFFSYMB35,JPEG Huffman symbol" hexmask.long.byte 0x24C 24.--31. 1. "DATA143,Data 143" hexmask.long.byte 0x24C 16.--23. 1. "DATA142,Data 142" newline hexmask.long.byte 0x24C 8.--15. 1. "DATA141,Data 141" hexmask.long.byte 0x24C 0.--7. 1. "DATA140,Data 140" line.long 0x250 "JPEG_HUFFSYMB36,JPEG Huffman symbol" hexmask.long.byte 0x250 24.--31. 1. "DATA147,Data 147" hexmask.long.byte 0x250 16.--23. 1. "DATA146,Data 146" newline hexmask.long.byte 0x250 8.--15. 1. "DATA145,Data 145" hexmask.long.byte 0x250 0.--7. 1. "DATA144,Data 144" line.long 0x254 "JPEG_HUFFSYMB37,JPEG Huffman symbol" hexmask.long.byte 0x254 24.--31. 1. "DATA151,Data 151" hexmask.long.byte 0x254 16.--23. 1. "DATA150,Data 150" newline hexmask.long.byte 0x254 8.--15. 1. "DATA149,Data 149" hexmask.long.byte 0x254 0.--7. 1. "DATA148,Data 148" line.long 0x258 "JPEG_HUFFSYMB38,JPEG Huffman symbol" hexmask.long.byte 0x258 24.--31. 1. "DATA155,Data 155" hexmask.long.byte 0x258 16.--23. 1. "DATA154,Data 154" newline hexmask.long.byte 0x258 8.--15. 1. "DATA153,Data 153" hexmask.long.byte 0x258 0.--7. 1. "DATA152,Data 152" line.long 0x25C "JPEG_HUFFSYMB39,JPEG Huffman symbol" hexmask.long.byte 0x25C 24.--31. 1. "DATA159,Data 159" hexmask.long.byte 0x25C 16.--23. 1. "DATA158,Data 158" newline hexmask.long.byte 0x25C 8.--15. 1. "DATA157,Data 157" hexmask.long.byte 0x25C 0.--7. 1. "DATA156,Data 156" line.long 0x260 "JPEG_HUFFSYMB40,JPEG Huffman symbol" hexmask.long.byte 0x260 24.--31. 1. "DATA163,Data 163" hexmask.long.byte 0x260 16.--23. 1. "DATA162,Data 162" newline hexmask.long.byte 0x260 8.--15. 1. "DATA161,Data 161" hexmask.long.byte 0x260 0.--7. 1. "DATA160,Data 160" line.long 0x264 "JPEG_HUFFSYMB41,JPEG Huffman symbol" hexmask.long.byte 0x264 24.--31. 1. "DATA167,Data 167" hexmask.long.byte 0x264 16.--23. 1. "DATA166,Data 166" newline hexmask.long.byte 0x264 8.--15. 1. "DATA165,Data 165" hexmask.long.byte 0x264 0.--7. 1. "DATA164,Data 164" line.long 0x268 "JPEG_HUFFSYMB42,JPEG Huffman symbol" hexmask.long.byte 0x268 24.--31. 1. "DATA171,Data 171" hexmask.long.byte 0x268 16.--23. 1. "DATA170,Data 170" newline hexmask.long.byte 0x268 8.--15. 1. "DATA169,Data 169" hexmask.long.byte 0x268 0.--7. 1. "DATA168,Data 168" line.long 0x26C "JPEG_HUFFSYMB43,JPEG Huffman symbol" hexmask.long.byte 0x26C 24.--31. 1. "DATA175,Data 175" hexmask.long.byte 0x26C 16.--23. 1. "DATA174,Data 174" newline hexmask.long.byte 0x26C 8.--15. 1. "DATA173,Data 173" hexmask.long.byte 0x26C 0.--7. 1. "DATA172,Data 172" line.long 0x270 "JPEG_HUFFSYMB44,JPEG Huffman symbol" hexmask.long.byte 0x270 24.--31. 1. "DATA179,Data 179" hexmask.long.byte 0x270 16.--23. 1. "DATA178,Data 178" newline hexmask.long.byte 0x270 8.--15. 1. "DATA177,Data 177" hexmask.long.byte 0x270 0.--7. 1. "DATA176,Data 176" line.long 0x274 "JPEG_HUFFSYMB45,JPEG Huffman symbol" hexmask.long.byte 0x274 24.--31. 1. "DATA183,Data 183" hexmask.long.byte 0x274 16.--23. 1. "DATA182,Data 182" newline hexmask.long.byte 0x274 8.--15. 1. "DATA181,Data 181" hexmask.long.byte 0x274 0.--7. 1. "DATA180,Data 180" line.long 0x278 "JPEG_HUFFSYMB46,JPEG Huffman symbol" hexmask.long.byte 0x278 24.--31. 1. "DATA187,Data 187" hexmask.long.byte 0x278 16.--23. 1. "DATA186,Data 186" newline hexmask.long.byte 0x278 8.--15. 1. "DATA185,Data 185" hexmask.long.byte 0x278 0.--7. 1. "DATA184,Data 184" line.long 0x27C "JPEG_HUFFSYMB47,JPEG Huffman symbol" hexmask.long.byte 0x27C 24.--31. 1. "DATA191,Data 191" hexmask.long.byte 0x27C 16.--23. 1. "DATA190,Data 190" newline hexmask.long.byte 0x27C 8.--15. 1. "DATA189,Data 189" hexmask.long.byte 0x27C 0.--7. 1. "DATA188,Data 188" line.long 0x280 "JPEG_HUFFSYMB48,JPEG Huffman symbol" hexmask.long.byte 0x280 24.--31. 1. "DATA195,Data 195" hexmask.long.byte 0x280 16.--23. 1. "DATA194,Data 194" newline hexmask.long.byte 0x280 8.--15. 1. "DATA193,Data 193" hexmask.long.byte 0x280 0.--7. 1. "DATA192,Data 192" line.long 0x284 "JPEG_HUFFSYMB49,JPEG Huffman symbol" hexmask.long.byte 0x284 24.--31. 1. "DATA199,Data 199" hexmask.long.byte 0x284 16.--23. 1. "DATA198,Data 198" newline hexmask.long.byte 0x284 8.--15. 1. "DATA197,Data 197" hexmask.long.byte 0x284 0.--7. 1. "DATA196,Data 196" line.long 0x288 "JPEG_HUFFSYMB50,JPEG Huffman symbol" hexmask.long.byte 0x288 24.--31. 1. "DATA203,Data 203" hexmask.long.byte 0x288 16.--23. 1. "DATA202,Data 202" newline hexmask.long.byte 0x288 8.--15. 1. "DATA201,Data 201" hexmask.long.byte 0x288 0.--7. 1. "DATA200,Data 200" line.long 0x28C "JPEG_HUFFSYMB51,JPEG Huffman symbol" hexmask.long.byte 0x28C 24.--31. 1. "DATA207,Data 207" hexmask.long.byte 0x28C 16.--23. 1. "DATA206,Data 206" newline hexmask.long.byte 0x28C 8.--15. 1. "DATA205,Data 205" hexmask.long.byte 0x28C 0.--7. 1. "DATA204,Data 204" line.long 0x290 "JPEG_HUFFSYMB52,JPEG Huffman symbol" hexmask.long.byte 0x290 24.--31. 1. "DATA211,Data 211" hexmask.long.byte 0x290 16.--23. 1. "DATA210,Data 210" newline hexmask.long.byte 0x290 8.--15. 1. "DATA209,Data 209" hexmask.long.byte 0x290 0.--7. 1. "DATA208,Data 208" line.long 0x294 "JPEG_HUFFSYMB53,JPEG Huffman symbol" hexmask.long.byte 0x294 24.--31. 1. "DATA215,Data 215" hexmask.long.byte 0x294 16.--23. 1. "DATA214,Data 214" newline hexmask.long.byte 0x294 8.--15. 1. "DATA213,Data 213" hexmask.long.byte 0x294 0.--7. 1. "DATA212,Data 212" line.long 0x298 "JPEG_HUFFSYMB54,JPEG Huffman symbol" hexmask.long.byte 0x298 24.--31. 1. "DATA219,Data 219" hexmask.long.byte 0x298 16.--23. 1. "DATA218,Data 218" newline hexmask.long.byte 0x298 8.--15. 1. "DATA217,Data 217" hexmask.long.byte 0x298 0.--7. 1. "DATA216,Data 216" line.long 0x29C "JPEG_HUFFSYMB55,JPEG Huffman symbol" hexmask.long.byte 0x29C 24.--31. 1. "DATA223,Data 223" hexmask.long.byte 0x29C 16.--23. 1. "DATA222,Data 222" newline hexmask.long.byte 0x29C 8.--15. 1. "DATA221,Data 221" hexmask.long.byte 0x29C 0.--7. 1. "DATA220,Data 220" line.long 0x2A0 "JPEG_HUFFSYMB56,JPEG Huffman symbol" hexmask.long.byte 0x2A0 24.--31. 1. "DATA227,Data 227" hexmask.long.byte 0x2A0 16.--23. 1. "DATA226,Data 226" newline hexmask.long.byte 0x2A0 8.--15. 1. "DATA225,Data 225" hexmask.long.byte 0x2A0 0.--7. 1. "DATA224,Data 224" line.long 0x2A4 "JPEG_HUFFSYMB57,JPEG Huffman symbol" hexmask.long.byte 0x2A4 24.--31. 1. "DATA231,Data 231" hexmask.long.byte 0x2A4 16.--23. 1. "DATA230,Data 230" newline hexmask.long.byte 0x2A4 8.--15. 1. "DATA229,Data 229" hexmask.long.byte 0x2A4 0.--7. 1. "DATA228,Data 228" line.long 0x2A8 "JPEG_HUFFSYMB58,JPEG Huffman symbol" hexmask.long.byte 0x2A8 24.--31. 1. "DATA235,Data 235" hexmask.long.byte 0x2A8 16.--23. 1. "DATA234,Data 234" newline hexmask.long.byte 0x2A8 8.--15. 1. "DATA233,Data 233" hexmask.long.byte 0x2A8 0.--7. 1. "DATA232,Data 232" line.long 0x2AC "JPEG_HUFFSYMB59,JPEG Huffman symbol" hexmask.long.byte 0x2AC 24.--31. 1. "DATA239,Data 239" hexmask.long.byte 0x2AC 16.--23. 1. "DATA238,Data 238" newline hexmask.long.byte 0x2AC 8.--15. 1. "DATA237,Data 237" hexmask.long.byte 0x2AC 0.--7. 1. "DATA236,Data 236" line.long 0x2B0 "JPEG_HUFFSYMB60,JPEG Huffman symbol" hexmask.long.byte 0x2B0 24.--31. 1. "DATA243,Data 243" hexmask.long.byte 0x2B0 16.--23. 1. "DATA242,Data 242" newline hexmask.long.byte 0x2B0 8.--15. 1. "DATA241,Data 241" hexmask.long.byte 0x2B0 0.--7. 1. "DATA240,Data 240" line.long 0x2B4 "JPEG_HUFFSYMB61,JPEG Huffman symbol" hexmask.long.byte 0x2B4 24.--31. 1. "DATA247,Data 247" hexmask.long.byte 0x2B4 16.--23. 1. "DATA246,Data 246" newline hexmask.long.byte 0x2B4 8.--15. 1. "DATA245,Data 245" hexmask.long.byte 0x2B4 0.--7. 1. "DATA244,Data 244" line.long 0x2B8 "JPEG_HUFFSYMB62,JPEG Huffman symbol" hexmask.long.byte 0x2B8 24.--31. 1. "DATA251,Data 251" hexmask.long.byte 0x2B8 16.--23. 1. "DATA250,Data 250" newline hexmask.long.byte 0x2B8 8.--15. 1. "DATA249,Data 249" hexmask.long.byte 0x2B8 0.--7. 1. "DATA248,Data 248" line.long 0x2BC "JPEG_HUFFSYMB63,JPEG Huffman symbol" hexmask.long.byte 0x2BC 24.--31. 1. "DATA255,Data 255" hexmask.long.byte 0x2BC 16.--23. 1. "DATA254,Data 254" newline hexmask.long.byte 0x2BC 8.--15. 1. "DATA253,Data 253" hexmask.long.byte 0x2BC 0.--7. 1. "DATA252,Data 252" line.long 0x2C0 "JPEG_HUFFSYMB64,JPEG Huffman symbol" hexmask.long.byte 0x2C0 24.--31. 1. "DATA259,Data 259" hexmask.long.byte 0x2C0 16.--23. 1. "DATA258,Data 258" newline hexmask.long.byte 0x2C0 8.--15. 1. "DATA257,Data 257" hexmask.long.byte 0x2C0 0.--7. 1. "DATA256,Data 256" line.long 0x2C4 "JPEG_HUFFSYMB65,JPEG Huffman symbol" hexmask.long.byte 0x2C4 24.--31. 1. "DATA263,Data 263" hexmask.long.byte 0x2C4 16.--23. 1. "DATA262,Data 262" newline hexmask.long.byte 0x2C4 8.--15. 1. "DATA261,Data 261" hexmask.long.byte 0x2C4 0.--7. 1. "DATA260,Data 260" line.long 0x2C8 "JPEG_HUFFSYMB66,JPEG Huffman symbol" hexmask.long.byte 0x2C8 24.--31. 1. "DATA267,Data 267" hexmask.long.byte 0x2C8 16.--23. 1. "DATA266,Data 266" newline hexmask.long.byte 0x2C8 8.--15. 1. "DATA265,Data 265" hexmask.long.byte 0x2C8 0.--7. 1. "DATA264,Data 264" line.long 0x2CC "JPEG_HUFFSYMB67,JPEG Huffman symbol" hexmask.long.byte 0x2CC 24.--31. 1. "DATA271,Data 271" hexmask.long.byte 0x2CC 16.--23. 1. "DATA270,Data 270" newline hexmask.long.byte 0x2CC 8.--15. 1. "DATA269,Data 269" hexmask.long.byte 0x2CC 0.--7. 1. "DATA268,Data 268" line.long 0x2D0 "JPEG_HUFFSYMB68,JPEG Huffman symbol" hexmask.long.byte 0x2D0 24.--31. 1. "DATA275,Data 275" hexmask.long.byte 0x2D0 16.--23. 1. "DATA274,Data 274" newline hexmask.long.byte 0x2D0 8.--15. 1. "DATA273,Data 273" hexmask.long.byte 0x2D0 0.--7. 1. "DATA272,Data 272" line.long 0x2D4 "JPEG_HUFFSYMB69,JPEG Huffman symbol" hexmask.long.byte 0x2D4 24.--31. 1. "DATA279,Data 279" hexmask.long.byte 0x2D4 16.--23. 1. "DATA278,Data 278" newline hexmask.long.byte 0x2D4 8.--15. 1. "DATA277,Data 277" hexmask.long.byte 0x2D4 0.--7. 1. "DATA276,Data 276" line.long 0x2D8 "JPEG_HUFFSYMB70,JPEG Huffman symbol" hexmask.long.byte 0x2D8 24.--31. 1. "DATA283,Data 283" hexmask.long.byte 0x2D8 16.--23. 1. "DATA282,Data 282" newline hexmask.long.byte 0x2D8 8.--15. 1. "DATA281,Data 281" hexmask.long.byte 0x2D8 0.--7. 1. "DATA280,Data 280" line.long 0x2DC "JPEG_HUFFSYMB71,JPEG Huffman symbol" hexmask.long.byte 0x2DC 24.--31. 1. "DATA287,Data 287" hexmask.long.byte 0x2DC 16.--23. 1. "DATA286,Data 286" newline hexmask.long.byte 0x2DC 8.--15. 1. "DATA285,Data 285" hexmask.long.byte 0x2DC 0.--7. 1. "DATA284,Data 284" line.long 0x2E0 "JPEG_HUFFSYMB72,JPEG Huffman symbol" hexmask.long.byte 0x2E0 24.--31. 1. "DATA291,Data 291" hexmask.long.byte 0x2E0 16.--23. 1. "DATA290,Data 290" newline hexmask.long.byte 0x2E0 8.--15. 1. "DATA289,Data 289" hexmask.long.byte 0x2E0 0.--7. 1. "DATA288,Data 288" line.long 0x2E4 "JPEG_HUFFSYMB73,JPEG Huffman symbol" hexmask.long.byte 0x2E4 24.--31. 1. "DATA295,Data 295" hexmask.long.byte 0x2E4 16.--23. 1. "DATA294,Data 294" newline hexmask.long.byte 0x2E4 8.--15. 1. "DATA293,Data 293" hexmask.long.byte 0x2E4 0.--7. 1. "DATA292,Data 292" line.long 0x2E8 "JPEG_HUFFSYMB74,JPEG Huffman symbol" hexmask.long.byte 0x2E8 24.--31. 1. "DATA299,Data 299" hexmask.long.byte 0x2E8 16.--23. 1. "DATA298,Data 298" newline hexmask.long.byte 0x2E8 8.--15. 1. "DATA297,Data 297" hexmask.long.byte 0x2E8 0.--7. 1. "DATA296,Data 296" line.long 0x2EC "JPEG_HUFFSYMB75,JPEG Huffman symbol" hexmask.long.byte 0x2EC 24.--31. 1. "DATA303,Data 303" hexmask.long.byte 0x2EC 16.--23. 1. "DATA302,Data 302" newline hexmask.long.byte 0x2EC 8.--15. 1. "DATA301,Data 301" hexmask.long.byte 0x2EC 0.--7. 1. "DATA300,Data 300" line.long 0x2F0 "JPEG_HUFFSYMB76,JPEG Huffman symbol" hexmask.long.byte 0x2F0 24.--31. 1. "DATA307,Data 307" hexmask.long.byte 0x2F0 16.--23. 1. "DATA306,Data 306" newline hexmask.long.byte 0x2F0 8.--15. 1. "DATA305,Data 305" hexmask.long.byte 0x2F0 0.--7. 1. "DATA304,Data 304" line.long 0x2F4 "JPEG_HUFFSYMB77,JPEG Huffman symbol" hexmask.long.byte 0x2F4 24.--31. 1. "DATA311,Data 311" hexmask.long.byte 0x2F4 16.--23. 1. "DATA310,Data 310" newline hexmask.long.byte 0x2F4 8.--15. 1. "DATA309,Data 309" hexmask.long.byte 0x2F4 0.--7. 1. "DATA308,Data 308" line.long 0x2F8 "JPEG_HUFFSYMB78,JPEG Huffman symbol" hexmask.long.byte 0x2F8 24.--31. 1. "DATA315,Data 315" hexmask.long.byte 0x2F8 16.--23. 1. "DATA314,Data 314" newline hexmask.long.byte 0x2F8 8.--15. 1. "DATA313,Data 313" hexmask.long.byte 0x2F8 0.--7. 1. "DATA312,Data 312" line.long 0x2FC "JPEG_HUFFSYMB79,JPEG Huffman symbol" hexmask.long.byte 0x2FC 24.--31. 1. "DATA319,Data 319" hexmask.long.byte 0x2FC 16.--23. 1. "DATA318,Data 318" newline hexmask.long.byte 0x2FC 8.--15. 1. "DATA317,Data 317" hexmask.long.byte 0x2FC 0.--7. 1. "DATA316,Data 316" line.long 0x300 "JPEG_HUFFSYMB80,JPEG Huffman symbol" hexmask.long.byte 0x300 24.--31. 1. "DATA323,Data 323" hexmask.long.byte 0x300 16.--23. 1. "DATA322,Data 322" newline hexmask.long.byte 0x300 8.--15. 1. "DATA321,Data 321" hexmask.long.byte 0x300 0.--7. 1. "DATA320,Data 320" line.long 0x304 "JPEG_HUFFSYMB81,JPEG Huffman symbol" hexmask.long.byte 0x304 24.--31. 1. "DATA327,Data 327" hexmask.long.byte 0x304 16.--23. 1. "DATA326,Data 326" newline hexmask.long.byte 0x304 8.--15. 1. "DATA325,Data 325" hexmask.long.byte 0x304 0.--7. 1. "DATA324,Data 324" line.long 0x308 "JPEG_HUFFSYMB82,JPEG Huffman symbol" hexmask.long.byte 0x308 24.--31. 1. "DATA331,Data 331" hexmask.long.byte 0x308 16.--23. 1. "DATA330,Data 330" newline hexmask.long.byte 0x308 8.--15. 1. "DATA329,Data 329" hexmask.long.byte 0x308 0.--7. 1. "DATA328,Data 328" line.long 0x30C "JPEG_HUFFSYMB83,JPEG Huffman symbol" hexmask.long.byte 0x30C 24.--31. 1. "DATA335,Data 335" hexmask.long.byte 0x30C 16.--23. 1. "DATA334,Data 334" newline hexmask.long.byte 0x30C 8.--15. 1. "DATA333,Data 333" hexmask.long.byte 0x30C 0.--7. 1. "DATA332,Data 332" line.long 0x310 "JPEG_DHTMEM0,JPEG DHT memory" hexmask.long.byte 0x310 24.--31. 1. "DATA3,Huffman table data 3" hexmask.long.byte 0x310 16.--23. 1. "DATA2,Huffman table data 2" newline hexmask.long.byte 0x310 8.--15. 1. "DATA1,Huffman table data 1" hexmask.long.byte 0x310 0.--7. 1. "DATA0,Huffman table data 0" line.long 0x314 "JPEG_DHTMEM1,JPEG DHT memory" hexmask.long.byte 0x314 24.--31. 1. "DATA7,Huffman table data 7" hexmask.long.byte 0x314 16.--23. 1. "DATA6,Huffman table data 6" newline hexmask.long.byte 0x314 8.--15. 1. "DATA5,Huffman table data 5" hexmask.long.byte 0x314 0.--7. 1. "DATA4,Huffman table data 4" line.long 0x318 "JPEG_DHTMEM2,JPEG DHT memory" hexmask.long.byte 0x318 24.--31. 1. "DATA11,Huffman table data 11" hexmask.long.byte 0x318 16.--23. 1. "DATA10,Huffman table data 10" newline hexmask.long.byte 0x318 8.--15. 1. "DATA9,Huffman table data 9" hexmask.long.byte 0x318 0.--7. 1. "DATA8,Huffman table data 8" line.long 0x31C "JPEG_DHTMEM3,JPEG DHT memory" hexmask.long.byte 0x31C 24.--31. 1. "DATA15,Huffman table data 15" hexmask.long.byte 0x31C 16.--23. 1. "DATA14,Huffman table data 14" newline hexmask.long.byte 0x31C 8.--15. 1. "DATA13,Huffman table data 13" hexmask.long.byte 0x31C 0.--7. 1. "DATA12,Huffman table data 12" line.long 0x320 "JPEG_DHTMEM4,JPEG DHT memory" hexmask.long.byte 0x320 24.--31. 1. "DATA19,Huffman table data 19" hexmask.long.byte 0x320 16.--23. 1. "DATA18,Huffman table data 18" newline hexmask.long.byte 0x320 8.--15. 1. "DATA17,Huffman table data 17" hexmask.long.byte 0x320 0.--7. 1. "DATA16,Huffman table data 16" line.long 0x324 "JPEG_DHTMEM5,JPEG DHT memory" hexmask.long.byte 0x324 24.--31. 1. "DATA23,Huffman table data 23" hexmask.long.byte 0x324 16.--23. 1. "DATA22,Huffman table data 22" newline hexmask.long.byte 0x324 8.--15. 1. "DATA21,Huffman table data 21" hexmask.long.byte 0x324 0.--7. 1. "DATA20,Huffman table data 20" line.long 0x328 "JPEG_DHTMEM6,JPEG DHT memory" hexmask.long.byte 0x328 24.--31. 1. "DATA27,Huffman table data 27" hexmask.long.byte 0x328 16.--23. 1. "DATA26,Huffman table data 26" newline hexmask.long.byte 0x328 8.--15. 1. "DATA25,Huffman table data 25" hexmask.long.byte 0x328 0.--7. 1. "DATA24,Huffman table data 24" line.long 0x32C "JPEG_DHTMEM7,JPEG DHT memory" hexmask.long.byte 0x32C 24.--31. 1. "DATA31,Huffman table data 31" hexmask.long.byte 0x32C 16.--23. 1. "DATA30,Huffman table data 30" newline hexmask.long.byte 0x32C 8.--15. 1. "DATA29,Huffman table data 29" hexmask.long.byte 0x32C 0.--7. 1. "DATA28,Huffman table data 28" line.long 0x330 "JPEG_DHTMEM8,JPEG DHT memory" hexmask.long.byte 0x330 24.--31. 1. "DATA35,Huffman table data 35" hexmask.long.byte 0x330 16.--23. 1. "DATA34,Huffman table data 34" newline hexmask.long.byte 0x330 8.--15. 1. "DATA33,Huffman table data 33" hexmask.long.byte 0x330 0.--7. 1. "DATA32,Huffman table data 32" line.long 0x334 "JPEG_DHTMEM9,JPEG DHT memory" hexmask.long.byte 0x334 24.--31. 1. "DATA39,Huffman table data 39" hexmask.long.byte 0x334 16.--23. 1. "DATA38,Huffman table data 38" newline hexmask.long.byte 0x334 8.--15. 1. "DATA37,Huffman table data 37" hexmask.long.byte 0x334 0.--7. 1. "DATA36,Huffman table data 36" line.long 0x338 "JPEG_DHTMEM10,JPEG DHT memory" hexmask.long.byte 0x338 24.--31. 1. "DATA43,Huffman table data 43" hexmask.long.byte 0x338 16.--23. 1. "DATA42,Huffman table data 42" newline hexmask.long.byte 0x338 8.--15. 1. "DATA41,Huffman table data 41" hexmask.long.byte 0x338 0.--7. 1. "DATA40,Huffman table data 40" line.long 0x33C "JPEG_DHTMEM11,JPEG DHT memory" hexmask.long.byte 0x33C 24.--31. 1. "DATA47,Huffman table data 47" hexmask.long.byte 0x33C 16.--23. 1. "DATA46,Huffman table data 46" newline hexmask.long.byte 0x33C 8.--15. 1. "DATA45,Huffman table data 45" hexmask.long.byte 0x33C 0.--7. 1. "DATA44,Huffman table data 44" line.long 0x340 "JPEG_DHTMEM12,JPEG DHT memory" hexmask.long.byte 0x340 24.--31. 1. "DATA51,Huffman table data 51" hexmask.long.byte 0x340 16.--23. 1. "DATA50,Huffman table data 50" newline hexmask.long.byte 0x340 8.--15. 1. "DATA49,Huffman table data 49" hexmask.long.byte 0x340 0.--7. 1. "DATA48,Huffman table data 48" line.long 0x344 "JPEG_DHTMEM13,JPEG DHT memory" hexmask.long.byte 0x344 24.--31. 1. "DATA55,Huffman table data 55" hexmask.long.byte 0x344 16.--23. 1. "DATA54,Huffman table data 54" newline hexmask.long.byte 0x344 8.--15. 1. "DATA53,Huffman table data 53" hexmask.long.byte 0x344 0.--7. 1. "DATA52,Huffman table data 52" line.long 0x348 "JPEG_DHTMEM14,JPEG DHT memory" hexmask.long.byte 0x348 24.--31. 1. "DATA59,Huffman table data 59" hexmask.long.byte 0x348 16.--23. 1. "DATA58,Huffman table data 58" newline hexmask.long.byte 0x348 8.--15. 1. "DATA57,Huffman table data 57" hexmask.long.byte 0x348 0.--7. 1. "DATA56,Huffman table data 56" line.long 0x34C "JPEG_DHTMEM15,JPEG DHT memory" hexmask.long.byte 0x34C 24.--31. 1. "DATA63,Huffman table data 63" hexmask.long.byte 0x34C 16.--23. 1. "DATA62,Huffman table data 62" newline hexmask.long.byte 0x34C 8.--15. 1. "DATA61,Huffman table data 61" hexmask.long.byte 0x34C 0.--7. 1. "DATA60,Huffman table data 60" line.long 0x350 "JPEG_DHTMEM16,JPEG DHT memory" hexmask.long.byte 0x350 24.--31. 1. "DATA67,Huffman table data 67" hexmask.long.byte 0x350 16.--23. 1. "DATA66,Huffman table data 66" newline hexmask.long.byte 0x350 8.--15. 1. "DATA65,Huffman table data 65" hexmask.long.byte 0x350 0.--7. 1. "DATA64,Huffman table data 64" line.long 0x354 "JPEG_DHTMEM17,JPEG DHT memory" hexmask.long.byte 0x354 24.--31. 1. "DATA71,Huffman table data 71" hexmask.long.byte 0x354 16.--23. 1. "DATA70,Huffman table data 70" newline hexmask.long.byte 0x354 8.--15. 1. "DATA69,Huffman table data 69" hexmask.long.byte 0x354 0.--7. 1. "DATA68,Huffman table data 68" line.long 0x358 "JPEG_DHTMEM18,JPEG DHT memory" hexmask.long.byte 0x358 24.--31. 1. "DATA75,Huffman table data 75" hexmask.long.byte 0x358 16.--23. 1. "DATA74,Huffman table data 74" newline hexmask.long.byte 0x358 8.--15. 1. "DATA73,Huffman table data 73" hexmask.long.byte 0x358 0.--7. 1. "DATA72,Huffman table data 72" line.long 0x35C "JPEG_DHTMEM19,JPEG DHT memory" hexmask.long.byte 0x35C 24.--31. 1. "DATA79,Huffman table data 79" hexmask.long.byte 0x35C 16.--23. 1. "DATA78,Huffman table data 78" newline hexmask.long.byte 0x35C 8.--15. 1. "DATA77,Huffman table data 77" hexmask.long.byte 0x35C 0.--7. 1. "DATA76,Huffman table data 76" line.long 0x360 "JPEG_DHTMEM20,JPEG DHT memory" hexmask.long.byte 0x360 24.--31. 1. "DATA83,Huffman table data 83" hexmask.long.byte 0x360 16.--23. 1. "DATA82,Huffman table data 82" newline hexmask.long.byte 0x360 8.--15. 1. "DATA81,Huffman table data 81" hexmask.long.byte 0x360 0.--7. 1. "DATA80,Huffman table data 80" line.long 0x364 "JPEG_DHTMEM21,JPEG DHT memory" hexmask.long.byte 0x364 24.--31. 1. "DATA87,Huffman table data 87" hexmask.long.byte 0x364 16.--23. 1. "DATA86,Huffman table data 86" newline hexmask.long.byte 0x364 8.--15. 1. "DATA85,Huffman table data 85" hexmask.long.byte 0x364 0.--7. 1. "DATA84,Huffman table data 84" line.long 0x368 "JPEG_DHTMEM22,JPEG DHT memory" hexmask.long.byte 0x368 24.--31. 1. "DATA91,Huffman table data 91" hexmask.long.byte 0x368 16.--23. 1. "DATA90,Huffman table data 90" newline hexmask.long.byte 0x368 8.--15. 1. "DATA89,Huffman table data 89" hexmask.long.byte 0x368 0.--7. 1. "DATA88,Huffman table data 88" line.long 0x36C "JPEG_DHTMEM23,JPEG DHT memory" hexmask.long.byte 0x36C 24.--31. 1. "DATA95,Huffman table data 95" hexmask.long.byte 0x36C 16.--23. 1. "DATA94,Huffman table data 94" newline hexmask.long.byte 0x36C 8.--15. 1. "DATA93,Huffman table data 93" hexmask.long.byte 0x36C 0.--7. 1. "DATA92,Huffman table data 92" line.long 0x370 "JPEG_DHTMEM24,JPEG DHT memory" hexmask.long.byte 0x370 24.--31. 1. "DATA99,Huffman table data 99" hexmask.long.byte 0x370 16.--23. 1. "DATA98,Huffman table data 98" newline hexmask.long.byte 0x370 8.--15. 1. "DATA97,Huffman table data 97" hexmask.long.byte 0x370 0.--7. 1. "DATA96,Huffman table data 96" line.long 0x374 "JPEG_DHTMEM25,JPEG DHT memory" hexmask.long.byte 0x374 24.--31. 1. "DATA103,Huffman table data 103" hexmask.long.byte 0x374 16.--23. 1. "DATA102,Huffman table data 102" newline hexmask.long.byte 0x374 8.--15. 1. "DATA101,Huffman table data 101" hexmask.long.byte 0x374 0.--7. 1. "DATA100,Huffman table data 100" line.long 0x378 "JPEG_DHTMEM26,JPEG DHT memory" hexmask.long.byte 0x378 24.--31. 1. "DATA107,Huffman table data 107" hexmask.long.byte 0x378 16.--23. 1. "DATA106,Huffman table data 106" newline hexmask.long.byte 0x378 8.--15. 1. "DATA105,Huffman table data 105" hexmask.long.byte 0x378 0.--7. 1. "DATA104,Huffman table data 104" line.long 0x37C "JPEG_DHTMEM27,JPEG DHT memory" hexmask.long.byte 0x37C 24.--31. 1. "DATA111,Huffman table data 111" hexmask.long.byte 0x37C 16.--23. 1. "DATA110,Huffman table data 110" newline hexmask.long.byte 0x37C 8.--15. 1. "DATA109,Huffman table data 109" hexmask.long.byte 0x37C 0.--7. 1. "DATA108,Huffman table data 108" line.long 0x380 "JPEG_DHTMEM28,JPEG DHT memory" hexmask.long.byte 0x380 24.--31. 1. "DATA115,Huffman table data 115" hexmask.long.byte 0x380 16.--23. 1. "DATA114,Huffman table data 114" newline hexmask.long.byte 0x380 8.--15. 1. "DATA113,Huffman table data 113" hexmask.long.byte 0x380 0.--7. 1. "DATA112,Huffman table data 112" line.long 0x384 "JPEG_DHTMEM29,JPEG DHT memory" hexmask.long.byte 0x384 24.--31. 1. "DATA119,Huffman table data 119" hexmask.long.byte 0x384 16.--23. 1. "DATA118,Huffman table data 118" newline hexmask.long.byte 0x384 8.--15. 1. "DATA117,Huffman table data 117" hexmask.long.byte 0x384 0.--7. 1. "DATA116,Huffman table data 116" line.long 0x388 "JPEG_DHTMEM30,JPEG DHT memory" hexmask.long.byte 0x388 24.--31. 1. "DATA123,Huffman table data 123" hexmask.long.byte 0x388 16.--23. 1. "DATA122,Huffman table data 122" newline hexmask.long.byte 0x388 8.--15. 1. "DATA121,Huffman table data 121" hexmask.long.byte 0x388 0.--7. 1. "DATA120,Huffman table data 120" line.long 0x38C "JPEG_DHTMEM31,JPEG DHT memory" hexmask.long.byte 0x38C 24.--31. 1. "DATA127,Huffman table data 127" hexmask.long.byte 0x38C 16.--23. 1. "DATA126,Huffman table data 126" newline hexmask.long.byte 0x38C 8.--15. 1. "DATA125,Huffman table data 125" hexmask.long.byte 0x38C 0.--7. 1. "DATA124,Huffman table data 124" line.long 0x390 "JPEG_DHTMEM32,JPEG DHT memory" hexmask.long.byte 0x390 24.--31. 1. "DATA131,Huffman table data 131" hexmask.long.byte 0x390 16.--23. 1. "DATA130,Huffman table data 130" newline hexmask.long.byte 0x390 8.--15. 1. "DATA129,Huffman table data 129" hexmask.long.byte 0x390 0.--7. 1. "DATA128,Huffman table data 128" line.long 0x394 "JPEG_DHTMEM33,JPEG DHT memory" hexmask.long.byte 0x394 24.--31. 1. "DATA135,Huffman table data 135" hexmask.long.byte 0x394 16.--23. 1. "DATA134,Huffman table data 134" newline hexmask.long.byte 0x394 8.--15. 1. "DATA133,Huffman table data 133" hexmask.long.byte 0x394 0.--7. 1. "DATA132,Huffman table data 132" line.long 0x398 "JPEG_DHTMEM34,JPEG DHT memory" hexmask.long.byte 0x398 24.--31. 1. "DATA139,Huffman table data 139" hexmask.long.byte 0x398 16.--23. 1. "DATA138,Huffman table data 138" newline hexmask.long.byte 0x398 8.--15. 1. "DATA137,Huffman table data 137" hexmask.long.byte 0x398 0.--7. 1. "DATA136,Huffman table data 136" line.long 0x39C "JPEG_DHTMEM35,JPEG DHT memory" hexmask.long.byte 0x39C 24.--31. 1. "DATA143,Huffman table data 143" hexmask.long.byte 0x39C 16.--23. 1. "DATA142,Huffman table data 142" newline hexmask.long.byte 0x39C 8.--15. 1. "DATA141,Huffman table data 141" hexmask.long.byte 0x39C 0.--7. 1. "DATA140,Huffman table data 140" line.long 0x3A0 "JPEG_DHTMEM36,JPEG DHT memory" hexmask.long.byte 0x3A0 24.--31. 1. "DATA147,Huffman table data 147" hexmask.long.byte 0x3A0 16.--23. 1. "DATA146,Huffman table data 146" newline hexmask.long.byte 0x3A0 8.--15. 1. "DATA145,Huffman table data 145" hexmask.long.byte 0x3A0 0.--7. 1. "DATA144,Huffman table data 144" line.long 0x3A4 "JPEG_DHTMEM37,JPEG DHT memory" hexmask.long.byte 0x3A4 24.--31. 1. "DATA151,Huffman table data 151" hexmask.long.byte 0x3A4 16.--23. 1. "DATA150,Huffman table data 150" newline hexmask.long.byte 0x3A4 8.--15. 1. "DATA149,Huffman table data 149" hexmask.long.byte 0x3A4 0.--7. 1. "DATA148,Huffman table data 148" line.long 0x3A8 "JPEG_DHTMEM38,JPEG DHT memory" hexmask.long.byte 0x3A8 24.--31. 1. "DATA155,Huffman table data 155" hexmask.long.byte 0x3A8 16.--23. 1. "DATA154,Huffman table data 154" newline hexmask.long.byte 0x3A8 8.--15. 1. "DATA153,Huffman table data 153" hexmask.long.byte 0x3A8 0.--7. 1. "DATA152,Huffman table data 152" line.long 0x3AC "JPEG_DHTMEM39,JPEG DHT memory" hexmask.long.byte 0x3AC 24.--31. 1. "DATA159,Huffman table data 159" hexmask.long.byte 0x3AC 16.--23. 1. "DATA158,Huffman table data 158" newline hexmask.long.byte 0x3AC 8.--15. 1. "DATA157,Huffman table data 157" hexmask.long.byte 0x3AC 0.--7. 1. "DATA156,Huffman table data 156" line.long 0x3B0 "JPEG_DHTMEM40,JPEG DHT memory" hexmask.long.byte 0x3B0 24.--31. 1. "DATA163,Huffman table data 163" hexmask.long.byte 0x3B0 16.--23. 1. "DATA162,Huffman table data 162" newline hexmask.long.byte 0x3B0 8.--15. 1. "DATA161,Huffman table data 161" hexmask.long.byte 0x3B0 0.--7. 1. "DATA160,Huffman table data 160" line.long 0x3B4 "JPEG_DHTMEM41,JPEG DHT memory" hexmask.long.byte 0x3B4 24.--31. 1. "DATA167,Huffman table data 167" hexmask.long.byte 0x3B4 16.--23. 1. "DATA166,Huffman table data 166" newline hexmask.long.byte 0x3B4 8.--15. 1. "DATA165,Huffman table data 165" hexmask.long.byte 0x3B4 0.--7. 1. "DATA164,Huffman table data 164" line.long 0x3B8 "JPEG_DHTMEM42,JPEG DHT memory" hexmask.long.byte 0x3B8 24.--31. 1. "DATA171,Huffman table data 171" hexmask.long.byte 0x3B8 16.--23. 1. "DATA170,Huffman table data 170" newline hexmask.long.byte 0x3B8 8.--15. 1. "DATA169,Huffman table data 169" hexmask.long.byte 0x3B8 0.--7. 1. "DATA168,Huffman table data 168" line.long 0x3BC "JPEG_DHTMEM43,JPEG DHT memory" hexmask.long.byte 0x3BC 24.--31. 1. "DATA175,Huffman table data 175" hexmask.long.byte 0x3BC 16.--23. 1. "DATA174,Huffman table data 174" newline hexmask.long.byte 0x3BC 8.--15. 1. "DATA173,Huffman table data 173" hexmask.long.byte 0x3BC 0.--7. 1. "DATA172,Huffman table data 172" line.long 0x3C0 "JPEG_DHTMEM44,JPEG DHT memory" hexmask.long.byte 0x3C0 24.--31. 1. "DATA179,Huffman table data 179" hexmask.long.byte 0x3C0 16.--23. 1. "DATA178,Huffman table data 178" newline hexmask.long.byte 0x3C0 8.--15. 1. "DATA177,Huffman table data 177" hexmask.long.byte 0x3C0 0.--7. 1. "DATA176,Huffman table data 176" line.long 0x3C4 "JPEG_DHTMEM45,JPEG DHT memory" hexmask.long.byte 0x3C4 24.--31. 1. "DATA183,Huffman table data 183" hexmask.long.byte 0x3C4 16.--23. 1. "DATA182,Huffman table data 182" newline hexmask.long.byte 0x3C4 8.--15. 1. "DATA181,Huffman table data 181" hexmask.long.byte 0x3C4 0.--7. 1. "DATA180,Huffman table data 180" line.long 0x3C8 "JPEG_DHTMEM46,JPEG DHT memory" hexmask.long.byte 0x3C8 24.--31. 1. "DATA187,Huffman table data 187" hexmask.long.byte 0x3C8 16.--23. 1. "DATA186,Huffman table data 186" newline hexmask.long.byte 0x3C8 8.--15. 1. "DATA185,Huffman table data 185" hexmask.long.byte 0x3C8 0.--7. 1. "DATA184,Huffman table data 184" line.long 0x3CC "JPEG_DHTMEM47,JPEG DHT memory" hexmask.long.byte 0x3CC 24.--31. 1. "DATA191,Huffman table data 191" hexmask.long.byte 0x3CC 16.--23. 1. "DATA190,Huffman table data 190" newline hexmask.long.byte 0x3CC 8.--15. 1. "DATA189,Huffman table data 189" hexmask.long.byte 0x3CC 0.--7. 1. "DATA188,Huffman table data 188" line.long 0x3D0 "JPEG_DHTMEM48,JPEG DHT memory" hexmask.long.byte 0x3D0 24.--31. 1. "DATA195,Huffman table data 195" hexmask.long.byte 0x3D0 16.--23. 1. "DATA194,Huffman table data 194" newline hexmask.long.byte 0x3D0 8.--15. 1. "DATA193,Huffman table data 193" hexmask.long.byte 0x3D0 0.--7. 1. "DATA192,Huffman table data 192" line.long 0x3D4 "JPEG_DHTMEM49,JPEG DHT memory" hexmask.long.byte 0x3D4 24.--31. 1. "DATA199,Huffman table data 199" hexmask.long.byte 0x3D4 16.--23. 1. "DATA198,Huffman table data 198" newline hexmask.long.byte 0x3D4 8.--15. 1. "DATA197,Huffman table data 197" hexmask.long.byte 0x3D4 0.--7. 1. "DATA196,Huffman table data 196" line.long 0x3D8 "JPEG_DHTMEM50,JPEG DHT memory" hexmask.long.byte 0x3D8 24.--31. 1. "DATA203,Huffman table data 203" hexmask.long.byte 0x3D8 16.--23. 1. "DATA202,Huffman table data 202" newline hexmask.long.byte 0x3D8 8.--15. 1. "DATA201,Huffman table data 201" hexmask.long.byte 0x3D8 0.--7. 1. "DATA200,Huffman table data 200" line.long 0x3DC "JPEG_DHTMEM51,JPEG DHT memory" hexmask.long.byte 0x3DC 24.--31. 1. "DATA207,Huffman table data 207" hexmask.long.byte 0x3DC 16.--23. 1. "DATA206,Huffman table data 206" newline hexmask.long.byte 0x3DC 8.--15. 1. "DATA205,Huffman table data 205" hexmask.long.byte 0x3DC 0.--7. 1. "DATA204,Huffman table data 204" line.long 0x3E0 "JPEG_DHTMEM52,JPEG DHT memory" hexmask.long.byte 0x3E0 24.--31. 1. "DATA211,Huffman table data 211" hexmask.long.byte 0x3E0 16.--23. 1. "DATA210,Huffman table data 210" newline hexmask.long.byte 0x3E0 8.--15. 1. "DATA209,Huffman table data 209" hexmask.long.byte 0x3E0 0.--7. 1. "DATA208,Huffman table data 208" line.long 0x3E4 "JPEG_DHTMEM53,JPEG DHT memory" hexmask.long.byte 0x3E4 24.--31. 1. "DATA215,Huffman table data 215" hexmask.long.byte 0x3E4 16.--23. 1. "DATA214,Huffman table data 214" newline hexmask.long.byte 0x3E4 8.--15. 1. "DATA213,Huffman table data 213" hexmask.long.byte 0x3E4 0.--7. 1. "DATA212,Huffman table data 212" line.long 0x3E8 "JPEG_DHTMEM54,JPEG DHT memory" hexmask.long.byte 0x3E8 24.--31. 1. "DATA219,Huffman table data 219" hexmask.long.byte 0x3E8 16.--23. 1. "DATA218,Huffman table data 218" newline hexmask.long.byte 0x3E8 8.--15. 1. "DATA217,Huffman table data 217" hexmask.long.byte 0x3E8 0.--7. 1. "DATA216,Huffman table data 216" line.long 0x3EC "JPEG_DHTMEM55,JPEG DHT memory" hexmask.long.byte 0x3EC 24.--31. 1. "DATA223,Huffman table data 223" hexmask.long.byte 0x3EC 16.--23. 1. "DATA222,Huffman table data 222" newline hexmask.long.byte 0x3EC 8.--15. 1. "DATA221,Huffman table data 221" hexmask.long.byte 0x3EC 0.--7. 1. "DATA220,Huffman table data 220" line.long 0x3F0 "JPEG_DHTMEM56,JPEG DHT memory" hexmask.long.byte 0x3F0 24.--31. 1. "DATA227,Huffman table data 227" hexmask.long.byte 0x3F0 16.--23. 1. "DATA226,Huffman table data 226" newline hexmask.long.byte 0x3F0 8.--15. 1. "DATA225,Huffman table data 225" hexmask.long.byte 0x3F0 0.--7. 1. "DATA224,Huffman table data 224" line.long 0x3F4 "JPEG_DHTMEM57,JPEG DHT memory" hexmask.long.byte 0x3F4 24.--31. 1. "DATA231,Huffman table data 231" hexmask.long.byte 0x3F4 16.--23. 1. "DATA230,Huffman table data 230" newline hexmask.long.byte 0x3F4 8.--15. 1. "DATA229,Huffman table data 229" hexmask.long.byte 0x3F4 0.--7. 1. "DATA228,Huffman table data 228" line.long 0x3F8 "JPEG_DHTMEM58,JPEG DHT memory" hexmask.long.byte 0x3F8 24.--31. 1. "DATA235,Huffman table data 235" hexmask.long.byte 0x3F8 16.--23. 1. "DATA234,Huffman table data 234" newline hexmask.long.byte 0x3F8 8.--15. 1. "DATA233,Huffman table data 233" hexmask.long.byte 0x3F8 0.--7. 1. "DATA232,Huffman table data 232" line.long 0x3FC "JPEG_DHTMEM59,JPEG DHT memory" hexmask.long.byte 0x3FC 24.--31. 1. "DATA239,Huffman table data 239" hexmask.long.byte 0x3FC 16.--23. 1. "DATA238,Huffman table data 238" newline hexmask.long.byte 0x3FC 8.--15. 1. "DATA237,Huffman table data 237" hexmask.long.byte 0x3FC 0.--7. 1. "DATA236,Huffman table data 236" line.long 0x400 "JPEG_DHTMEM60,JPEG DHT memory" hexmask.long.byte 0x400 24.--31. 1. "DATA243,Huffman table data 243" hexmask.long.byte 0x400 16.--23. 1. "DATA242,Huffman table data 242" newline hexmask.long.byte 0x400 8.--15. 1. "DATA241,Huffman table data 241" hexmask.long.byte 0x400 0.--7. 1. "DATA240,Huffman table data 240" line.long 0x404 "JPEG_DHTMEM61,JPEG DHT memory" hexmask.long.byte 0x404 24.--31. 1. "DATA247,Huffman table data 247" hexmask.long.byte 0x404 16.--23. 1. "DATA246,Huffman table data 246" newline hexmask.long.byte 0x404 8.--15. 1. "DATA245,Huffman table data 245" hexmask.long.byte 0x404 0.--7. 1. "DATA244,Huffman table data 244" line.long 0x408 "JPEG_DHTMEM62,JPEG DHT memory" hexmask.long.byte 0x408 24.--31. 1. "DATA251,Huffman table data 251" hexmask.long.byte 0x408 16.--23. 1. "DATA250,Huffman table data 250" newline hexmask.long.byte 0x408 8.--15. 1. "DATA249,Huffman table data 249" hexmask.long.byte 0x408 0.--7. 1. "DATA248,Huffman table data 248" line.long 0x40C "JPEG_DHTMEM63,JPEG DHT memory" hexmask.long.byte 0x40C 24.--31. 1. "DATA255,Huffman table data 255" hexmask.long.byte 0x40C 16.--23. 1. "DATA254,Huffman table data 254" newline hexmask.long.byte 0x40C 8.--15. 1. "DATA253,Huffman table data 253" hexmask.long.byte 0x40C 0.--7. 1. "DATA252,Huffman table data 252" line.long 0x410 "JPEG_DHTMEM64,JPEG DHT memory" hexmask.long.byte 0x410 24.--31. 1. "DATA259,Huffman table data 259" hexmask.long.byte 0x410 16.--23. 1. "DATA258,Huffman table data 258" newline hexmask.long.byte 0x410 8.--15. 1. "DATA257,Huffman table data 257" hexmask.long.byte 0x410 0.--7. 1. "DATA256,Huffman table data 256" line.long 0x414 "JPEG_DHTMEM65,JPEG DHT memory" hexmask.long.byte 0x414 24.--31. 1. "DATA263,Huffman table data 263" hexmask.long.byte 0x414 16.--23. 1. "DATA262,Huffman table data 262" newline hexmask.long.byte 0x414 8.--15. 1. "DATA261,Huffman table data 261" hexmask.long.byte 0x414 0.--7. 1. "DATA260,Huffman table data 260" line.long 0x418 "JPEG_DHTMEM66,JPEG DHT memory" hexmask.long.byte 0x418 24.--31. 1. "DATA267,Huffman table data 267" hexmask.long.byte 0x418 16.--23. 1. "DATA266,Huffman table data 266" newline hexmask.long.byte 0x418 8.--15. 1. "DATA265,Huffman table data 265" hexmask.long.byte 0x418 0.--7. 1. "DATA264,Huffman table data 264" line.long 0x41C "JPEG_DHTMEM67,JPEG DHT memory" hexmask.long.byte 0x41C 24.--31. 1. "DATA271,Huffman table data 271" hexmask.long.byte 0x41C 16.--23. 1. "DATA270,Huffman table data 270" newline hexmask.long.byte 0x41C 8.--15. 1. "DATA269,Huffman table data 269" hexmask.long.byte 0x41C 0.--7. 1. "DATA268,Huffman table data 268" line.long 0x420 "JPEG_DHTMEM68,JPEG DHT memory" hexmask.long.byte 0x420 24.--31. 1. "DATA275,Huffman table data 275" hexmask.long.byte 0x420 16.--23. 1. "DATA274,Huffman table data 274" newline hexmask.long.byte 0x420 8.--15. 1. "DATA273,Huffman table data 273" hexmask.long.byte 0x420 0.--7. 1. "DATA272,Huffman table data 272" line.long 0x424 "JPEG_DHTMEM69,JPEG DHT memory" hexmask.long.byte 0x424 24.--31. 1. "DATA279,Huffman table data 279" hexmask.long.byte 0x424 16.--23. 1. "DATA278,Huffman table data 278" newline hexmask.long.byte 0x424 8.--15. 1. "DATA277,Huffman table data 277" hexmask.long.byte 0x424 0.--7. 1. "DATA276,Huffman table data 276" line.long 0x428 "JPEG_DHTMEM70,JPEG DHT memory" hexmask.long.byte 0x428 24.--31. 1. "DATA283,Huffman table data 283" hexmask.long.byte 0x428 16.--23. 1. "DATA282,Huffman table data 282" newline hexmask.long.byte 0x428 8.--15. 1. "DATA281,Huffman table data 281" hexmask.long.byte 0x428 0.--7. 1. "DATA280,Huffman table data 280" line.long 0x42C "JPEG_DHTMEM71,JPEG DHT memory" hexmask.long.byte 0x42C 24.--31. 1. "DATA287,Huffman table data 287" hexmask.long.byte 0x42C 16.--23. 1. "DATA286,Huffman table data 286" newline hexmask.long.byte 0x42C 8.--15. 1. "DATA285,Huffman table data 285" hexmask.long.byte 0x42C 0.--7. 1. "DATA284,Huffman table data 284" line.long 0x430 "JPEG_DHTMEM72,JPEG DHT memory" hexmask.long.byte 0x430 24.--31. 1. "DATA291,Huffman table data 291" hexmask.long.byte 0x430 16.--23. 1. "DATA290,Huffman table data 290" newline hexmask.long.byte 0x430 8.--15. 1. "DATA289,Huffman table data 289" hexmask.long.byte 0x430 0.--7. 1. "DATA288,Huffman table data 288" line.long 0x434 "JPEG_DHTMEM73,JPEG DHT memory" hexmask.long.byte 0x434 24.--31. 1. "DATA295,Huffman table data 295" hexmask.long.byte 0x434 16.--23. 1. "DATA294,Huffman table data 294" newline hexmask.long.byte 0x434 8.--15. 1. "DATA293,Huffman table data 293" hexmask.long.byte 0x434 0.--7. 1. "DATA292,Huffman table data 292" line.long 0x438 "JPEG_DHTMEM74,JPEG DHT memory" hexmask.long.byte 0x438 24.--31. 1. "DATA299,Huffman table data 299" hexmask.long.byte 0x438 16.--23. 1. "DATA298,Huffman table data 298" newline hexmask.long.byte 0x438 8.--15. 1. "DATA297,Huffman table data 297" hexmask.long.byte 0x438 0.--7. 1. "DATA296,Huffman table data 296" line.long 0x43C "JPEG_DHTMEM75,JPEG DHT memory" hexmask.long.byte 0x43C 24.--31. 1. "DATA303,Huffman table data 303" hexmask.long.byte 0x43C 16.--23. 1. "DATA302,Huffman table data 302" newline hexmask.long.byte 0x43C 8.--15. 1. "DATA301,Huffman table data 301" hexmask.long.byte 0x43C 0.--7. 1. "DATA300,Huffman table data 300" line.long 0x440 "JPEG_DHTMEM76,JPEG DHT memory" hexmask.long.byte 0x440 24.--31. 1. "DATA307,Huffman table data 307" hexmask.long.byte 0x440 16.--23. 1. "DATA306,Huffman table data 306" newline hexmask.long.byte 0x440 8.--15. 1. "DATA305,Huffman table data 305" hexmask.long.byte 0x440 0.--7. 1. "DATA304,Huffman table data 304" line.long 0x444 "JPEG_DHTMEM77,JPEG DHT memory" hexmask.long.byte 0x444 24.--31. 1. "DATA311,Huffman table data 311" hexmask.long.byte 0x444 16.--23. 1. "DATA310,Huffman table data 310" newline hexmask.long.byte 0x444 8.--15. 1. "DATA309,Huffman table data 309" hexmask.long.byte 0x444 0.--7. 1. "DATA308,Huffman table data 308" line.long 0x448 "JPEG_DHTMEM78,JPEG DHT memory" hexmask.long.byte 0x448 24.--31. 1. "DATA315,Huffman table data 315" hexmask.long.byte 0x448 16.--23. 1. "DATA314,Huffman table data 314" newline hexmask.long.byte 0x448 8.--15. 1. "DATA313,Huffman table data 313" hexmask.long.byte 0x448 0.--7. 1. "DATA312,Huffman table data 312" line.long 0x44C "JPEG_DHTMEM79,JPEG DHT memory" hexmask.long.byte 0x44C 24.--31. 1. "DATA319,Huffman table data 319" hexmask.long.byte 0x44C 16.--23. 1. "DATA318,Huffman table data 318" newline hexmask.long.byte 0x44C 8.--15. 1. "DATA317,Huffman table data 317" hexmask.long.byte 0x44C 0.--7. 1. "DATA316,Huffman table data 316" line.long 0x450 "JPEG_DHTMEM80,JPEG DHT memory" hexmask.long.byte 0x450 24.--31. 1. "DATA323,Huffman table data 323" hexmask.long.byte 0x450 16.--23. 1. "DATA322,Huffman table data 322" newline hexmask.long.byte 0x450 8.--15. 1. "DATA321,Huffman table data 321" hexmask.long.byte 0x450 0.--7. 1. "DATA320,Huffman table data 320" line.long 0x454 "JPEG_DHTMEM81,JPEG DHT memory" hexmask.long.byte 0x454 24.--31. 1. "DATA327,Huffman table data 327" hexmask.long.byte 0x454 16.--23. 1. "DATA326,Huffman table data 326" newline hexmask.long.byte 0x454 8.--15. 1. "DATA325,Huffman table data 325" hexmask.long.byte 0x454 0.--7. 1. "DATA324,Huffman table data 324" line.long 0x458 "JPEG_DHTMEM82,JPEG DHT memory" hexmask.long.byte 0x458 24.--31. 1. "DATA331,Huffman table data 331" hexmask.long.byte 0x458 16.--23. 1. "DATA330,Huffman table data 330" newline hexmask.long.byte 0x458 8.--15. 1. "DATA329,Huffman table data 329" hexmask.long.byte 0x458 0.--7. 1. "DATA328,Huffman table data 328" line.long 0x45C "JPEG_DHTMEM83,JPEG DHT memory" hexmask.long.byte 0x45C 24.--31. 1. "DATA335,Huffman table data 335" hexmask.long.byte 0x45C 16.--23. 1. "DATA334,Huffman table data 334" newline hexmask.long.byte 0x45C 8.--15. 1. "DATA333,Huffman table data 333" hexmask.long.byte 0x45C 0.--7. 1. "DATA332,Huffman table data 332" line.long 0x460 "JPEG_DHTMEM84,JPEG DHT memory" hexmask.long.byte 0x460 24.--31. 1. "DATA339,Huffman table data 339" hexmask.long.byte 0x460 16.--23. 1. "DATA338,Huffman table data 338" newline hexmask.long.byte 0x460 8.--15. 1. "DATA337,Huffman table data 337" hexmask.long.byte 0x460 0.--7. 1. "DATA336,Huffman table data 336" line.long 0x464 "JPEG_DHTMEM85,JPEG DHT memory" hexmask.long.byte 0x464 24.--31. 1. "DATA343,Huffman table data 343" hexmask.long.byte 0x464 16.--23. 1. "DATA342,Huffman table data 342" newline hexmask.long.byte 0x464 8.--15. 1. "DATA341,Huffman table data 341" hexmask.long.byte 0x464 0.--7. 1. "DATA340,Huffman table data 340" line.long 0x468 "JPEG_DHTMEM86,JPEG DHT memory" hexmask.long.byte 0x468 24.--31. 1. "DATA347,Huffman table data 347" hexmask.long.byte 0x468 16.--23. 1. "DATA346,Huffman table data 346" newline hexmask.long.byte 0x468 8.--15. 1. "DATA345,Huffman table data 345" hexmask.long.byte 0x468 0.--7. 1. "DATA344,Huffman table data 344" line.long 0x46C "JPEG_DHTMEM87,JPEG DHT memory" hexmask.long.byte 0x46C 24.--31. 1. "DATA351,Huffman table data 351" hexmask.long.byte 0x46C 16.--23. 1. "DATA350,Huffman table data 350" newline hexmask.long.byte 0x46C 8.--15. 1. "DATA349,Huffman table data 349" hexmask.long.byte 0x46C 0.--7. 1. "DATA348,Huffman table data 348" line.long 0x470 "JPEG_DHTMEM88,JPEG DHT memory" hexmask.long.byte 0x470 24.--31. 1. "DATA355,Huffman table data 355" hexmask.long.byte 0x470 16.--23. 1. "DATA354,Huffman table data 354" newline hexmask.long.byte 0x470 8.--15. 1. "DATA353,Huffman table data 353" hexmask.long.byte 0x470 0.--7. 1. "DATA352,Huffman table data 352" line.long 0x474 "JPEG_DHTMEM89,JPEG DHT memory" hexmask.long.byte 0x474 24.--31. 1. "DATA359,Huffman table data 359" hexmask.long.byte 0x474 16.--23. 1. "DATA358,Huffman table data 358" newline hexmask.long.byte 0x474 8.--15. 1. "DATA357,Huffman table data 357" hexmask.long.byte 0x474 0.--7. 1. "DATA356,Huffman table data 356" line.long 0x478 "JPEG_DHTMEM90,JPEG DHT memory" hexmask.long.byte 0x478 24.--31. 1. "DATA363,Huffman table data 363" hexmask.long.byte 0x478 16.--23. 1. "DATA362,Huffman table data 362" newline hexmask.long.byte 0x478 8.--15. 1. "DATA361,Huffman table data 361" hexmask.long.byte 0x478 0.--7. 1. "DATA360,Huffman table data 360" line.long 0x47C "JPEG_DHTMEM91,JPEG DHT memory" hexmask.long.byte 0x47C 24.--31. 1. "DATA367,Huffman table data 367" hexmask.long.byte 0x47C 16.--23. 1. "DATA366,Huffman table data 366" newline hexmask.long.byte 0x47C 8.--15. 1. "DATA365,Huffman table data 365" hexmask.long.byte 0x47C 0.--7. 1. "DATA364,Huffman table data 364" line.long 0x480 "JPEG_DHTMEM92,JPEG DHT memory" hexmask.long.byte 0x480 24.--31. 1. "DATA371,Huffman table data 371" hexmask.long.byte 0x480 16.--23. 1. "DATA370,Huffman table data 370" newline hexmask.long.byte 0x480 8.--15. 1. "DATA369,Huffman table data 369" hexmask.long.byte 0x480 0.--7. 1. "DATA368,Huffman table data 368" line.long 0x484 "JPEG_DHTMEM93,JPEG DHT memory" hexmask.long.byte 0x484 24.--31. 1. "DATA375,Huffman table data 375" hexmask.long.byte 0x484 16.--23. 1. "DATA374,Huffman table data 374" newline hexmask.long.byte 0x484 8.--15. 1. "DATA373,Huffman table data 373" hexmask.long.byte 0x484 0.--7. 1. "DATA372,Huffman table data 372" line.long 0x488 "JPEG_DHTMEM94,JPEG DHT memory" hexmask.long.byte 0x488 24.--31. 1. "DATA379,Huffman table data 379" hexmask.long.byte 0x488 16.--23. 1. "DATA378,Huffman table data 378" newline hexmask.long.byte 0x488 8.--15. 1. "DATA377,Huffman table data 377" hexmask.long.byte 0x488 0.--7. 1. "DATA376,Huffman table data 376" line.long 0x48C "JPEG_DHTMEM95,JPEG DHT memory" hexmask.long.byte 0x48C 24.--31. 1. "DATA383,Huffman table data 383" hexmask.long.byte 0x48C 16.--23. 1. "DATA382,Huffman table data 382" newline hexmask.long.byte 0x48C 8.--15. 1. "DATA381,Huffman table data 381" hexmask.long.byte 0x48C 0.--7. 1. "DATA380,Huffman table data 380" line.long 0x490 "JPEG_DHTMEM96,JPEG DHT memory" hexmask.long.byte 0x490 24.--31. 1. "DATA387,Huffman table data 387" hexmask.long.byte 0x490 16.--23. 1. "DATA386,Huffman table data 386" newline hexmask.long.byte 0x490 8.--15. 1. "DATA385,Huffman table data 385" hexmask.long.byte 0x490 0.--7. 1. "DATA384,Huffman table data 384" line.long 0x494 "JPEG_DHTMEM97,JPEG DHT memory" hexmask.long.byte 0x494 24.--31. 1. "DATA391,Huffman table data 391" hexmask.long.byte 0x494 16.--23. 1. "DATA390,Huffman table data 390" newline hexmask.long.byte 0x494 8.--15. 1. "DATA389,Huffman table data 389" hexmask.long.byte 0x494 0.--7. 1. "DATA388,Huffman table data 388" line.long 0x498 "JPEG_DHTMEM98,JPEG DHT memory" hexmask.long.byte 0x498 24.--31. 1. "DATA395,Huffman table data 395" hexmask.long.byte 0x498 16.--23. 1. "DATA394,Huffman table data 394" newline hexmask.long.byte 0x498 8.--15. 1. "DATA393,Huffman table data 393" hexmask.long.byte 0x498 0.--7. 1. "DATA392,Huffman table data 392" line.long 0x49C "JPEG_DHTMEM99,JPEG DHT memory" hexmask.long.byte 0x49C 24.--31. 1. "DATA399,Huffman table data 399" hexmask.long.byte 0x49C 16.--23. 1. "DATA398,Huffman table data 398" newline hexmask.long.byte 0x49C 8.--15. 1. "DATA397,Huffman table data 397" hexmask.long.byte 0x49C 0.--7. 1. "DATA396,Huffman table data 396" line.long 0x4A0 "JPEG_DHTMEM100,JPEG DHT memory" hexmask.long.byte 0x4A0 24.--31. 1. "DATA403,Huffman table data 403" hexmask.long.byte 0x4A0 16.--23. 1. "DATA402,Huffman table data 402" newline hexmask.long.byte 0x4A0 8.--15. 1. "DATA401,Huffman table data 401" hexmask.long.byte 0x4A0 0.--7. 1. "DATA400,Huffman table data 400" line.long 0x4A4 "JPEG_DHTMEM101,JPEG DHT memory" hexmask.long.byte 0x4A4 24.--31. 1. "DATA407,Huffman table data 407" hexmask.long.byte 0x4A4 16.--23. 1. "DATA406,Huffman table data 406" newline hexmask.long.byte 0x4A4 8.--15. 1. "DATA405,Huffman table data 405" hexmask.long.byte 0x4A4 0.--7. 1. "DATA404,Huffman table data 404" line.long 0x4A8 "JPEG_DHTMEM102,JPEG DHT memory" hexmask.long.byte 0x4A8 24.--31. 1. "DATA411,Huffman table data 411" hexmask.long.byte 0x4A8 16.--23. 1. "DATA410,Huffman table data 410" newline hexmask.long.byte 0x4A8 8.--15. 1. "DATA409,Huffman table data 409" hexmask.long.byte 0x4A8 0.--7. 1. "DATA408,Huffman table data 408" group.long 0x500++0xDF line.long 0x0 "JPEG_HUFFENC_AC0_0,JPEG Huffman encoder AC0" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_AC0_1,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x8 "JPEG_HUFFENC_AC0_2,JPEG Huffman encoder AC0" hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0xC "JPEG_HUFFENC_AC0_3,JPEG Huffman encoder AC0" hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x10 "JPEG_HUFFENC_AC0_4,JPEG Huffman encoder AC0" hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x14 "JPEG_HUFFENC_AC0_5,JPEG Huffman encoder AC0" hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x18 "JPEG_HUFFENC_AC0_6,JPEG Huffman encoder AC0" hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x1C "JPEG_HUFFENC_AC0_7,JPEG Huffman encoder AC0" hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x20 "JPEG_HUFFENC_AC0_8,JPEG Huffman encoder AC0" hexmask.long.byte 0x20 24.--27. 1. "HLEN17,Huffman length 17" hexmask.long.byte 0x20 16.--23. 1. "HCODE17,Huffman code 17" newline hexmask.long.byte 0x20 8.--11. 1. "HLEN16,Huffman length 16" hexmask.long.byte 0x20 0.--7. 1. "HCODE16,Huffman code 16" line.long 0x24 "JPEG_HUFFENC_AC0_9,JPEG Huffman encoder AC0" hexmask.long.byte 0x24 24.--27. 1. "HLEN19,Huffman length 19" hexmask.long.byte 0x24 16.--23. 1. "HCODE19,Huffman code 19" newline hexmask.long.byte 0x24 8.--11. 1. "HLEN18,Huffman length 18" hexmask.long.byte 0x24 0.--7. 1. "HCODE18,Huffman code 18" line.long 0x28 "JPEG_HUFFENC_AC0_10,JPEG Huffman encoder AC0" hexmask.long.byte 0x28 24.--27. 1. "HLEN21,Huffman length 21" hexmask.long.byte 0x28 16.--23. 1. "HCODE21,Huffman code 21" newline hexmask.long.byte 0x28 8.--11. 1. "HLEN20,Huffman length 20" hexmask.long.byte 0x28 0.--7. 1. "HCODE20,Huffman code 20" line.long 0x2C "JPEG_HUFFENC_AC0_11,JPEG Huffman encoder AC0" hexmask.long.byte 0x2C 24.--27. 1. "HLEN23,Huffman length 23" hexmask.long.byte 0x2C 16.--23. 1. "HCODE23,Huffman code 23" newline hexmask.long.byte 0x2C 8.--11. 1. "HLEN22,Huffman length 22" hexmask.long.byte 0x2C 0.--7. 1. "HCODE22,Huffman code 22" line.long 0x30 "JPEG_HUFFENC_AC0_12,JPEG Huffman encoder AC0" hexmask.long.byte 0x30 24.--27. 1. "HLEN25,Huffman length 25" hexmask.long.byte 0x30 16.--23. 1. "HCODE25,Huffman code 25" newline hexmask.long.byte 0x30 8.--11. 1. "HLEN24,Huffman length 24" hexmask.long.byte 0x30 0.--7. 1. "HCODE24,Huffman code 24" line.long 0x34 "JPEG_HUFFENC_AC0_13,JPEG Huffman encoder AC0" hexmask.long.byte 0x34 24.--27. 1. "HLEN27,Huffman length 27" hexmask.long.byte 0x34 16.--23. 1. "HCODE27,Huffman code 27" newline hexmask.long.byte 0x34 8.--11. 1. "HLEN26,Huffman length 26" hexmask.long.byte 0x34 0.--7. 1. "HCODE26,Huffman code 26" line.long 0x38 "JPEG_HUFFENC_AC0_14,JPEG Huffman encoder AC0" hexmask.long.byte 0x38 24.--27. 1. "HLEN29,Huffman length 29" hexmask.long.byte 0x38 16.--23. 1. "HCODE29,Huffman code 29" newline hexmask.long.byte 0x38 8.--11. 1. "HLEN28,Huffman length 28" hexmask.long.byte 0x38 0.--7. 1. "HCODE28,Huffman code 28" line.long 0x3C "JPEG_HUFFENC_AC0_15,JPEG Huffman encoder AC0" hexmask.long.byte 0x3C 24.--27. 1. "HLEN31,Huffman length 31" hexmask.long.byte 0x3C 16.--23. 1. "HCODE31,Huffman code 31" newline hexmask.long.byte 0x3C 8.--11. 1. "HLEN30,Huffman length 30" hexmask.long.byte 0x3C 0.--7. 1. "HCODE30,Huffman code 30" line.long 0x40 "JPEG_HUFFENC_AC0_16,JPEG Huffman encoder AC0" hexmask.long.byte 0x40 24.--27. 1. "HLEN33,Huffman length 33" hexmask.long.byte 0x40 16.--23. 1. "HCODE33,Huffman code 33" newline hexmask.long.byte 0x40 8.--11. 1. "HLEN32,Huffman length 32" hexmask.long.byte 0x40 0.--7. 1. "HCODE32,Huffman code 32" line.long 0x44 "JPEG_HUFFENC_AC0_17,JPEG Huffman encoder AC0" hexmask.long.byte 0x44 24.--27. 1. "HLEN35,Huffman length 35" hexmask.long.byte 0x44 16.--23. 1. "HCODE35,Huffman code 35" newline hexmask.long.byte 0x44 8.--11. 1. "HLEN34,Huffman length 34" hexmask.long.byte 0x44 0.--7. 1. "HCODE34,Huffman code 34" line.long 0x48 "JPEG_HUFFENC_AC0_18,JPEG Huffman encoder AC0" hexmask.long.byte 0x48 24.--27. 1. "HLEN37,Huffman length 37" hexmask.long.byte 0x48 16.--23. 1. "HCODE37,Huffman code 37" newline hexmask.long.byte 0x48 8.--11. 1. "HLEN36,Huffman length 36" hexmask.long.byte 0x48 0.--7. 1. "HCODE36,Huffman code 36" line.long 0x4C "JPEG_HUFFENC_AC0_19,JPEG Huffman encoder AC0" hexmask.long.byte 0x4C 24.--27. 1. "HLEN39,Huffman length 39" hexmask.long.byte 0x4C 16.--23. 1. "HCODE39,Huffman code 39" newline hexmask.long.byte 0x4C 8.--11. 1. "HLEN38,Huffman length 38" hexmask.long.byte 0x4C 0.--7. 1. "HCODE38,Huffman code 38" line.long 0x50 "JPEG_HUFFENC_AC0_20,JPEG Huffman encoder AC0" hexmask.long.byte 0x50 24.--27. 1. "HLEN41,Huffman length 41" hexmask.long.byte 0x50 16.--23. 1. "HCODE41,Huffman code 41" newline hexmask.long.byte 0x50 8.--11. 1. "HLEN40,Huffman length 40" hexmask.long.byte 0x50 0.--7. 1. "HCODE40,Huffman code 40" line.long 0x54 "JPEG_HUFFENC_AC0_21,JPEG Huffman encoder AC0" hexmask.long.byte 0x54 24.--27. 1. "HLEN43,Huffman length 43" hexmask.long.byte 0x54 16.--23. 1. "HCODE43,Huffman code 43" newline hexmask.long.byte 0x54 8.--11. 1. "HLEN42,Huffman length 42" hexmask.long.byte 0x54 0.--7. 1. "HCODE42,Huffman code 42" line.long 0x58 "JPEG_HUFFENC_AC0_22,JPEG Huffman encoder AC0" hexmask.long.byte 0x58 24.--27. 1. "HLEN45,Huffman length 45" hexmask.long.byte 0x58 16.--23. 1. "HCODE45,Huffman code 45" newline hexmask.long.byte 0x58 8.--11. 1. "HLEN44,Huffman length 44" hexmask.long.byte 0x58 0.--7. 1. "HCODE44,Huffman code 44" line.long 0x5C "JPEG_HUFFENC_AC0_23,JPEG Huffman encoder AC0" hexmask.long.byte 0x5C 24.--27. 1. "HLEN47,Huffman length 47" hexmask.long.byte 0x5C 16.--23. 1. "HCODE47,Huffman code 47" newline hexmask.long.byte 0x5C 8.--11. 1. "HLEN46,Huffman length 46" hexmask.long.byte 0x5C 0.--7. 1. "HCODE46,Huffman code 46" line.long 0x60 "JPEG_HUFFENC_AC0_24,JPEG Huffman encoder AC0" hexmask.long.byte 0x60 24.--27. 1. "HLEN49,Huffman length 49" hexmask.long.byte 0x60 16.--23. 1. "HCODE49,Huffman code 49" newline hexmask.long.byte 0x60 8.--11. 1. "HLEN48,Huffman length 48" hexmask.long.byte 0x60 0.--7. 1. "HCODE48,Huffman code 48" line.long 0x64 "JPEG_HUFFENC_AC0_25,JPEG Huffman encoder AC0" hexmask.long.byte 0x64 24.--27. 1. "HLEN51,Huffman length 51" hexmask.long.byte 0x64 16.--23. 1. "HCODE51,Huffman code 51" newline hexmask.long.byte 0x64 8.--11. 1. "HLEN50,Huffman length 50" hexmask.long.byte 0x64 0.--7. 1. "HCODE50,Huffman code 50" line.long 0x68 "JPEG_HUFFENC_AC0_26,JPEG Huffman encoder AC0" hexmask.long.byte 0x68 24.--27. 1. "HLEN53,Huffman length 53" hexmask.long.byte 0x68 16.--23. 1. "HCODE53,Huffman code 53" newline hexmask.long.byte 0x68 8.--11. 1. "HLEN52,Huffman length 52" hexmask.long.byte 0x68 0.--7. 1. "HCODE52,Huffman code 52" line.long 0x6C "JPEG_HUFFENC_AC0_27,JPEG Huffman encoder AC0" hexmask.long.byte 0x6C 24.--27. 1. "HLEN55,Huffman length 55" hexmask.long.byte 0x6C 16.--23. 1. "HCODE55,Huffman code 55" newline hexmask.long.byte 0x6C 8.--11. 1. "HLEN54,Huffman length 54" hexmask.long.byte 0x6C 0.--7. 1. "HCODE54,Huffman code 54" line.long 0x70 "JPEG_HUFFENC_AC0_28,JPEG Huffman encoder AC0" hexmask.long.byte 0x70 24.--27. 1. "HLEN57,Huffman length 57" hexmask.long.byte 0x70 16.--23. 1. "HCODE57,Huffman code 57" newline hexmask.long.byte 0x70 8.--11. 1. "HLEN56,Huffman length 56" hexmask.long.byte 0x70 0.--7. 1. "HCODE56,Huffman code 56" line.long 0x74 "JPEG_HUFFENC_AC0_29,JPEG Huffman encoder AC0" hexmask.long.byte 0x74 24.--27. 1. "HLEN59,Huffman length 59" hexmask.long.byte 0x74 16.--23. 1. "HCODE59,Huffman code 59" newline hexmask.long.byte 0x74 8.--11. 1. "HLEN58,Huffman length 58" hexmask.long.byte 0x74 0.--7. 1. "HCODE58,Huffman code 58" line.long 0x78 "JPEG_HUFFENC_AC0_30,JPEG Huffman encoder AC0" hexmask.long.byte 0x78 24.--27. 1. "HLEN61,Huffman length 61" hexmask.long.byte 0x78 16.--23. 1. "HCODE61,Huffman code 61" newline hexmask.long.byte 0x78 8.--11. 1. "HLEN60,Huffman length 60" hexmask.long.byte 0x78 0.--7. 1. "HCODE60,Huffman code 60" line.long 0x7C "JPEG_HUFFENC_AC0_31,JPEG Huffman encoder AC0" hexmask.long.byte 0x7C 24.--27. 1. "HLEN63,Huffman length 63" hexmask.long.byte 0x7C 16.--23. 1. "HCODE63,Huffman code 63" newline hexmask.long.byte 0x7C 8.--11. 1. "HLEN62,Huffman length 62" hexmask.long.byte 0x7C 0.--7. 1. "HCODE62,Huffman code 62" line.long 0x80 "JPEG_HUFFENC_AC0_32,JPEG Huffman encoder AC0" hexmask.long.byte 0x80 24.--27. 1. "HLEN65,Huffman length 65" hexmask.long.byte 0x80 16.--23. 1. "HCODE65,Huffman code 65" newline hexmask.long.byte 0x80 8.--11. 1. "HLEN64,Huffman length 64" hexmask.long.byte 0x80 0.--7. 1. "HCODE64,Huffman code 64" line.long 0x84 "JPEG_HUFFENC_AC0_33,JPEG Huffman encoder AC0" hexmask.long.byte 0x84 24.--27. 1. "HLEN67,Huffman length 67" hexmask.long.byte 0x84 16.--23. 1. "HCODE67,Huffman code 67" newline hexmask.long.byte 0x84 8.--11. 1. "HLEN66,Huffman length 66" hexmask.long.byte 0x84 0.--7. 1. "HCODE66,Huffman code 66" line.long 0x88 "JPEG_HUFFENC_AC0_34,JPEG Huffman encoder AC0" hexmask.long.byte 0x88 24.--27. 1. "HLEN69,Huffman length 69" hexmask.long.byte 0x88 16.--23. 1. "HCODE69,Huffman code 69" newline hexmask.long.byte 0x88 8.--11. 1. "HLEN68,Huffman length 68" hexmask.long.byte 0x88 0.--7. 1. "HCODE68,Huffman code 68" line.long 0x8C "JPEG_HUFFENC_AC0_35,JPEG Huffman encoder AC0" hexmask.long.byte 0x8C 24.--27. 1. "HLEN71,Huffman length 71" hexmask.long.byte 0x8C 16.--23. 1. "HCODE71,Huffman code 71" newline hexmask.long.byte 0x8C 8.--11. 1. "HLEN70,Huffman length 70" hexmask.long.byte 0x8C 0.--7. 1. "HCODE70,Huffman code 70" line.long 0x90 "JPEG_HUFFENC_AC0_36,JPEG Huffman encoder AC0" hexmask.long.byte 0x90 24.--27. 1. "HLEN73,Huffman length 73" hexmask.long.byte 0x90 16.--23. 1. "HCODE73,Huffman code 73" newline hexmask.long.byte 0x90 8.--11. 1. "HLEN72,Huffman length 72" hexmask.long.byte 0x90 0.--7. 1. "HCODE72,Huffman code 72" line.long 0x94 "JPEG_HUFFENC_AC0_37,JPEG Huffman encoder AC0" hexmask.long.byte 0x94 24.--27. 1. "HLEN75,Huffman length 75" hexmask.long.byte 0x94 16.--23. 1. "HCODE75,Huffman code 75" newline hexmask.long.byte 0x94 8.--11. 1. "HLEN74,Huffman length 74" hexmask.long.byte 0x94 0.--7. 1. "HCODE74,Huffman code 74" line.long 0x98 "JPEG_HUFFENC_AC0_38,JPEG Huffman encoder AC0" hexmask.long.byte 0x98 24.--27. 1. "HLEN77,Huffman length 77" hexmask.long.byte 0x98 16.--23. 1. "HCODE77,Huffman code 77" newline hexmask.long.byte 0x98 8.--11. 1. "HLEN76,Huffman length 76" hexmask.long.byte 0x98 0.--7. 1. "HCODE76,Huffman code 76" line.long 0x9C "JPEG_HUFFENC_AC0_39,JPEG Huffman encoder AC0" hexmask.long.byte 0x9C 24.--27. 1. "HLEN79,Huffman length 79" hexmask.long.byte 0x9C 16.--23. 1. "HCODE79,Huffman code 79" newline hexmask.long.byte 0x9C 8.--11. 1. "HLEN78,Huffman length 78" hexmask.long.byte 0x9C 0.--7. 1. "HCODE78,Huffman code 78" line.long 0xA0 "JPEG_HUFFENC_AC0_40,JPEG Huffman encoder AC0" hexmask.long.byte 0xA0 24.--27. 1. "HLEN81,Huffman length 81" hexmask.long.byte 0xA0 16.--23. 1. "HCODE81,Huffman code 81" newline hexmask.long.byte 0xA0 8.--11. 1. "HLEN80,Huffman length 80" hexmask.long.byte 0xA0 0.--7. 1. "HCODE80,Huffman code 80" line.long 0xA4 "JPEG_HUFFENC_AC0_41,JPEG Huffman encoder AC0" hexmask.long.byte 0xA4 24.--27. 1. "HLEN83,Huffman length 83" hexmask.long.byte 0xA4 16.--23. 1. "HCODE83,Huffman code 83" newline hexmask.long.byte 0xA4 8.--11. 1. "HLEN82,Huffman length 82" hexmask.long.byte 0xA4 0.--7. 1. "HCODE82,Huffman code 82" line.long 0xA8 "JPEG_HUFFENC_AC0_42,JPEG Huffman encoder AC0" hexmask.long.byte 0xA8 24.--27. 1. "HLEN85,Huffman length 85" hexmask.long.byte 0xA8 16.--23. 1. "HCODE85,Huffman code 85" newline hexmask.long.byte 0xA8 8.--11. 1. "HLEN84,Huffman length 84" hexmask.long.byte 0xA8 0.--7. 1. "HCODE84,Huffman code 84" line.long 0xAC "JPEG_HUFFENC_AC0_43,JPEG Huffman encoder AC0" hexmask.long.byte 0xAC 24.--27. 1. "HLEN87,Huffman length 87" hexmask.long.byte 0xAC 16.--23. 1. "HCODE87,Huffman code 87" newline hexmask.long.byte 0xAC 8.--11. 1. "HLEN86,Huffman length 86" hexmask.long.byte 0xAC 0.--7. 1. "HCODE86,Huffman code 86" line.long 0xB0 "JPEG_HUFFENC_AC0_44,JPEG Huffman encoder AC0" hexmask.long.byte 0xB0 24.--27. 1. "HLEN89,Huffman length 89" hexmask.long.byte 0xB0 16.--23. 1. "HCODE89,Huffman code 89" newline hexmask.long.byte 0xB0 8.--11. 1. "HLEN88,Huffman length 88" hexmask.long.byte 0xB0 0.--7. 1. "HCODE88,Huffman code 88" line.long 0xB4 "JPEG_HUFFENC_AC0_45,JPEG Huffman encoder AC0" hexmask.long.byte 0xB4 24.--27. 1. "HLEN91,Huffman length 91" hexmask.long.byte 0xB4 16.--23. 1. "HCODE91,Huffman code 91" newline hexmask.long.byte 0xB4 8.--11. 1. "HLEN90,Huffman length 90" hexmask.long.byte 0xB4 0.--7. 1. "HCODE90,Huffman code 90" line.long 0xB8 "JPEG_HUFFENC_AC0_46,JPEG Huffman encoder AC0" hexmask.long.byte 0xB8 24.--27. 1. "HLEN93,Huffman length 93" hexmask.long.byte 0xB8 16.--23. 1. "HCODE93,Huffman code 93" newline hexmask.long.byte 0xB8 8.--11. 1. "HLEN92,Huffman length 92" hexmask.long.byte 0xB8 0.--7. 1. "HCODE92,Huffman code 92" line.long 0xBC "JPEG_HUFFENC_AC0_47,JPEG Huffman encoder AC0" hexmask.long.byte 0xBC 24.--27. 1. "HLEN95,Huffman length 95" hexmask.long.byte 0xBC 16.--23. 1. "HCODE95,Huffman code 95" newline hexmask.long.byte 0xBC 8.--11. 1. "HLEN94,Huffman length 94" hexmask.long.byte 0xBC 0.--7. 1. "HCODE94,Huffman code 94" line.long 0xC0 "JPEG_HUFFENC_AC0_48,JPEG Huffman encoder AC0" hexmask.long.byte 0xC0 24.--27. 1. "HLEN97,Huffman length 97" hexmask.long.byte 0xC0 16.--23. 1. "HCODE97,Huffman code 97" newline hexmask.long.byte 0xC0 8.--11. 1. "HLEN96,Huffman length 96" hexmask.long.byte 0xC0 0.--7. 1. "HCODE96,Huffman code 96" line.long 0xC4 "JPEG_HUFFENC_AC0_49,JPEG Huffman encoder AC0" hexmask.long.byte 0xC4 24.--27. 1. "HLEN99,Huffman length 99" hexmask.long.byte 0xC4 16.--23. 1. "HCODE99,Huffman code 99" newline hexmask.long.byte 0xC4 8.--11. 1. "HLEN98,Huffman length 98" hexmask.long.byte 0xC4 0.--7. 1. "HCODE98,Huffman code 98" line.long 0xC8 "JPEG_HUFFENC_AC0_50,JPEG Huffman encoder AC0" hexmask.long.byte 0xC8 24.--27. 1. "HLEN101,Huffman length 101" hexmask.long.byte 0xC8 16.--23. 1. "HCODE101,Huffman code 101" newline hexmask.long.byte 0xC8 8.--11. 1. "HLEN100,Huffman length 100" hexmask.long.byte 0xC8 0.--7. 1. "HCODE100,Huffman code 100" line.long 0xCC "JPEG_HUFFENC_AC0_51,JPEG Huffman encoder AC0" hexmask.long.byte 0xCC 24.--27. 1. "HLEN103,Huffman length 103" hexmask.long.byte 0xCC 16.--23. 1. "HCODE103,Huffman code 103" newline hexmask.long.byte 0xCC 8.--11. 1. "HLEN102,Huffman length 102" hexmask.long.byte 0xCC 0.--7. 1. "HCODE102,Huffman code 102" line.long 0xD0 "JPEG_HUFFENC_AC0_52,JPEG Huffman encoder AC0" hexmask.long.byte 0xD0 24.--27. 1. "HLEN105,Huffman length 105" hexmask.long.byte 0xD0 16.--23. 1. "HCODE105,Huffman code 105" newline hexmask.long.byte 0xD0 8.--11. 1. "HLEN104,Huffman length 104" hexmask.long.byte 0xD0 0.--7. 1. "HCODE104,Huffman code 104" line.long 0xD4 "JPEG_HUFFENC_AC0_53,JPEG Huffman encoder AC0" hexmask.long.byte 0xD4 24.--27. 1. "HLEN107,Huffman length 107" hexmask.long.byte 0xD4 16.--23. 1. "HCODE107,Huffman code 107" newline hexmask.long.byte 0xD4 8.--11. 1. "HLEN106,Huffman length 106" hexmask.long.byte 0xD4 0.--7. 1. "HCODE106,Huffman code 106" line.long 0xD8 "JPEG_HUFFENC_AC0_54,JPEG Huffman encoder AC0" hexmask.long.byte 0xD8 24.--27. 1. "HLEN109,Huffman length 109" hexmask.long.byte 0xD8 16.--23. 1. "HCODE109,Huffman code 109" newline hexmask.long.byte 0xD8 8.--11. 1. "HLEN108,Huffman length 108" hexmask.long.byte 0xD8 0.--7. 1. "HCODE108,Huffman code 108" line.long 0xDC "JPEG_HUFFENC_AC0_55,JPEG Huffman encoder AC0" hexmask.long.byte 0xDC 24.--27. 1. "HLEN111,Huffman length 111" hexmask.long.byte 0xDC 16.--23. 1. "HCODE111,Huffman code 111" newline hexmask.long.byte 0xDC 8.--11. 1. "HLEN110,Huffman length 110" hexmask.long.byte 0xDC 0.--7. 1. "HCODE110,Huffman code 110" group.long 0x5DC++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_0,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_AC0_56,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN113,Huffman length 113" hexmask.long.byte 0x4 16.--23. 1. "HCODE113,Huffman code 113" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN112,Huffman length 112" hexmask.long.byte 0x4 0.--7. 1. "HCODE112,Huffman code 112" group.long 0x5E0++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_1,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x0 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x0 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x4 "JPEG_HUFFENC_AC0_57,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN115,Huffman length 115" hexmask.long.byte 0x4 16.--23. 1. "HCODE115,Huffman code 115" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN114,Huffman length 114" hexmask.long.byte 0x4 0.--7. 1. "HCODE114,Huffman code 114" group.long 0x5E4++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_2,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x0 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x0 0.--7. 1. "HCODE4,Huffman code 4" line.long 0x4 "JPEG_HUFFENC_AC0_58,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN117,Huffman length 117" hexmask.long.byte 0x4 16.--23. 1. "HCODE117,Huffman code 117" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN116,Huffman length 116" hexmask.long.byte 0x4 0.--7. 1. "HCODE116,Huffman code 116" group.long 0x5E8++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_3,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0x0 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0x0 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x4 "JPEG_HUFFENC_AC0_59,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN119,Huffman length 119" hexmask.long.byte 0x4 16.--23. 1. "HCODE119,Huffman code 119" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN118,Huffman length 118" hexmask.long.byte 0x4 0.--7. 1. "HCODE118,Huffman code 118" group.long 0x5EC++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_4,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x0 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x0 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x4 "JPEG_HUFFENC_AC0_60,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN121,Huffman length 121" hexmask.long.byte 0x4 16.--23. 1. "HCODE121,Huffman code 121" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN120,Huffman length 120" hexmask.long.byte 0x4 0.--7. 1. "HCODE120,Huffman code 120" group.long 0x5F0++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_5,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x0 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x0 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x4 "JPEG_HUFFENC_AC0_61,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN123,Huffman length 123" hexmask.long.byte 0x4 16.--23. 1. "HCODE123,Huffman code 123" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN122,Huffman length 122" hexmask.long.byte 0x4 0.--7. 1. "HCODE122,Huffman code 122" group.long 0x5F4++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_6,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x0 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x0 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x4 "JPEG_HUFFENC_AC0_62,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN125,Huffman length 125" hexmask.long.byte 0x4 16.--23. 1. "HCODE125,Huffman code 125" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN124,Huffman length 124" hexmask.long.byte 0x4 0.--7. 1. "HCODE124,Huffman code 124" group.long 0x5F8++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_7,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x0 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x0 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x4 "JPEG_HUFFENC_AC0_63,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN127,Huffman length 127" hexmask.long.byte 0x4 16.--23. 1. "HCODE127,Huffman code 127" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN126,Huffman length 126" hexmask.long.byte 0x4 0.--7. 1. "HCODE126,Huffman code 126" group.long 0x5FC++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_8,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN17,Huffman length 17" hexmask.long.byte 0x0 16.--23. 1. "HCODE17,Huffman code 17" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN16,Huffman length 16" hexmask.long.byte 0x0 0.--7. 1. "HCODE16,Huffman code 16" line.long 0x4 "JPEG_HUFFENC_AC0_64,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN129,Huffman length 129" hexmask.long.byte 0x4 16.--23. 1. "HCODE129,Huffman code 129" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN128,Huffman length 128" hexmask.long.byte 0x4 0.--7. 1. "HCODE128,Huffman code 128" group.long 0x600++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_9,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN19,Huffman length 19" hexmask.long.byte 0x0 16.--23. 1. "HCODE19,Huffman code 19" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN18,Huffman length 18" hexmask.long.byte 0x0 0.--7. 1. "HCODE18,Huffman code 18" line.long 0x4 "JPEG_HUFFENC_AC0_65,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN131,Huffman length 131" hexmask.long.byte 0x4 16.--23. 1. "HCODE131,Huffman code 131" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN130,Huffman length 130" hexmask.long.byte 0x4 0.--7. 1. "HCODE130,Huffman code 130" group.long 0x604++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_10,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN21,Huffman length 21" hexmask.long.byte 0x0 16.--23. 1. "HCODE21,Huffman code 21" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN20,Huffman length 20" hexmask.long.byte 0x0 0.--7. 1. "HCODE20,Huffman code 20" line.long 0x4 "JPEG_HUFFENC_AC0_66,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN133,Huffman length 133" hexmask.long.byte 0x4 16.--23. 1. "HCODE133,Huffman code 133" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN132,Huffman length 132" hexmask.long.byte 0x4 0.--7. 1. "HCODE132,Huffman code 132" group.long 0x608++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_11,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN23,Huffman length 23" hexmask.long.byte 0x0 16.--23. 1. "HCODE23,Huffman code 23" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN22,Huffman length 22" hexmask.long.byte 0x0 0.--7. 1. "HCODE22,Huffman code 22" line.long 0x4 "JPEG_HUFFENC_AC0_67,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN135,Huffman length 135" hexmask.long.byte 0x4 16.--23. 1. "HCODE135,Huffman code 135" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN134,Huffman length 134" hexmask.long.byte 0x4 0.--7. 1. "HCODE134,Huffman code 134" group.long 0x60C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_12,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN25,Huffman length 25" hexmask.long.byte 0x0 16.--23. 1. "HCODE25,Huffman code 25" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN24,Huffman length 24" hexmask.long.byte 0x0 0.--7. 1. "HCODE24,Huffman code 24" line.long 0x4 "JPEG_HUFFENC_AC0_68,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN137,Huffman length 137" hexmask.long.byte 0x4 16.--23. 1. "HCODE137,Huffman code 137" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN136,Huffman length 136" hexmask.long.byte 0x4 0.--7. 1. "HCODE136,Huffman code 136" group.long 0x610++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_13,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN27,Huffman length 27" hexmask.long.byte 0x0 16.--23. 1. "HCODE27,Huffman code 27" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN26,Huffman length 26" hexmask.long.byte 0x0 0.--7. 1. "HCODE26,Huffman code 26" line.long 0x4 "JPEG_HUFFENC_AC0_69,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN139,Huffman length 139" hexmask.long.byte 0x4 16.--23. 1. "HCODE139,Huffman code 139" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN138,Huffman length 138" hexmask.long.byte 0x4 0.--7. 1. "HCODE138,Huffman code 138" group.long 0x614++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_14,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN29,Huffman length 29" hexmask.long.byte 0x0 16.--23. 1. "HCODE29,Huffman code 29" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN28,Huffman length 28" hexmask.long.byte 0x0 0.--7. 1. "HCODE28,Huffman code 28" line.long 0x4 "JPEG_HUFFENC_AC0_70,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN141,Huffman length 141" hexmask.long.byte 0x4 16.--23. 1. "HCODE141,Huffman code 141" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN140,Huffman length 140" hexmask.long.byte 0x4 0.--7. 1. "HCODE140,Huffman code 140" group.long 0x618++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_15,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN31,Huffman length 31" hexmask.long.byte 0x0 16.--23. 1. "HCODE31,Huffman code 31" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN30,Huffman length 30" hexmask.long.byte 0x0 0.--7. 1. "HCODE30,Huffman code 30" line.long 0x4 "JPEG_HUFFENC_AC0_71,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN143,Huffman length 143" hexmask.long.byte 0x4 16.--23. 1. "HCODE143,Huffman code 143" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN142,Huffman length 142" hexmask.long.byte 0x4 0.--7. 1. "HCODE142,Huffman code 142" group.long 0x61C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_16,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN33,Huffman length 33" hexmask.long.byte 0x0 16.--23. 1. "HCODE33,Huffman code 33" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN32,Huffman length 32" hexmask.long.byte 0x0 0.--7. 1. "HCODE32,Huffman code 32" line.long 0x4 "JPEG_HUFFENC_AC0_72,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN145,Huffman length 145" hexmask.long.byte 0x4 16.--23. 1. "HCODE145,Huffman code 145" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN144,Huffman length 144" hexmask.long.byte 0x4 0.--7. 1. "HCODE144,Huffman code 144" group.long 0x620++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_17,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN35,Huffman length 35" hexmask.long.byte 0x0 16.--23. 1. "HCODE35,Huffman code 35" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN34,Huffman length 34" hexmask.long.byte 0x0 0.--7. 1. "HCODE34,Huffman code 34" line.long 0x4 "JPEG_HUFFENC_AC0_73,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN147,Huffman length 147" hexmask.long.byte 0x4 16.--23. 1. "HCODE147,Huffman code 147" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN146,Huffman length 146" hexmask.long.byte 0x4 0.--7. 1. "HCODE146,Huffman code 146" group.long 0x624++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_18,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN37,Huffman length 37" hexmask.long.byte 0x0 16.--23. 1. "HCODE37,Huffman code 37" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN36,Huffman length 36" hexmask.long.byte 0x0 0.--7. 1. "HCODE36,Huffman code 36" line.long 0x4 "JPEG_HUFFENC_AC0_74,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN149,Huffman length 149" hexmask.long.byte 0x4 16.--23. 1. "HCODE149,Huffman code 149" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN148,Huffman length 148" hexmask.long.byte 0x4 0.--7. 1. "HCODE148,Huffman code 148" group.long 0x628++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_19,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN39,Huffman length 39" hexmask.long.byte 0x0 16.--23. 1. "HCODE39,Huffman code 39" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN38,Huffman length 38" hexmask.long.byte 0x0 0.--7. 1. "HCODE38,Huffman code 38" line.long 0x4 "JPEG_HUFFENC_AC0_75,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN151,Huffman length 151" hexmask.long.byte 0x4 16.--23. 1. "HCODE151,Huffman code 151" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN150,Huffman length 150" hexmask.long.byte 0x4 0.--7. 1. "HCODE150,Huffman code 150" group.long 0x62C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_20,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN41,Huffman length 41" hexmask.long.byte 0x0 16.--23. 1. "HCODE41,Huffman code 41" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN40,Huffman length 40" hexmask.long.byte 0x0 0.--7. 1. "HCODE40,Huffman code 40" line.long 0x4 "JPEG_HUFFENC_AC0_76,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN153,Huffman length 153" hexmask.long.byte 0x4 16.--23. 1. "HCODE153,Huffman code 153" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN152,Huffman length 152" hexmask.long.byte 0x4 0.--7. 1. "HCODE152,Huffman code 152" group.long 0x630++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_21,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN43,Huffman length 43" hexmask.long.byte 0x0 16.--23. 1. "HCODE43,Huffman code 43" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN42,Huffman length 42" hexmask.long.byte 0x0 0.--7. 1. "HCODE42,Huffman code 42" line.long 0x4 "JPEG_HUFFENC_AC0_77,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN155,Huffman length 155" hexmask.long.byte 0x4 16.--23. 1. "HCODE155,Huffman code 155" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN154,Huffman length 154" hexmask.long.byte 0x4 0.--7. 1. "HCODE154,Huffman code 154" group.long 0x634++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_22,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN45,Huffman length 45" hexmask.long.byte 0x0 16.--23. 1. "HCODE45,Huffman code 45" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN44,Huffman length 44" hexmask.long.byte 0x0 0.--7. 1. "HCODE44,Huffman code 44" line.long 0x4 "JPEG_HUFFENC_AC0_78,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN157,Huffman length 157" hexmask.long.byte 0x4 16.--23. 1. "HCODE157,Huffman code 157" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN156,Huffman length 156" hexmask.long.byte 0x4 0.--7. 1. "HCODE156,Huffman code 156" group.long 0x638++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_23,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN47,Huffman length 47" hexmask.long.byte 0x0 16.--23. 1. "HCODE47,Huffman code 47" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN46,Huffman length 46" hexmask.long.byte 0x0 0.--7. 1. "HCODE46,Huffman code 46" line.long 0x4 "JPEG_HUFFENC_AC0_79,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN159,Huffman length 159" hexmask.long.byte 0x4 16.--23. 1. "HCODE159,Huffman code 159" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN158,Huffman length 158" hexmask.long.byte 0x4 0.--7. 1. "HCODE158,Huffman code 158" group.long 0x63C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_24,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN49,Huffman length 49" hexmask.long.byte 0x0 16.--23. 1. "HCODE49,Huffman code 49" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN48,Huffman length 48" hexmask.long.byte 0x0 0.--7. 1. "HCODE48,Huffman code 48" line.long 0x4 "JPEG_HUFFENC_AC0_80,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN161,Huffman length 161" hexmask.long.byte 0x4 16.--23. 1. "HCODE161,Huffman code 161" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN160,Huffman length 160" hexmask.long.byte 0x4 0.--7. 1. "HCODE160,Huffman code 160" group.long 0x640++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_25,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN51,Huffman length 51" hexmask.long.byte 0x0 16.--23. 1. "HCODE51,Huffman code 51" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN50,Huffman length 50" hexmask.long.byte 0x0 0.--7. 1. "HCODE50,Huffman code 50" line.long 0x4 "JPEG_HUFFENC_AC0_81,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN163,Huffman length 163" hexmask.long.byte 0x4 16.--23. 1. "HCODE163,Huffman code 163" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN162,Huffman length 162" hexmask.long.byte 0x4 0.--7. 1. "HCODE162,Huffman code 162" group.long 0x644++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_26,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN53,Huffman length 53" hexmask.long.byte 0x0 16.--23. 1. "HCODE53,Huffman code 53" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN52,Huffman length 52" hexmask.long.byte 0x0 0.--7. 1. "HCODE52,Huffman code 52" line.long 0x4 "JPEG_HUFFENC_AC0_82,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN165,Huffman length 165" hexmask.long.byte 0x4 16.--23. 1. "HCODE165,Huffman code 165" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN164,Huffman length 164" hexmask.long.byte 0x4 0.--7. 1. "HCODE164,Huffman code 164" group.long 0x648++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_27,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN55,Huffman length 55" hexmask.long.byte 0x0 16.--23. 1. "HCODE55,Huffman code 55" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN54,Huffman length 54" hexmask.long.byte 0x0 0.--7. 1. "HCODE54,Huffman code 54" line.long 0x4 "JPEG_HUFFENC_AC0_83,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN167,Huffman length 167" hexmask.long.byte 0x4 16.--23. 1. "HCODE167,Huffman code 167" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN166,Huffman length 166" hexmask.long.byte 0x4 0.--7. 1. "HCODE166,Huffman code 166" group.long 0x64C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_28,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN57,Huffman length 57" hexmask.long.byte 0x0 16.--23. 1. "HCODE57,Huffman code 57" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN56,Huffman length 56" hexmask.long.byte 0x0 0.--7. 1. "HCODE56,Huffman code 56" line.long 0x4 "JPEG_HUFFENC_AC0_84,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN169,Huffman length 169" hexmask.long.byte 0x4 16.--23. 1. "HCODE169,Huffman code 169" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN168,Huffman length 168" hexmask.long.byte 0x4 0.--7. 1. "HCODE168,Huffman code 168" group.long 0x650++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_29,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN59,Huffman length 59" hexmask.long.byte 0x0 16.--23. 1. "HCODE59,Huffman code 59" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN58,Huffman length 58" hexmask.long.byte 0x0 0.--7. 1. "HCODE58,Huffman code 58" line.long 0x4 "JPEG_HUFFENC_AC0_85,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN171,Huffman length 171" hexmask.long.byte 0x4 16.--23. 1. "HCODE171,Huffman code 171" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN170,Huffman length 170" hexmask.long.byte 0x4 0.--7. 1. "HCODE170,Huffman code 170" group.long 0x654++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_30,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN61,Huffman length 61" hexmask.long.byte 0x0 16.--23. 1. "HCODE61,Huffman code 61" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN60,Huffman length 60" hexmask.long.byte 0x0 0.--7. 1. "HCODE60,Huffman code 60" line.long 0x4 "JPEG_HUFFENC_AC0_86,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN173,Huffman length 173" hexmask.long.byte 0x4 16.--23. 1. "HCODE173,Huffman code 173" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN172,Huffman length 172" hexmask.long.byte 0x4 0.--7. 1. "HCODE172,Huffman code 172" group.long 0x658++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_31,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN63,Huffman length 63" hexmask.long.byte 0x0 16.--23. 1. "HCODE63,Huffman code 63" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN62,Huffman length 62" hexmask.long.byte 0x0 0.--7. 1. "HCODE62,Huffman code 62" line.long 0x4 "JPEG_HUFFENC_AC0_87,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN175,Huffman length 175" hexmask.long.byte 0x4 16.--23. 1. "HCODE175,Huffman code 175" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN174,Huffman length 174" hexmask.long.byte 0x4 0.--7. 1. "HCODE174,Huffman code 174" group.long 0x65C++0xDF line.long 0x0 "JPEG_HUFFENC_AC1_32,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN65,Huffman length 65" hexmask.long.byte 0x0 16.--23. 1. "HCODE65,Huffman code 65" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN64,Huffman length 64" hexmask.long.byte 0x0 0.--7. 1. "HCODE64,Huffman code 64" line.long 0x4 "JPEG_HUFFENC_AC1_33,JPEG Huffman encoder AC1" hexmask.long.byte 0x4 24.--27. 1. "HLEN67,Huffman length 67" hexmask.long.byte 0x4 16.--23. 1. "HCODE67,Huffman code 67" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN66,Huffman length 66" hexmask.long.byte 0x4 0.--7. 1. "HCODE66,Huffman code 66" line.long 0x8 "JPEG_HUFFENC_AC1_34,JPEG Huffman encoder AC1" hexmask.long.byte 0x8 24.--27. 1. "HLEN69,Huffman length 69" hexmask.long.byte 0x8 16.--23. 1. "HCODE69,Huffman code 69" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN68,Huffman length 68" hexmask.long.byte 0x8 0.--7. 1. "HCODE68,Huffman code 68" line.long 0xC "JPEG_HUFFENC_AC1_35,JPEG Huffman encoder AC1" hexmask.long.byte 0xC 24.--27. 1. "HLEN71,Huffman length 71" hexmask.long.byte 0xC 16.--23. 1. "HCODE71,Huffman code 71" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN70,Huffman length 70" hexmask.long.byte 0xC 0.--7. 1. "HCODE70,Huffman code 70" line.long 0x10 "JPEG_HUFFENC_AC1_36,JPEG Huffman encoder AC1" hexmask.long.byte 0x10 24.--27. 1. "HLEN73,Huffman length 73" hexmask.long.byte 0x10 16.--23. 1. "HCODE73,Huffman code 73" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN72,Huffman length 72" hexmask.long.byte 0x10 0.--7. 1. "HCODE72,Huffman code 72" line.long 0x14 "JPEG_HUFFENC_AC1_37,JPEG Huffman encoder AC1" hexmask.long.byte 0x14 24.--27. 1. "HLEN75,Huffman length 75" hexmask.long.byte 0x14 16.--23. 1. "HCODE75,Huffman code 75" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN74,Huffman length 74" hexmask.long.byte 0x14 0.--7. 1. "HCODE74,Huffman code 74" line.long 0x18 "JPEG_HUFFENC_AC1_38,JPEG Huffman encoder AC1" hexmask.long.byte 0x18 24.--27. 1. "HLEN77,Huffman length 77" hexmask.long.byte 0x18 16.--23. 1. "HCODE77,Huffman code 77" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN76,Huffman length 76" hexmask.long.byte 0x18 0.--7. 1. "HCODE76,Huffman code 76" line.long 0x1C "JPEG_HUFFENC_AC1_39,JPEG Huffman encoder AC1" hexmask.long.byte 0x1C 24.--27. 1. "HLEN79,Huffman length 79" hexmask.long.byte 0x1C 16.--23. 1. "HCODE79,Huffman code 79" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN78,Huffman length 78" hexmask.long.byte 0x1C 0.--7. 1. "HCODE78,Huffman code 78" line.long 0x20 "JPEG_HUFFENC_AC1_40,JPEG Huffman encoder AC1" hexmask.long.byte 0x20 24.--27. 1. "HLEN81,Huffman length 81" hexmask.long.byte 0x20 16.--23. 1. "HCODE81,Huffman code 81" newline hexmask.long.byte 0x20 8.--11. 1. "HLEN80,Huffman length 80" hexmask.long.byte 0x20 0.--7. 1. "HCODE80,Huffman code 80" line.long 0x24 "JPEG_HUFFENC_AC1_41,JPEG Huffman encoder AC1" hexmask.long.byte 0x24 24.--27. 1. "HLEN83,Huffman length 83" hexmask.long.byte 0x24 16.--23. 1. "HCODE83,Huffman code 83" newline hexmask.long.byte 0x24 8.--11. 1. "HLEN82,Huffman length 82" hexmask.long.byte 0x24 0.--7. 1. "HCODE82,Huffman code 82" line.long 0x28 "JPEG_HUFFENC_AC1_42,JPEG Huffman encoder AC1" hexmask.long.byte 0x28 24.--27. 1. "HLEN85,Huffman length 85" hexmask.long.byte 0x28 16.--23. 1. "HCODE85,Huffman code 85" newline hexmask.long.byte 0x28 8.--11. 1. "HLEN84,Huffman length 84" hexmask.long.byte 0x28 0.--7. 1. "HCODE84,Huffman code 84" line.long 0x2C "JPEG_HUFFENC_AC1_43,JPEG Huffman encoder AC1" hexmask.long.byte 0x2C 24.--27. 1. "HLEN87,Huffman length 87" hexmask.long.byte 0x2C 16.--23. 1. "HCODE87,Huffman code 87" newline hexmask.long.byte 0x2C 8.--11. 1. "HLEN86,Huffman length 86" hexmask.long.byte 0x2C 0.--7. 1. "HCODE86,Huffman code 86" line.long 0x30 "JPEG_HUFFENC_AC1_44,JPEG Huffman encoder AC1" hexmask.long.byte 0x30 24.--27. 1. "HLEN89,Huffman length 89" hexmask.long.byte 0x30 16.--23. 1. "HCODE89,Huffman code 89" newline hexmask.long.byte 0x30 8.--11. 1. "HLEN88,Huffman length 88" hexmask.long.byte 0x30 0.--7. 1. "HCODE88,Huffman code 88" line.long 0x34 "JPEG_HUFFENC_AC1_45,JPEG Huffman encoder AC1" hexmask.long.byte 0x34 24.--27. 1. "HLEN91,Huffman length 91" hexmask.long.byte 0x34 16.--23. 1. "HCODE91,Huffman code 91" newline hexmask.long.byte 0x34 8.--11. 1. "HLEN90,Huffman length 90" hexmask.long.byte 0x34 0.--7. 1. "HCODE90,Huffman code 90" line.long 0x38 "JPEG_HUFFENC_AC1_46,JPEG Huffman encoder AC1" hexmask.long.byte 0x38 24.--27. 1. "HLEN93,Huffman length 93" hexmask.long.byte 0x38 16.--23. 1. "HCODE93,Huffman code 93" newline hexmask.long.byte 0x38 8.--11. 1. "HLEN92,Huffman length 92" hexmask.long.byte 0x38 0.--7. 1. "HCODE92,Huffman code 92" line.long 0x3C "JPEG_HUFFENC_AC1_47,JPEG Huffman encoder AC1" hexmask.long.byte 0x3C 24.--27. 1. "HLEN95,Huffman length 95" hexmask.long.byte 0x3C 16.--23. 1. "HCODE95,Huffman code 95" newline hexmask.long.byte 0x3C 8.--11. 1. "HLEN94,Huffman length 94" hexmask.long.byte 0x3C 0.--7. 1. "HCODE94,Huffman code 94" line.long 0x40 "JPEG_HUFFENC_AC1_48,JPEG Huffman encoder AC1" hexmask.long.byte 0x40 24.--27. 1. "HLEN97,Huffman length 97" hexmask.long.byte 0x40 16.--23. 1. "HCODE97,Huffman code 97" newline hexmask.long.byte 0x40 8.--11. 1. "HLEN96,Huffman length 96" hexmask.long.byte 0x40 0.--7. 1. "HCODE96,Huffman code 96" line.long 0x44 "JPEG_HUFFENC_AC1_49,JPEG Huffman encoder AC1" hexmask.long.byte 0x44 24.--27. 1. "HLEN99,Huffman length 99" hexmask.long.byte 0x44 16.--23. 1. "HCODE99,Huffman code 99" newline hexmask.long.byte 0x44 8.--11. 1. "HLEN98,Huffman length 98" hexmask.long.byte 0x44 0.--7. 1. "HCODE98,Huffman code 98" line.long 0x48 "JPEG_HUFFENC_AC1_50,JPEG Huffman encoder AC1" hexmask.long.byte 0x48 24.--27. 1. "HLEN101,Huffman length 101" hexmask.long.byte 0x48 16.--23. 1. "HCODE101,Huffman code 101" newline hexmask.long.byte 0x48 8.--11. 1. "HLEN100,Huffman length 100" hexmask.long.byte 0x48 0.--7. 1. "HCODE100,Huffman code 100" line.long 0x4C "JPEG_HUFFENC_AC1_51,JPEG Huffman encoder AC1" hexmask.long.byte 0x4C 24.--27. 1. "HLEN103,Huffman length 103" hexmask.long.byte 0x4C 16.--23. 1. "HCODE103,Huffman code 103" newline hexmask.long.byte 0x4C 8.--11. 1. "HLEN102,Huffman length 102" hexmask.long.byte 0x4C 0.--7. 1. "HCODE102,Huffman code 102" line.long 0x50 "JPEG_HUFFENC_AC1_52,JPEG Huffman encoder AC1" hexmask.long.byte 0x50 24.--27. 1. "HLEN105,Huffman length 105" hexmask.long.byte 0x50 16.--23. 1. "HCODE105,Huffman code 105" newline hexmask.long.byte 0x50 8.--11. 1. "HLEN104,Huffman length 104" hexmask.long.byte 0x50 0.--7. 1. "HCODE104,Huffman code 104" line.long 0x54 "JPEG_HUFFENC_AC1_53,JPEG Huffman encoder AC1" hexmask.long.byte 0x54 24.--27. 1. "HLEN107,Huffman length 107" hexmask.long.byte 0x54 16.--23. 1. "HCODE107,Huffman code 107" newline hexmask.long.byte 0x54 8.--11. 1. "HLEN106,Huffman length 106" hexmask.long.byte 0x54 0.--7. 1. "HCODE106,Huffman code 106" line.long 0x58 "JPEG_HUFFENC_AC1_54,JPEG Huffman encoder AC1" hexmask.long.byte 0x58 24.--27. 1. "HLEN109,Huffman length 109" hexmask.long.byte 0x58 16.--23. 1. "HCODE109,Huffman code 109" newline hexmask.long.byte 0x58 8.--11. 1. "HLEN108,Huffman length 108" hexmask.long.byte 0x58 0.--7. 1. "HCODE108,Huffman code 108" line.long 0x5C "JPEG_HUFFENC_AC1_55,JPEG Huffman encoder AC1" hexmask.long.byte 0x5C 24.--27. 1. "HLEN111,Huffman length 111" hexmask.long.byte 0x5C 16.--23. 1. "HCODE111,Huffman code 111" newline hexmask.long.byte 0x5C 8.--11. 1. "HLEN110,Huffman length 110" hexmask.long.byte 0x5C 0.--7. 1. "HCODE110,Huffman code 110" line.long 0x60 "JPEG_HUFFENC_AC1_56,JPEG Huffman encoder AC1" hexmask.long.byte 0x60 24.--27. 1. "HLEN113,Huffman length 113" hexmask.long.byte 0x60 16.--23. 1. "HCODE113,Huffman code 113" newline hexmask.long.byte 0x60 8.--11. 1. "HLEN112,Huffman length 112" hexmask.long.byte 0x60 0.--7. 1. "HCODE112,Huffman code 112" line.long 0x64 "JPEG_HUFFENC_AC1_57,JPEG Huffman encoder AC1" hexmask.long.byte 0x64 24.--27. 1. "HLEN115,Huffman length 115" hexmask.long.byte 0x64 16.--23. 1. "HCODE115,Huffman code 115" newline hexmask.long.byte 0x64 8.--11. 1. "HLEN114,Huffman length 114" hexmask.long.byte 0x64 0.--7. 1. "HCODE114,Huffman code 114" line.long 0x68 "JPEG_HUFFENC_AC1_58,JPEG Huffman encoder AC1" hexmask.long.byte 0x68 24.--27. 1. "HLEN117,Huffman length 117" hexmask.long.byte 0x68 16.--23. 1. "HCODE117,Huffman code 117" newline hexmask.long.byte 0x68 8.--11. 1. "HLEN116,Huffman length 116" hexmask.long.byte 0x68 0.--7. 1. "HCODE116,Huffman code 116" line.long 0x6C "JPEG_HUFFENC_AC1_59,JPEG Huffman encoder AC1" hexmask.long.byte 0x6C 24.--27. 1. "HLEN119,Huffman length 119" hexmask.long.byte 0x6C 16.--23. 1. "HCODE119,Huffman code 119" newline hexmask.long.byte 0x6C 8.--11. 1. "HLEN118,Huffman length 118" hexmask.long.byte 0x6C 0.--7. 1. "HCODE118,Huffman code 118" line.long 0x70 "JPEG_HUFFENC_AC1_60,JPEG Huffman encoder AC1" hexmask.long.byte 0x70 24.--27. 1. "HLEN121,Huffman length 121" hexmask.long.byte 0x70 16.--23. 1. "HCODE121,Huffman code 121" newline hexmask.long.byte 0x70 8.--11. 1. "HLEN120,Huffman length 120" hexmask.long.byte 0x70 0.--7. 1. "HCODE120,Huffman code 120" line.long 0x74 "JPEG_HUFFENC_AC1_61,JPEG Huffman encoder AC1" hexmask.long.byte 0x74 24.--27. 1. "HLEN123,Huffman length 123" hexmask.long.byte 0x74 16.--23. 1. "HCODE123,Huffman code 123" newline hexmask.long.byte 0x74 8.--11. 1. "HLEN122,Huffman length 122" hexmask.long.byte 0x74 0.--7. 1. "HCODE122,Huffman code 122" line.long 0x78 "JPEG_HUFFENC_AC1_62,JPEG Huffman encoder AC1" hexmask.long.byte 0x78 24.--27. 1. "HLEN125,Huffman length 125" hexmask.long.byte 0x78 16.--23. 1. "HCODE125,Huffman code 125" newline hexmask.long.byte 0x78 8.--11. 1. "HLEN124,Huffman length 124" hexmask.long.byte 0x78 0.--7. 1. "HCODE124,Huffman code 124" line.long 0x7C "JPEG_HUFFENC_AC1_63,JPEG Huffman encoder AC1" hexmask.long.byte 0x7C 24.--27. 1. "HLEN127,Huffman length 127" hexmask.long.byte 0x7C 16.--23. 1. "HCODE127,Huffman code 127" newline hexmask.long.byte 0x7C 8.--11. 1. "HLEN126,Huffman length 126" hexmask.long.byte 0x7C 0.--7. 1. "HCODE126,Huffman code 126" line.long 0x80 "JPEG_HUFFENC_AC1_64,JPEG Huffman encoder AC1" hexmask.long.byte 0x80 24.--27. 1. "HLEN129,Huffman length 129" hexmask.long.byte 0x80 16.--23. 1. "HCODE129,Huffman code 129" newline hexmask.long.byte 0x80 8.--11. 1. "HLEN128,Huffman length 128" hexmask.long.byte 0x80 0.--7. 1. "HCODE128,Huffman code 128" line.long 0x84 "JPEG_HUFFENC_AC1_65,JPEG Huffman encoder AC1" hexmask.long.byte 0x84 24.--27. 1. "HLEN131,Huffman length 131" hexmask.long.byte 0x84 16.--23. 1. "HCODE131,Huffman code 131" newline hexmask.long.byte 0x84 8.--11. 1. "HLEN130,Huffman length 130" hexmask.long.byte 0x84 0.--7. 1. "HCODE130,Huffman code 130" line.long 0x88 "JPEG_HUFFENC_AC1_66,JPEG Huffman encoder AC1" hexmask.long.byte 0x88 24.--27. 1. "HLEN133,Huffman length 133" hexmask.long.byte 0x88 16.--23. 1. "HCODE133,Huffman code 133" newline hexmask.long.byte 0x88 8.--11. 1. "HLEN132,Huffman length 132" hexmask.long.byte 0x88 0.--7. 1. "HCODE132,Huffman code 132" line.long 0x8C "JPEG_HUFFENC_AC1_67,JPEG Huffman encoder AC1" hexmask.long.byte 0x8C 24.--27. 1. "HLEN135,Huffman length 135" hexmask.long.byte 0x8C 16.--23. 1. "HCODE135,Huffman code 135" newline hexmask.long.byte 0x8C 8.--11. 1. "HLEN134,Huffman length 134" hexmask.long.byte 0x8C 0.--7. 1. "HCODE134,Huffman code 134" line.long 0x90 "JPEG_HUFFENC_AC1_68,JPEG Huffman encoder AC1" hexmask.long.byte 0x90 24.--27. 1. "HLEN137,Huffman length 137" hexmask.long.byte 0x90 16.--23. 1. "HCODE137,Huffman code 137" newline hexmask.long.byte 0x90 8.--11. 1. "HLEN136,Huffman length 136" hexmask.long.byte 0x90 0.--7. 1. "HCODE136,Huffman code 136" line.long 0x94 "JPEG_HUFFENC_AC1_69,JPEG Huffman encoder AC1" hexmask.long.byte 0x94 24.--27. 1. "HLEN139,Huffman length 139" hexmask.long.byte 0x94 16.--23. 1. "HCODE139,Huffman code 139" newline hexmask.long.byte 0x94 8.--11. 1. "HLEN138,Huffman length 138" hexmask.long.byte 0x94 0.--7. 1. "HCODE138,Huffman code 138" line.long 0x98 "JPEG_HUFFENC_AC1_70,JPEG Huffman encoder AC1" hexmask.long.byte 0x98 24.--27. 1. "HLEN141,Huffman length 141" hexmask.long.byte 0x98 16.--23. 1. "HCODE141,Huffman code 141" newline hexmask.long.byte 0x98 8.--11. 1. "HLEN140,Huffman length 140" hexmask.long.byte 0x98 0.--7. 1. "HCODE140,Huffman code 140" line.long 0x9C "JPEG_HUFFENC_AC1_71,JPEG Huffman encoder AC1" hexmask.long.byte 0x9C 24.--27. 1. "HLEN143,Huffman length 143" hexmask.long.byte 0x9C 16.--23. 1. "HCODE143,Huffman code 143" newline hexmask.long.byte 0x9C 8.--11. 1. "HLEN142,Huffman length 142" hexmask.long.byte 0x9C 0.--7. 1. "HCODE142,Huffman code 142" line.long 0xA0 "JPEG_HUFFENC_AC1_72,JPEG Huffman encoder AC1" hexmask.long.byte 0xA0 24.--27. 1. "HLEN145,Huffman length 145" hexmask.long.byte 0xA0 16.--23. 1. "HCODE145,Huffman code 145" newline hexmask.long.byte 0xA0 8.--11. 1. "HLEN144,Huffman length 144" hexmask.long.byte 0xA0 0.--7. 1. "HCODE144,Huffman code 144" line.long 0xA4 "JPEG_HUFFENC_AC1_73,JPEG Huffman encoder AC1" hexmask.long.byte 0xA4 24.--27. 1. "HLEN147,Huffman length 147" hexmask.long.byte 0xA4 16.--23. 1. "HCODE147,Huffman code 147" newline hexmask.long.byte 0xA4 8.--11. 1. "HLEN146,Huffman length 146" hexmask.long.byte 0xA4 0.--7. 1. "HCODE146,Huffman code 146" line.long 0xA8 "JPEG_HUFFENC_AC1_74,JPEG Huffman encoder AC1" hexmask.long.byte 0xA8 24.--27. 1. "HLEN149,Huffman length 149" hexmask.long.byte 0xA8 16.--23. 1. "HCODE149,Huffman code 149" newline hexmask.long.byte 0xA8 8.--11. 1. "HLEN148,Huffman length 148" hexmask.long.byte 0xA8 0.--7. 1. "HCODE148,Huffman code 148" line.long 0xAC "JPEG_HUFFENC_AC1_75,JPEG Huffman encoder AC1" hexmask.long.byte 0xAC 24.--27. 1. "HLEN151,Huffman length 151" hexmask.long.byte 0xAC 16.--23. 1. "HCODE151,Huffman code 151" newline hexmask.long.byte 0xAC 8.--11. 1. "HLEN150,Huffman length 150" hexmask.long.byte 0xAC 0.--7. 1. "HCODE150,Huffman code 150" line.long 0xB0 "JPEG_HUFFENC_AC1_76,JPEG Huffman encoder AC1" hexmask.long.byte 0xB0 24.--27. 1. "HLEN153,Huffman length 153" hexmask.long.byte 0xB0 16.--23. 1. "HCODE153,Huffman code 153" newline hexmask.long.byte 0xB0 8.--11. 1. "HLEN152,Huffman length 152" hexmask.long.byte 0xB0 0.--7. 1. "HCODE152,Huffman code 152" line.long 0xB4 "JPEG_HUFFENC_AC1_77,JPEG Huffman encoder AC1" hexmask.long.byte 0xB4 24.--27. 1. "HLEN155,Huffman length 155" hexmask.long.byte 0xB4 16.--23. 1. "HCODE155,Huffman code 155" newline hexmask.long.byte 0xB4 8.--11. 1. "HLEN154,Huffman length 154" hexmask.long.byte 0xB4 0.--7. 1. "HCODE154,Huffman code 154" line.long 0xB8 "JPEG_HUFFENC_AC1_78,JPEG Huffman encoder AC1" hexmask.long.byte 0xB8 24.--27. 1. "HLEN157,Huffman length 157" hexmask.long.byte 0xB8 16.--23. 1. "HCODE157,Huffman code 157" newline hexmask.long.byte 0xB8 8.--11. 1. "HLEN156,Huffman length 156" hexmask.long.byte 0xB8 0.--7. 1. "HCODE156,Huffman code 156" line.long 0xBC "JPEG_HUFFENC_AC1_79,JPEG Huffman encoder AC1" hexmask.long.byte 0xBC 24.--27. 1. "HLEN159,Huffman length 159" hexmask.long.byte 0xBC 16.--23. 1. "HCODE159,Huffman code 159" newline hexmask.long.byte 0xBC 8.--11. 1. "HLEN158,Huffman length 158" hexmask.long.byte 0xBC 0.--7. 1. "HCODE158,Huffman code 158" line.long 0xC0 "JPEG_HUFFENC_AC1_80,JPEG Huffman encoder AC1" hexmask.long.byte 0xC0 24.--27. 1. "HLEN161,Huffman length 161" hexmask.long.byte 0xC0 16.--23. 1. "HCODE161,Huffman code 161" newline hexmask.long.byte 0xC0 8.--11. 1. "HLEN160,Huffman length 160" hexmask.long.byte 0xC0 0.--7. 1. "HCODE160,Huffman code 160" line.long 0xC4 "JPEG_HUFFENC_AC1_81,JPEG Huffman encoder AC1" hexmask.long.byte 0xC4 24.--27. 1. "HLEN163,Huffman length 163" hexmask.long.byte 0xC4 16.--23. 1. "HCODE163,Huffman code 163" newline hexmask.long.byte 0xC4 8.--11. 1. "HLEN162,Huffman length 162" hexmask.long.byte 0xC4 0.--7. 1. "HCODE162,Huffman code 162" line.long 0xC8 "JPEG_HUFFENC_AC1_82,JPEG Huffman encoder AC1" hexmask.long.byte 0xC8 24.--27. 1. "HLEN165,Huffman length 165" hexmask.long.byte 0xC8 16.--23. 1. "HCODE165,Huffman code 165" newline hexmask.long.byte 0xC8 8.--11. 1. "HLEN164,Huffman length 164" hexmask.long.byte 0xC8 0.--7. 1. "HCODE164,Huffman code 164" line.long 0xCC "JPEG_HUFFENC_AC1_83,JPEG Huffman encoder AC1" hexmask.long.byte 0xCC 24.--27. 1. "HLEN167,Huffman length 167" hexmask.long.byte 0xCC 16.--23. 1. "HCODE167,Huffman code 167" newline hexmask.long.byte 0xCC 8.--11. 1. "HLEN166,Huffman length 166" hexmask.long.byte 0xCC 0.--7. 1. "HCODE166,Huffman code 166" line.long 0xD0 "JPEG_HUFFENC_AC1_84,JPEG Huffman encoder AC1" hexmask.long.byte 0xD0 24.--27. 1. "HLEN169,Huffman length 169" hexmask.long.byte 0xD0 16.--23. 1. "HCODE169,Huffman code 169" newline hexmask.long.byte 0xD0 8.--11. 1. "HLEN168,Huffman length 168" hexmask.long.byte 0xD0 0.--7. 1. "HCODE168,Huffman code 168" line.long 0xD4 "JPEG_HUFFENC_AC1_85,JPEG Huffman encoder AC1" hexmask.long.byte 0xD4 24.--27. 1. "HLEN171,Huffman length 171" hexmask.long.byte 0xD4 16.--23. 1. "HCODE171,Huffman code 171" newline hexmask.long.byte 0xD4 8.--11. 1. "HLEN170,Huffman length 170" hexmask.long.byte 0xD4 0.--7. 1. "HCODE170,Huffman code 170" line.long 0xD8 "JPEG_HUFFENC_AC1_86,JPEG Huffman encoder AC1" hexmask.long.byte 0xD8 24.--27. 1. "HLEN173,Huffman length 173" hexmask.long.byte 0xD8 16.--23. 1. "HCODE173,Huffman code 173" newline hexmask.long.byte 0xD8 8.--11. 1. "HLEN172,Huffman length 172" hexmask.long.byte 0xD8 0.--7. 1. "HCODE172,Huffman code 172" line.long 0xDC "JPEG_HUFFENC_AC1_87,JPEG Huffman encoder AC1" hexmask.long.byte 0xDC 24.--27. 1. "HLEN175,Huffman length 175" hexmask.long.byte 0xDC 16.--23. 1. "HCODE175,Huffman code 175" newline hexmask.long.byte 0xDC 8.--11. 1. "HLEN174,Huffman length 174" hexmask.long.byte 0xDC 0.--7. 1. "HCODE174,Huffman code 174" group.long 0x7C0++0x1F line.long 0x0 "JPEG_HUFFENC_DC0_0,JPEG Huffman encoder DC0" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_DC0_1,JPEG Huffman encoder DC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x8 "JPEG_HUFFENC_DC0_2,JPEG Huffman encoder DC0" hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0xC "JPEG_HUFFENC_DC0_3,JPEG Huffman encoder DC0" hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x10 "JPEG_HUFFENC_DC0_4,JPEG Huffman encoder DC0" hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x14 "JPEG_HUFFENC_DC0_5,JPEG Huffman encoder DC0" hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x18 "JPEG_HUFFENC_DC0_6,JPEG Huffman encoder DC0" hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x1C "JPEG_HUFFENC_DC0_7,JPEG Huffman encoder DC0" hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14" group.long 0x89C++0x1F line.long 0x0 "JPEG_HUFFENC_DC1_0,JPEG Huffman encoder DC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_DC1_1,JPEG Huffman encoder DC1" hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x8 "JPEG_HUFFENC_DC1_2,JPEG Huffman encoder DC1" hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0xC "JPEG_HUFFENC_DC1_3,JPEG Huffman encoder DC1" hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x10 "JPEG_HUFFENC_DC1_4,JPEG Huffman encoder DC1" hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x14 "JPEG_HUFFENC_DC1_5,JPEG Huffman encoder DC1" hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x18 "JPEG_HUFFENC_DC1_6,JPEG Huffman encoder DC1" hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x1C "JPEG_HUFFENC_DC1_7,JPEG Huffman encoder DC1" hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14" tree.end tree "SEC_JPEG" base ad:0x5002A000 wgroup.long 0x0++0x3 line.long 0x0 "JPEG_CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start" "0: Stop/abort,1: Start" group.long 0x4++0x1B line.long 0x0 "JPEG_CONFR1,JPEG codec configuration register 1" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size" bitfld.long 0x0 8. "HDR,Header processing" "0: Disable,1: Enable" newline bitfld.long 0x0 6.--7. "NS,Number of components for scan" "0,1,2,3" bitfld.long 0x0 4.--5. "COLSPACE,Color space" "0: Grayscale (1 quantization table),1: YUV (2 quantization tables),2: RGB (3 quantization tables),3: CMYK (4 quantization tables)" newline bitfld.long 0x0 3. "DE,Codec operation as coder or decoder" "0: Code,1: Decode" bitfld.long 0x0 0.--1. "NF,Number of color components" "0: Grayscale (1 color component),1: - (2 color components),2: YUV or RGB (3 color components),3: CMYK (4 color components)" line.long 0x4 "JPEG_CONFR2,JPEG codec configuration register 2" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCUs" line.long 0x8 "JPEG_CONFR3,JPEG codec configuration register 3" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size" line.long 0xC "JPEG_CONFR4,JPEG codec configuration register 4" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of blocks" bitfld.long 0xC 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0xC 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0xC 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x10 "JPEG_CONFR5,JPEG codec configuration register 5" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of blocks" bitfld.long 0x10 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x10 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x10 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x14 "JPEG_CONFR6,JPEG codec configuration register 6" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of blocks" bitfld.long 0x14 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x14 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x14 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x18 "JPEG_CONFR7,JPEG codec configuration register 7" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of blocks" bitfld.long 0x18 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x18 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x18 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" group.long 0x30++0x3 line.long 0x0 "JPEG_CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO flush" "0: No effect,1: Output FIFO is flushed" bitfld.long 0x0 13. "IFF,Input FIFO flush" "0: No effect,1: Input FIFO is flushed" newline bitfld.long 0x0 12. "ODMAEN,Output DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "IDMAEN,Input DMA enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "HPDIE,Header parsing done interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 5. "EOCIE,End of conversion interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO not empty interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 3. "OFTIE,Output FIFO threshold interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO not full interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 1. "IFTIE,Input FIFO threshold interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "JCEN,JPEG core enable" "0: Disabled (internal registers are reset).,1: Enabled (internal registers are accessible)." rgroup.long 0x34++0x3 line.long 0x0 "JPEG_SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec operation flag" "0: Not in progress,1: In progress" bitfld.long 0x0 6. "HPDF,Header parsing done flag" "0: Not completed,1: Completed" newline bitfld.long 0x0 5. "EOCF,End of conversion flag" "0: Not completed,1: Completed" bitfld.long 0x0 4. "OFNEF,Output FIFO not empty flag" "0: Empty (data not available),1: Not empty (data available)" newline bitfld.long 0x0 3. "OFTF,Output FIFO threshold flag" "0: Below threshold,1: At or above threshold" bitfld.long 0x0 2. "IFNFF,Input FIFO not full flag" "0: Full,1: Not full" newline bitfld.long 0x0 1. "IFTF,Input FIFO threshold flag" "0: At or above threshold,1: Below threshold." group.long 0x38++0x3 line.long 0x0 "JPEG_CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear header parsing done flag" "0: No effect,1: Clear" bitfld.long 0x0 5. "CEOCF,Clear end of conversion flag" "0: No effect,1: Clear" wgroup.long 0x40++0x3 line.long 0x0 "JPEG_DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input FIFO" rgroup.long 0x44++0x3 line.long 0x0 "JPEG_DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data output FIFO" group.long 0x50++0x4AB line.long 0x0 "JPEG_QMEM0_0,JPEG quantization memory 0" hexmask.long.byte 0x0 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x0 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x0 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x0 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x4 "JPEG_QMEM0_1,JPEG quantization memory 0" hexmask.long.byte 0x4 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x4 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x4 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x4 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x8 "JPEG_QMEM0_2,JPEG quantization memory 0" hexmask.long.byte 0x8 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x8 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x8 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x8 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0xC "JPEG_QMEM0_3,JPEG quantization memory 0" hexmask.long.byte 0xC 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0xC 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0xC 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0xC 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x10 "JPEG_QMEM0_4,JPEG quantization memory 0" hexmask.long.byte 0x10 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x10 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x10 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x10 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x14 "JPEG_QMEM0_5,JPEG quantization memory 0" hexmask.long.byte 0x14 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x14 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x14 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x14 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x18 "JPEG_QMEM0_6,JPEG quantization memory 0" hexmask.long.byte 0x18 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x18 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x18 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x18 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x1C "JPEG_QMEM0_7,JPEG quantization memory 0" hexmask.long.byte 0x1C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x1C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x1C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x1C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0x20 "JPEG_QMEM0_8,JPEG quantization memory 0" hexmask.long.byte 0x20 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0x20 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0x20 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0x20 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0x24 "JPEG_QMEM0_9,JPEG quantization memory 0" hexmask.long.byte 0x24 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0x24 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0x24 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0x24 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0x28 "JPEG_QMEM0_10,JPEG quantization memory 0" hexmask.long.byte 0x28 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0x28 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0x28 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0x28 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0x2C "JPEG_QMEM0_11,JPEG quantization memory 0" hexmask.long.byte 0x2C 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0x2C 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0x2C 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0x2C 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0x30 "JPEG_QMEM0_12,JPEG quantization memory 0" hexmask.long.byte 0x30 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0x30 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0x30 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0x30 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0x34 "JPEG_QMEM0_13,JPEG quantization memory 0" hexmask.long.byte 0x34 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0x34 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0x34 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0x34 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0x38 "JPEG_QMEM0_14,JPEG quantization memory 0" hexmask.long.byte 0x38 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0x38 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0x38 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0x38 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0x3C "JPEG_QMEM0_15,JPEG quantization memory 0" hexmask.long.byte 0x3C 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0x3C 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0x3C 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0x3C 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x40 "JPEG_QMEM1_0,JPEG quantization memory 1" hexmask.long.byte 0x40 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x40 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x40 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x40 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x44 "JPEG_QMEM1_1,JPEG quantization memory 1" hexmask.long.byte 0x44 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x44 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x44 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x44 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x48 "JPEG_QMEM1_2,JPEG quantization memory 1" hexmask.long.byte 0x48 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x48 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x48 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x48 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0x4C "JPEG_QMEM1_3,JPEG quantization memory 1" hexmask.long.byte 0x4C 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0x4C 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0x4C 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0x4C 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x50 "JPEG_QMEM1_4,JPEG quantization memory 1" hexmask.long.byte 0x50 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x50 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x50 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x50 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x54 "JPEG_QMEM1_5,JPEG quantization memory 1" hexmask.long.byte 0x54 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x54 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x54 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x54 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x58 "JPEG_QMEM1_6,JPEG quantization memory 1" hexmask.long.byte 0x58 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x58 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x58 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x58 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x5C "JPEG_QMEM1_7,JPEG quantization memory 1" hexmask.long.byte 0x5C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x5C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x5C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x5C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0x60 "JPEG_QMEM1_8,JPEG quantization memory 1" hexmask.long.byte 0x60 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0x60 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0x60 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0x60 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0x64 "JPEG_QMEM1_9,JPEG quantization memory 1" hexmask.long.byte 0x64 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0x64 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0x64 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0x64 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0x68 "JPEG_QMEM1_10,JPEG quantization memory 1" hexmask.long.byte 0x68 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0x68 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0x68 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0x68 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0x6C "JPEG_QMEM1_11,JPEG quantization memory 1" hexmask.long.byte 0x6C 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0x6C 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0x6C 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0x6C 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0x70 "JPEG_QMEM1_12,JPEG quantization memory 1" hexmask.long.byte 0x70 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0x70 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0x70 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0x70 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0x74 "JPEG_QMEM1_13,JPEG quantization memory 1" hexmask.long.byte 0x74 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0x74 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0x74 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0x74 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0x78 "JPEG_QMEM1_14,JPEG quantization memory 1" hexmask.long.byte 0x78 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0x78 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0x78 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0x78 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0x7C "JPEG_QMEM1_15,JPEG quantization memory 1" hexmask.long.byte 0x7C 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0x7C 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0x7C 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0x7C 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x80 "JPEG_QMEM2_0,JPEG quantization memory 2" hexmask.long.byte 0x80 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x80 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x80 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x80 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x84 "JPEG_QMEM2_1,JPEG quantization memory 2" hexmask.long.byte 0x84 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x84 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x84 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x84 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x88 "JPEG_QMEM2_2,JPEG quantization memory 2" hexmask.long.byte 0x88 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x88 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x88 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x88 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0x8C "JPEG_QMEM2_3,JPEG quantization memory 2" hexmask.long.byte 0x8C 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0x8C 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0x8C 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0x8C 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x90 "JPEG_QMEM2_4,JPEG quantization memory 2" hexmask.long.byte 0x90 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x90 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x90 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x90 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x94 "JPEG_QMEM2_5,JPEG quantization memory 2" hexmask.long.byte 0x94 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x94 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x94 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x94 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x98 "JPEG_QMEM2_6,JPEG quantization memory 2" hexmask.long.byte 0x98 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x98 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x98 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x98 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x9C "JPEG_QMEM2_7,JPEG quantization memory 2" hexmask.long.byte 0x9C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x9C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x9C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x9C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0xA0 "JPEG_QMEM2_8,JPEG quantization memory 2" hexmask.long.byte 0xA0 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0xA0 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0xA0 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0xA0 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0xA4 "JPEG_QMEM2_9,JPEG quantization memory 2" hexmask.long.byte 0xA4 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0xA4 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0xA4 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0xA4 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0xA8 "JPEG_QMEM2_10,JPEG quantization memory 2" hexmask.long.byte 0xA8 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0xA8 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0xA8 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0xA8 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0xAC "JPEG_QMEM2_11,JPEG quantization memory 2" hexmask.long.byte 0xAC 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0xAC 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0xAC 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0xAC 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0xB0 "JPEG_QMEM2_12,JPEG quantization memory 2" hexmask.long.byte 0xB0 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0xB0 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0xB0 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0xB0 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0xB4 "JPEG_QMEM2_13,JPEG quantization memory 2" hexmask.long.byte 0xB4 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0xB4 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0xB4 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0xB4 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0xB8 "JPEG_QMEM2_14,JPEG quantization memory 2" hexmask.long.byte 0xB8 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0xB8 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0xB8 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0xB8 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0xBC "JPEG_QMEM2_15,JPEG quantization memory 2" hexmask.long.byte 0xBC 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0xBC 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0xBC 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0xBC 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0xC0 "JPEG_QMEM3_0,JPEG quantization memory 3" hexmask.long.byte 0xC0 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0xC0 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0xC0 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0xC0 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0xC4 "JPEG_QMEM3_1,JPEG quantization memory 3" hexmask.long.byte 0xC4 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0xC4 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0xC4 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0xC4 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0xC8 "JPEG_QMEM3_2,JPEG quantization memory 3" hexmask.long.byte 0xC8 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0xC8 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0xC8 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0xC8 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0xCC "JPEG_QMEM3_3,JPEG quantization memory 3" hexmask.long.byte 0xCC 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0xCC 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0xCC 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0xCC 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0xD0 "JPEG_QMEM3_4,JPEG quantization memory 3" hexmask.long.byte 0xD0 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0xD0 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0xD0 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0xD0 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0xD4 "JPEG_QMEM3_5,JPEG quantization memory 3" hexmask.long.byte 0xD4 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0xD4 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0xD4 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0xD4 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0xD8 "JPEG_QMEM3_6,JPEG quantization memory 3" hexmask.long.byte 0xD8 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0xD8 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0xD8 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0xD8 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0xDC "JPEG_QMEM3_7,JPEG quantization memory 3" hexmask.long.byte 0xDC 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0xDC 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0xDC 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0xDC 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0xE0 "JPEG_QMEM3_8,JPEG quantization memory 3" hexmask.long.byte 0xE0 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0xE0 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0xE0 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0xE0 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0xE4 "JPEG_QMEM3_9,JPEG quantization memory 3" hexmask.long.byte 0xE4 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0xE4 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0xE4 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0xE4 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0xE8 "JPEG_QMEM3_10,JPEG quantization memory 3" hexmask.long.byte 0xE8 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0xE8 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0xE8 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0xE8 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0xEC "JPEG_QMEM3_11,JPEG quantization memory 3" hexmask.long.byte 0xEC 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0xEC 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0xEC 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0xEC 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0xF0 "JPEG_QMEM3_12,JPEG quantization memory 3" hexmask.long.byte 0xF0 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0xF0 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0xF0 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0xF0 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0xF4 "JPEG_QMEM3_13,JPEG quantization memory 3" hexmask.long.byte 0xF4 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0xF4 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0xF4 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0xF4 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0xF8 "JPEG_QMEM3_14,JPEG quantization memory 3" hexmask.long.byte 0xF8 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0xF8 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0xF8 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0xF8 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0xFC "JPEG_QMEM3_15,JPEG quantization memory 3" hexmask.long.byte 0xFC 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0xFC 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0xFC 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0xFC 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x100 "JPEG_HUFFMIN0_0,JPEG Huffman min" hexmask.long 0x100 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x104 "JPEG_HUFFMIN0_1,JPEG Huffman min" hexmask.long 0x104 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x108 "JPEG_HUFFMIN0_2,JPEG Huffman min" hexmask.long 0x108 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x10C "JPEG_HUFFMIN0_3,JPEG Huffman min 0 [alternate]" hexmask.long.byte 0x10C 0.--3. 1. "DATA0,Minimum Huffman value" line.long 0x110 "JPEG_HUFFMIN1_0,JPEG Huffman min" hexmask.long 0x110 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x114 "JPEG_HUFFMIN1_1,JPEG Huffman min" hexmask.long 0x114 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x118 "JPEG_HUFFMIN1_2,JPEG Huffman min" hexmask.long 0x118 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x11C "JPEG_HUFFMIN1_3,JPEG Huffman min 1 [alternate]" hexmask.long.byte 0x11C 0.--3. 1. "DATA1,Minimum Huffman value" line.long 0x120 "JPEG_HUFFMIN2_0,JPEG Huffman min" hexmask.long 0x120 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x124 "JPEG_HUFFMIN2_1,JPEG Huffman min" hexmask.long 0x124 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x128 "JPEG_HUFFMIN2_2,JPEG Huffman min" hexmask.long 0x128 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x12C "JPEG_HUFFMIN2_3,JPEG Huffman min 2 [alternate]" hexmask.long.byte 0x12C 0.--3. 1. "DATA2,Minimum Huffman value" line.long 0x130 "JPEG_HUFFMIN3_0,JPEG Huffman min" hexmask.long 0x130 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x134 "JPEG_HUFFMIN3_1,JPEG Huffman min" hexmask.long 0x134 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x138 "JPEG_HUFFMIN3_2,JPEG Huffman min" hexmask.long 0x138 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x13C "JPEG_HUFFMIN3_3,JPEG Huffman min 3 [alternate]" hexmask.long.byte 0x13C 0.--3. 1. "DATA3,Minimum Huffman value" line.long 0x140 "JPEG_HUFFBASE0,JPEG Huffman base" hexmask.long.word 0x140 16.--24. 1. "DATA1,Data 1" hexmask.long.word 0x140 0.--8. 1. "DATA0,Data 0" line.long 0x144 "JPEG_HUFFBASE1,JPEG Huffman base" hexmask.long.word 0x144 16.--24. 1. "DATA3,Data 3" hexmask.long.word 0x144 0.--8. 1. "DATA2,Data 2" line.long 0x148 "JPEG_HUFFBASE2,JPEG Huffman base" hexmask.long.word 0x148 16.--24. 1. "DATA5,Data 5" hexmask.long.word 0x148 0.--8. 1. "DATA4,Data 4" line.long 0x14C "JPEG_HUFFBASE3,JPEG Huffman base" hexmask.long.word 0x14C 16.--24. 1. "DATA7,Data 7" hexmask.long.word 0x14C 0.--8. 1. "DATA6,Data 6" line.long 0x150 "JPEG_HUFFBASE4,JPEG Huffman base" hexmask.long.word 0x150 16.--24. 1. "DATA9,Data 9" hexmask.long.word 0x150 0.--8. 1. "DATA8,Data 8" line.long 0x154 "JPEG_HUFFBASE5,JPEG Huffman base" hexmask.long.word 0x154 16.--24. 1. "DATA11,Data 11" hexmask.long.word 0x154 0.--8. 1. "DATA10,Data 10" line.long 0x158 "JPEG_HUFFBASE6,JPEG Huffman base" hexmask.long.word 0x158 16.--24. 1. "DATA13,Data 13" hexmask.long.word 0x158 0.--8. 1. "DATA12,Data 12" line.long 0x15C "JPEG_HUFFBASE7,JPEG Huffman base" hexmask.long.word 0x15C 16.--24. 1. "DATA15,Data 15" hexmask.long.word 0x15C 0.--8. 1. "DATA14,Data 14" line.long 0x160 "JPEG_HUFFBASE8,JPEG Huffman base" hexmask.long.word 0x160 16.--24. 1. "DATA17,Data 17" hexmask.long.word 0x160 0.--8. 1. "DATA16,Data 16" line.long 0x164 "JPEG_HUFFBASE9,JPEG Huffman base" hexmask.long.word 0x164 16.--24. 1. "DATA19,Data 19" hexmask.long.word 0x164 0.--8. 1. "DATA18,Data 18" line.long 0x168 "JPEG_HUFFBASE10,JPEG Huffman base" hexmask.long.word 0x168 16.--24. 1. "DATA21,Data 21" hexmask.long.word 0x168 0.--8. 1. "DATA20,Data 20" line.long 0x16C "JPEG_HUFFBASE11,JPEG Huffman base" hexmask.long.word 0x16C 16.--24. 1. "DATA23,Data 23" hexmask.long.word 0x16C 0.--8. 1. "DATA22,Data 22" line.long 0x170 "JPEG_HUFFBASE12,JPEG Huffman base" hexmask.long.word 0x170 16.--24. 1. "DATA25,Data 25" hexmask.long.word 0x170 0.--8. 1. "DATA24,Data 24" line.long 0x174 "JPEG_HUFFBASE13,JPEG Huffman base" hexmask.long.word 0x174 16.--24. 1. "DATA27,Data 27" hexmask.long.word 0x174 0.--8. 1. "DATA26,Data 26" line.long 0x178 "JPEG_HUFFBASE14,JPEG Huffman base" hexmask.long.word 0x178 16.--24. 1. "DATA29,Data 29" hexmask.long.word 0x178 0.--8. 1. "DATA28,Data 28" line.long 0x17C "JPEG_HUFFBASE15,JPEG Huffman base" hexmask.long.word 0x17C 16.--24. 1. "DATA31,Data 31" hexmask.long.word 0x17C 0.--8. 1. "DATA30,Data 30" line.long 0x180 "JPEG_HUFFBASE16,JPEG Huffman base" hexmask.long.word 0x180 16.--24. 1. "DATA33,Data 33" hexmask.long.word 0x180 0.--8. 1. "DATA32,Data 32" line.long 0x184 "JPEG_HUFFBASE17,JPEG Huffman base" hexmask.long.word 0x184 16.--24. 1. "DATA35,Data 35" hexmask.long.word 0x184 0.--8. 1. "DATA34,Data 34" line.long 0x188 "JPEG_HUFFBASE18,JPEG Huffman base" hexmask.long.word 0x188 16.--24. 1. "DATA37,Data 37" hexmask.long.word 0x188 0.--8. 1. "DATA36,Data 36" line.long 0x18C "JPEG_HUFFBASE19,JPEG Huffman base" hexmask.long.word 0x18C 16.--24. 1. "DATA39,Data 39" hexmask.long.word 0x18C 0.--8. 1. "DATA38,Data 38" line.long 0x190 "JPEG_HUFFBASE20,JPEG Huffman base" hexmask.long.word 0x190 16.--24. 1. "DATA41,Data 41" hexmask.long.word 0x190 0.--8. 1. "DATA40,Data 40" line.long 0x194 "JPEG_HUFFBASE21,JPEG Huffman base" hexmask.long.word 0x194 16.--24. 1. "DATA43,Data 43" hexmask.long.word 0x194 0.--8. 1. "DATA42,Data 42" line.long 0x198 "JPEG_HUFFBASE22,JPEG Huffman base" hexmask.long.word 0x198 16.--24. 1. "DATA45,Data 45" hexmask.long.word 0x198 0.--8. 1. "DATA44,Data 44" line.long 0x19C "JPEG_HUFFBASE23,JPEG Huffman base" hexmask.long.word 0x19C 16.--24. 1. "DATA47,Data 47" hexmask.long.word 0x19C 0.--8. 1. "DATA46,Data 46" line.long 0x1A0 "JPEG_HUFFBASE24,JPEG Huffman base" hexmask.long.word 0x1A0 16.--24. 1. "DATA49,Data 49" hexmask.long.word 0x1A0 0.--8. 1. "DATA48,Data 48" line.long 0x1A4 "JPEG_HUFFBASE25,JPEG Huffman base" hexmask.long.word 0x1A4 16.--24. 1. "DATA51,Data 51" hexmask.long.word 0x1A4 0.--8. 1. "DATA50,Data 50" line.long 0x1A8 "JPEG_HUFFBASE26,JPEG Huffman base" hexmask.long.word 0x1A8 16.--24. 1. "DATA53,Data 53" hexmask.long.word 0x1A8 0.--8. 1. "DATA52,Data 52" line.long 0x1AC "JPEG_HUFFBASE27,JPEG Huffman base" hexmask.long.word 0x1AC 16.--24. 1. "DATA55,Data 55" hexmask.long.word 0x1AC 0.--8. 1. "DATA54,Data 54" line.long 0x1B0 "JPEG_HUFFBASE28,JPEG Huffman base" hexmask.long.word 0x1B0 16.--24. 1. "DATA57,Data 57" hexmask.long.word 0x1B0 0.--8. 1. "DATA56,Data 56" line.long 0x1B4 "JPEG_HUFFBASE29,JPEG Huffman base" hexmask.long.word 0x1B4 16.--24. 1. "DATA59,Data 59" hexmask.long.word 0x1B4 0.--8. 1. "DATA58,Data 58" line.long 0x1B8 "JPEG_HUFFBASE30,JPEG Huffman base" hexmask.long.word 0x1B8 16.--24. 1. "DATA61,Data 61" hexmask.long.word 0x1B8 0.--8. 1. "DATA60,Data 60" line.long 0x1BC "JPEG_HUFFBASE31,JPEG Huffman base" hexmask.long.word 0x1BC 16.--24. 1. "DATA63,Data 63" hexmask.long.word 0x1BC 0.--8. 1. "DATA62,Data 62" line.long 0x1C0 "JPEG_HUFFSYMB0,JPEG Huffman symbol" hexmask.long.byte 0x1C0 24.--31. 1. "DATA3,Data 3" hexmask.long.byte 0x1C0 16.--23. 1. "DATA2,Data 2" newline hexmask.long.byte 0x1C0 8.--15. 1. "DATA1,Data 1" hexmask.long.byte 0x1C0 0.--7. 1. "DATA0,Data 0" line.long 0x1C4 "JPEG_HUFFSYMB1,JPEG Huffman symbol" hexmask.long.byte 0x1C4 24.--31. 1. "DATA7,Data 7" hexmask.long.byte 0x1C4 16.--23. 1. "DATA6,Data 6" newline hexmask.long.byte 0x1C4 8.--15. 1. "DATA5,Data 5" hexmask.long.byte 0x1C4 0.--7. 1. "DATA4,Data 4" line.long 0x1C8 "JPEG_HUFFSYMB2,JPEG Huffman symbol" hexmask.long.byte 0x1C8 24.--31. 1. "DATA11,Data 11" hexmask.long.byte 0x1C8 16.--23. 1. "DATA10,Data 10" newline hexmask.long.byte 0x1C8 8.--15. 1. "DATA9,Data 9" hexmask.long.byte 0x1C8 0.--7. 1. "DATA8,Data 8" line.long 0x1CC "JPEG_HUFFSYMB3,JPEG Huffman symbol" hexmask.long.byte 0x1CC 24.--31. 1. "DATA15,Data 15" hexmask.long.byte 0x1CC 16.--23. 1. "DATA14,Data 14" newline hexmask.long.byte 0x1CC 8.--15. 1. "DATA13,Data 13" hexmask.long.byte 0x1CC 0.--7. 1. "DATA12,Data 12" line.long 0x1D0 "JPEG_HUFFSYMB4,JPEG Huffman symbol" hexmask.long.byte 0x1D0 24.--31. 1. "DATA19,Data 19" hexmask.long.byte 0x1D0 16.--23. 1. "DATA18,Data 18" newline hexmask.long.byte 0x1D0 8.--15. 1. "DATA17,Data 17" hexmask.long.byte 0x1D0 0.--7. 1. "DATA16,Data 16" line.long 0x1D4 "JPEG_HUFFSYMB5,JPEG Huffman symbol" hexmask.long.byte 0x1D4 24.--31. 1. "DATA23,Data 23" hexmask.long.byte 0x1D4 16.--23. 1. "DATA22,Data 22" newline hexmask.long.byte 0x1D4 8.--15. 1. "DATA21,Data 21" hexmask.long.byte 0x1D4 0.--7. 1. "DATA20,Data 20" line.long 0x1D8 "JPEG_HUFFSYMB6,JPEG Huffman symbol" hexmask.long.byte 0x1D8 24.--31. 1. "DATA27,Data 27" hexmask.long.byte 0x1D8 16.--23. 1. "DATA26,Data 26" newline hexmask.long.byte 0x1D8 8.--15. 1. "DATA25,Data 25" hexmask.long.byte 0x1D8 0.--7. 1. "DATA24,Data 24" line.long 0x1DC "JPEG_HUFFSYMB7,JPEG Huffman symbol" hexmask.long.byte 0x1DC 24.--31. 1. "DATA31,Data 31" hexmask.long.byte 0x1DC 16.--23. 1. "DATA30,Data 30" newline hexmask.long.byte 0x1DC 8.--15. 1. "DATA29,Data 29" hexmask.long.byte 0x1DC 0.--7. 1. "DATA28,Data 28" line.long 0x1E0 "JPEG_HUFFSYMB8,JPEG Huffman symbol" hexmask.long.byte 0x1E0 24.--31. 1. "DATA35,Data 35" hexmask.long.byte 0x1E0 16.--23. 1. "DATA34,Data 34" newline hexmask.long.byte 0x1E0 8.--15. 1. "DATA33,Data 33" hexmask.long.byte 0x1E0 0.--7. 1. "DATA32,Data 32" line.long 0x1E4 "JPEG_HUFFSYMB9,JPEG Huffman symbol" hexmask.long.byte 0x1E4 24.--31. 1. "DATA39,Data 39" hexmask.long.byte 0x1E4 16.--23. 1. "DATA38,Data 38" newline hexmask.long.byte 0x1E4 8.--15. 1. "DATA37,Data 37" hexmask.long.byte 0x1E4 0.--7. 1. "DATA36,Data 36" line.long 0x1E8 "JPEG_HUFFSYMB10,JPEG Huffman symbol" hexmask.long.byte 0x1E8 24.--31. 1. "DATA43,Data 43" hexmask.long.byte 0x1E8 16.--23. 1. "DATA42,Data 42" newline hexmask.long.byte 0x1E8 8.--15. 1. "DATA41,Data 41" hexmask.long.byte 0x1E8 0.--7. 1. "DATA40,Data 40" line.long 0x1EC "JPEG_HUFFSYMB11,JPEG Huffman symbol" hexmask.long.byte 0x1EC 24.--31. 1. "DATA47,Data 47" hexmask.long.byte 0x1EC 16.--23. 1. "DATA46,Data 46" newline hexmask.long.byte 0x1EC 8.--15. 1. "DATA45,Data 45" hexmask.long.byte 0x1EC 0.--7. 1. "DATA44,Data 44" line.long 0x1F0 "JPEG_HUFFSYMB12,JPEG Huffman symbol" hexmask.long.byte 0x1F0 24.--31. 1. "DATA51,Data 51" hexmask.long.byte 0x1F0 16.--23. 1. "DATA50,Data 50" newline hexmask.long.byte 0x1F0 8.--15. 1. "DATA49,Data 49" hexmask.long.byte 0x1F0 0.--7. 1. "DATA48,Data 48" line.long 0x1F4 "JPEG_HUFFSYMB13,JPEG Huffman symbol" hexmask.long.byte 0x1F4 24.--31. 1. "DATA55,Data 55" hexmask.long.byte 0x1F4 16.--23. 1. "DATA54,Data 54" newline hexmask.long.byte 0x1F4 8.--15. 1. "DATA53,Data 53" hexmask.long.byte 0x1F4 0.--7. 1. "DATA52,Data 52" line.long 0x1F8 "JPEG_HUFFSYMB14,JPEG Huffman symbol" hexmask.long.byte 0x1F8 24.--31. 1. "DATA59,Data 59" hexmask.long.byte 0x1F8 16.--23. 1. "DATA58,Data 58" newline hexmask.long.byte 0x1F8 8.--15. 1. "DATA57,Data 57" hexmask.long.byte 0x1F8 0.--7. 1. "DATA56,Data 56" line.long 0x1FC "JPEG_HUFFSYMB15,JPEG Huffman symbol" hexmask.long.byte 0x1FC 24.--31. 1. "DATA63,Data 63" hexmask.long.byte 0x1FC 16.--23. 1. "DATA62,Data 62" newline hexmask.long.byte 0x1FC 8.--15. 1. "DATA61,Data 61" hexmask.long.byte 0x1FC 0.--7. 1. "DATA60,Data 60" line.long 0x200 "JPEG_HUFFSYMB16,JPEG Huffman symbol" hexmask.long.byte 0x200 24.--31. 1. "DATA67,Data 67" hexmask.long.byte 0x200 16.--23. 1. "DATA66,Data 66" newline hexmask.long.byte 0x200 8.--15. 1. "DATA65,Data 65" hexmask.long.byte 0x200 0.--7. 1. "DATA64,Data 64" line.long 0x204 "JPEG_HUFFSYMB17,JPEG Huffman symbol" hexmask.long.byte 0x204 24.--31. 1. "DATA71,Data 71" hexmask.long.byte 0x204 16.--23. 1. "DATA70,Data 70" newline hexmask.long.byte 0x204 8.--15. 1. "DATA69,Data 69" hexmask.long.byte 0x204 0.--7. 1. "DATA68,Data 68" line.long 0x208 "JPEG_HUFFSYMB18,JPEG Huffman symbol" hexmask.long.byte 0x208 24.--31. 1. "DATA75,Data 75" hexmask.long.byte 0x208 16.--23. 1. "DATA74,Data 74" newline hexmask.long.byte 0x208 8.--15. 1. "DATA73,Data 73" hexmask.long.byte 0x208 0.--7. 1. "DATA72,Data 72" line.long 0x20C "JPEG_HUFFSYMB19,JPEG Huffman symbol" hexmask.long.byte 0x20C 24.--31. 1. "DATA79,Data 79" hexmask.long.byte 0x20C 16.--23. 1. "DATA78,Data 78" newline hexmask.long.byte 0x20C 8.--15. 1. "DATA77,Data 77" hexmask.long.byte 0x20C 0.--7. 1. "DATA76,Data 76" line.long 0x210 "JPEG_HUFFSYMB20,JPEG Huffman symbol" hexmask.long.byte 0x210 24.--31. 1. "DATA83,Data 83" hexmask.long.byte 0x210 16.--23. 1. "DATA82,Data 82" newline hexmask.long.byte 0x210 8.--15. 1. "DATA81,Data 81" hexmask.long.byte 0x210 0.--7. 1. "DATA80,Data 80" line.long 0x214 "JPEG_HUFFSYMB21,JPEG Huffman symbol" hexmask.long.byte 0x214 24.--31. 1. "DATA87,Data 87" hexmask.long.byte 0x214 16.--23. 1. "DATA86,Data 86" newline hexmask.long.byte 0x214 8.--15. 1. "DATA85,Data 85" hexmask.long.byte 0x214 0.--7. 1. "DATA84,Data 84" line.long 0x218 "JPEG_HUFFSYMB22,JPEG Huffman symbol" hexmask.long.byte 0x218 24.--31. 1. "DATA91,Data 91" hexmask.long.byte 0x218 16.--23. 1. "DATA90,Data 90" newline hexmask.long.byte 0x218 8.--15. 1. "DATA89,Data 89" hexmask.long.byte 0x218 0.--7. 1. "DATA88,Data 88" line.long 0x21C "JPEG_HUFFSYMB23,JPEG Huffman symbol" hexmask.long.byte 0x21C 24.--31. 1. "DATA95,Data 95" hexmask.long.byte 0x21C 16.--23. 1. "DATA94,Data 94" newline hexmask.long.byte 0x21C 8.--15. 1. "DATA93,Data 93" hexmask.long.byte 0x21C 0.--7. 1. "DATA92,Data 92" line.long 0x220 "JPEG_HUFFSYMB24,JPEG Huffman symbol" hexmask.long.byte 0x220 24.--31. 1. "DATA99,Data 99" hexmask.long.byte 0x220 16.--23. 1. "DATA98,Data 98" newline hexmask.long.byte 0x220 8.--15. 1. "DATA97,Data 97" hexmask.long.byte 0x220 0.--7. 1. "DATA96,Data 96" line.long 0x224 "JPEG_HUFFSYMB25,JPEG Huffman symbol" hexmask.long.byte 0x224 24.--31. 1. "DATA103,Data 103" hexmask.long.byte 0x224 16.--23. 1. "DATA102,Data 102" newline hexmask.long.byte 0x224 8.--15. 1. "DATA101,Data 101" hexmask.long.byte 0x224 0.--7. 1. "DATA100,Data 100" line.long 0x228 "JPEG_HUFFSYMB26,JPEG Huffman symbol" hexmask.long.byte 0x228 24.--31. 1. "DATA107,Data 107" hexmask.long.byte 0x228 16.--23. 1. "DATA106,Data 106" newline hexmask.long.byte 0x228 8.--15. 1. "DATA105,Data 105" hexmask.long.byte 0x228 0.--7. 1. "DATA104,Data 104" line.long 0x22C "JPEG_HUFFSYMB27,JPEG Huffman symbol" hexmask.long.byte 0x22C 24.--31. 1. "DATA111,Data 111" hexmask.long.byte 0x22C 16.--23. 1. "DATA110,Data 110" newline hexmask.long.byte 0x22C 8.--15. 1. "DATA109,Data 109" hexmask.long.byte 0x22C 0.--7. 1. "DATA108,Data 108" line.long 0x230 "JPEG_HUFFSYMB28,JPEG Huffman symbol" hexmask.long.byte 0x230 24.--31. 1. "DATA115,Data 115" hexmask.long.byte 0x230 16.--23. 1. "DATA114,Data 114" newline hexmask.long.byte 0x230 8.--15. 1. "DATA113,Data 113" hexmask.long.byte 0x230 0.--7. 1. "DATA112,Data 112" line.long 0x234 "JPEG_HUFFSYMB29,JPEG Huffman symbol" hexmask.long.byte 0x234 24.--31. 1. "DATA119,Data 119" hexmask.long.byte 0x234 16.--23. 1. "DATA118,Data 118" newline hexmask.long.byte 0x234 8.--15. 1. "DATA117,Data 117" hexmask.long.byte 0x234 0.--7. 1. "DATA116,Data 116" line.long 0x238 "JPEG_HUFFSYMB30,JPEG Huffman symbol" hexmask.long.byte 0x238 24.--31. 1. "DATA123,Data 123" hexmask.long.byte 0x238 16.--23. 1. "DATA122,Data 122" newline hexmask.long.byte 0x238 8.--15. 1. "DATA121,Data 121" hexmask.long.byte 0x238 0.--7. 1. "DATA120,Data 120" line.long 0x23C "JPEG_HUFFSYMB31,JPEG Huffman symbol" hexmask.long.byte 0x23C 24.--31. 1. "DATA127,Data 127" hexmask.long.byte 0x23C 16.--23. 1. "DATA126,Data 126" newline hexmask.long.byte 0x23C 8.--15. 1. "DATA125,Data 125" hexmask.long.byte 0x23C 0.--7. 1. "DATA124,Data 124" line.long 0x240 "JPEG_HUFFSYMB32,JPEG Huffman symbol" hexmask.long.byte 0x240 24.--31. 1. "DATA131,Data 131" hexmask.long.byte 0x240 16.--23. 1. "DATA130,Data 130" newline hexmask.long.byte 0x240 8.--15. 1. "DATA129,Data 129" hexmask.long.byte 0x240 0.--7. 1. "DATA128,Data 128" line.long 0x244 "JPEG_HUFFSYMB33,JPEG Huffman symbol" hexmask.long.byte 0x244 24.--31. 1. "DATA135,Data 135" hexmask.long.byte 0x244 16.--23. 1. "DATA134,Data 134" newline hexmask.long.byte 0x244 8.--15. 1. "DATA133,Data 133" hexmask.long.byte 0x244 0.--7. 1. "DATA132,Data 132" line.long 0x248 "JPEG_HUFFSYMB34,JPEG Huffman symbol" hexmask.long.byte 0x248 24.--31. 1. "DATA139,Data 139" hexmask.long.byte 0x248 16.--23. 1. "DATA138,Data 138" newline hexmask.long.byte 0x248 8.--15. 1. "DATA137,Data 137" hexmask.long.byte 0x248 0.--7. 1. "DATA136,Data 136" line.long 0x24C "JPEG_HUFFSYMB35,JPEG Huffman symbol" hexmask.long.byte 0x24C 24.--31. 1. "DATA143,Data 143" hexmask.long.byte 0x24C 16.--23. 1. "DATA142,Data 142" newline hexmask.long.byte 0x24C 8.--15. 1. "DATA141,Data 141" hexmask.long.byte 0x24C 0.--7. 1. "DATA140,Data 140" line.long 0x250 "JPEG_HUFFSYMB36,JPEG Huffman symbol" hexmask.long.byte 0x250 24.--31. 1. "DATA147,Data 147" hexmask.long.byte 0x250 16.--23. 1. "DATA146,Data 146" newline hexmask.long.byte 0x250 8.--15. 1. "DATA145,Data 145" hexmask.long.byte 0x250 0.--7. 1. "DATA144,Data 144" line.long 0x254 "JPEG_HUFFSYMB37,JPEG Huffman symbol" hexmask.long.byte 0x254 24.--31. 1. "DATA151,Data 151" hexmask.long.byte 0x254 16.--23. 1. "DATA150,Data 150" newline hexmask.long.byte 0x254 8.--15. 1. "DATA149,Data 149" hexmask.long.byte 0x254 0.--7. 1. "DATA148,Data 148" line.long 0x258 "JPEG_HUFFSYMB38,JPEG Huffman symbol" hexmask.long.byte 0x258 24.--31. 1. "DATA155,Data 155" hexmask.long.byte 0x258 16.--23. 1. "DATA154,Data 154" newline hexmask.long.byte 0x258 8.--15. 1. "DATA153,Data 153" hexmask.long.byte 0x258 0.--7. 1. "DATA152,Data 152" line.long 0x25C "JPEG_HUFFSYMB39,JPEG Huffman symbol" hexmask.long.byte 0x25C 24.--31. 1. "DATA159,Data 159" hexmask.long.byte 0x25C 16.--23. 1. "DATA158,Data 158" newline hexmask.long.byte 0x25C 8.--15. 1. "DATA157,Data 157" hexmask.long.byte 0x25C 0.--7. 1. "DATA156,Data 156" line.long 0x260 "JPEG_HUFFSYMB40,JPEG Huffman symbol" hexmask.long.byte 0x260 24.--31. 1. "DATA163,Data 163" hexmask.long.byte 0x260 16.--23. 1. "DATA162,Data 162" newline hexmask.long.byte 0x260 8.--15. 1. "DATA161,Data 161" hexmask.long.byte 0x260 0.--7. 1. "DATA160,Data 160" line.long 0x264 "JPEG_HUFFSYMB41,JPEG Huffman symbol" hexmask.long.byte 0x264 24.--31. 1. "DATA167,Data 167" hexmask.long.byte 0x264 16.--23. 1. "DATA166,Data 166" newline hexmask.long.byte 0x264 8.--15. 1. "DATA165,Data 165" hexmask.long.byte 0x264 0.--7. 1. "DATA164,Data 164" line.long 0x268 "JPEG_HUFFSYMB42,JPEG Huffman symbol" hexmask.long.byte 0x268 24.--31. 1. "DATA171,Data 171" hexmask.long.byte 0x268 16.--23. 1. "DATA170,Data 170" newline hexmask.long.byte 0x268 8.--15. 1. "DATA169,Data 169" hexmask.long.byte 0x268 0.--7. 1. "DATA168,Data 168" line.long 0x26C "JPEG_HUFFSYMB43,JPEG Huffman symbol" hexmask.long.byte 0x26C 24.--31. 1. "DATA175,Data 175" hexmask.long.byte 0x26C 16.--23. 1. "DATA174,Data 174" newline hexmask.long.byte 0x26C 8.--15. 1. "DATA173,Data 173" hexmask.long.byte 0x26C 0.--7. 1. "DATA172,Data 172" line.long 0x270 "JPEG_HUFFSYMB44,JPEG Huffman symbol" hexmask.long.byte 0x270 24.--31. 1. "DATA179,Data 179" hexmask.long.byte 0x270 16.--23. 1. "DATA178,Data 178" newline hexmask.long.byte 0x270 8.--15. 1. "DATA177,Data 177" hexmask.long.byte 0x270 0.--7. 1. "DATA176,Data 176" line.long 0x274 "JPEG_HUFFSYMB45,JPEG Huffman symbol" hexmask.long.byte 0x274 24.--31. 1. "DATA183,Data 183" hexmask.long.byte 0x274 16.--23. 1. "DATA182,Data 182" newline hexmask.long.byte 0x274 8.--15. 1. "DATA181,Data 181" hexmask.long.byte 0x274 0.--7. 1. "DATA180,Data 180" line.long 0x278 "JPEG_HUFFSYMB46,JPEG Huffman symbol" hexmask.long.byte 0x278 24.--31. 1. "DATA187,Data 187" hexmask.long.byte 0x278 16.--23. 1. "DATA186,Data 186" newline hexmask.long.byte 0x278 8.--15. 1. "DATA185,Data 185" hexmask.long.byte 0x278 0.--7. 1. "DATA184,Data 184" line.long 0x27C "JPEG_HUFFSYMB47,JPEG Huffman symbol" hexmask.long.byte 0x27C 24.--31. 1. "DATA191,Data 191" hexmask.long.byte 0x27C 16.--23. 1. "DATA190,Data 190" newline hexmask.long.byte 0x27C 8.--15. 1. "DATA189,Data 189" hexmask.long.byte 0x27C 0.--7. 1. "DATA188,Data 188" line.long 0x280 "JPEG_HUFFSYMB48,JPEG Huffman symbol" hexmask.long.byte 0x280 24.--31. 1. "DATA195,Data 195" hexmask.long.byte 0x280 16.--23. 1. "DATA194,Data 194" newline hexmask.long.byte 0x280 8.--15. 1. "DATA193,Data 193" hexmask.long.byte 0x280 0.--7. 1. "DATA192,Data 192" line.long 0x284 "JPEG_HUFFSYMB49,JPEG Huffman symbol" hexmask.long.byte 0x284 24.--31. 1. "DATA199,Data 199" hexmask.long.byte 0x284 16.--23. 1. "DATA198,Data 198" newline hexmask.long.byte 0x284 8.--15. 1. "DATA197,Data 197" hexmask.long.byte 0x284 0.--7. 1. "DATA196,Data 196" line.long 0x288 "JPEG_HUFFSYMB50,JPEG Huffman symbol" hexmask.long.byte 0x288 24.--31. 1. "DATA203,Data 203" hexmask.long.byte 0x288 16.--23. 1. "DATA202,Data 202" newline hexmask.long.byte 0x288 8.--15. 1. "DATA201,Data 201" hexmask.long.byte 0x288 0.--7. 1. "DATA200,Data 200" line.long 0x28C "JPEG_HUFFSYMB51,JPEG Huffman symbol" hexmask.long.byte 0x28C 24.--31. 1. "DATA207,Data 207" hexmask.long.byte 0x28C 16.--23. 1. "DATA206,Data 206" newline hexmask.long.byte 0x28C 8.--15. 1. "DATA205,Data 205" hexmask.long.byte 0x28C 0.--7. 1. "DATA204,Data 204" line.long 0x290 "JPEG_HUFFSYMB52,JPEG Huffman symbol" hexmask.long.byte 0x290 24.--31. 1. "DATA211,Data 211" hexmask.long.byte 0x290 16.--23. 1. "DATA210,Data 210" newline hexmask.long.byte 0x290 8.--15. 1. "DATA209,Data 209" hexmask.long.byte 0x290 0.--7. 1. "DATA208,Data 208" line.long 0x294 "JPEG_HUFFSYMB53,JPEG Huffman symbol" hexmask.long.byte 0x294 24.--31. 1. "DATA215,Data 215" hexmask.long.byte 0x294 16.--23. 1. "DATA214,Data 214" newline hexmask.long.byte 0x294 8.--15. 1. "DATA213,Data 213" hexmask.long.byte 0x294 0.--7. 1. "DATA212,Data 212" line.long 0x298 "JPEG_HUFFSYMB54,JPEG Huffman symbol" hexmask.long.byte 0x298 24.--31. 1. "DATA219,Data 219" hexmask.long.byte 0x298 16.--23. 1. "DATA218,Data 218" newline hexmask.long.byte 0x298 8.--15. 1. "DATA217,Data 217" hexmask.long.byte 0x298 0.--7. 1. "DATA216,Data 216" line.long 0x29C "JPEG_HUFFSYMB55,JPEG Huffman symbol" hexmask.long.byte 0x29C 24.--31. 1. "DATA223,Data 223" hexmask.long.byte 0x29C 16.--23. 1. "DATA222,Data 222" newline hexmask.long.byte 0x29C 8.--15. 1. "DATA221,Data 221" hexmask.long.byte 0x29C 0.--7. 1. "DATA220,Data 220" line.long 0x2A0 "JPEG_HUFFSYMB56,JPEG Huffman symbol" hexmask.long.byte 0x2A0 24.--31. 1. "DATA227,Data 227" hexmask.long.byte 0x2A0 16.--23. 1. "DATA226,Data 226" newline hexmask.long.byte 0x2A0 8.--15. 1. "DATA225,Data 225" hexmask.long.byte 0x2A0 0.--7. 1. "DATA224,Data 224" line.long 0x2A4 "JPEG_HUFFSYMB57,JPEG Huffman symbol" hexmask.long.byte 0x2A4 24.--31. 1. "DATA231,Data 231" hexmask.long.byte 0x2A4 16.--23. 1. "DATA230,Data 230" newline hexmask.long.byte 0x2A4 8.--15. 1. "DATA229,Data 229" hexmask.long.byte 0x2A4 0.--7. 1. "DATA228,Data 228" line.long 0x2A8 "JPEG_HUFFSYMB58,JPEG Huffman symbol" hexmask.long.byte 0x2A8 24.--31. 1. "DATA235,Data 235" hexmask.long.byte 0x2A8 16.--23. 1. "DATA234,Data 234" newline hexmask.long.byte 0x2A8 8.--15. 1. "DATA233,Data 233" hexmask.long.byte 0x2A8 0.--7. 1. "DATA232,Data 232" line.long 0x2AC "JPEG_HUFFSYMB59,JPEG Huffman symbol" hexmask.long.byte 0x2AC 24.--31. 1. "DATA239,Data 239" hexmask.long.byte 0x2AC 16.--23. 1. "DATA238,Data 238" newline hexmask.long.byte 0x2AC 8.--15. 1. "DATA237,Data 237" hexmask.long.byte 0x2AC 0.--7. 1. "DATA236,Data 236" line.long 0x2B0 "JPEG_HUFFSYMB60,JPEG Huffman symbol" hexmask.long.byte 0x2B0 24.--31. 1. "DATA243,Data 243" hexmask.long.byte 0x2B0 16.--23. 1. "DATA242,Data 242" newline hexmask.long.byte 0x2B0 8.--15. 1. "DATA241,Data 241" hexmask.long.byte 0x2B0 0.--7. 1. "DATA240,Data 240" line.long 0x2B4 "JPEG_HUFFSYMB61,JPEG Huffman symbol" hexmask.long.byte 0x2B4 24.--31. 1. "DATA247,Data 247" hexmask.long.byte 0x2B4 16.--23. 1. "DATA246,Data 246" newline hexmask.long.byte 0x2B4 8.--15. 1. "DATA245,Data 245" hexmask.long.byte 0x2B4 0.--7. 1. "DATA244,Data 244" line.long 0x2B8 "JPEG_HUFFSYMB62,JPEG Huffman symbol" hexmask.long.byte 0x2B8 24.--31. 1. "DATA251,Data 251" hexmask.long.byte 0x2B8 16.--23. 1. "DATA250,Data 250" newline hexmask.long.byte 0x2B8 8.--15. 1. "DATA249,Data 249" hexmask.long.byte 0x2B8 0.--7. 1. "DATA248,Data 248" line.long 0x2BC "JPEG_HUFFSYMB63,JPEG Huffman symbol" hexmask.long.byte 0x2BC 24.--31. 1. "DATA255,Data 255" hexmask.long.byte 0x2BC 16.--23. 1. "DATA254,Data 254" newline hexmask.long.byte 0x2BC 8.--15. 1. "DATA253,Data 253" hexmask.long.byte 0x2BC 0.--7. 1. "DATA252,Data 252" line.long 0x2C0 "JPEG_HUFFSYMB64,JPEG Huffman symbol" hexmask.long.byte 0x2C0 24.--31. 1. "DATA259,Data 259" hexmask.long.byte 0x2C0 16.--23. 1. "DATA258,Data 258" newline hexmask.long.byte 0x2C0 8.--15. 1. "DATA257,Data 257" hexmask.long.byte 0x2C0 0.--7. 1. "DATA256,Data 256" line.long 0x2C4 "JPEG_HUFFSYMB65,JPEG Huffman symbol" hexmask.long.byte 0x2C4 24.--31. 1. "DATA263,Data 263" hexmask.long.byte 0x2C4 16.--23. 1. "DATA262,Data 262" newline hexmask.long.byte 0x2C4 8.--15. 1. "DATA261,Data 261" hexmask.long.byte 0x2C4 0.--7. 1. "DATA260,Data 260" line.long 0x2C8 "JPEG_HUFFSYMB66,JPEG Huffman symbol" hexmask.long.byte 0x2C8 24.--31. 1. "DATA267,Data 267" hexmask.long.byte 0x2C8 16.--23. 1. "DATA266,Data 266" newline hexmask.long.byte 0x2C8 8.--15. 1. "DATA265,Data 265" hexmask.long.byte 0x2C8 0.--7. 1. "DATA264,Data 264" line.long 0x2CC "JPEG_HUFFSYMB67,JPEG Huffman symbol" hexmask.long.byte 0x2CC 24.--31. 1. "DATA271,Data 271" hexmask.long.byte 0x2CC 16.--23. 1. "DATA270,Data 270" newline hexmask.long.byte 0x2CC 8.--15. 1. "DATA269,Data 269" hexmask.long.byte 0x2CC 0.--7. 1. "DATA268,Data 268" line.long 0x2D0 "JPEG_HUFFSYMB68,JPEG Huffman symbol" hexmask.long.byte 0x2D0 24.--31. 1. "DATA275,Data 275" hexmask.long.byte 0x2D0 16.--23. 1. "DATA274,Data 274" newline hexmask.long.byte 0x2D0 8.--15. 1. "DATA273,Data 273" hexmask.long.byte 0x2D0 0.--7. 1. "DATA272,Data 272" line.long 0x2D4 "JPEG_HUFFSYMB69,JPEG Huffman symbol" hexmask.long.byte 0x2D4 24.--31. 1. "DATA279,Data 279" hexmask.long.byte 0x2D4 16.--23. 1. "DATA278,Data 278" newline hexmask.long.byte 0x2D4 8.--15. 1. "DATA277,Data 277" hexmask.long.byte 0x2D4 0.--7. 1. "DATA276,Data 276" line.long 0x2D8 "JPEG_HUFFSYMB70,JPEG Huffman symbol" hexmask.long.byte 0x2D8 24.--31. 1. "DATA283,Data 283" hexmask.long.byte 0x2D8 16.--23. 1. "DATA282,Data 282" newline hexmask.long.byte 0x2D8 8.--15. 1. "DATA281,Data 281" hexmask.long.byte 0x2D8 0.--7. 1. "DATA280,Data 280" line.long 0x2DC "JPEG_HUFFSYMB71,JPEG Huffman symbol" hexmask.long.byte 0x2DC 24.--31. 1. "DATA287,Data 287" hexmask.long.byte 0x2DC 16.--23. 1. "DATA286,Data 286" newline hexmask.long.byte 0x2DC 8.--15. 1. "DATA285,Data 285" hexmask.long.byte 0x2DC 0.--7. 1. "DATA284,Data 284" line.long 0x2E0 "JPEG_HUFFSYMB72,JPEG Huffman symbol" hexmask.long.byte 0x2E0 24.--31. 1. "DATA291,Data 291" hexmask.long.byte 0x2E0 16.--23. 1. "DATA290,Data 290" newline hexmask.long.byte 0x2E0 8.--15. 1. "DATA289,Data 289" hexmask.long.byte 0x2E0 0.--7. 1. "DATA288,Data 288" line.long 0x2E4 "JPEG_HUFFSYMB73,JPEG Huffman symbol" hexmask.long.byte 0x2E4 24.--31. 1. "DATA295,Data 295" hexmask.long.byte 0x2E4 16.--23. 1. "DATA294,Data 294" newline hexmask.long.byte 0x2E4 8.--15. 1. "DATA293,Data 293" hexmask.long.byte 0x2E4 0.--7. 1. "DATA292,Data 292" line.long 0x2E8 "JPEG_HUFFSYMB74,JPEG Huffman symbol" hexmask.long.byte 0x2E8 24.--31. 1. "DATA299,Data 299" hexmask.long.byte 0x2E8 16.--23. 1. "DATA298,Data 298" newline hexmask.long.byte 0x2E8 8.--15. 1. "DATA297,Data 297" hexmask.long.byte 0x2E8 0.--7. 1. "DATA296,Data 296" line.long 0x2EC "JPEG_HUFFSYMB75,JPEG Huffman symbol" hexmask.long.byte 0x2EC 24.--31. 1. "DATA303,Data 303" hexmask.long.byte 0x2EC 16.--23. 1. "DATA302,Data 302" newline hexmask.long.byte 0x2EC 8.--15. 1. "DATA301,Data 301" hexmask.long.byte 0x2EC 0.--7. 1. "DATA300,Data 300" line.long 0x2F0 "JPEG_HUFFSYMB76,JPEG Huffman symbol" hexmask.long.byte 0x2F0 24.--31. 1. "DATA307,Data 307" hexmask.long.byte 0x2F0 16.--23. 1. "DATA306,Data 306" newline hexmask.long.byte 0x2F0 8.--15. 1. "DATA305,Data 305" hexmask.long.byte 0x2F0 0.--7. 1. "DATA304,Data 304" line.long 0x2F4 "JPEG_HUFFSYMB77,JPEG Huffman symbol" hexmask.long.byte 0x2F4 24.--31. 1. "DATA311,Data 311" hexmask.long.byte 0x2F4 16.--23. 1. "DATA310,Data 310" newline hexmask.long.byte 0x2F4 8.--15. 1. "DATA309,Data 309" hexmask.long.byte 0x2F4 0.--7. 1. "DATA308,Data 308" line.long 0x2F8 "JPEG_HUFFSYMB78,JPEG Huffman symbol" hexmask.long.byte 0x2F8 24.--31. 1. "DATA315,Data 315" hexmask.long.byte 0x2F8 16.--23. 1. "DATA314,Data 314" newline hexmask.long.byte 0x2F8 8.--15. 1. "DATA313,Data 313" hexmask.long.byte 0x2F8 0.--7. 1. "DATA312,Data 312" line.long 0x2FC "JPEG_HUFFSYMB79,JPEG Huffman symbol" hexmask.long.byte 0x2FC 24.--31. 1. "DATA319,Data 319" hexmask.long.byte 0x2FC 16.--23. 1. "DATA318,Data 318" newline hexmask.long.byte 0x2FC 8.--15. 1. "DATA317,Data 317" hexmask.long.byte 0x2FC 0.--7. 1. "DATA316,Data 316" line.long 0x300 "JPEG_HUFFSYMB80,JPEG Huffman symbol" hexmask.long.byte 0x300 24.--31. 1. "DATA323,Data 323" hexmask.long.byte 0x300 16.--23. 1. "DATA322,Data 322" newline hexmask.long.byte 0x300 8.--15. 1. "DATA321,Data 321" hexmask.long.byte 0x300 0.--7. 1. "DATA320,Data 320" line.long 0x304 "JPEG_HUFFSYMB81,JPEG Huffman symbol" hexmask.long.byte 0x304 24.--31. 1. "DATA327,Data 327" hexmask.long.byte 0x304 16.--23. 1. "DATA326,Data 326" newline hexmask.long.byte 0x304 8.--15. 1. "DATA325,Data 325" hexmask.long.byte 0x304 0.--7. 1. "DATA324,Data 324" line.long 0x308 "JPEG_HUFFSYMB82,JPEG Huffman symbol" hexmask.long.byte 0x308 24.--31. 1. "DATA331,Data 331" hexmask.long.byte 0x308 16.--23. 1. "DATA330,Data 330" newline hexmask.long.byte 0x308 8.--15. 1. "DATA329,Data 329" hexmask.long.byte 0x308 0.--7. 1. "DATA328,Data 328" line.long 0x30C "JPEG_HUFFSYMB83,JPEG Huffman symbol" hexmask.long.byte 0x30C 24.--31. 1. "DATA335,Data 335" hexmask.long.byte 0x30C 16.--23. 1. "DATA334,Data 334" newline hexmask.long.byte 0x30C 8.--15. 1. "DATA333,Data 333" hexmask.long.byte 0x30C 0.--7. 1. "DATA332,Data 332" line.long 0x310 "JPEG_DHTMEM0,JPEG DHT memory" hexmask.long.byte 0x310 24.--31. 1. "DATA3,Huffman table data 3" hexmask.long.byte 0x310 16.--23. 1. "DATA2,Huffman table data 2" newline hexmask.long.byte 0x310 8.--15. 1. "DATA1,Huffman table data 1" hexmask.long.byte 0x310 0.--7. 1. "DATA0,Huffman table data 0" line.long 0x314 "JPEG_DHTMEM1,JPEG DHT memory" hexmask.long.byte 0x314 24.--31. 1. "DATA7,Huffman table data 7" hexmask.long.byte 0x314 16.--23. 1. "DATA6,Huffman table data 6" newline hexmask.long.byte 0x314 8.--15. 1. "DATA5,Huffman table data 5" hexmask.long.byte 0x314 0.--7. 1. "DATA4,Huffman table data 4" line.long 0x318 "JPEG_DHTMEM2,JPEG DHT memory" hexmask.long.byte 0x318 24.--31. 1. "DATA11,Huffman table data 11" hexmask.long.byte 0x318 16.--23. 1. "DATA10,Huffman table data 10" newline hexmask.long.byte 0x318 8.--15. 1. "DATA9,Huffman table data 9" hexmask.long.byte 0x318 0.--7. 1. "DATA8,Huffman table data 8" line.long 0x31C "JPEG_DHTMEM3,JPEG DHT memory" hexmask.long.byte 0x31C 24.--31. 1. "DATA15,Huffman table data 15" hexmask.long.byte 0x31C 16.--23. 1. "DATA14,Huffman table data 14" newline hexmask.long.byte 0x31C 8.--15. 1. "DATA13,Huffman table data 13" hexmask.long.byte 0x31C 0.--7. 1. "DATA12,Huffman table data 12" line.long 0x320 "JPEG_DHTMEM4,JPEG DHT memory" hexmask.long.byte 0x320 24.--31. 1. "DATA19,Huffman table data 19" hexmask.long.byte 0x320 16.--23. 1. "DATA18,Huffman table data 18" newline hexmask.long.byte 0x320 8.--15. 1. "DATA17,Huffman table data 17" hexmask.long.byte 0x320 0.--7. 1. "DATA16,Huffman table data 16" line.long 0x324 "JPEG_DHTMEM5,JPEG DHT memory" hexmask.long.byte 0x324 24.--31. 1. "DATA23,Huffman table data 23" hexmask.long.byte 0x324 16.--23. 1. "DATA22,Huffman table data 22" newline hexmask.long.byte 0x324 8.--15. 1. "DATA21,Huffman table data 21" hexmask.long.byte 0x324 0.--7. 1. "DATA20,Huffman table data 20" line.long 0x328 "JPEG_DHTMEM6,JPEG DHT memory" hexmask.long.byte 0x328 24.--31. 1. "DATA27,Huffman table data 27" hexmask.long.byte 0x328 16.--23. 1. "DATA26,Huffman table data 26" newline hexmask.long.byte 0x328 8.--15. 1. "DATA25,Huffman table data 25" hexmask.long.byte 0x328 0.--7. 1. "DATA24,Huffman table data 24" line.long 0x32C "JPEG_DHTMEM7,JPEG DHT memory" hexmask.long.byte 0x32C 24.--31. 1. "DATA31,Huffman table data 31" hexmask.long.byte 0x32C 16.--23. 1. "DATA30,Huffman table data 30" newline hexmask.long.byte 0x32C 8.--15. 1. "DATA29,Huffman table data 29" hexmask.long.byte 0x32C 0.--7. 1. "DATA28,Huffman table data 28" line.long 0x330 "JPEG_DHTMEM8,JPEG DHT memory" hexmask.long.byte 0x330 24.--31. 1. "DATA35,Huffman table data 35" hexmask.long.byte 0x330 16.--23. 1. "DATA34,Huffman table data 34" newline hexmask.long.byte 0x330 8.--15. 1. "DATA33,Huffman table data 33" hexmask.long.byte 0x330 0.--7. 1. "DATA32,Huffman table data 32" line.long 0x334 "JPEG_DHTMEM9,JPEG DHT memory" hexmask.long.byte 0x334 24.--31. 1. "DATA39,Huffman table data 39" hexmask.long.byte 0x334 16.--23. 1. "DATA38,Huffman table data 38" newline hexmask.long.byte 0x334 8.--15. 1. "DATA37,Huffman table data 37" hexmask.long.byte 0x334 0.--7. 1. "DATA36,Huffman table data 36" line.long 0x338 "JPEG_DHTMEM10,JPEG DHT memory" hexmask.long.byte 0x338 24.--31. 1. "DATA43,Huffman table data 43" hexmask.long.byte 0x338 16.--23. 1. "DATA42,Huffman table data 42" newline hexmask.long.byte 0x338 8.--15. 1. "DATA41,Huffman table data 41" hexmask.long.byte 0x338 0.--7. 1. "DATA40,Huffman table data 40" line.long 0x33C "JPEG_DHTMEM11,JPEG DHT memory" hexmask.long.byte 0x33C 24.--31. 1. "DATA47,Huffman table data 47" hexmask.long.byte 0x33C 16.--23. 1. "DATA46,Huffman table data 46" newline hexmask.long.byte 0x33C 8.--15. 1. "DATA45,Huffman table data 45" hexmask.long.byte 0x33C 0.--7. 1. "DATA44,Huffman table data 44" line.long 0x340 "JPEG_DHTMEM12,JPEG DHT memory" hexmask.long.byte 0x340 24.--31. 1. "DATA51,Huffman table data 51" hexmask.long.byte 0x340 16.--23. 1. "DATA50,Huffman table data 50" newline hexmask.long.byte 0x340 8.--15. 1. "DATA49,Huffman table data 49" hexmask.long.byte 0x340 0.--7. 1. "DATA48,Huffman table data 48" line.long 0x344 "JPEG_DHTMEM13,JPEG DHT memory" hexmask.long.byte 0x344 24.--31. 1. "DATA55,Huffman table data 55" hexmask.long.byte 0x344 16.--23. 1. "DATA54,Huffman table data 54" newline hexmask.long.byte 0x344 8.--15. 1. "DATA53,Huffman table data 53" hexmask.long.byte 0x344 0.--7. 1. "DATA52,Huffman table data 52" line.long 0x348 "JPEG_DHTMEM14,JPEG DHT memory" hexmask.long.byte 0x348 24.--31. 1. "DATA59,Huffman table data 59" hexmask.long.byte 0x348 16.--23. 1. "DATA58,Huffman table data 58" newline hexmask.long.byte 0x348 8.--15. 1. "DATA57,Huffman table data 57" hexmask.long.byte 0x348 0.--7. 1. "DATA56,Huffman table data 56" line.long 0x34C "JPEG_DHTMEM15,JPEG DHT memory" hexmask.long.byte 0x34C 24.--31. 1. "DATA63,Huffman table data 63" hexmask.long.byte 0x34C 16.--23. 1. "DATA62,Huffman table data 62" newline hexmask.long.byte 0x34C 8.--15. 1. "DATA61,Huffman table data 61" hexmask.long.byte 0x34C 0.--7. 1. "DATA60,Huffman table data 60" line.long 0x350 "JPEG_DHTMEM16,JPEG DHT memory" hexmask.long.byte 0x350 24.--31. 1. "DATA67,Huffman table data 67" hexmask.long.byte 0x350 16.--23. 1. "DATA66,Huffman table data 66" newline hexmask.long.byte 0x350 8.--15. 1. "DATA65,Huffman table data 65" hexmask.long.byte 0x350 0.--7. 1. "DATA64,Huffman table data 64" line.long 0x354 "JPEG_DHTMEM17,JPEG DHT memory" hexmask.long.byte 0x354 24.--31. 1. "DATA71,Huffman table data 71" hexmask.long.byte 0x354 16.--23. 1. "DATA70,Huffman table data 70" newline hexmask.long.byte 0x354 8.--15. 1. "DATA69,Huffman table data 69" hexmask.long.byte 0x354 0.--7. 1. "DATA68,Huffman table data 68" line.long 0x358 "JPEG_DHTMEM18,JPEG DHT memory" hexmask.long.byte 0x358 24.--31. 1. "DATA75,Huffman table data 75" hexmask.long.byte 0x358 16.--23. 1. "DATA74,Huffman table data 74" newline hexmask.long.byte 0x358 8.--15. 1. "DATA73,Huffman table data 73" hexmask.long.byte 0x358 0.--7. 1. "DATA72,Huffman table data 72" line.long 0x35C "JPEG_DHTMEM19,JPEG DHT memory" hexmask.long.byte 0x35C 24.--31. 1. "DATA79,Huffman table data 79" hexmask.long.byte 0x35C 16.--23. 1. "DATA78,Huffman table data 78" newline hexmask.long.byte 0x35C 8.--15. 1. "DATA77,Huffman table data 77" hexmask.long.byte 0x35C 0.--7. 1. "DATA76,Huffman table data 76" line.long 0x360 "JPEG_DHTMEM20,JPEG DHT memory" hexmask.long.byte 0x360 24.--31. 1. "DATA83,Huffman table data 83" hexmask.long.byte 0x360 16.--23. 1. "DATA82,Huffman table data 82" newline hexmask.long.byte 0x360 8.--15. 1. "DATA81,Huffman table data 81" hexmask.long.byte 0x360 0.--7. 1. "DATA80,Huffman table data 80" line.long 0x364 "JPEG_DHTMEM21,JPEG DHT memory" hexmask.long.byte 0x364 24.--31. 1. "DATA87,Huffman table data 87" hexmask.long.byte 0x364 16.--23. 1. "DATA86,Huffman table data 86" newline hexmask.long.byte 0x364 8.--15. 1. "DATA85,Huffman table data 85" hexmask.long.byte 0x364 0.--7. 1. "DATA84,Huffman table data 84" line.long 0x368 "JPEG_DHTMEM22,JPEG DHT memory" hexmask.long.byte 0x368 24.--31. 1. "DATA91,Huffman table data 91" hexmask.long.byte 0x368 16.--23. 1. "DATA90,Huffman table data 90" newline hexmask.long.byte 0x368 8.--15. 1. "DATA89,Huffman table data 89" hexmask.long.byte 0x368 0.--7. 1. "DATA88,Huffman table data 88" line.long 0x36C "JPEG_DHTMEM23,JPEG DHT memory" hexmask.long.byte 0x36C 24.--31. 1. "DATA95,Huffman table data 95" hexmask.long.byte 0x36C 16.--23. 1. "DATA94,Huffman table data 94" newline hexmask.long.byte 0x36C 8.--15. 1. "DATA93,Huffman table data 93" hexmask.long.byte 0x36C 0.--7. 1. "DATA92,Huffman table data 92" line.long 0x370 "JPEG_DHTMEM24,JPEG DHT memory" hexmask.long.byte 0x370 24.--31. 1. "DATA99,Huffman table data 99" hexmask.long.byte 0x370 16.--23. 1. "DATA98,Huffman table data 98" newline hexmask.long.byte 0x370 8.--15. 1. "DATA97,Huffman table data 97" hexmask.long.byte 0x370 0.--7. 1. "DATA96,Huffman table data 96" line.long 0x374 "JPEG_DHTMEM25,JPEG DHT memory" hexmask.long.byte 0x374 24.--31. 1. "DATA103,Huffman table data 103" hexmask.long.byte 0x374 16.--23. 1. "DATA102,Huffman table data 102" newline hexmask.long.byte 0x374 8.--15. 1. "DATA101,Huffman table data 101" hexmask.long.byte 0x374 0.--7. 1. "DATA100,Huffman table data 100" line.long 0x378 "JPEG_DHTMEM26,JPEG DHT memory" hexmask.long.byte 0x378 24.--31. 1. "DATA107,Huffman table data 107" hexmask.long.byte 0x378 16.--23. 1. "DATA106,Huffman table data 106" newline hexmask.long.byte 0x378 8.--15. 1. "DATA105,Huffman table data 105" hexmask.long.byte 0x378 0.--7. 1. "DATA104,Huffman table data 104" line.long 0x37C "JPEG_DHTMEM27,JPEG DHT memory" hexmask.long.byte 0x37C 24.--31. 1. "DATA111,Huffman table data 111" hexmask.long.byte 0x37C 16.--23. 1. "DATA110,Huffman table data 110" newline hexmask.long.byte 0x37C 8.--15. 1. "DATA109,Huffman table data 109" hexmask.long.byte 0x37C 0.--7. 1. "DATA108,Huffman table data 108" line.long 0x380 "JPEG_DHTMEM28,JPEG DHT memory" hexmask.long.byte 0x380 24.--31. 1. "DATA115,Huffman table data 115" hexmask.long.byte 0x380 16.--23. 1. "DATA114,Huffman table data 114" newline hexmask.long.byte 0x380 8.--15. 1. "DATA113,Huffman table data 113" hexmask.long.byte 0x380 0.--7. 1. "DATA112,Huffman table data 112" line.long 0x384 "JPEG_DHTMEM29,JPEG DHT memory" hexmask.long.byte 0x384 24.--31. 1. "DATA119,Huffman table data 119" hexmask.long.byte 0x384 16.--23. 1. "DATA118,Huffman table data 118" newline hexmask.long.byte 0x384 8.--15. 1. "DATA117,Huffman table data 117" hexmask.long.byte 0x384 0.--7. 1. "DATA116,Huffman table data 116" line.long 0x388 "JPEG_DHTMEM30,JPEG DHT memory" hexmask.long.byte 0x388 24.--31. 1. "DATA123,Huffman table data 123" hexmask.long.byte 0x388 16.--23. 1. "DATA122,Huffman table data 122" newline hexmask.long.byte 0x388 8.--15. 1. "DATA121,Huffman table data 121" hexmask.long.byte 0x388 0.--7. 1. "DATA120,Huffman table data 120" line.long 0x38C "JPEG_DHTMEM31,JPEG DHT memory" hexmask.long.byte 0x38C 24.--31. 1. "DATA127,Huffman table data 127" hexmask.long.byte 0x38C 16.--23. 1. "DATA126,Huffman table data 126" newline hexmask.long.byte 0x38C 8.--15. 1. "DATA125,Huffman table data 125" hexmask.long.byte 0x38C 0.--7. 1. "DATA124,Huffman table data 124" line.long 0x390 "JPEG_DHTMEM32,JPEG DHT memory" hexmask.long.byte 0x390 24.--31. 1. "DATA131,Huffman table data 131" hexmask.long.byte 0x390 16.--23. 1. "DATA130,Huffman table data 130" newline hexmask.long.byte 0x390 8.--15. 1. "DATA129,Huffman table data 129" hexmask.long.byte 0x390 0.--7. 1. "DATA128,Huffman table data 128" line.long 0x394 "JPEG_DHTMEM33,JPEG DHT memory" hexmask.long.byte 0x394 24.--31. 1. "DATA135,Huffman table data 135" hexmask.long.byte 0x394 16.--23. 1. "DATA134,Huffman table data 134" newline hexmask.long.byte 0x394 8.--15. 1. "DATA133,Huffman table data 133" hexmask.long.byte 0x394 0.--7. 1. "DATA132,Huffman table data 132" line.long 0x398 "JPEG_DHTMEM34,JPEG DHT memory" hexmask.long.byte 0x398 24.--31. 1. "DATA139,Huffman table data 139" hexmask.long.byte 0x398 16.--23. 1. "DATA138,Huffman table data 138" newline hexmask.long.byte 0x398 8.--15. 1. "DATA137,Huffman table data 137" hexmask.long.byte 0x398 0.--7. 1. "DATA136,Huffman table data 136" line.long 0x39C "JPEG_DHTMEM35,JPEG DHT memory" hexmask.long.byte 0x39C 24.--31. 1. "DATA143,Huffman table data 143" hexmask.long.byte 0x39C 16.--23. 1. "DATA142,Huffman table data 142" newline hexmask.long.byte 0x39C 8.--15. 1. "DATA141,Huffman table data 141" hexmask.long.byte 0x39C 0.--7. 1. "DATA140,Huffman table data 140" line.long 0x3A0 "JPEG_DHTMEM36,JPEG DHT memory" hexmask.long.byte 0x3A0 24.--31. 1. "DATA147,Huffman table data 147" hexmask.long.byte 0x3A0 16.--23. 1. "DATA146,Huffman table data 146" newline hexmask.long.byte 0x3A0 8.--15. 1. "DATA145,Huffman table data 145" hexmask.long.byte 0x3A0 0.--7. 1. "DATA144,Huffman table data 144" line.long 0x3A4 "JPEG_DHTMEM37,JPEG DHT memory" hexmask.long.byte 0x3A4 24.--31. 1. "DATA151,Huffman table data 151" hexmask.long.byte 0x3A4 16.--23. 1. "DATA150,Huffman table data 150" newline hexmask.long.byte 0x3A4 8.--15. 1. "DATA149,Huffman table data 149" hexmask.long.byte 0x3A4 0.--7. 1. "DATA148,Huffman table data 148" line.long 0x3A8 "JPEG_DHTMEM38,JPEG DHT memory" hexmask.long.byte 0x3A8 24.--31. 1. "DATA155,Huffman table data 155" hexmask.long.byte 0x3A8 16.--23. 1. "DATA154,Huffman table data 154" newline hexmask.long.byte 0x3A8 8.--15. 1. "DATA153,Huffman table data 153" hexmask.long.byte 0x3A8 0.--7. 1. "DATA152,Huffman table data 152" line.long 0x3AC "JPEG_DHTMEM39,JPEG DHT memory" hexmask.long.byte 0x3AC 24.--31. 1. "DATA159,Huffman table data 159" hexmask.long.byte 0x3AC 16.--23. 1. "DATA158,Huffman table data 158" newline hexmask.long.byte 0x3AC 8.--15. 1. "DATA157,Huffman table data 157" hexmask.long.byte 0x3AC 0.--7. 1. "DATA156,Huffman table data 156" line.long 0x3B0 "JPEG_DHTMEM40,JPEG DHT memory" hexmask.long.byte 0x3B0 24.--31. 1. "DATA163,Huffman table data 163" hexmask.long.byte 0x3B0 16.--23. 1. "DATA162,Huffman table data 162" newline hexmask.long.byte 0x3B0 8.--15. 1. "DATA161,Huffman table data 161" hexmask.long.byte 0x3B0 0.--7. 1. "DATA160,Huffman table data 160" line.long 0x3B4 "JPEG_DHTMEM41,JPEG DHT memory" hexmask.long.byte 0x3B4 24.--31. 1. "DATA167,Huffman table data 167" hexmask.long.byte 0x3B4 16.--23. 1. "DATA166,Huffman table data 166" newline hexmask.long.byte 0x3B4 8.--15. 1. "DATA165,Huffman table data 165" hexmask.long.byte 0x3B4 0.--7. 1. "DATA164,Huffman table data 164" line.long 0x3B8 "JPEG_DHTMEM42,JPEG DHT memory" hexmask.long.byte 0x3B8 24.--31. 1. "DATA171,Huffman table data 171" hexmask.long.byte 0x3B8 16.--23. 1. "DATA170,Huffman table data 170" newline hexmask.long.byte 0x3B8 8.--15. 1. "DATA169,Huffman table data 169" hexmask.long.byte 0x3B8 0.--7. 1. "DATA168,Huffman table data 168" line.long 0x3BC "JPEG_DHTMEM43,JPEG DHT memory" hexmask.long.byte 0x3BC 24.--31. 1. "DATA175,Huffman table data 175" hexmask.long.byte 0x3BC 16.--23. 1. "DATA174,Huffman table data 174" newline hexmask.long.byte 0x3BC 8.--15. 1. "DATA173,Huffman table data 173" hexmask.long.byte 0x3BC 0.--7. 1. "DATA172,Huffman table data 172" line.long 0x3C0 "JPEG_DHTMEM44,JPEG DHT memory" hexmask.long.byte 0x3C0 24.--31. 1. "DATA179,Huffman table data 179" hexmask.long.byte 0x3C0 16.--23. 1. "DATA178,Huffman table data 178" newline hexmask.long.byte 0x3C0 8.--15. 1. "DATA177,Huffman table data 177" hexmask.long.byte 0x3C0 0.--7. 1. "DATA176,Huffman table data 176" line.long 0x3C4 "JPEG_DHTMEM45,JPEG DHT memory" hexmask.long.byte 0x3C4 24.--31. 1. "DATA183,Huffman table data 183" hexmask.long.byte 0x3C4 16.--23. 1. "DATA182,Huffman table data 182" newline hexmask.long.byte 0x3C4 8.--15. 1. "DATA181,Huffman table data 181" hexmask.long.byte 0x3C4 0.--7. 1. "DATA180,Huffman table data 180" line.long 0x3C8 "JPEG_DHTMEM46,JPEG DHT memory" hexmask.long.byte 0x3C8 24.--31. 1. "DATA187,Huffman table data 187" hexmask.long.byte 0x3C8 16.--23. 1. "DATA186,Huffman table data 186" newline hexmask.long.byte 0x3C8 8.--15. 1. "DATA185,Huffman table data 185" hexmask.long.byte 0x3C8 0.--7. 1. "DATA184,Huffman table data 184" line.long 0x3CC "JPEG_DHTMEM47,JPEG DHT memory" hexmask.long.byte 0x3CC 24.--31. 1. "DATA191,Huffman table data 191" hexmask.long.byte 0x3CC 16.--23. 1. "DATA190,Huffman table data 190" newline hexmask.long.byte 0x3CC 8.--15. 1. "DATA189,Huffman table data 189" hexmask.long.byte 0x3CC 0.--7. 1. "DATA188,Huffman table data 188" line.long 0x3D0 "JPEG_DHTMEM48,JPEG DHT memory" hexmask.long.byte 0x3D0 24.--31. 1. "DATA195,Huffman table data 195" hexmask.long.byte 0x3D0 16.--23. 1. "DATA194,Huffman table data 194" newline hexmask.long.byte 0x3D0 8.--15. 1. "DATA193,Huffman table data 193" hexmask.long.byte 0x3D0 0.--7. 1. "DATA192,Huffman table data 192" line.long 0x3D4 "JPEG_DHTMEM49,JPEG DHT memory" hexmask.long.byte 0x3D4 24.--31. 1. "DATA199,Huffman table data 199" hexmask.long.byte 0x3D4 16.--23. 1. "DATA198,Huffman table data 198" newline hexmask.long.byte 0x3D4 8.--15. 1. "DATA197,Huffman table data 197" hexmask.long.byte 0x3D4 0.--7. 1. "DATA196,Huffman table data 196" line.long 0x3D8 "JPEG_DHTMEM50,JPEG DHT memory" hexmask.long.byte 0x3D8 24.--31. 1. "DATA203,Huffman table data 203" hexmask.long.byte 0x3D8 16.--23. 1. "DATA202,Huffman table data 202" newline hexmask.long.byte 0x3D8 8.--15. 1. "DATA201,Huffman table data 201" hexmask.long.byte 0x3D8 0.--7. 1. "DATA200,Huffman table data 200" line.long 0x3DC "JPEG_DHTMEM51,JPEG DHT memory" hexmask.long.byte 0x3DC 24.--31. 1. "DATA207,Huffman table data 207" hexmask.long.byte 0x3DC 16.--23. 1. "DATA206,Huffman table data 206" newline hexmask.long.byte 0x3DC 8.--15. 1. "DATA205,Huffman table data 205" hexmask.long.byte 0x3DC 0.--7. 1. "DATA204,Huffman table data 204" line.long 0x3E0 "JPEG_DHTMEM52,JPEG DHT memory" hexmask.long.byte 0x3E0 24.--31. 1. "DATA211,Huffman table data 211" hexmask.long.byte 0x3E0 16.--23. 1. "DATA210,Huffman table data 210" newline hexmask.long.byte 0x3E0 8.--15. 1. "DATA209,Huffman table data 209" hexmask.long.byte 0x3E0 0.--7. 1. "DATA208,Huffman table data 208" line.long 0x3E4 "JPEG_DHTMEM53,JPEG DHT memory" hexmask.long.byte 0x3E4 24.--31. 1. "DATA215,Huffman table data 215" hexmask.long.byte 0x3E4 16.--23. 1. "DATA214,Huffman table data 214" newline hexmask.long.byte 0x3E4 8.--15. 1. "DATA213,Huffman table data 213" hexmask.long.byte 0x3E4 0.--7. 1. "DATA212,Huffman table data 212" line.long 0x3E8 "JPEG_DHTMEM54,JPEG DHT memory" hexmask.long.byte 0x3E8 24.--31. 1. "DATA219,Huffman table data 219" hexmask.long.byte 0x3E8 16.--23. 1. "DATA218,Huffman table data 218" newline hexmask.long.byte 0x3E8 8.--15. 1. "DATA217,Huffman table data 217" hexmask.long.byte 0x3E8 0.--7. 1. "DATA216,Huffman table data 216" line.long 0x3EC "JPEG_DHTMEM55,JPEG DHT memory" hexmask.long.byte 0x3EC 24.--31. 1. "DATA223,Huffman table data 223" hexmask.long.byte 0x3EC 16.--23. 1. "DATA222,Huffman table data 222" newline hexmask.long.byte 0x3EC 8.--15. 1. "DATA221,Huffman table data 221" hexmask.long.byte 0x3EC 0.--7. 1. "DATA220,Huffman table data 220" line.long 0x3F0 "JPEG_DHTMEM56,JPEG DHT memory" hexmask.long.byte 0x3F0 24.--31. 1. "DATA227,Huffman table data 227" hexmask.long.byte 0x3F0 16.--23. 1. "DATA226,Huffman table data 226" newline hexmask.long.byte 0x3F0 8.--15. 1. "DATA225,Huffman table data 225" hexmask.long.byte 0x3F0 0.--7. 1. "DATA224,Huffman table data 224" line.long 0x3F4 "JPEG_DHTMEM57,JPEG DHT memory" hexmask.long.byte 0x3F4 24.--31. 1. "DATA231,Huffman table data 231" hexmask.long.byte 0x3F4 16.--23. 1. "DATA230,Huffman table data 230" newline hexmask.long.byte 0x3F4 8.--15. 1. "DATA229,Huffman table data 229" hexmask.long.byte 0x3F4 0.--7. 1. "DATA228,Huffman table data 228" line.long 0x3F8 "JPEG_DHTMEM58,JPEG DHT memory" hexmask.long.byte 0x3F8 24.--31. 1. "DATA235,Huffman table data 235" hexmask.long.byte 0x3F8 16.--23. 1. "DATA234,Huffman table data 234" newline hexmask.long.byte 0x3F8 8.--15. 1. "DATA233,Huffman table data 233" hexmask.long.byte 0x3F8 0.--7. 1. "DATA232,Huffman table data 232" line.long 0x3FC "JPEG_DHTMEM59,JPEG DHT memory" hexmask.long.byte 0x3FC 24.--31. 1. "DATA239,Huffman table data 239" hexmask.long.byte 0x3FC 16.--23. 1. "DATA238,Huffman table data 238" newline hexmask.long.byte 0x3FC 8.--15. 1. "DATA237,Huffman table data 237" hexmask.long.byte 0x3FC 0.--7. 1. "DATA236,Huffman table data 236" line.long 0x400 "JPEG_DHTMEM60,JPEG DHT memory" hexmask.long.byte 0x400 24.--31. 1. "DATA243,Huffman table data 243" hexmask.long.byte 0x400 16.--23. 1. "DATA242,Huffman table data 242" newline hexmask.long.byte 0x400 8.--15. 1. "DATA241,Huffman table data 241" hexmask.long.byte 0x400 0.--7. 1. "DATA240,Huffman table data 240" line.long 0x404 "JPEG_DHTMEM61,JPEG DHT memory" hexmask.long.byte 0x404 24.--31. 1. "DATA247,Huffman table data 247" hexmask.long.byte 0x404 16.--23. 1. "DATA246,Huffman table data 246" newline hexmask.long.byte 0x404 8.--15. 1. "DATA245,Huffman table data 245" hexmask.long.byte 0x404 0.--7. 1. "DATA244,Huffman table data 244" line.long 0x408 "JPEG_DHTMEM62,JPEG DHT memory" hexmask.long.byte 0x408 24.--31. 1. "DATA251,Huffman table data 251" hexmask.long.byte 0x408 16.--23. 1. "DATA250,Huffman table data 250" newline hexmask.long.byte 0x408 8.--15. 1. "DATA249,Huffman table data 249" hexmask.long.byte 0x408 0.--7. 1. "DATA248,Huffman table data 248" line.long 0x40C "JPEG_DHTMEM63,JPEG DHT memory" hexmask.long.byte 0x40C 24.--31. 1. "DATA255,Huffman table data 255" hexmask.long.byte 0x40C 16.--23. 1. "DATA254,Huffman table data 254" newline hexmask.long.byte 0x40C 8.--15. 1. "DATA253,Huffman table data 253" hexmask.long.byte 0x40C 0.--7. 1. "DATA252,Huffman table data 252" line.long 0x410 "JPEG_DHTMEM64,JPEG DHT memory" hexmask.long.byte 0x410 24.--31. 1. "DATA259,Huffman table data 259" hexmask.long.byte 0x410 16.--23. 1. "DATA258,Huffman table data 258" newline hexmask.long.byte 0x410 8.--15. 1. "DATA257,Huffman table data 257" hexmask.long.byte 0x410 0.--7. 1. "DATA256,Huffman table data 256" line.long 0x414 "JPEG_DHTMEM65,JPEG DHT memory" hexmask.long.byte 0x414 24.--31. 1. "DATA263,Huffman table data 263" hexmask.long.byte 0x414 16.--23. 1. "DATA262,Huffman table data 262" newline hexmask.long.byte 0x414 8.--15. 1. "DATA261,Huffman table data 261" hexmask.long.byte 0x414 0.--7. 1. "DATA260,Huffman table data 260" line.long 0x418 "JPEG_DHTMEM66,JPEG DHT memory" hexmask.long.byte 0x418 24.--31. 1. "DATA267,Huffman table data 267" hexmask.long.byte 0x418 16.--23. 1. "DATA266,Huffman table data 266" newline hexmask.long.byte 0x418 8.--15. 1. "DATA265,Huffman table data 265" hexmask.long.byte 0x418 0.--7. 1. "DATA264,Huffman table data 264" line.long 0x41C "JPEG_DHTMEM67,JPEG DHT memory" hexmask.long.byte 0x41C 24.--31. 1. "DATA271,Huffman table data 271" hexmask.long.byte 0x41C 16.--23. 1. "DATA270,Huffman table data 270" newline hexmask.long.byte 0x41C 8.--15. 1. "DATA269,Huffman table data 269" hexmask.long.byte 0x41C 0.--7. 1. "DATA268,Huffman table data 268" line.long 0x420 "JPEG_DHTMEM68,JPEG DHT memory" hexmask.long.byte 0x420 24.--31. 1. "DATA275,Huffman table data 275" hexmask.long.byte 0x420 16.--23. 1. "DATA274,Huffman table data 274" newline hexmask.long.byte 0x420 8.--15. 1. "DATA273,Huffman table data 273" hexmask.long.byte 0x420 0.--7. 1. "DATA272,Huffman table data 272" line.long 0x424 "JPEG_DHTMEM69,JPEG DHT memory" hexmask.long.byte 0x424 24.--31. 1. "DATA279,Huffman table data 279" hexmask.long.byte 0x424 16.--23. 1. "DATA278,Huffman table data 278" newline hexmask.long.byte 0x424 8.--15. 1. "DATA277,Huffman table data 277" hexmask.long.byte 0x424 0.--7. 1. "DATA276,Huffman table data 276" line.long 0x428 "JPEG_DHTMEM70,JPEG DHT memory" hexmask.long.byte 0x428 24.--31. 1. "DATA283,Huffman table data 283" hexmask.long.byte 0x428 16.--23. 1. "DATA282,Huffman table data 282" newline hexmask.long.byte 0x428 8.--15. 1. "DATA281,Huffman table data 281" hexmask.long.byte 0x428 0.--7. 1. "DATA280,Huffman table data 280" line.long 0x42C "JPEG_DHTMEM71,JPEG DHT memory" hexmask.long.byte 0x42C 24.--31. 1. "DATA287,Huffman table data 287" hexmask.long.byte 0x42C 16.--23. 1. "DATA286,Huffman table data 286" newline hexmask.long.byte 0x42C 8.--15. 1. "DATA285,Huffman table data 285" hexmask.long.byte 0x42C 0.--7. 1. "DATA284,Huffman table data 284" line.long 0x430 "JPEG_DHTMEM72,JPEG DHT memory" hexmask.long.byte 0x430 24.--31. 1. "DATA291,Huffman table data 291" hexmask.long.byte 0x430 16.--23. 1. "DATA290,Huffman table data 290" newline hexmask.long.byte 0x430 8.--15. 1. "DATA289,Huffman table data 289" hexmask.long.byte 0x430 0.--7. 1. "DATA288,Huffman table data 288" line.long 0x434 "JPEG_DHTMEM73,JPEG DHT memory" hexmask.long.byte 0x434 24.--31. 1. "DATA295,Huffman table data 295" hexmask.long.byte 0x434 16.--23. 1. "DATA294,Huffman table data 294" newline hexmask.long.byte 0x434 8.--15. 1. "DATA293,Huffman table data 293" hexmask.long.byte 0x434 0.--7. 1. "DATA292,Huffman table data 292" line.long 0x438 "JPEG_DHTMEM74,JPEG DHT memory" hexmask.long.byte 0x438 24.--31. 1. "DATA299,Huffman table data 299" hexmask.long.byte 0x438 16.--23. 1. "DATA298,Huffman table data 298" newline hexmask.long.byte 0x438 8.--15. 1. "DATA297,Huffman table data 297" hexmask.long.byte 0x438 0.--7. 1. "DATA296,Huffman table data 296" line.long 0x43C "JPEG_DHTMEM75,JPEG DHT memory" hexmask.long.byte 0x43C 24.--31. 1. "DATA303,Huffman table data 303" hexmask.long.byte 0x43C 16.--23. 1. "DATA302,Huffman table data 302" newline hexmask.long.byte 0x43C 8.--15. 1. "DATA301,Huffman table data 301" hexmask.long.byte 0x43C 0.--7. 1. "DATA300,Huffman table data 300" line.long 0x440 "JPEG_DHTMEM76,JPEG DHT memory" hexmask.long.byte 0x440 24.--31. 1. "DATA307,Huffman table data 307" hexmask.long.byte 0x440 16.--23. 1. "DATA306,Huffman table data 306" newline hexmask.long.byte 0x440 8.--15. 1. "DATA305,Huffman table data 305" hexmask.long.byte 0x440 0.--7. 1. "DATA304,Huffman table data 304" line.long 0x444 "JPEG_DHTMEM77,JPEG DHT memory" hexmask.long.byte 0x444 24.--31. 1. "DATA311,Huffman table data 311" hexmask.long.byte 0x444 16.--23. 1. "DATA310,Huffman table data 310" newline hexmask.long.byte 0x444 8.--15. 1. "DATA309,Huffman table data 309" hexmask.long.byte 0x444 0.--7. 1. "DATA308,Huffman table data 308" line.long 0x448 "JPEG_DHTMEM78,JPEG DHT memory" hexmask.long.byte 0x448 24.--31. 1. "DATA315,Huffman table data 315" hexmask.long.byte 0x448 16.--23. 1. "DATA314,Huffman table data 314" newline hexmask.long.byte 0x448 8.--15. 1. "DATA313,Huffman table data 313" hexmask.long.byte 0x448 0.--7. 1. "DATA312,Huffman table data 312" line.long 0x44C "JPEG_DHTMEM79,JPEG DHT memory" hexmask.long.byte 0x44C 24.--31. 1. "DATA319,Huffman table data 319" hexmask.long.byte 0x44C 16.--23. 1. "DATA318,Huffman table data 318" newline hexmask.long.byte 0x44C 8.--15. 1. "DATA317,Huffman table data 317" hexmask.long.byte 0x44C 0.--7. 1. "DATA316,Huffman table data 316" line.long 0x450 "JPEG_DHTMEM80,JPEG DHT memory" hexmask.long.byte 0x450 24.--31. 1. "DATA323,Huffman table data 323" hexmask.long.byte 0x450 16.--23. 1. "DATA322,Huffman table data 322" newline hexmask.long.byte 0x450 8.--15. 1. "DATA321,Huffman table data 321" hexmask.long.byte 0x450 0.--7. 1. "DATA320,Huffman table data 320" line.long 0x454 "JPEG_DHTMEM81,JPEG DHT memory" hexmask.long.byte 0x454 24.--31. 1. "DATA327,Huffman table data 327" hexmask.long.byte 0x454 16.--23. 1. "DATA326,Huffman table data 326" newline hexmask.long.byte 0x454 8.--15. 1. "DATA325,Huffman table data 325" hexmask.long.byte 0x454 0.--7. 1. "DATA324,Huffman table data 324" line.long 0x458 "JPEG_DHTMEM82,JPEG DHT memory" hexmask.long.byte 0x458 24.--31. 1. "DATA331,Huffman table data 331" hexmask.long.byte 0x458 16.--23. 1. "DATA330,Huffman table data 330" newline hexmask.long.byte 0x458 8.--15. 1. "DATA329,Huffman table data 329" hexmask.long.byte 0x458 0.--7. 1. "DATA328,Huffman table data 328" line.long 0x45C "JPEG_DHTMEM83,JPEG DHT memory" hexmask.long.byte 0x45C 24.--31. 1. "DATA335,Huffman table data 335" hexmask.long.byte 0x45C 16.--23. 1. "DATA334,Huffman table data 334" newline hexmask.long.byte 0x45C 8.--15. 1. "DATA333,Huffman table data 333" hexmask.long.byte 0x45C 0.--7. 1. "DATA332,Huffman table data 332" line.long 0x460 "JPEG_DHTMEM84,JPEG DHT memory" hexmask.long.byte 0x460 24.--31. 1. "DATA339,Huffman table data 339" hexmask.long.byte 0x460 16.--23. 1. "DATA338,Huffman table data 338" newline hexmask.long.byte 0x460 8.--15. 1. "DATA337,Huffman table data 337" hexmask.long.byte 0x460 0.--7. 1. "DATA336,Huffman table data 336" line.long 0x464 "JPEG_DHTMEM85,JPEG DHT memory" hexmask.long.byte 0x464 24.--31. 1. "DATA343,Huffman table data 343" hexmask.long.byte 0x464 16.--23. 1. "DATA342,Huffman table data 342" newline hexmask.long.byte 0x464 8.--15. 1. "DATA341,Huffman table data 341" hexmask.long.byte 0x464 0.--7. 1. "DATA340,Huffman table data 340" line.long 0x468 "JPEG_DHTMEM86,JPEG DHT memory" hexmask.long.byte 0x468 24.--31. 1. "DATA347,Huffman table data 347" hexmask.long.byte 0x468 16.--23. 1. "DATA346,Huffman table data 346" newline hexmask.long.byte 0x468 8.--15. 1. "DATA345,Huffman table data 345" hexmask.long.byte 0x468 0.--7. 1. "DATA344,Huffman table data 344" line.long 0x46C "JPEG_DHTMEM87,JPEG DHT memory" hexmask.long.byte 0x46C 24.--31. 1. "DATA351,Huffman table data 351" hexmask.long.byte 0x46C 16.--23. 1. "DATA350,Huffman table data 350" newline hexmask.long.byte 0x46C 8.--15. 1. "DATA349,Huffman table data 349" hexmask.long.byte 0x46C 0.--7. 1. "DATA348,Huffman table data 348" line.long 0x470 "JPEG_DHTMEM88,JPEG DHT memory" hexmask.long.byte 0x470 24.--31. 1. "DATA355,Huffman table data 355" hexmask.long.byte 0x470 16.--23. 1. "DATA354,Huffman table data 354" newline hexmask.long.byte 0x470 8.--15. 1. "DATA353,Huffman table data 353" hexmask.long.byte 0x470 0.--7. 1. "DATA352,Huffman table data 352" line.long 0x474 "JPEG_DHTMEM89,JPEG DHT memory" hexmask.long.byte 0x474 24.--31. 1. "DATA359,Huffman table data 359" hexmask.long.byte 0x474 16.--23. 1. "DATA358,Huffman table data 358" newline hexmask.long.byte 0x474 8.--15. 1. "DATA357,Huffman table data 357" hexmask.long.byte 0x474 0.--7. 1. "DATA356,Huffman table data 356" line.long 0x478 "JPEG_DHTMEM90,JPEG DHT memory" hexmask.long.byte 0x478 24.--31. 1. "DATA363,Huffman table data 363" hexmask.long.byte 0x478 16.--23. 1. "DATA362,Huffman table data 362" newline hexmask.long.byte 0x478 8.--15. 1. "DATA361,Huffman table data 361" hexmask.long.byte 0x478 0.--7. 1. "DATA360,Huffman table data 360" line.long 0x47C "JPEG_DHTMEM91,JPEG DHT memory" hexmask.long.byte 0x47C 24.--31. 1. "DATA367,Huffman table data 367" hexmask.long.byte 0x47C 16.--23. 1. "DATA366,Huffman table data 366" newline hexmask.long.byte 0x47C 8.--15. 1. "DATA365,Huffman table data 365" hexmask.long.byte 0x47C 0.--7. 1. "DATA364,Huffman table data 364" line.long 0x480 "JPEG_DHTMEM92,JPEG DHT memory" hexmask.long.byte 0x480 24.--31. 1. "DATA371,Huffman table data 371" hexmask.long.byte 0x480 16.--23. 1. "DATA370,Huffman table data 370" newline hexmask.long.byte 0x480 8.--15. 1. "DATA369,Huffman table data 369" hexmask.long.byte 0x480 0.--7. 1. "DATA368,Huffman table data 368" line.long 0x484 "JPEG_DHTMEM93,JPEG DHT memory" hexmask.long.byte 0x484 24.--31. 1. "DATA375,Huffman table data 375" hexmask.long.byte 0x484 16.--23. 1. "DATA374,Huffman table data 374" newline hexmask.long.byte 0x484 8.--15. 1. "DATA373,Huffman table data 373" hexmask.long.byte 0x484 0.--7. 1. "DATA372,Huffman table data 372" line.long 0x488 "JPEG_DHTMEM94,JPEG DHT memory" hexmask.long.byte 0x488 24.--31. 1. "DATA379,Huffman table data 379" hexmask.long.byte 0x488 16.--23. 1. "DATA378,Huffman table data 378" newline hexmask.long.byte 0x488 8.--15. 1. "DATA377,Huffman table data 377" hexmask.long.byte 0x488 0.--7. 1. "DATA376,Huffman table data 376" line.long 0x48C "JPEG_DHTMEM95,JPEG DHT memory" hexmask.long.byte 0x48C 24.--31. 1. "DATA383,Huffman table data 383" hexmask.long.byte 0x48C 16.--23. 1. "DATA382,Huffman table data 382" newline hexmask.long.byte 0x48C 8.--15. 1. "DATA381,Huffman table data 381" hexmask.long.byte 0x48C 0.--7. 1. "DATA380,Huffman table data 380" line.long 0x490 "JPEG_DHTMEM96,JPEG DHT memory" hexmask.long.byte 0x490 24.--31. 1. "DATA387,Huffman table data 387" hexmask.long.byte 0x490 16.--23. 1. "DATA386,Huffman table data 386" newline hexmask.long.byte 0x490 8.--15. 1. "DATA385,Huffman table data 385" hexmask.long.byte 0x490 0.--7. 1. "DATA384,Huffman table data 384" line.long 0x494 "JPEG_DHTMEM97,JPEG DHT memory" hexmask.long.byte 0x494 24.--31. 1. "DATA391,Huffman table data 391" hexmask.long.byte 0x494 16.--23. 1. "DATA390,Huffman table data 390" newline hexmask.long.byte 0x494 8.--15. 1. "DATA389,Huffman table data 389" hexmask.long.byte 0x494 0.--7. 1. "DATA388,Huffman table data 388" line.long 0x498 "JPEG_DHTMEM98,JPEG DHT memory" hexmask.long.byte 0x498 24.--31. 1. "DATA395,Huffman table data 395" hexmask.long.byte 0x498 16.--23. 1. "DATA394,Huffman table data 394" newline hexmask.long.byte 0x498 8.--15. 1. "DATA393,Huffman table data 393" hexmask.long.byte 0x498 0.--7. 1. "DATA392,Huffman table data 392" line.long 0x49C "JPEG_DHTMEM99,JPEG DHT memory" hexmask.long.byte 0x49C 24.--31. 1. "DATA399,Huffman table data 399" hexmask.long.byte 0x49C 16.--23. 1. "DATA398,Huffman table data 398" newline hexmask.long.byte 0x49C 8.--15. 1. "DATA397,Huffman table data 397" hexmask.long.byte 0x49C 0.--7. 1. "DATA396,Huffman table data 396" line.long 0x4A0 "JPEG_DHTMEM100,JPEG DHT memory" hexmask.long.byte 0x4A0 24.--31. 1. "DATA403,Huffman table data 403" hexmask.long.byte 0x4A0 16.--23. 1. "DATA402,Huffman table data 402" newline hexmask.long.byte 0x4A0 8.--15. 1. "DATA401,Huffman table data 401" hexmask.long.byte 0x4A0 0.--7. 1. "DATA400,Huffman table data 400" line.long 0x4A4 "JPEG_DHTMEM101,JPEG DHT memory" hexmask.long.byte 0x4A4 24.--31. 1. "DATA407,Huffman table data 407" hexmask.long.byte 0x4A4 16.--23. 1. "DATA406,Huffman table data 406" newline hexmask.long.byte 0x4A4 8.--15. 1. "DATA405,Huffman table data 405" hexmask.long.byte 0x4A4 0.--7. 1. "DATA404,Huffman table data 404" line.long 0x4A8 "JPEG_DHTMEM102,JPEG DHT memory" hexmask.long.byte 0x4A8 24.--31. 1. "DATA411,Huffman table data 411" hexmask.long.byte 0x4A8 16.--23. 1. "DATA410,Huffman table data 410" newline hexmask.long.byte 0x4A8 8.--15. 1. "DATA409,Huffman table data 409" hexmask.long.byte 0x4A8 0.--7. 1. "DATA408,Huffman table data 408" group.long 0x500++0xDF line.long 0x0 "JPEG_HUFFENC_AC0_0,JPEG Huffman encoder AC0" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_AC0_1,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x8 "JPEG_HUFFENC_AC0_2,JPEG Huffman encoder AC0" hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0xC "JPEG_HUFFENC_AC0_3,JPEG Huffman encoder AC0" hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x10 "JPEG_HUFFENC_AC0_4,JPEG Huffman encoder AC0" hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x14 "JPEG_HUFFENC_AC0_5,JPEG Huffman encoder AC0" hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x18 "JPEG_HUFFENC_AC0_6,JPEG Huffman encoder AC0" hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x1C "JPEG_HUFFENC_AC0_7,JPEG Huffman encoder AC0" hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x20 "JPEG_HUFFENC_AC0_8,JPEG Huffman encoder AC0" hexmask.long.byte 0x20 24.--27. 1. "HLEN17,Huffman length 17" hexmask.long.byte 0x20 16.--23. 1. "HCODE17,Huffman code 17" newline hexmask.long.byte 0x20 8.--11. 1. "HLEN16,Huffman length 16" hexmask.long.byte 0x20 0.--7. 1. "HCODE16,Huffman code 16" line.long 0x24 "JPEG_HUFFENC_AC0_9,JPEG Huffman encoder AC0" hexmask.long.byte 0x24 24.--27. 1. "HLEN19,Huffman length 19" hexmask.long.byte 0x24 16.--23. 1. "HCODE19,Huffman code 19" newline hexmask.long.byte 0x24 8.--11. 1. "HLEN18,Huffman length 18" hexmask.long.byte 0x24 0.--7. 1. "HCODE18,Huffman code 18" line.long 0x28 "JPEG_HUFFENC_AC0_10,JPEG Huffman encoder AC0" hexmask.long.byte 0x28 24.--27. 1. "HLEN21,Huffman length 21" hexmask.long.byte 0x28 16.--23. 1. "HCODE21,Huffman code 21" newline hexmask.long.byte 0x28 8.--11. 1. "HLEN20,Huffman length 20" hexmask.long.byte 0x28 0.--7. 1. "HCODE20,Huffman code 20" line.long 0x2C "JPEG_HUFFENC_AC0_11,JPEG Huffman encoder AC0" hexmask.long.byte 0x2C 24.--27. 1. "HLEN23,Huffman length 23" hexmask.long.byte 0x2C 16.--23. 1. "HCODE23,Huffman code 23" newline hexmask.long.byte 0x2C 8.--11. 1. "HLEN22,Huffman length 22" hexmask.long.byte 0x2C 0.--7. 1. "HCODE22,Huffman code 22" line.long 0x30 "JPEG_HUFFENC_AC0_12,JPEG Huffman encoder AC0" hexmask.long.byte 0x30 24.--27. 1. "HLEN25,Huffman length 25" hexmask.long.byte 0x30 16.--23. 1. "HCODE25,Huffman code 25" newline hexmask.long.byte 0x30 8.--11. 1. "HLEN24,Huffman length 24" hexmask.long.byte 0x30 0.--7. 1. "HCODE24,Huffman code 24" line.long 0x34 "JPEG_HUFFENC_AC0_13,JPEG Huffman encoder AC0" hexmask.long.byte 0x34 24.--27. 1. "HLEN27,Huffman length 27" hexmask.long.byte 0x34 16.--23. 1. "HCODE27,Huffman code 27" newline hexmask.long.byte 0x34 8.--11. 1. "HLEN26,Huffman length 26" hexmask.long.byte 0x34 0.--7. 1. "HCODE26,Huffman code 26" line.long 0x38 "JPEG_HUFFENC_AC0_14,JPEG Huffman encoder AC0" hexmask.long.byte 0x38 24.--27. 1. "HLEN29,Huffman length 29" hexmask.long.byte 0x38 16.--23. 1. "HCODE29,Huffman code 29" newline hexmask.long.byte 0x38 8.--11. 1. "HLEN28,Huffman length 28" hexmask.long.byte 0x38 0.--7. 1. "HCODE28,Huffman code 28" line.long 0x3C "JPEG_HUFFENC_AC0_15,JPEG Huffman encoder AC0" hexmask.long.byte 0x3C 24.--27. 1. "HLEN31,Huffman length 31" hexmask.long.byte 0x3C 16.--23. 1. "HCODE31,Huffman code 31" newline hexmask.long.byte 0x3C 8.--11. 1. "HLEN30,Huffman length 30" hexmask.long.byte 0x3C 0.--7. 1. "HCODE30,Huffman code 30" line.long 0x40 "JPEG_HUFFENC_AC0_16,JPEG Huffman encoder AC0" hexmask.long.byte 0x40 24.--27. 1. "HLEN33,Huffman length 33" hexmask.long.byte 0x40 16.--23. 1. "HCODE33,Huffman code 33" newline hexmask.long.byte 0x40 8.--11. 1. "HLEN32,Huffman length 32" hexmask.long.byte 0x40 0.--7. 1. "HCODE32,Huffman code 32" line.long 0x44 "JPEG_HUFFENC_AC0_17,JPEG Huffman encoder AC0" hexmask.long.byte 0x44 24.--27. 1. "HLEN35,Huffman length 35" hexmask.long.byte 0x44 16.--23. 1. "HCODE35,Huffman code 35" newline hexmask.long.byte 0x44 8.--11. 1. "HLEN34,Huffman length 34" hexmask.long.byte 0x44 0.--7. 1. "HCODE34,Huffman code 34" line.long 0x48 "JPEG_HUFFENC_AC0_18,JPEG Huffman encoder AC0" hexmask.long.byte 0x48 24.--27. 1. "HLEN37,Huffman length 37" hexmask.long.byte 0x48 16.--23. 1. "HCODE37,Huffman code 37" newline hexmask.long.byte 0x48 8.--11. 1. "HLEN36,Huffman length 36" hexmask.long.byte 0x48 0.--7. 1. "HCODE36,Huffman code 36" line.long 0x4C "JPEG_HUFFENC_AC0_19,JPEG Huffman encoder AC0" hexmask.long.byte 0x4C 24.--27. 1. "HLEN39,Huffman length 39" hexmask.long.byte 0x4C 16.--23. 1. "HCODE39,Huffman code 39" newline hexmask.long.byte 0x4C 8.--11. 1. "HLEN38,Huffman length 38" hexmask.long.byte 0x4C 0.--7. 1. "HCODE38,Huffman code 38" line.long 0x50 "JPEG_HUFFENC_AC0_20,JPEG Huffman encoder AC0" hexmask.long.byte 0x50 24.--27. 1. "HLEN41,Huffman length 41" hexmask.long.byte 0x50 16.--23. 1. "HCODE41,Huffman code 41" newline hexmask.long.byte 0x50 8.--11. 1. "HLEN40,Huffman length 40" hexmask.long.byte 0x50 0.--7. 1. "HCODE40,Huffman code 40" line.long 0x54 "JPEG_HUFFENC_AC0_21,JPEG Huffman encoder AC0" hexmask.long.byte 0x54 24.--27. 1. "HLEN43,Huffman length 43" hexmask.long.byte 0x54 16.--23. 1. "HCODE43,Huffman code 43" newline hexmask.long.byte 0x54 8.--11. 1. "HLEN42,Huffman length 42" hexmask.long.byte 0x54 0.--7. 1. "HCODE42,Huffman code 42" line.long 0x58 "JPEG_HUFFENC_AC0_22,JPEG Huffman encoder AC0" hexmask.long.byte 0x58 24.--27. 1. "HLEN45,Huffman length 45" hexmask.long.byte 0x58 16.--23. 1. "HCODE45,Huffman code 45" newline hexmask.long.byte 0x58 8.--11. 1. "HLEN44,Huffman length 44" hexmask.long.byte 0x58 0.--7. 1. "HCODE44,Huffman code 44" line.long 0x5C "JPEG_HUFFENC_AC0_23,JPEG Huffman encoder AC0" hexmask.long.byte 0x5C 24.--27. 1. "HLEN47,Huffman length 47" hexmask.long.byte 0x5C 16.--23. 1. "HCODE47,Huffman code 47" newline hexmask.long.byte 0x5C 8.--11. 1. "HLEN46,Huffman length 46" hexmask.long.byte 0x5C 0.--7. 1. "HCODE46,Huffman code 46" line.long 0x60 "JPEG_HUFFENC_AC0_24,JPEG Huffman encoder AC0" hexmask.long.byte 0x60 24.--27. 1. "HLEN49,Huffman length 49" hexmask.long.byte 0x60 16.--23. 1. "HCODE49,Huffman code 49" newline hexmask.long.byte 0x60 8.--11. 1. "HLEN48,Huffman length 48" hexmask.long.byte 0x60 0.--7. 1. "HCODE48,Huffman code 48" line.long 0x64 "JPEG_HUFFENC_AC0_25,JPEG Huffman encoder AC0" hexmask.long.byte 0x64 24.--27. 1. "HLEN51,Huffman length 51" hexmask.long.byte 0x64 16.--23. 1. "HCODE51,Huffman code 51" newline hexmask.long.byte 0x64 8.--11. 1. "HLEN50,Huffman length 50" hexmask.long.byte 0x64 0.--7. 1. "HCODE50,Huffman code 50" line.long 0x68 "JPEG_HUFFENC_AC0_26,JPEG Huffman encoder AC0" hexmask.long.byte 0x68 24.--27. 1. "HLEN53,Huffman length 53" hexmask.long.byte 0x68 16.--23. 1. "HCODE53,Huffman code 53" newline hexmask.long.byte 0x68 8.--11. 1. "HLEN52,Huffman length 52" hexmask.long.byte 0x68 0.--7. 1. "HCODE52,Huffman code 52" line.long 0x6C "JPEG_HUFFENC_AC0_27,JPEG Huffman encoder AC0" hexmask.long.byte 0x6C 24.--27. 1. "HLEN55,Huffman length 55" hexmask.long.byte 0x6C 16.--23. 1. "HCODE55,Huffman code 55" newline hexmask.long.byte 0x6C 8.--11. 1. "HLEN54,Huffman length 54" hexmask.long.byte 0x6C 0.--7. 1. "HCODE54,Huffman code 54" line.long 0x70 "JPEG_HUFFENC_AC0_28,JPEG Huffman encoder AC0" hexmask.long.byte 0x70 24.--27. 1. "HLEN57,Huffman length 57" hexmask.long.byte 0x70 16.--23. 1. "HCODE57,Huffman code 57" newline hexmask.long.byte 0x70 8.--11. 1. "HLEN56,Huffman length 56" hexmask.long.byte 0x70 0.--7. 1. "HCODE56,Huffman code 56" line.long 0x74 "JPEG_HUFFENC_AC0_29,JPEG Huffman encoder AC0" hexmask.long.byte 0x74 24.--27. 1. "HLEN59,Huffman length 59" hexmask.long.byte 0x74 16.--23. 1. "HCODE59,Huffman code 59" newline hexmask.long.byte 0x74 8.--11. 1. "HLEN58,Huffman length 58" hexmask.long.byte 0x74 0.--7. 1. "HCODE58,Huffman code 58" line.long 0x78 "JPEG_HUFFENC_AC0_30,JPEG Huffman encoder AC0" hexmask.long.byte 0x78 24.--27. 1. "HLEN61,Huffman length 61" hexmask.long.byte 0x78 16.--23. 1. "HCODE61,Huffman code 61" newline hexmask.long.byte 0x78 8.--11. 1. "HLEN60,Huffman length 60" hexmask.long.byte 0x78 0.--7. 1. "HCODE60,Huffman code 60" line.long 0x7C "JPEG_HUFFENC_AC0_31,JPEG Huffman encoder AC0" hexmask.long.byte 0x7C 24.--27. 1. "HLEN63,Huffman length 63" hexmask.long.byte 0x7C 16.--23. 1. "HCODE63,Huffman code 63" newline hexmask.long.byte 0x7C 8.--11. 1. "HLEN62,Huffman length 62" hexmask.long.byte 0x7C 0.--7. 1. "HCODE62,Huffman code 62" line.long 0x80 "JPEG_HUFFENC_AC0_32,JPEG Huffman encoder AC0" hexmask.long.byte 0x80 24.--27. 1. "HLEN65,Huffman length 65" hexmask.long.byte 0x80 16.--23. 1. "HCODE65,Huffman code 65" newline hexmask.long.byte 0x80 8.--11. 1. "HLEN64,Huffman length 64" hexmask.long.byte 0x80 0.--7. 1. "HCODE64,Huffman code 64" line.long 0x84 "JPEG_HUFFENC_AC0_33,JPEG Huffman encoder AC0" hexmask.long.byte 0x84 24.--27. 1. "HLEN67,Huffman length 67" hexmask.long.byte 0x84 16.--23. 1. "HCODE67,Huffman code 67" newline hexmask.long.byte 0x84 8.--11. 1. "HLEN66,Huffman length 66" hexmask.long.byte 0x84 0.--7. 1. "HCODE66,Huffman code 66" line.long 0x88 "JPEG_HUFFENC_AC0_34,JPEG Huffman encoder AC0" hexmask.long.byte 0x88 24.--27. 1. "HLEN69,Huffman length 69" hexmask.long.byte 0x88 16.--23. 1. "HCODE69,Huffman code 69" newline hexmask.long.byte 0x88 8.--11. 1. "HLEN68,Huffman length 68" hexmask.long.byte 0x88 0.--7. 1. "HCODE68,Huffman code 68" line.long 0x8C "JPEG_HUFFENC_AC0_35,JPEG Huffman encoder AC0" hexmask.long.byte 0x8C 24.--27. 1. "HLEN71,Huffman length 71" hexmask.long.byte 0x8C 16.--23. 1. "HCODE71,Huffman code 71" newline hexmask.long.byte 0x8C 8.--11. 1. "HLEN70,Huffman length 70" hexmask.long.byte 0x8C 0.--7. 1. "HCODE70,Huffman code 70" line.long 0x90 "JPEG_HUFFENC_AC0_36,JPEG Huffman encoder AC0" hexmask.long.byte 0x90 24.--27. 1. "HLEN73,Huffman length 73" hexmask.long.byte 0x90 16.--23. 1. "HCODE73,Huffman code 73" newline hexmask.long.byte 0x90 8.--11. 1. "HLEN72,Huffman length 72" hexmask.long.byte 0x90 0.--7. 1. "HCODE72,Huffman code 72" line.long 0x94 "JPEG_HUFFENC_AC0_37,JPEG Huffman encoder AC0" hexmask.long.byte 0x94 24.--27. 1. "HLEN75,Huffman length 75" hexmask.long.byte 0x94 16.--23. 1. "HCODE75,Huffman code 75" newline hexmask.long.byte 0x94 8.--11. 1. "HLEN74,Huffman length 74" hexmask.long.byte 0x94 0.--7. 1. "HCODE74,Huffman code 74" line.long 0x98 "JPEG_HUFFENC_AC0_38,JPEG Huffman encoder AC0" hexmask.long.byte 0x98 24.--27. 1. "HLEN77,Huffman length 77" hexmask.long.byte 0x98 16.--23. 1. "HCODE77,Huffman code 77" newline hexmask.long.byte 0x98 8.--11. 1. "HLEN76,Huffman length 76" hexmask.long.byte 0x98 0.--7. 1. "HCODE76,Huffman code 76" line.long 0x9C "JPEG_HUFFENC_AC0_39,JPEG Huffman encoder AC0" hexmask.long.byte 0x9C 24.--27. 1. "HLEN79,Huffman length 79" hexmask.long.byte 0x9C 16.--23. 1. "HCODE79,Huffman code 79" newline hexmask.long.byte 0x9C 8.--11. 1. "HLEN78,Huffman length 78" hexmask.long.byte 0x9C 0.--7. 1. "HCODE78,Huffman code 78" line.long 0xA0 "JPEG_HUFFENC_AC0_40,JPEG Huffman encoder AC0" hexmask.long.byte 0xA0 24.--27. 1. "HLEN81,Huffman length 81" hexmask.long.byte 0xA0 16.--23. 1. "HCODE81,Huffman code 81" newline hexmask.long.byte 0xA0 8.--11. 1. "HLEN80,Huffman length 80" hexmask.long.byte 0xA0 0.--7. 1. "HCODE80,Huffman code 80" line.long 0xA4 "JPEG_HUFFENC_AC0_41,JPEG Huffman encoder AC0" hexmask.long.byte 0xA4 24.--27. 1. "HLEN83,Huffman length 83" hexmask.long.byte 0xA4 16.--23. 1. "HCODE83,Huffman code 83" newline hexmask.long.byte 0xA4 8.--11. 1. "HLEN82,Huffman length 82" hexmask.long.byte 0xA4 0.--7. 1. "HCODE82,Huffman code 82" line.long 0xA8 "JPEG_HUFFENC_AC0_42,JPEG Huffman encoder AC0" hexmask.long.byte 0xA8 24.--27. 1. "HLEN85,Huffman length 85" hexmask.long.byte 0xA8 16.--23. 1. "HCODE85,Huffman code 85" newline hexmask.long.byte 0xA8 8.--11. 1. "HLEN84,Huffman length 84" hexmask.long.byte 0xA8 0.--7. 1. "HCODE84,Huffman code 84" line.long 0xAC "JPEG_HUFFENC_AC0_43,JPEG Huffman encoder AC0" hexmask.long.byte 0xAC 24.--27. 1. "HLEN87,Huffman length 87" hexmask.long.byte 0xAC 16.--23. 1. "HCODE87,Huffman code 87" newline hexmask.long.byte 0xAC 8.--11. 1. "HLEN86,Huffman length 86" hexmask.long.byte 0xAC 0.--7. 1. "HCODE86,Huffman code 86" line.long 0xB0 "JPEG_HUFFENC_AC0_44,JPEG Huffman encoder AC0" hexmask.long.byte 0xB0 24.--27. 1. "HLEN89,Huffman length 89" hexmask.long.byte 0xB0 16.--23. 1. "HCODE89,Huffman code 89" newline hexmask.long.byte 0xB0 8.--11. 1. "HLEN88,Huffman length 88" hexmask.long.byte 0xB0 0.--7. 1. "HCODE88,Huffman code 88" line.long 0xB4 "JPEG_HUFFENC_AC0_45,JPEG Huffman encoder AC0" hexmask.long.byte 0xB4 24.--27. 1. "HLEN91,Huffman length 91" hexmask.long.byte 0xB4 16.--23. 1. "HCODE91,Huffman code 91" newline hexmask.long.byte 0xB4 8.--11. 1. "HLEN90,Huffman length 90" hexmask.long.byte 0xB4 0.--7. 1. "HCODE90,Huffman code 90" line.long 0xB8 "JPEG_HUFFENC_AC0_46,JPEG Huffman encoder AC0" hexmask.long.byte 0xB8 24.--27. 1. "HLEN93,Huffman length 93" hexmask.long.byte 0xB8 16.--23. 1. "HCODE93,Huffman code 93" newline hexmask.long.byte 0xB8 8.--11. 1. "HLEN92,Huffman length 92" hexmask.long.byte 0xB8 0.--7. 1. "HCODE92,Huffman code 92" line.long 0xBC "JPEG_HUFFENC_AC0_47,JPEG Huffman encoder AC0" hexmask.long.byte 0xBC 24.--27. 1. "HLEN95,Huffman length 95" hexmask.long.byte 0xBC 16.--23. 1. "HCODE95,Huffman code 95" newline hexmask.long.byte 0xBC 8.--11. 1. "HLEN94,Huffman length 94" hexmask.long.byte 0xBC 0.--7. 1. "HCODE94,Huffman code 94" line.long 0xC0 "JPEG_HUFFENC_AC0_48,JPEG Huffman encoder AC0" hexmask.long.byte 0xC0 24.--27. 1. "HLEN97,Huffman length 97" hexmask.long.byte 0xC0 16.--23. 1. "HCODE97,Huffman code 97" newline hexmask.long.byte 0xC0 8.--11. 1. "HLEN96,Huffman length 96" hexmask.long.byte 0xC0 0.--7. 1. "HCODE96,Huffman code 96" line.long 0xC4 "JPEG_HUFFENC_AC0_49,JPEG Huffman encoder AC0" hexmask.long.byte 0xC4 24.--27. 1. "HLEN99,Huffman length 99" hexmask.long.byte 0xC4 16.--23. 1. "HCODE99,Huffman code 99" newline hexmask.long.byte 0xC4 8.--11. 1. "HLEN98,Huffman length 98" hexmask.long.byte 0xC4 0.--7. 1. "HCODE98,Huffman code 98" line.long 0xC8 "JPEG_HUFFENC_AC0_50,JPEG Huffman encoder AC0" hexmask.long.byte 0xC8 24.--27. 1. "HLEN101,Huffman length 101" hexmask.long.byte 0xC8 16.--23. 1. "HCODE101,Huffman code 101" newline hexmask.long.byte 0xC8 8.--11. 1. "HLEN100,Huffman length 100" hexmask.long.byte 0xC8 0.--7. 1. "HCODE100,Huffman code 100" line.long 0xCC "JPEG_HUFFENC_AC0_51,JPEG Huffman encoder AC0" hexmask.long.byte 0xCC 24.--27. 1. "HLEN103,Huffman length 103" hexmask.long.byte 0xCC 16.--23. 1. "HCODE103,Huffman code 103" newline hexmask.long.byte 0xCC 8.--11. 1. "HLEN102,Huffman length 102" hexmask.long.byte 0xCC 0.--7. 1. "HCODE102,Huffman code 102" line.long 0xD0 "JPEG_HUFFENC_AC0_52,JPEG Huffman encoder AC0" hexmask.long.byte 0xD0 24.--27. 1. "HLEN105,Huffman length 105" hexmask.long.byte 0xD0 16.--23. 1. "HCODE105,Huffman code 105" newline hexmask.long.byte 0xD0 8.--11. 1. "HLEN104,Huffman length 104" hexmask.long.byte 0xD0 0.--7. 1. "HCODE104,Huffman code 104" line.long 0xD4 "JPEG_HUFFENC_AC0_53,JPEG Huffman encoder AC0" hexmask.long.byte 0xD4 24.--27. 1. "HLEN107,Huffman length 107" hexmask.long.byte 0xD4 16.--23. 1. "HCODE107,Huffman code 107" newline hexmask.long.byte 0xD4 8.--11. 1. "HLEN106,Huffman length 106" hexmask.long.byte 0xD4 0.--7. 1. "HCODE106,Huffman code 106" line.long 0xD8 "JPEG_HUFFENC_AC0_54,JPEG Huffman encoder AC0" hexmask.long.byte 0xD8 24.--27. 1. "HLEN109,Huffman length 109" hexmask.long.byte 0xD8 16.--23. 1. "HCODE109,Huffman code 109" newline hexmask.long.byte 0xD8 8.--11. 1. "HLEN108,Huffman length 108" hexmask.long.byte 0xD8 0.--7. 1. "HCODE108,Huffman code 108" line.long 0xDC "JPEG_HUFFENC_AC0_55,JPEG Huffman encoder AC0" hexmask.long.byte 0xDC 24.--27. 1. "HLEN111,Huffman length 111" hexmask.long.byte 0xDC 16.--23. 1. "HCODE111,Huffman code 111" newline hexmask.long.byte 0xDC 8.--11. 1. "HLEN110,Huffman length 110" hexmask.long.byte 0xDC 0.--7. 1. "HCODE110,Huffman code 110" group.long 0x5DC++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_0,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_AC0_56,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN113,Huffman length 113" hexmask.long.byte 0x4 16.--23. 1. "HCODE113,Huffman code 113" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN112,Huffman length 112" hexmask.long.byte 0x4 0.--7. 1. "HCODE112,Huffman code 112" group.long 0x5E0++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_1,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x0 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x0 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x4 "JPEG_HUFFENC_AC0_57,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN115,Huffman length 115" hexmask.long.byte 0x4 16.--23. 1. "HCODE115,Huffman code 115" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN114,Huffman length 114" hexmask.long.byte 0x4 0.--7. 1. "HCODE114,Huffman code 114" group.long 0x5E4++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_2,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x0 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x0 0.--7. 1. "HCODE4,Huffman code 4" line.long 0x4 "JPEG_HUFFENC_AC0_58,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN117,Huffman length 117" hexmask.long.byte 0x4 16.--23. 1. "HCODE117,Huffman code 117" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN116,Huffman length 116" hexmask.long.byte 0x4 0.--7. 1. "HCODE116,Huffman code 116" group.long 0x5E8++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_3,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0x0 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0x0 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x4 "JPEG_HUFFENC_AC0_59,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN119,Huffman length 119" hexmask.long.byte 0x4 16.--23. 1. "HCODE119,Huffman code 119" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN118,Huffman length 118" hexmask.long.byte 0x4 0.--7. 1. "HCODE118,Huffman code 118" group.long 0x5EC++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_4,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x0 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x0 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x4 "JPEG_HUFFENC_AC0_60,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN121,Huffman length 121" hexmask.long.byte 0x4 16.--23. 1. "HCODE121,Huffman code 121" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN120,Huffman length 120" hexmask.long.byte 0x4 0.--7. 1. "HCODE120,Huffman code 120" group.long 0x5F0++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_5,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x0 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x0 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x4 "JPEG_HUFFENC_AC0_61,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN123,Huffman length 123" hexmask.long.byte 0x4 16.--23. 1. "HCODE123,Huffman code 123" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN122,Huffman length 122" hexmask.long.byte 0x4 0.--7. 1. "HCODE122,Huffman code 122" group.long 0x5F4++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_6,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x0 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x0 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x4 "JPEG_HUFFENC_AC0_62,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN125,Huffman length 125" hexmask.long.byte 0x4 16.--23. 1. "HCODE125,Huffman code 125" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN124,Huffman length 124" hexmask.long.byte 0x4 0.--7. 1. "HCODE124,Huffman code 124" group.long 0x5F8++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_7,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x0 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x0 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x4 "JPEG_HUFFENC_AC0_63,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN127,Huffman length 127" hexmask.long.byte 0x4 16.--23. 1. "HCODE127,Huffman code 127" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN126,Huffman length 126" hexmask.long.byte 0x4 0.--7. 1. "HCODE126,Huffman code 126" group.long 0x5FC++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_8,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN17,Huffman length 17" hexmask.long.byte 0x0 16.--23. 1. "HCODE17,Huffman code 17" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN16,Huffman length 16" hexmask.long.byte 0x0 0.--7. 1. "HCODE16,Huffman code 16" line.long 0x4 "JPEG_HUFFENC_AC0_64,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN129,Huffman length 129" hexmask.long.byte 0x4 16.--23. 1. "HCODE129,Huffman code 129" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN128,Huffman length 128" hexmask.long.byte 0x4 0.--7. 1. "HCODE128,Huffman code 128" group.long 0x600++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_9,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN19,Huffman length 19" hexmask.long.byte 0x0 16.--23. 1. "HCODE19,Huffman code 19" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN18,Huffman length 18" hexmask.long.byte 0x0 0.--7. 1. "HCODE18,Huffman code 18" line.long 0x4 "JPEG_HUFFENC_AC0_65,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN131,Huffman length 131" hexmask.long.byte 0x4 16.--23. 1. "HCODE131,Huffman code 131" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN130,Huffman length 130" hexmask.long.byte 0x4 0.--7. 1. "HCODE130,Huffman code 130" group.long 0x604++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_10,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN21,Huffman length 21" hexmask.long.byte 0x0 16.--23. 1. "HCODE21,Huffman code 21" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN20,Huffman length 20" hexmask.long.byte 0x0 0.--7. 1. "HCODE20,Huffman code 20" line.long 0x4 "JPEG_HUFFENC_AC0_66,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN133,Huffman length 133" hexmask.long.byte 0x4 16.--23. 1. "HCODE133,Huffman code 133" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN132,Huffman length 132" hexmask.long.byte 0x4 0.--7. 1. "HCODE132,Huffman code 132" group.long 0x608++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_11,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN23,Huffman length 23" hexmask.long.byte 0x0 16.--23. 1. "HCODE23,Huffman code 23" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN22,Huffman length 22" hexmask.long.byte 0x0 0.--7. 1. "HCODE22,Huffman code 22" line.long 0x4 "JPEG_HUFFENC_AC0_67,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN135,Huffman length 135" hexmask.long.byte 0x4 16.--23. 1. "HCODE135,Huffman code 135" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN134,Huffman length 134" hexmask.long.byte 0x4 0.--7. 1. "HCODE134,Huffman code 134" group.long 0x60C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_12,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN25,Huffman length 25" hexmask.long.byte 0x0 16.--23. 1. "HCODE25,Huffman code 25" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN24,Huffman length 24" hexmask.long.byte 0x0 0.--7. 1. "HCODE24,Huffman code 24" line.long 0x4 "JPEG_HUFFENC_AC0_68,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN137,Huffman length 137" hexmask.long.byte 0x4 16.--23. 1. "HCODE137,Huffman code 137" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN136,Huffman length 136" hexmask.long.byte 0x4 0.--7. 1. "HCODE136,Huffman code 136" group.long 0x610++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_13,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN27,Huffman length 27" hexmask.long.byte 0x0 16.--23. 1. "HCODE27,Huffman code 27" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN26,Huffman length 26" hexmask.long.byte 0x0 0.--7. 1. "HCODE26,Huffman code 26" line.long 0x4 "JPEG_HUFFENC_AC0_69,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN139,Huffman length 139" hexmask.long.byte 0x4 16.--23. 1. "HCODE139,Huffman code 139" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN138,Huffman length 138" hexmask.long.byte 0x4 0.--7. 1. "HCODE138,Huffman code 138" group.long 0x614++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_14,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN29,Huffman length 29" hexmask.long.byte 0x0 16.--23. 1. "HCODE29,Huffman code 29" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN28,Huffman length 28" hexmask.long.byte 0x0 0.--7. 1. "HCODE28,Huffman code 28" line.long 0x4 "JPEG_HUFFENC_AC0_70,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN141,Huffman length 141" hexmask.long.byte 0x4 16.--23. 1. "HCODE141,Huffman code 141" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN140,Huffman length 140" hexmask.long.byte 0x4 0.--7. 1. "HCODE140,Huffman code 140" group.long 0x618++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_15,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN31,Huffman length 31" hexmask.long.byte 0x0 16.--23. 1. "HCODE31,Huffman code 31" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN30,Huffman length 30" hexmask.long.byte 0x0 0.--7. 1. "HCODE30,Huffman code 30" line.long 0x4 "JPEG_HUFFENC_AC0_71,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN143,Huffman length 143" hexmask.long.byte 0x4 16.--23. 1. "HCODE143,Huffman code 143" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN142,Huffman length 142" hexmask.long.byte 0x4 0.--7. 1. "HCODE142,Huffman code 142" group.long 0x61C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_16,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN33,Huffman length 33" hexmask.long.byte 0x0 16.--23. 1. "HCODE33,Huffman code 33" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN32,Huffman length 32" hexmask.long.byte 0x0 0.--7. 1. "HCODE32,Huffman code 32" line.long 0x4 "JPEG_HUFFENC_AC0_72,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN145,Huffman length 145" hexmask.long.byte 0x4 16.--23. 1. "HCODE145,Huffman code 145" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN144,Huffman length 144" hexmask.long.byte 0x4 0.--7. 1. "HCODE144,Huffman code 144" group.long 0x620++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_17,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN35,Huffman length 35" hexmask.long.byte 0x0 16.--23. 1. "HCODE35,Huffman code 35" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN34,Huffman length 34" hexmask.long.byte 0x0 0.--7. 1. "HCODE34,Huffman code 34" line.long 0x4 "JPEG_HUFFENC_AC0_73,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN147,Huffman length 147" hexmask.long.byte 0x4 16.--23. 1. "HCODE147,Huffman code 147" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN146,Huffman length 146" hexmask.long.byte 0x4 0.--7. 1. "HCODE146,Huffman code 146" group.long 0x624++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_18,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN37,Huffman length 37" hexmask.long.byte 0x0 16.--23. 1. "HCODE37,Huffman code 37" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN36,Huffman length 36" hexmask.long.byte 0x0 0.--7. 1. "HCODE36,Huffman code 36" line.long 0x4 "JPEG_HUFFENC_AC0_74,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN149,Huffman length 149" hexmask.long.byte 0x4 16.--23. 1. "HCODE149,Huffman code 149" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN148,Huffman length 148" hexmask.long.byte 0x4 0.--7. 1. "HCODE148,Huffman code 148" group.long 0x628++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_19,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN39,Huffman length 39" hexmask.long.byte 0x0 16.--23. 1. "HCODE39,Huffman code 39" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN38,Huffman length 38" hexmask.long.byte 0x0 0.--7. 1. "HCODE38,Huffman code 38" line.long 0x4 "JPEG_HUFFENC_AC0_75,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN151,Huffman length 151" hexmask.long.byte 0x4 16.--23. 1. "HCODE151,Huffman code 151" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN150,Huffman length 150" hexmask.long.byte 0x4 0.--7. 1. "HCODE150,Huffman code 150" group.long 0x62C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_20,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN41,Huffman length 41" hexmask.long.byte 0x0 16.--23. 1. "HCODE41,Huffman code 41" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN40,Huffman length 40" hexmask.long.byte 0x0 0.--7. 1. "HCODE40,Huffman code 40" line.long 0x4 "JPEG_HUFFENC_AC0_76,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN153,Huffman length 153" hexmask.long.byte 0x4 16.--23. 1. "HCODE153,Huffman code 153" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN152,Huffman length 152" hexmask.long.byte 0x4 0.--7. 1. "HCODE152,Huffman code 152" group.long 0x630++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_21,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN43,Huffman length 43" hexmask.long.byte 0x0 16.--23. 1. "HCODE43,Huffman code 43" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN42,Huffman length 42" hexmask.long.byte 0x0 0.--7. 1. "HCODE42,Huffman code 42" line.long 0x4 "JPEG_HUFFENC_AC0_77,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN155,Huffman length 155" hexmask.long.byte 0x4 16.--23. 1. "HCODE155,Huffman code 155" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN154,Huffman length 154" hexmask.long.byte 0x4 0.--7. 1. "HCODE154,Huffman code 154" group.long 0x634++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_22,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN45,Huffman length 45" hexmask.long.byte 0x0 16.--23. 1. "HCODE45,Huffman code 45" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN44,Huffman length 44" hexmask.long.byte 0x0 0.--7. 1. "HCODE44,Huffman code 44" line.long 0x4 "JPEG_HUFFENC_AC0_78,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN157,Huffman length 157" hexmask.long.byte 0x4 16.--23. 1. "HCODE157,Huffman code 157" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN156,Huffman length 156" hexmask.long.byte 0x4 0.--7. 1. "HCODE156,Huffman code 156" group.long 0x638++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_23,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN47,Huffman length 47" hexmask.long.byte 0x0 16.--23. 1. "HCODE47,Huffman code 47" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN46,Huffman length 46" hexmask.long.byte 0x0 0.--7. 1. "HCODE46,Huffman code 46" line.long 0x4 "JPEG_HUFFENC_AC0_79,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN159,Huffman length 159" hexmask.long.byte 0x4 16.--23. 1. "HCODE159,Huffman code 159" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN158,Huffman length 158" hexmask.long.byte 0x4 0.--7. 1. "HCODE158,Huffman code 158" group.long 0x63C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_24,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN49,Huffman length 49" hexmask.long.byte 0x0 16.--23. 1. "HCODE49,Huffman code 49" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN48,Huffman length 48" hexmask.long.byte 0x0 0.--7. 1. "HCODE48,Huffman code 48" line.long 0x4 "JPEG_HUFFENC_AC0_80,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN161,Huffman length 161" hexmask.long.byte 0x4 16.--23. 1. "HCODE161,Huffman code 161" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN160,Huffman length 160" hexmask.long.byte 0x4 0.--7. 1. "HCODE160,Huffman code 160" group.long 0x640++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_25,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN51,Huffman length 51" hexmask.long.byte 0x0 16.--23. 1. "HCODE51,Huffman code 51" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN50,Huffman length 50" hexmask.long.byte 0x0 0.--7. 1. "HCODE50,Huffman code 50" line.long 0x4 "JPEG_HUFFENC_AC0_81,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN163,Huffman length 163" hexmask.long.byte 0x4 16.--23. 1. "HCODE163,Huffman code 163" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN162,Huffman length 162" hexmask.long.byte 0x4 0.--7. 1. "HCODE162,Huffman code 162" group.long 0x644++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_26,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN53,Huffman length 53" hexmask.long.byte 0x0 16.--23. 1. "HCODE53,Huffman code 53" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN52,Huffman length 52" hexmask.long.byte 0x0 0.--7. 1. "HCODE52,Huffman code 52" line.long 0x4 "JPEG_HUFFENC_AC0_82,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN165,Huffman length 165" hexmask.long.byte 0x4 16.--23. 1. "HCODE165,Huffman code 165" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN164,Huffman length 164" hexmask.long.byte 0x4 0.--7. 1. "HCODE164,Huffman code 164" group.long 0x648++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_27,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN55,Huffman length 55" hexmask.long.byte 0x0 16.--23. 1. "HCODE55,Huffman code 55" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN54,Huffman length 54" hexmask.long.byte 0x0 0.--7. 1. "HCODE54,Huffman code 54" line.long 0x4 "JPEG_HUFFENC_AC0_83,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN167,Huffman length 167" hexmask.long.byte 0x4 16.--23. 1. "HCODE167,Huffman code 167" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN166,Huffman length 166" hexmask.long.byte 0x4 0.--7. 1. "HCODE166,Huffman code 166" group.long 0x64C++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_28,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN57,Huffman length 57" hexmask.long.byte 0x0 16.--23. 1. "HCODE57,Huffman code 57" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN56,Huffman length 56" hexmask.long.byte 0x0 0.--7. 1. "HCODE56,Huffman code 56" line.long 0x4 "JPEG_HUFFENC_AC0_84,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN169,Huffman length 169" hexmask.long.byte 0x4 16.--23. 1. "HCODE169,Huffman code 169" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN168,Huffman length 168" hexmask.long.byte 0x4 0.--7. 1. "HCODE168,Huffman code 168" group.long 0x650++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_29,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN59,Huffman length 59" hexmask.long.byte 0x0 16.--23. 1. "HCODE59,Huffman code 59" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN58,Huffman length 58" hexmask.long.byte 0x0 0.--7. 1. "HCODE58,Huffman code 58" line.long 0x4 "JPEG_HUFFENC_AC0_85,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN171,Huffman length 171" hexmask.long.byte 0x4 16.--23. 1. "HCODE171,Huffman code 171" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN170,Huffman length 170" hexmask.long.byte 0x4 0.--7. 1. "HCODE170,Huffman code 170" group.long 0x654++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_30,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN61,Huffman length 61" hexmask.long.byte 0x0 16.--23. 1. "HCODE61,Huffman code 61" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN60,Huffman length 60" hexmask.long.byte 0x0 0.--7. 1. "HCODE60,Huffman code 60" line.long 0x4 "JPEG_HUFFENC_AC0_86,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN173,Huffman length 173" hexmask.long.byte 0x4 16.--23. 1. "HCODE173,Huffman code 173" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN172,Huffman length 172" hexmask.long.byte 0x4 0.--7. 1. "HCODE172,Huffman code 172" group.long 0x658++0x7 line.long 0x0 "JPEG_HUFFENC_AC1_31,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN63,Huffman length 63" hexmask.long.byte 0x0 16.--23. 1. "HCODE63,Huffman code 63" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN62,Huffman length 62" hexmask.long.byte 0x0 0.--7. 1. "HCODE62,Huffman code 62" line.long 0x4 "JPEG_HUFFENC_AC0_87,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN175,Huffman length 175" hexmask.long.byte 0x4 16.--23. 1. "HCODE175,Huffman code 175" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN174,Huffman length 174" hexmask.long.byte 0x4 0.--7. 1. "HCODE174,Huffman code 174" group.long 0x65C++0xDF line.long 0x0 "JPEG_HUFFENC_AC1_32,JPEG Huffman encoder AC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN65,Huffman length 65" hexmask.long.byte 0x0 16.--23. 1. "HCODE65,Huffman code 65" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN64,Huffman length 64" hexmask.long.byte 0x0 0.--7. 1. "HCODE64,Huffman code 64" line.long 0x4 "JPEG_HUFFENC_AC1_33,JPEG Huffman encoder AC1" hexmask.long.byte 0x4 24.--27. 1. "HLEN67,Huffman length 67" hexmask.long.byte 0x4 16.--23. 1. "HCODE67,Huffman code 67" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN66,Huffman length 66" hexmask.long.byte 0x4 0.--7. 1. "HCODE66,Huffman code 66" line.long 0x8 "JPEG_HUFFENC_AC1_34,JPEG Huffman encoder AC1" hexmask.long.byte 0x8 24.--27. 1. "HLEN69,Huffman length 69" hexmask.long.byte 0x8 16.--23. 1. "HCODE69,Huffman code 69" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN68,Huffman length 68" hexmask.long.byte 0x8 0.--7. 1. "HCODE68,Huffman code 68" line.long 0xC "JPEG_HUFFENC_AC1_35,JPEG Huffman encoder AC1" hexmask.long.byte 0xC 24.--27. 1. "HLEN71,Huffman length 71" hexmask.long.byte 0xC 16.--23. 1. "HCODE71,Huffman code 71" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN70,Huffman length 70" hexmask.long.byte 0xC 0.--7. 1. "HCODE70,Huffman code 70" line.long 0x10 "JPEG_HUFFENC_AC1_36,JPEG Huffman encoder AC1" hexmask.long.byte 0x10 24.--27. 1. "HLEN73,Huffman length 73" hexmask.long.byte 0x10 16.--23. 1. "HCODE73,Huffman code 73" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN72,Huffman length 72" hexmask.long.byte 0x10 0.--7. 1. "HCODE72,Huffman code 72" line.long 0x14 "JPEG_HUFFENC_AC1_37,JPEG Huffman encoder AC1" hexmask.long.byte 0x14 24.--27. 1. "HLEN75,Huffman length 75" hexmask.long.byte 0x14 16.--23. 1. "HCODE75,Huffman code 75" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN74,Huffman length 74" hexmask.long.byte 0x14 0.--7. 1. "HCODE74,Huffman code 74" line.long 0x18 "JPEG_HUFFENC_AC1_38,JPEG Huffman encoder AC1" hexmask.long.byte 0x18 24.--27. 1. "HLEN77,Huffman length 77" hexmask.long.byte 0x18 16.--23. 1. "HCODE77,Huffman code 77" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN76,Huffman length 76" hexmask.long.byte 0x18 0.--7. 1. "HCODE76,Huffman code 76" line.long 0x1C "JPEG_HUFFENC_AC1_39,JPEG Huffman encoder AC1" hexmask.long.byte 0x1C 24.--27. 1. "HLEN79,Huffman length 79" hexmask.long.byte 0x1C 16.--23. 1. "HCODE79,Huffman code 79" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN78,Huffman length 78" hexmask.long.byte 0x1C 0.--7. 1. "HCODE78,Huffman code 78" line.long 0x20 "JPEG_HUFFENC_AC1_40,JPEG Huffman encoder AC1" hexmask.long.byte 0x20 24.--27. 1. "HLEN81,Huffman length 81" hexmask.long.byte 0x20 16.--23. 1. "HCODE81,Huffman code 81" newline hexmask.long.byte 0x20 8.--11. 1. "HLEN80,Huffman length 80" hexmask.long.byte 0x20 0.--7. 1. "HCODE80,Huffman code 80" line.long 0x24 "JPEG_HUFFENC_AC1_41,JPEG Huffman encoder AC1" hexmask.long.byte 0x24 24.--27. 1. "HLEN83,Huffman length 83" hexmask.long.byte 0x24 16.--23. 1. "HCODE83,Huffman code 83" newline hexmask.long.byte 0x24 8.--11. 1. "HLEN82,Huffman length 82" hexmask.long.byte 0x24 0.--7. 1. "HCODE82,Huffman code 82" line.long 0x28 "JPEG_HUFFENC_AC1_42,JPEG Huffman encoder AC1" hexmask.long.byte 0x28 24.--27. 1. "HLEN85,Huffman length 85" hexmask.long.byte 0x28 16.--23. 1. "HCODE85,Huffman code 85" newline hexmask.long.byte 0x28 8.--11. 1. "HLEN84,Huffman length 84" hexmask.long.byte 0x28 0.--7. 1. "HCODE84,Huffman code 84" line.long 0x2C "JPEG_HUFFENC_AC1_43,JPEG Huffman encoder AC1" hexmask.long.byte 0x2C 24.--27. 1. "HLEN87,Huffman length 87" hexmask.long.byte 0x2C 16.--23. 1. "HCODE87,Huffman code 87" newline hexmask.long.byte 0x2C 8.--11. 1. "HLEN86,Huffman length 86" hexmask.long.byte 0x2C 0.--7. 1. "HCODE86,Huffman code 86" line.long 0x30 "JPEG_HUFFENC_AC1_44,JPEG Huffman encoder AC1" hexmask.long.byte 0x30 24.--27. 1. "HLEN89,Huffman length 89" hexmask.long.byte 0x30 16.--23. 1. "HCODE89,Huffman code 89" newline hexmask.long.byte 0x30 8.--11. 1. "HLEN88,Huffman length 88" hexmask.long.byte 0x30 0.--7. 1. "HCODE88,Huffman code 88" line.long 0x34 "JPEG_HUFFENC_AC1_45,JPEG Huffman encoder AC1" hexmask.long.byte 0x34 24.--27. 1. "HLEN91,Huffman length 91" hexmask.long.byte 0x34 16.--23. 1. "HCODE91,Huffman code 91" newline hexmask.long.byte 0x34 8.--11. 1. "HLEN90,Huffman length 90" hexmask.long.byte 0x34 0.--7. 1. "HCODE90,Huffman code 90" line.long 0x38 "JPEG_HUFFENC_AC1_46,JPEG Huffman encoder AC1" hexmask.long.byte 0x38 24.--27. 1. "HLEN93,Huffman length 93" hexmask.long.byte 0x38 16.--23. 1. "HCODE93,Huffman code 93" newline hexmask.long.byte 0x38 8.--11. 1. "HLEN92,Huffman length 92" hexmask.long.byte 0x38 0.--7. 1. "HCODE92,Huffman code 92" line.long 0x3C "JPEG_HUFFENC_AC1_47,JPEG Huffman encoder AC1" hexmask.long.byte 0x3C 24.--27. 1. "HLEN95,Huffman length 95" hexmask.long.byte 0x3C 16.--23. 1. "HCODE95,Huffman code 95" newline hexmask.long.byte 0x3C 8.--11. 1. "HLEN94,Huffman length 94" hexmask.long.byte 0x3C 0.--7. 1. "HCODE94,Huffman code 94" line.long 0x40 "JPEG_HUFFENC_AC1_48,JPEG Huffman encoder AC1" hexmask.long.byte 0x40 24.--27. 1. "HLEN97,Huffman length 97" hexmask.long.byte 0x40 16.--23. 1. "HCODE97,Huffman code 97" newline hexmask.long.byte 0x40 8.--11. 1. "HLEN96,Huffman length 96" hexmask.long.byte 0x40 0.--7. 1. "HCODE96,Huffman code 96" line.long 0x44 "JPEG_HUFFENC_AC1_49,JPEG Huffman encoder AC1" hexmask.long.byte 0x44 24.--27. 1. "HLEN99,Huffman length 99" hexmask.long.byte 0x44 16.--23. 1. "HCODE99,Huffman code 99" newline hexmask.long.byte 0x44 8.--11. 1. "HLEN98,Huffman length 98" hexmask.long.byte 0x44 0.--7. 1. "HCODE98,Huffman code 98" line.long 0x48 "JPEG_HUFFENC_AC1_50,JPEG Huffman encoder AC1" hexmask.long.byte 0x48 24.--27. 1. "HLEN101,Huffman length 101" hexmask.long.byte 0x48 16.--23. 1. "HCODE101,Huffman code 101" newline hexmask.long.byte 0x48 8.--11. 1. "HLEN100,Huffman length 100" hexmask.long.byte 0x48 0.--7. 1. "HCODE100,Huffman code 100" line.long 0x4C "JPEG_HUFFENC_AC1_51,JPEG Huffman encoder AC1" hexmask.long.byte 0x4C 24.--27. 1. "HLEN103,Huffman length 103" hexmask.long.byte 0x4C 16.--23. 1. "HCODE103,Huffman code 103" newline hexmask.long.byte 0x4C 8.--11. 1. "HLEN102,Huffman length 102" hexmask.long.byte 0x4C 0.--7. 1. "HCODE102,Huffman code 102" line.long 0x50 "JPEG_HUFFENC_AC1_52,JPEG Huffman encoder AC1" hexmask.long.byte 0x50 24.--27. 1. "HLEN105,Huffman length 105" hexmask.long.byte 0x50 16.--23. 1. "HCODE105,Huffman code 105" newline hexmask.long.byte 0x50 8.--11. 1. "HLEN104,Huffman length 104" hexmask.long.byte 0x50 0.--7. 1. "HCODE104,Huffman code 104" line.long 0x54 "JPEG_HUFFENC_AC1_53,JPEG Huffman encoder AC1" hexmask.long.byte 0x54 24.--27. 1. "HLEN107,Huffman length 107" hexmask.long.byte 0x54 16.--23. 1. "HCODE107,Huffman code 107" newline hexmask.long.byte 0x54 8.--11. 1. "HLEN106,Huffman length 106" hexmask.long.byte 0x54 0.--7. 1. "HCODE106,Huffman code 106" line.long 0x58 "JPEG_HUFFENC_AC1_54,JPEG Huffman encoder AC1" hexmask.long.byte 0x58 24.--27. 1. "HLEN109,Huffman length 109" hexmask.long.byte 0x58 16.--23. 1. "HCODE109,Huffman code 109" newline hexmask.long.byte 0x58 8.--11. 1. "HLEN108,Huffman length 108" hexmask.long.byte 0x58 0.--7. 1. "HCODE108,Huffman code 108" line.long 0x5C "JPEG_HUFFENC_AC1_55,JPEG Huffman encoder AC1" hexmask.long.byte 0x5C 24.--27. 1. "HLEN111,Huffman length 111" hexmask.long.byte 0x5C 16.--23. 1. "HCODE111,Huffman code 111" newline hexmask.long.byte 0x5C 8.--11. 1. "HLEN110,Huffman length 110" hexmask.long.byte 0x5C 0.--7. 1. "HCODE110,Huffman code 110" line.long 0x60 "JPEG_HUFFENC_AC1_56,JPEG Huffman encoder AC1" hexmask.long.byte 0x60 24.--27. 1. "HLEN113,Huffman length 113" hexmask.long.byte 0x60 16.--23. 1. "HCODE113,Huffman code 113" newline hexmask.long.byte 0x60 8.--11. 1. "HLEN112,Huffman length 112" hexmask.long.byte 0x60 0.--7. 1. "HCODE112,Huffman code 112" line.long 0x64 "JPEG_HUFFENC_AC1_57,JPEG Huffman encoder AC1" hexmask.long.byte 0x64 24.--27. 1. "HLEN115,Huffman length 115" hexmask.long.byte 0x64 16.--23. 1. "HCODE115,Huffman code 115" newline hexmask.long.byte 0x64 8.--11. 1. "HLEN114,Huffman length 114" hexmask.long.byte 0x64 0.--7. 1. "HCODE114,Huffman code 114" line.long 0x68 "JPEG_HUFFENC_AC1_58,JPEG Huffman encoder AC1" hexmask.long.byte 0x68 24.--27. 1. "HLEN117,Huffman length 117" hexmask.long.byte 0x68 16.--23. 1. "HCODE117,Huffman code 117" newline hexmask.long.byte 0x68 8.--11. 1. "HLEN116,Huffman length 116" hexmask.long.byte 0x68 0.--7. 1. "HCODE116,Huffman code 116" line.long 0x6C "JPEG_HUFFENC_AC1_59,JPEG Huffman encoder AC1" hexmask.long.byte 0x6C 24.--27. 1. "HLEN119,Huffman length 119" hexmask.long.byte 0x6C 16.--23. 1. "HCODE119,Huffman code 119" newline hexmask.long.byte 0x6C 8.--11. 1. "HLEN118,Huffman length 118" hexmask.long.byte 0x6C 0.--7. 1. "HCODE118,Huffman code 118" line.long 0x70 "JPEG_HUFFENC_AC1_60,JPEG Huffman encoder AC1" hexmask.long.byte 0x70 24.--27. 1. "HLEN121,Huffman length 121" hexmask.long.byte 0x70 16.--23. 1. "HCODE121,Huffman code 121" newline hexmask.long.byte 0x70 8.--11. 1. "HLEN120,Huffman length 120" hexmask.long.byte 0x70 0.--7. 1. "HCODE120,Huffman code 120" line.long 0x74 "JPEG_HUFFENC_AC1_61,JPEG Huffman encoder AC1" hexmask.long.byte 0x74 24.--27. 1. "HLEN123,Huffman length 123" hexmask.long.byte 0x74 16.--23. 1. "HCODE123,Huffman code 123" newline hexmask.long.byte 0x74 8.--11. 1. "HLEN122,Huffman length 122" hexmask.long.byte 0x74 0.--7. 1. "HCODE122,Huffman code 122" line.long 0x78 "JPEG_HUFFENC_AC1_62,JPEG Huffman encoder AC1" hexmask.long.byte 0x78 24.--27. 1. "HLEN125,Huffman length 125" hexmask.long.byte 0x78 16.--23. 1. "HCODE125,Huffman code 125" newline hexmask.long.byte 0x78 8.--11. 1. "HLEN124,Huffman length 124" hexmask.long.byte 0x78 0.--7. 1. "HCODE124,Huffman code 124" line.long 0x7C "JPEG_HUFFENC_AC1_63,JPEG Huffman encoder AC1" hexmask.long.byte 0x7C 24.--27. 1. "HLEN127,Huffman length 127" hexmask.long.byte 0x7C 16.--23. 1. "HCODE127,Huffman code 127" newline hexmask.long.byte 0x7C 8.--11. 1. "HLEN126,Huffman length 126" hexmask.long.byte 0x7C 0.--7. 1. "HCODE126,Huffman code 126" line.long 0x80 "JPEG_HUFFENC_AC1_64,JPEG Huffman encoder AC1" hexmask.long.byte 0x80 24.--27. 1. "HLEN129,Huffman length 129" hexmask.long.byte 0x80 16.--23. 1. "HCODE129,Huffman code 129" newline hexmask.long.byte 0x80 8.--11. 1. "HLEN128,Huffman length 128" hexmask.long.byte 0x80 0.--7. 1. "HCODE128,Huffman code 128" line.long 0x84 "JPEG_HUFFENC_AC1_65,JPEG Huffman encoder AC1" hexmask.long.byte 0x84 24.--27. 1. "HLEN131,Huffman length 131" hexmask.long.byte 0x84 16.--23. 1. "HCODE131,Huffman code 131" newline hexmask.long.byte 0x84 8.--11. 1. "HLEN130,Huffman length 130" hexmask.long.byte 0x84 0.--7. 1. "HCODE130,Huffman code 130" line.long 0x88 "JPEG_HUFFENC_AC1_66,JPEG Huffman encoder AC1" hexmask.long.byte 0x88 24.--27. 1. "HLEN133,Huffman length 133" hexmask.long.byte 0x88 16.--23. 1. "HCODE133,Huffman code 133" newline hexmask.long.byte 0x88 8.--11. 1. "HLEN132,Huffman length 132" hexmask.long.byte 0x88 0.--7. 1. "HCODE132,Huffman code 132" line.long 0x8C "JPEG_HUFFENC_AC1_67,JPEG Huffman encoder AC1" hexmask.long.byte 0x8C 24.--27. 1. "HLEN135,Huffman length 135" hexmask.long.byte 0x8C 16.--23. 1. "HCODE135,Huffman code 135" newline hexmask.long.byte 0x8C 8.--11. 1. "HLEN134,Huffman length 134" hexmask.long.byte 0x8C 0.--7. 1. "HCODE134,Huffman code 134" line.long 0x90 "JPEG_HUFFENC_AC1_68,JPEG Huffman encoder AC1" hexmask.long.byte 0x90 24.--27. 1. "HLEN137,Huffman length 137" hexmask.long.byte 0x90 16.--23. 1. "HCODE137,Huffman code 137" newline hexmask.long.byte 0x90 8.--11. 1. "HLEN136,Huffman length 136" hexmask.long.byte 0x90 0.--7. 1. "HCODE136,Huffman code 136" line.long 0x94 "JPEG_HUFFENC_AC1_69,JPEG Huffman encoder AC1" hexmask.long.byte 0x94 24.--27. 1. "HLEN139,Huffman length 139" hexmask.long.byte 0x94 16.--23. 1. "HCODE139,Huffman code 139" newline hexmask.long.byte 0x94 8.--11. 1. "HLEN138,Huffman length 138" hexmask.long.byte 0x94 0.--7. 1. "HCODE138,Huffman code 138" line.long 0x98 "JPEG_HUFFENC_AC1_70,JPEG Huffman encoder AC1" hexmask.long.byte 0x98 24.--27. 1. "HLEN141,Huffman length 141" hexmask.long.byte 0x98 16.--23. 1. "HCODE141,Huffman code 141" newline hexmask.long.byte 0x98 8.--11. 1. "HLEN140,Huffman length 140" hexmask.long.byte 0x98 0.--7. 1. "HCODE140,Huffman code 140" line.long 0x9C "JPEG_HUFFENC_AC1_71,JPEG Huffman encoder AC1" hexmask.long.byte 0x9C 24.--27. 1. "HLEN143,Huffman length 143" hexmask.long.byte 0x9C 16.--23. 1. "HCODE143,Huffman code 143" newline hexmask.long.byte 0x9C 8.--11. 1. "HLEN142,Huffman length 142" hexmask.long.byte 0x9C 0.--7. 1. "HCODE142,Huffman code 142" line.long 0xA0 "JPEG_HUFFENC_AC1_72,JPEG Huffman encoder AC1" hexmask.long.byte 0xA0 24.--27. 1. "HLEN145,Huffman length 145" hexmask.long.byte 0xA0 16.--23. 1. "HCODE145,Huffman code 145" newline hexmask.long.byte 0xA0 8.--11. 1. "HLEN144,Huffman length 144" hexmask.long.byte 0xA0 0.--7. 1. "HCODE144,Huffman code 144" line.long 0xA4 "JPEG_HUFFENC_AC1_73,JPEG Huffman encoder AC1" hexmask.long.byte 0xA4 24.--27. 1. "HLEN147,Huffman length 147" hexmask.long.byte 0xA4 16.--23. 1. "HCODE147,Huffman code 147" newline hexmask.long.byte 0xA4 8.--11. 1. "HLEN146,Huffman length 146" hexmask.long.byte 0xA4 0.--7. 1. "HCODE146,Huffman code 146" line.long 0xA8 "JPEG_HUFFENC_AC1_74,JPEG Huffman encoder AC1" hexmask.long.byte 0xA8 24.--27. 1. "HLEN149,Huffman length 149" hexmask.long.byte 0xA8 16.--23. 1. "HCODE149,Huffman code 149" newline hexmask.long.byte 0xA8 8.--11. 1. "HLEN148,Huffman length 148" hexmask.long.byte 0xA8 0.--7. 1. "HCODE148,Huffman code 148" line.long 0xAC "JPEG_HUFFENC_AC1_75,JPEG Huffman encoder AC1" hexmask.long.byte 0xAC 24.--27. 1. "HLEN151,Huffman length 151" hexmask.long.byte 0xAC 16.--23. 1. "HCODE151,Huffman code 151" newline hexmask.long.byte 0xAC 8.--11. 1. "HLEN150,Huffman length 150" hexmask.long.byte 0xAC 0.--7. 1. "HCODE150,Huffman code 150" line.long 0xB0 "JPEG_HUFFENC_AC1_76,JPEG Huffman encoder AC1" hexmask.long.byte 0xB0 24.--27. 1. "HLEN153,Huffman length 153" hexmask.long.byte 0xB0 16.--23. 1. "HCODE153,Huffman code 153" newline hexmask.long.byte 0xB0 8.--11. 1. "HLEN152,Huffman length 152" hexmask.long.byte 0xB0 0.--7. 1. "HCODE152,Huffman code 152" line.long 0xB4 "JPEG_HUFFENC_AC1_77,JPEG Huffman encoder AC1" hexmask.long.byte 0xB4 24.--27. 1. "HLEN155,Huffman length 155" hexmask.long.byte 0xB4 16.--23. 1. "HCODE155,Huffman code 155" newline hexmask.long.byte 0xB4 8.--11. 1. "HLEN154,Huffman length 154" hexmask.long.byte 0xB4 0.--7. 1. "HCODE154,Huffman code 154" line.long 0xB8 "JPEG_HUFFENC_AC1_78,JPEG Huffman encoder AC1" hexmask.long.byte 0xB8 24.--27. 1. "HLEN157,Huffman length 157" hexmask.long.byte 0xB8 16.--23. 1. "HCODE157,Huffman code 157" newline hexmask.long.byte 0xB8 8.--11. 1. "HLEN156,Huffman length 156" hexmask.long.byte 0xB8 0.--7. 1. "HCODE156,Huffman code 156" line.long 0xBC "JPEG_HUFFENC_AC1_79,JPEG Huffman encoder AC1" hexmask.long.byte 0xBC 24.--27. 1. "HLEN159,Huffman length 159" hexmask.long.byte 0xBC 16.--23. 1. "HCODE159,Huffman code 159" newline hexmask.long.byte 0xBC 8.--11. 1. "HLEN158,Huffman length 158" hexmask.long.byte 0xBC 0.--7. 1. "HCODE158,Huffman code 158" line.long 0xC0 "JPEG_HUFFENC_AC1_80,JPEG Huffman encoder AC1" hexmask.long.byte 0xC0 24.--27. 1. "HLEN161,Huffman length 161" hexmask.long.byte 0xC0 16.--23. 1. "HCODE161,Huffman code 161" newline hexmask.long.byte 0xC0 8.--11. 1. "HLEN160,Huffman length 160" hexmask.long.byte 0xC0 0.--7. 1. "HCODE160,Huffman code 160" line.long 0xC4 "JPEG_HUFFENC_AC1_81,JPEG Huffman encoder AC1" hexmask.long.byte 0xC4 24.--27. 1. "HLEN163,Huffman length 163" hexmask.long.byte 0xC4 16.--23. 1. "HCODE163,Huffman code 163" newline hexmask.long.byte 0xC4 8.--11. 1. "HLEN162,Huffman length 162" hexmask.long.byte 0xC4 0.--7. 1. "HCODE162,Huffman code 162" line.long 0xC8 "JPEG_HUFFENC_AC1_82,JPEG Huffman encoder AC1" hexmask.long.byte 0xC8 24.--27. 1. "HLEN165,Huffman length 165" hexmask.long.byte 0xC8 16.--23. 1. "HCODE165,Huffman code 165" newline hexmask.long.byte 0xC8 8.--11. 1. "HLEN164,Huffman length 164" hexmask.long.byte 0xC8 0.--7. 1. "HCODE164,Huffman code 164" line.long 0xCC "JPEG_HUFFENC_AC1_83,JPEG Huffman encoder AC1" hexmask.long.byte 0xCC 24.--27. 1. "HLEN167,Huffman length 167" hexmask.long.byte 0xCC 16.--23. 1. "HCODE167,Huffman code 167" newline hexmask.long.byte 0xCC 8.--11. 1. "HLEN166,Huffman length 166" hexmask.long.byte 0xCC 0.--7. 1. "HCODE166,Huffman code 166" line.long 0xD0 "JPEG_HUFFENC_AC1_84,JPEG Huffman encoder AC1" hexmask.long.byte 0xD0 24.--27. 1. "HLEN169,Huffman length 169" hexmask.long.byte 0xD0 16.--23. 1. "HCODE169,Huffman code 169" newline hexmask.long.byte 0xD0 8.--11. 1. "HLEN168,Huffman length 168" hexmask.long.byte 0xD0 0.--7. 1. "HCODE168,Huffman code 168" line.long 0xD4 "JPEG_HUFFENC_AC1_85,JPEG Huffman encoder AC1" hexmask.long.byte 0xD4 24.--27. 1. "HLEN171,Huffman length 171" hexmask.long.byte 0xD4 16.--23. 1. "HCODE171,Huffman code 171" newline hexmask.long.byte 0xD4 8.--11. 1. "HLEN170,Huffman length 170" hexmask.long.byte 0xD4 0.--7. 1. "HCODE170,Huffman code 170" line.long 0xD8 "JPEG_HUFFENC_AC1_86,JPEG Huffman encoder AC1" hexmask.long.byte 0xD8 24.--27. 1. "HLEN173,Huffman length 173" hexmask.long.byte 0xD8 16.--23. 1. "HCODE173,Huffman code 173" newline hexmask.long.byte 0xD8 8.--11. 1. "HLEN172,Huffman length 172" hexmask.long.byte 0xD8 0.--7. 1. "HCODE172,Huffman code 172" line.long 0xDC "JPEG_HUFFENC_AC1_87,JPEG Huffman encoder AC1" hexmask.long.byte 0xDC 24.--27. 1. "HLEN175,Huffman length 175" hexmask.long.byte 0xDC 16.--23. 1. "HCODE175,Huffman code 175" newline hexmask.long.byte 0xDC 8.--11. 1. "HLEN174,Huffman length 174" hexmask.long.byte 0xDC 0.--7. 1. "HCODE174,Huffman code 174" group.long 0x7C0++0x1F line.long 0x0 "JPEG_HUFFENC_DC0_0,JPEG Huffman encoder DC0" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_DC0_1,JPEG Huffman encoder DC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x8 "JPEG_HUFFENC_DC0_2,JPEG Huffman encoder DC0" hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0xC "JPEG_HUFFENC_DC0_3,JPEG Huffman encoder DC0" hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x10 "JPEG_HUFFENC_DC0_4,JPEG Huffman encoder DC0" hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x14 "JPEG_HUFFENC_DC0_5,JPEG Huffman encoder DC0" hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x18 "JPEG_HUFFENC_DC0_6,JPEG Huffman encoder DC0" hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x1C "JPEG_HUFFENC_DC0_7,JPEG Huffman encoder DC0" hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14" group.long 0x89C++0x1F line.long 0x0 "JPEG_HUFFENC_DC1_0,JPEG Huffman encoder DC1" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_DC1_1,JPEG Huffman encoder DC1" hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x8 "JPEG_HUFFENC_DC1_2,JPEG Huffman encoder DC1" hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0xC "JPEG_HUFFENC_DC1_3,JPEG Huffman encoder DC1" hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x10 "JPEG_HUFFENC_DC1_4,JPEG Huffman encoder DC1" hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x14 "JPEG_HUFFENC_DC1_5,JPEG Huffman encoder DC1" hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x18 "JPEG_HUFFENC_DC1_6,JPEG Huffman encoder DC1" hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x1C "JPEG_HUFFENC_DC1_7,JPEG Huffman encoder DC1" hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14" tree.end tree.end endif tree "LPDMA (Low-power Direct Memory Access Controller)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "LPDMA1" base ad:0x46025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x8++0x3 line.long 0x0 "LPDMA_RCFGLOCKR,LPDMA configuration lock register" bitfld.long 0x0 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x0 2. "LOCK2,LOCK2" "0,1" newline bitfld.long 0x0 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x0 0. "LOCK0,LOCK0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "LPDMA_MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "LPDMA_SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" endif group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" newline bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" endif line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" endif hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." newline sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" newline bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" endif line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" endif hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." newline sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" newline bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" endif line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" endif hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." newline sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" newline bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" endif line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" endif hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." newline sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." sif (cpuis("STM32U575*")) group.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel 0 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,LPDMA channel 0 status register" endif sif (cpuis("STM32U575*")) group.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel 1 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,LPDMA channel 1 status register" endif sif (cpuis("STM32U575*")) group.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel 2 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,LPDMA channel 2 status register" endif sif (cpuis("STM32U575*")) group.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel 3 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,LPDMA channel 3 status register" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_LPDMA1" base ad:0x56025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x8++0x3 line.long 0x0 "LPDMA_RCFGLOCKR,LPDMA configuration lock register" bitfld.long 0x0 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x0 2. "LOCK2,LOCK2" "0,1" newline bitfld.long 0x0 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x0 0. "LOCK0,LOCK0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "LPDMA_MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "LPDMA_SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" endif group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" newline bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" endif line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" endif hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." newline sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" newline bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" endif line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" endif hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." newline sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" newline bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" endif line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" endif hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." newline sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" newline bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" endif rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" sif (cpuis("STM32U575*")) rbitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" rbitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline rbitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" rbitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline rbitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." rbitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline rbitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." newline bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." newline endif sif (cpuis("STM32U575*")) rbitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" endif group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" endif group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" newline bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" endif line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" bitfld.long 0x4 11. "BREQ,BREQ" "0,1" newline bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" endif sif (cpuis("STM32U575*")) bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" endif hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." newline sif (cpuis("STM32U575*")) bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." endif sif (cpuis("STM32U575*")) bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline endif sif (cpuis("STM32U575*")) bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." endif hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline endif hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." sif (cpuis("STM32U575*")) group.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel 0 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,LPDMA channel 0 status register" endif sif (cpuis("STM32U575*")) group.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel 1 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,LPDMA channel 1 status register" endif sif (cpuis("STM32U575*")) group.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel 2 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,LPDMA channel 2 status register" endif sif (cpuis("STM32U575*")) group.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel 3 flag clear register" endif sif (cpuis("STM32U575*")) group.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,LPDMA channel 3 status register" endif tree.end endif sif (cpuis("STM32U585*")) tree "LPDMA1" base ad:0x46025000 group.long 0x0++0xB line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "LPDMA_RCFGLOCKR,LPDMA configuration lock register" bitfld.long 0x8 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x8 2. "LOCK2,LOCK2" "0,1" newline bitfld.long 0x8 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x8 0. "LOCK0,LOCK0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "LPDMA_MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "LPDMA_SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,LPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of LPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,LPDMA channel 0 status register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,LPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" newline bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." newline bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "LPDMA_C0TR2,LPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." newline bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection" line.long 0x8 "LPDMA_C0BR1,LPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "LPDMA_C1LBAR,LPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of LPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,LPDMA channel 1 status register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,LPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" newline bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." newline bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "LPDMA_C1TR2,LPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." newline bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection" line.long 0x8 "LPDMA_C1BR1,LPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "LPDMA_C2LBAR,LPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of LPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,LPDMA channel 2 status register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,LPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" newline bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." newline bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "LPDMA_C2TR2,LPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." newline bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection" line.long 0x8 "LPDMA_C2BR1,LPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "LPDMA_C3LBAR,LPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of LPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,LPDMA channel 3 status register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,LPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" newline bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." newline bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "LPDMA_C3TR2,LPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." newline bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection" line.long 0x8 "LPDMA_C3BR1,LPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end tree "SEC_LPDMA1" base ad:0x56025000 group.long 0x0++0xB line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" line.long 0x8 "LPDMA_RCFGLOCKR,LPDMA configuration lock register" bitfld.long 0x8 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x8 2. "LOCK2,LOCK2" "0,1" newline bitfld.long 0x8 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x8 0. "LOCK0,LOCK0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "LPDMA_MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "LPDMA_SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,LPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of LPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,LPDMA channel 0 status register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,LPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" newline bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." newline bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "LPDMA_C0TR2,LPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." newline bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection" line.long 0x8 "LPDMA_C0BR1,LPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "LPDMA_C1LBAR,LPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of LPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,LPDMA channel 1 status register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,LPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" newline bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." newline bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "LPDMA_C1TR2,LPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." newline bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection" line.long 0x8 "LPDMA_C1BR1,LPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "LPDMA_C2LBAR,LPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of LPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,LPDMA channel 2 status register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,LPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" newline bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." newline bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "LPDMA_C2TR2,LPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." newline bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection" line.long 0x8 "LPDMA_C2BR1,LPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "LPDMA_C3LBAR,LPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of LPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,LPDMA channel 3 status register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: clears the corresponding TOF flag" bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" newline bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." newline bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" newline bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,LPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x LPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" newline bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." newline bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the LPDMA transfer to the destination" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" bitfld.long 0x0 19. "DINC,destination incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the LPDMA transfer from the source" "0: LPDMA transfer non-secure,1: LPDMA transfer secure" newline bitfld.long 0x0 11. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: If destination data width > source data width" bitfld.long 0x0 3. "SINC,source incrementing single" "0: fixed single,1: contiguously incremented single" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a single in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "LPDMA_C3TR2,LPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when LPDMA_CxBR1.BNDT[15:0] =..,1: same as 00,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first single read of each..,1: same as 00,2: at link level: a LLI link transfer is..,3: at programmed single level: each programmed.." newline bitfld.long 0x4 11. "BREQ,block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection" line.long 0x8 "LPDMA_C3BR1,LPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory" "0: no LPDMA_CxBR1 update from memory and internally..,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update LPDMA_CxSAR from memory" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR register from memory" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR register from memory" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32U595*")) tree "LPDMA1" base ad:0x46025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end tree "SEC_LPDMA1" base ad:0x56025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end endif sif (cpuis("STM32U599*")) tree "LPDMA1" base ad:0x46025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end tree "SEC_LPDMA1" base ad:0x56025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end endif sif (cpuis("STM32U5A5*")) tree "LPDMA1" base ad:0x46025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end tree "SEC_LPDMA1" base ad:0x56025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end endif sif (cpuis("STM32U5A9*")) tree "LPDMA1" base ad:0x46025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end tree "SEC_LPDMA1" base ad:0x56025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end endif sif (cpuis("STM32U5F*")) tree "LPDMA1" base ad:0x46025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end tree "SEC_LPDMA1" base ad:0x56025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end endif sif (cpuis("STM32U5G*")) tree "LPDMA1" base ad:0x46025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end tree "SEC_LPDMA1" base ad:0x56025000 group.long 0x0++0x7 line.long 0x0 "LPDMA_SECCFGR,LPDMA secure configuration register" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" line.long 0x4 "LPDMA_PRIVCFGR,LPDMA privileged configuration register" bitfld.long 0x4 3. "PRIV3,PRIV3" "0,1" bitfld.long 0x4 2. "PRIV2,PRIV2" "0,1" newline bitfld.long 0x4 1. "PRIV1,PRIV1" "0,1" bitfld.long 0x4 0. "PRIV0,PRIV0" "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MISR,LPDMA non-secure masked interrupt status register" bitfld.long 0x0 3. "MIS3,MIS3" "0,1" bitfld.long 0x0 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x0 1. "MIS1,MIS1" "0,1" bitfld.long 0x0 0. "MIS0,MIS0" "0,1" line.long 0x4 "SMISR,LPDMA secure masked interrupt status register" bitfld.long 0x4 3. "MIS3,MIS3" "0,1" bitfld.long 0x4 2. "MIS2,MIS2" "0,1" newline bitfld.long 0x4 1. "MIS1,MIS1" "0,1" bitfld.long 0x4 0. "MIS0,MIS0" "0,1" group.long 0x50++0x3 line.long 0x0 "LPDMA_C0LBAR,channel x linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "LPDMA_C0FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x60++0x3 line.long 0x0 "LPDMA_C0SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x64++0x3 line.long 0x0 "LPDMA_C0CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x90++0x13 line.long 0x0 "LPDMA_C0TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C0TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11 these bits are ignored. Else a DMA transfer is conditioned by (at.." "0: at block level,1: at 2D/repeated block level for channel x=12 to 15,?,?" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C0BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C0SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C0DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "LPDMA_C0LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C1LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "LPDMA_C1FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0xE0++0x3 line.long 0x0 "LPDMA_C1SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0xE4++0x3 line.long 0x0 "LPDMA_C1CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x110++0x13 line.long 0x0 "LPDMA_C1TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C1TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C1BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C1SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C1DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "LPDMA_C1LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C2LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "LPDMA_C2FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x160++0x3 line.long 0x0 "LPDMA_C2SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x164++0x3 line.long 0x0 "LPDMA_C2CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x190++0x13 line.long 0x0 "LPDMA_C2TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C2TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C2BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C2SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C2DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "LPDMA_C2LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." line.long 0x4 "LPDMA_C3LBAR,channel x linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of DMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "LPDMA_C3FCR,LPDMA channel x flag clear register" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag" "0: no effect,1: clears the corresponding SUSPF flag" bitfld.long 0x0 12. "USEF,user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag" "0: no effect,1: clears the corresponding USEF flag" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag" "0: no effect,1: clears the corresponding ULEF flag" bitfld.long 0x0 10. "DTEF,data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag" "0: no effect,1: clears the corresponding DTEF flag" newline bitfld.long 0x0 9. "HTF,half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag" "0: no effect,1: clears the corresponding HTF flag" bitfld.long 0x0 8. "TCF,transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag" "0: no effect,1: clears the corresponding TCF flag" rgroup.long 0x1E0++0x3 line.long 0x0 "LPDMA_C3SR,channel x status register" bitfld.long 0x0 13. "SUSPF,completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag - 0: no user setting error event - 1: a user setting error event occurred" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer depending on the transfer complete event mode i.e." "0: no half transfer event,1: an half transfer event occurred An half transfer.." bitfld.long 0x0 8. "TCF,transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete or a LLI transfer complete including the upload of.." "0: no transfer complete event,1: a transfer complete event occurred A transfer.." newline bitfld.long 0x0 0. "IDLEF,idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be.." "0: the channel is not in idle state,1: the channel is in idle state This idle flag is.." group.long 0x1E4++0x3 line.long 0x0 "LPDMA_C3CR,channel x control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the DMA transfer of the channel x vs others- 00: low priority low weight- 01: low priority mid weight- 10: low priority high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1." "0: low priority,1: low priority,?,?" bitfld.long 0x0 16. "LSM,Link Step mode:- 0: channel is executed for the full linked-list and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e." "0: the 16 low significant bits of the link address..,1: channel is executed once for the current LLI:*.." newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend - 0: write: resume channel read: channel not suspended - 1: write: suspend channel read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 2. Else:.." "0: write: resume channel,1: write: suspend channel" bitfld.long 0x0 1. "RESET,reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO the reset of the channel internal state and the reset of the SUSP and EN bits whatever is written.." "0: no channel reset,1: channel reset This bit is write only" newline bitfld.long 0x0 0. "EN,enable - 0: write: ignored read: channel disabled - 1: write: enable channel read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit whatever is written into this bit 0. Else: * this bit is de-asserted.." "0: write: ignored,1: write: enable channel" group.long 0x210++0x13 line.long 0x0 "LPDMA_C3TR1,LPDMA channel x transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" bitfld.long 0x0 19. "DINC,destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address pointed by DMA_CxDAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a.." "0: fixed burst-,1: contiguously incremented burstThe destination.." newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user.." "0: byte-,1: half-word,?,?" bitfld.long 0x0 15. "SSEC,security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when.." "0: non-secure-,1: secure" newline bitfld.long 0x0 11.--12. "PAM,PAM" "0,1,2,3" bitfld.long 0x0 3. "SINC,source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address pointed by DMA_CxSAR is either kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous.." "0: fixed burst-,1: contiguously incremented burstThe source address" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting.." "0: byte-,1: half-word,?,?" line.long 0x4 "LPDMA_C3TR2,LPDMA channel x transfer register 2" bitfld.long 0x4 30.--31. "TCEM,Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is.." "0: at block level,1: channel x=0 to,?,?" bitfld.long 0x4 24.--25. "TRIGPOL,Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00" "0: no trigger,1: trigger on the rising edge,?,?" newline hexmask.long.byte 0x4 16.--20. 1. "TRIGSEL,Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer with an active trigger event if TRIGPOL[1:0] !=00." bitfld.long 0x4 14.--15. "TRIGM,Trigger mode" "0,1,2,3" newline bitfld.long 0x4 11. "BREQ,BREQ" "0,1" bitfld.long 0x4 9. "SWREQ,Software request When LPDMA_CxCR.EN is asserted this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And.." "0: no software request,1: software request" newline hexmask.long.byte 0x4 0.--4. 1. "REQSEL,DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer) this bit is ignored. Else the selected hardware request as per Table 12 is.." line.long 0x8 "LPDMA_C3BR1,LPDMA channel x block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "LPDMA_C3SAR,LPDMA channel x source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "LPDMA_C3DAR,LPDMA channel x destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x3 line.long 0x0 "LPDMA_C3LLR,LPDMA channel x linked-list address register" bitfld.long 0x0 31. "UT1,Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update" "0: no LPDMA_CxTR1 update,1: LPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update" "0: no LPDMA_CxTR2 update,1: LPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0 the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the.." "0: no LPDMA_CxBR1 update,1: LPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update" "0: no LPDMA_CxSAR update,1: LPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update" "0: no LPDMA_CxDAR update,1: LPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update" "0: no LPDMA_CxLLR update,1: LPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file." tree.end endif tree.end tree "LPGPIO (Low-power General-Purpose Inputs/Outputs)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "LPGPIO1" base ad:0x46020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" newline bitfld.long 0x0 3. "MODE3,MODE3" "0,1" bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" newline bitfld.long 0x0 3. "ID3,ID3" "0,1" bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 0.--15. 1. "IDy,IDy" endif group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" newline bitfld.long 0x0 3. "OD3,OD3" "0,1" bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 15. "ODy15,ODy15" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "ODy14,ODy14" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 13. "ODy13,ODy13" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 12. "ODy12,ODy12" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "ODy11,ODy11" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 10. "ODy10,ODy10" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 9. "ODy9,ODy9" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 8. "ODy8,ODy8" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 7. "ODy7,ODy7" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 6. "ODy6,ODy6" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 5. "ODy5,ODy5" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 4. "ODy4,ODy4" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "ODy3,ODy3" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "ODy2,ODy2" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 1. "ODy1,ODy1" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 0. "ODy0,ODy0" "0,1" endif wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" newline bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" newline bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRy31,BRy31" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30. "BRy30,BRy30" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 29. "BRy29,BRy29" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 28. "BRy28,BRy28" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "BRy27,BRy27" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 26. "BRy26,BRy26" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 25. "BRy25,BRy25" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24. "BRy24,BRy24" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 23. "BRy23,BRy23" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22. "BRy22,BRy22" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 21. "BRy21,BRy21" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 20. "BRy20,BRy20" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "BRy19,BRy19" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 18. "BRy18,BRy18" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "BRy17,BRy17" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "BRy16,BRy16" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 15. "BSy15,BSy15" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "BSy14,BSy14" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 13. "BSy13,BSy13" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 12. "BSy12,BSy12" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BSy11,BSy11" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 10. "BSy10,BSy10" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 9. "BSy9,BSy9" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 8. "BSy8,BSy8" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 7. "BSy7,BSy7" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 6. "BSy6,BSy6" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 5. "BSy5,BSy5" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 4. "BSy4,BSy4" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "BSy3,BSy3" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "BSy2,BSy2" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 1. "BSy1,BSy1" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 0. "BSy0,BSy0" "0,1" endif wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" newline bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 15. "BRy15,BRy15" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "BRy14,BRy14" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 13. "BRy13,BRy13" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 12. "BRy12,BRy12" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BRy11,BRy11" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 10. "BRy10,BRy10" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 9. "BRy9,BRy9" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 8. "BRy8,BRy8" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 7. "BRy7,BRy7" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 6. "BRy6,BRy6" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 5. "BRy5,BRy5" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 4. "BRy4,BRy4" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "BRy3,BRy3" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "BRy2,BRy2" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 1. "BRy1,BRy1" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 0. "BRy0,BRy0" "0,1" endif sif (cpuis("STM32U575*")) rgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_LPGPIO1" base ad:0x56020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" newline bitfld.long 0x0 3. "MODE3,MODE3" "0,1" bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" newline bitfld.long 0x0 3. "ID3,ID3" "0,1" bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 0.--15. 1. "IDy,IDy" endif group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" newline bitfld.long 0x0 3. "OD3,OD3" "0,1" bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 15. "ODy15,ODy15" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "ODy14,ODy14" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 13. "ODy13,ODy13" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 12. "ODy12,ODy12" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "ODy11,ODy11" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 10. "ODy10,ODy10" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 9. "ODy9,ODy9" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 8. "ODy8,ODy8" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 7. "ODy7,ODy7" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 6. "ODy6,ODy6" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 5. "ODy5,ODy5" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 4. "ODy4,ODy4" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "ODy3,ODy3" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "ODy2,ODy2" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 1. "ODy1,ODy1" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 0. "ODy0,ODy0" "0,1" endif wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" newline bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" newline bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 31. "BRy31,BRy31" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 30. "BRy30,BRy30" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 29. "BRy29,BRy29" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 28. "BRy28,BRy28" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 27. "BRy27,BRy27" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 26. "BRy26,BRy26" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 25. "BRy25,BRy25" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 24. "BRy24,BRy24" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 23. "BRy23,BRy23" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 22. "BRy22,BRy22" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 21. "BRy21,BRy21" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 20. "BRy20,BRy20" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 19. "BRy19,BRy19" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 18. "BRy18,BRy18" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 17. "BRy17,BRy17" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 16. "BRy16,BRy16" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 15. "BSy15,BSy15" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "BSy14,BSy14" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 13. "BSy13,BSy13" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 12. "BSy12,BSy12" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BSy11,BSy11" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 10. "BSy10,BSy10" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 9. "BSy9,BSy9" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 8. "BSy8,BSy8" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 7. "BSy7,BSy7" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 6. "BSy6,BSy6" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 5. "BSy5,BSy5" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 4. "BSy4,BSy4" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "BSy3,BSy3" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "BSy2,BSy2" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 1. "BSy1,BSy1" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 0. "BSy0,BSy0" "0,1" endif wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" newline bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 15. "BRy15,BRy15" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 14. "BRy14,BRy14" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 13. "BRy13,BRy13" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 12. "BRy12,BRy12" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 11. "BRy11,BRy11" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 10. "BRy10,BRy10" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 9. "BRy9,BRy9" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 8. "BRy8,BRy8" "0,1" newline endif sif (cpuis("STM32U575*")) bitfld.long 0x0 7. "BRy7,BRy7" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 6. "BRy6,BRy6" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 5. "BRy5,BRy5" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 4. "BRy4,BRy4" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 3. "BRy3,BRy3" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 2. "BRy2,BRy2" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 1. "BRy1,BRy1" "0,1" endif sif (cpuis("STM32U575*")) bitfld.long 0x0 0. "BRy0,BRy0" "0,1" endif sif (cpuis("STM32U575*")) rgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" endif tree.end endif sif (cpuis("STM32U585*")) tree "LPGPIO1" base ad:0x46020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" newline bitfld.long 0x0 3. "MODE3,MODE3" "0,1" bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" hexmask.long.word 0x0 0.--15. 1. "IDy,IDy" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "ODy15,ODy15" "0,1" bitfld.long 0x0 14. "ODy14,ODy14" "0,1" bitfld.long 0x0 13. "ODy13,ODy13" "0,1" bitfld.long 0x0 12. "ODy12,ODy12" "0,1" bitfld.long 0x0 11. "ODy11,ODy11" "0,1" bitfld.long 0x0 10. "ODy10,ODy10" "0,1" bitfld.long 0x0 9. "ODy9,ODy9" "0,1" bitfld.long 0x0 8. "ODy8,ODy8" "0,1" bitfld.long 0x0 7. "ODy7,ODy7" "0,1" bitfld.long 0x0 6. "ODy6,ODy6" "0,1" bitfld.long 0x0 5. "ODy5,ODy5" "0,1" bitfld.long 0x0 4. "ODy4,ODy4" "0,1" newline bitfld.long 0x0 3. "ODy3,ODy3" "0,1" bitfld.long 0x0 2. "ODy2,ODy2" "0,1" bitfld.long 0x0 1. "ODy1,ODy1" "0,1" bitfld.long 0x0 0. "ODy0,ODy0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BRy31,BRy31" "0,1" bitfld.long 0x0 30. "BRy30,BRy30" "0,1" bitfld.long 0x0 29. "BRy29,BRy29" "0,1" bitfld.long 0x0 28. "BRy28,BRy28" "0,1" bitfld.long 0x0 27. "BRy27,BRy27" "0,1" bitfld.long 0x0 26. "BRy26,BRy26" "0,1" bitfld.long 0x0 25. "BRy25,BRy25" "0,1" bitfld.long 0x0 24. "BRy24,BRy24" "0,1" bitfld.long 0x0 23. "BRy23,BRy23" "0,1" bitfld.long 0x0 22. "BRy22,BRy22" "0,1" bitfld.long 0x0 21. "BRy21,BRy21" "0,1" bitfld.long 0x0 20. "BRy20,BRy20" "0,1" newline bitfld.long 0x0 19. "BRy19,BRy19" "0,1" bitfld.long 0x0 18. "BRy18,BRy18" "0,1" bitfld.long 0x0 17. "BRy17,BRy17" "0,1" bitfld.long 0x0 16. "BRy16,BRy16" "0,1" bitfld.long 0x0 15. "BSy15,BSy15" "0,1" bitfld.long 0x0 14. "BSy14,BSy14" "0,1" bitfld.long 0x0 13. "BSy13,BSy13" "0,1" bitfld.long 0x0 12. "BSy12,BSy12" "0,1" bitfld.long 0x0 11. "BSy11,BSy11" "0,1" bitfld.long 0x0 10. "BSy10,BSy10" "0,1" bitfld.long 0x0 9. "BSy9,BSy9" "0,1" bitfld.long 0x0 8. "BSy8,BSy8" "0,1" newline bitfld.long 0x0 7. "BSy7,BSy7" "0,1" bitfld.long 0x0 6. "BSy6,BSy6" "0,1" bitfld.long 0x0 5. "BSy5,BSy5" "0,1" bitfld.long 0x0 4. "BSy4,BSy4" "0,1" bitfld.long 0x0 3. "BSy3,BSy3" "0,1" bitfld.long 0x0 2. "BSy2,BSy2" "0,1" bitfld.long 0x0 1. "BSy1,BSy1" "0,1" bitfld.long 0x0 0. "BSy0,BSy0" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BRy15,BRy15" "0,1" bitfld.long 0x0 14. "BRy14,BRy14" "0,1" bitfld.long 0x0 13. "BRy13,BRy13" "0,1" bitfld.long 0x0 12. "BRy12,BRy12" "0,1" bitfld.long 0x0 11. "BRy11,BRy11" "0,1" bitfld.long 0x0 10. "BRy10,BRy10" "0,1" bitfld.long 0x0 9. "BRy9,BRy9" "0,1" bitfld.long 0x0 8. "BRy8,BRy8" "0,1" bitfld.long 0x0 7. "BRy7,BRy7" "0,1" bitfld.long 0x0 6. "BRy6,BRy6" "0,1" bitfld.long 0x0 5. "BRy5,BRy5" "0,1" bitfld.long 0x0 4. "BRy4,BRy4" "0,1" newline bitfld.long 0x0 3. "BRy3,BRy3" "0,1" bitfld.long 0x0 2. "BRy2,BRy2" "0,1" bitfld.long 0x0 1. "BRy1,BRy1" "0,1" bitfld.long 0x0 0. "BRy0,BRy0" "0,1" tree.end tree "SEC_LPGPIO1" base ad:0x56020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" newline bitfld.long 0x0 3. "MODE3,MODE3" "0,1" bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" hexmask.long.word 0x0 0.--15. 1. "IDy,IDy" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "ODy15,ODy15" "0,1" bitfld.long 0x0 14. "ODy14,ODy14" "0,1" bitfld.long 0x0 13. "ODy13,ODy13" "0,1" bitfld.long 0x0 12. "ODy12,ODy12" "0,1" bitfld.long 0x0 11. "ODy11,ODy11" "0,1" bitfld.long 0x0 10. "ODy10,ODy10" "0,1" bitfld.long 0x0 9. "ODy9,ODy9" "0,1" bitfld.long 0x0 8. "ODy8,ODy8" "0,1" bitfld.long 0x0 7. "ODy7,ODy7" "0,1" bitfld.long 0x0 6. "ODy6,ODy6" "0,1" bitfld.long 0x0 5. "ODy5,ODy5" "0,1" bitfld.long 0x0 4. "ODy4,ODy4" "0,1" newline bitfld.long 0x0 3. "ODy3,ODy3" "0,1" bitfld.long 0x0 2. "ODy2,ODy2" "0,1" bitfld.long 0x0 1. "ODy1,ODy1" "0,1" bitfld.long 0x0 0. "ODy0,ODy0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BRy31,BRy31" "0,1" bitfld.long 0x0 30. "BRy30,BRy30" "0,1" bitfld.long 0x0 29. "BRy29,BRy29" "0,1" bitfld.long 0x0 28. "BRy28,BRy28" "0,1" bitfld.long 0x0 27. "BRy27,BRy27" "0,1" bitfld.long 0x0 26. "BRy26,BRy26" "0,1" bitfld.long 0x0 25. "BRy25,BRy25" "0,1" bitfld.long 0x0 24. "BRy24,BRy24" "0,1" bitfld.long 0x0 23. "BRy23,BRy23" "0,1" bitfld.long 0x0 22. "BRy22,BRy22" "0,1" bitfld.long 0x0 21. "BRy21,BRy21" "0,1" bitfld.long 0x0 20. "BRy20,BRy20" "0,1" newline bitfld.long 0x0 19. "BRy19,BRy19" "0,1" bitfld.long 0x0 18. "BRy18,BRy18" "0,1" bitfld.long 0x0 17. "BRy17,BRy17" "0,1" bitfld.long 0x0 16. "BRy16,BRy16" "0,1" bitfld.long 0x0 15. "BSy15,BSy15" "0,1" bitfld.long 0x0 14. "BSy14,BSy14" "0,1" bitfld.long 0x0 13. "BSy13,BSy13" "0,1" bitfld.long 0x0 12. "BSy12,BSy12" "0,1" bitfld.long 0x0 11. "BSy11,BSy11" "0,1" bitfld.long 0x0 10. "BSy10,BSy10" "0,1" bitfld.long 0x0 9. "BSy9,BSy9" "0,1" bitfld.long 0x0 8. "BSy8,BSy8" "0,1" newline bitfld.long 0x0 7. "BSy7,BSy7" "0,1" bitfld.long 0x0 6. "BSy6,BSy6" "0,1" bitfld.long 0x0 5. "BSy5,BSy5" "0,1" bitfld.long 0x0 4. "BSy4,BSy4" "0,1" bitfld.long 0x0 3. "BSy3,BSy3" "0,1" bitfld.long 0x0 2. "BSy2,BSy2" "0,1" bitfld.long 0x0 1. "BSy1,BSy1" "0,1" bitfld.long 0x0 0. "BSy0,BSy0" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BRy15,BRy15" "0,1" bitfld.long 0x0 14. "BRy14,BRy14" "0,1" bitfld.long 0x0 13. "BRy13,BRy13" "0,1" bitfld.long 0x0 12. "BRy12,BRy12" "0,1" bitfld.long 0x0 11. "BRy11,BRy11" "0,1" bitfld.long 0x0 10. "BRy10,BRy10" "0,1" bitfld.long 0x0 9. "BRy9,BRy9" "0,1" bitfld.long 0x0 8. "BRy8,BRy8" "0,1" bitfld.long 0x0 7. "BRy7,BRy7" "0,1" bitfld.long 0x0 6. "BRy6,BRy6" "0,1" bitfld.long 0x0 5. "BRy5,BRy5" "0,1" bitfld.long 0x0 4. "BRy4,BRy4" "0,1" newline bitfld.long 0x0 3. "BRy3,BRy3" "0,1" bitfld.long 0x0 2. "BRy2,BRy2" "0,1" bitfld.long 0x0 1. "BRy1,BRy1" "0,1" bitfld.long 0x0 0. "BRy0,BRy0" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "LPGPIO1" base ad:0x46020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end tree "SEC_LPGPIO1" base ad:0x56020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "LPGPIO1" base ad:0x46020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end tree "SEC_LPGPIO1" base ad:0x56020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "LPGPIO1" base ad:0x46020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end tree "SEC_LPGPIO1" base ad:0x56020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "LPGPIO1" base ad:0x46020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end tree "SEC_LPGPIO1" base ad:0x56020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "LPGPIO1" base ad:0x46020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end tree "SEC_LPGPIO1" base ad:0x56020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "LPGPIO1" base ad:0x46020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end tree "SEC_LPGPIO1" base ad:0x56020000 group.long 0x0++0x3 line.long 0x0 "LPGPIO_MODER,LPGPIO port mode register" bitfld.long 0x0 15. "MODE15,MODE15" "0,1" bitfld.long 0x0 14. "MODE14,MODE14" "0,1" bitfld.long 0x0 13. "MODE13,MODE13" "0,1" bitfld.long 0x0 12. "MODE12,MODE12" "0,1" bitfld.long 0x0 11. "MODE11,MODE11" "0,1" bitfld.long 0x0 10. "MODE10,MODE10" "0,1" bitfld.long 0x0 9. "MODE9,MODE9" "0,1" bitfld.long 0x0 8. "MODE8,MODE8" "0,1" bitfld.long 0x0 7. "MODE7,MODE7" "0,1" bitfld.long 0x0 6. "MODE6,MODE6" "0,1" bitfld.long 0x0 5. "MODE5,MODE5" "0,1" bitfld.long 0x0 4. "MODE4,MODE4" "0,1" bitfld.long 0x0 3. "MODE3,MODE3" "0,1" newline bitfld.long 0x0 2. "MODE2,MODE2" "0,1" bitfld.long 0x0 1. "MODE1,MODE1" "0,1" bitfld.long 0x0 0. "MODE0,MODE0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "LPGPIO_IDR,LPGPIO port input data register" bitfld.long 0x0 15. "ID15,ID15" "0,1" bitfld.long 0x0 14. "ID14,ID14" "0,1" bitfld.long 0x0 13. "ID13,ID13" "0,1" bitfld.long 0x0 12. "ID12,ID12" "0,1" bitfld.long 0x0 11. "ID11,ID11" "0,1" bitfld.long 0x0 10. "ID10,ID10" "0,1" bitfld.long 0x0 9. "ID9,ID9" "0,1" bitfld.long 0x0 8. "ID8,ID8" "0,1" bitfld.long 0x0 7. "ID7,ID7" "0,1" bitfld.long 0x0 6. "ID6,ID6" "0,1" bitfld.long 0x0 5. "ID5,ID5" "0,1" bitfld.long 0x0 4. "ID4,ID4" "0,1" bitfld.long 0x0 3. "ID3,ID3" "0,1" newline bitfld.long 0x0 2. "ID2,ID2" "0,1" bitfld.long 0x0 1. "ID1,ID1" "0,1" bitfld.long 0x0 0. "ID0,ID0" "0,1" group.long 0x14++0x3 line.long 0x0 "LPGPIO_ODR,LPGPIO port output data register" bitfld.long 0x0 15. "OD15,OD15" "0,1" bitfld.long 0x0 14. "OD14,OD14" "0,1" bitfld.long 0x0 13. "OD13,OD13" "0,1" bitfld.long 0x0 12. "OD12,OD12" "0,1" bitfld.long 0x0 11. "OD11,OD11" "0,1" bitfld.long 0x0 10. "OD10,OD10" "0,1" bitfld.long 0x0 9. "OD9,OD9" "0,1" bitfld.long 0x0 8. "OD8,OD8" "0,1" bitfld.long 0x0 7. "OD7,OD7" "0,1" bitfld.long 0x0 6. "OD6,OD6" "0,1" bitfld.long 0x0 5. "OD5,OD5" "0,1" bitfld.long 0x0 4. "OD4,OD4" "0,1" bitfld.long 0x0 3. "OD3,OD3" "0,1" newline bitfld.long 0x0 2. "OD2,OD2" "0,1" bitfld.long 0x0 1. "OD1,OD1" "0,1" bitfld.long 0x0 0. "OD0,OD0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "LPGPIO_BSRR,LPGPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" newline bitfld.long 0x0 18. "BR2,BR2" "0,1" bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" newline bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "LPGPIO_BRR,LPGPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" newline bitfld.long 0x0 2. "BR2,BR2" "0,1" bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" tree.end endif tree.end tree "LPTIM (Low-power Timer)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "LPTIM1" base ad:0x46004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" sif (cpuis("STM32U575*")) rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" newline hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_LPTIM1" base ad:0x56004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" sif (cpuis("STM32U575*")) rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" newline hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "LPTIM2" base ad:0x40009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" sif (cpuis("STM32U575*")) rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" newline hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_LPTIM2" base ad:0x50009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" sif (cpuis("STM32U575*")) rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" newline hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "LPTIM3" base ad:0x46004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" sif (cpuis("STM32U575*")) rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" newline hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_LPTIM3" base ad:0x56004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" sif (cpuis("STM32U575*")) rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" newline hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "LPTIM4" base ad:0x46004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" sif (cpuis("STM32U575*")) rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" newline hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_LPTIM4" base ad:0x56004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" sif (cpuis("STM32U575*")) rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" newline hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" endif tree.end endif sif (cpuis("STM32U585*")) tree "LPTIM1" base ad:0x46004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" newline bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" tree.end tree "SEC_LPTIM1" base ad:0x56004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" newline bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" tree.end endif sif (cpuis("STM32U585*")) tree "LPTIM2" base ad:0x40009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" newline bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" tree.end tree "SEC_LPTIM2" base ad:0x50009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" newline bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" tree.end endif sif (cpuis("STM32U585*")) tree "LPTIM3" base ad:0x46004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" newline bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" tree.end tree "SEC_LPTIM3" base ad:0x56004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" newline bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" tree.end endif sif (cpuis("STM32U585*")) tree "LPTIM4" base ad:0x46004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" newline bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" newline bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" newline bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" tree.end tree "SEC_LPTIM4" base ad:0x56004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" newline bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" newline bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" newline bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" rgroup.long 0x3EC++0x7 line.long 0x0 "HWCFGR2,LPTIM peripheral hardware configuration register 2" bitfld.long 0x0 16. "CFG3,peripheral hardware configuration 3" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,peripheral hardware configuration 1" line.long 0x4 "HWCFGR1,LPTIM peripheral hardware configuration register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG4,peripheral hardware configuration 4" hexmask.long.byte 0x4 16.--19. 1. "CFG3,peripheral hardware configuration 3" hexmask.long.byte 0x4 8.--15. 1. "CFG2,peripheral hardware configuration 2" hexmask.long.byte 0x4 0.--7. 1. "CFG1,peripheral hardware configuration 1" tree.end endif sif (cpuis("STM32U595*")) tree "LPTIM1" base ad:0x46004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM1" base ad:0x56004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U595*")) tree "LPTIM2" base ad:0x40009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM2" base ad:0x50009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U595*")) tree "LPTIM3" base ad:0x46004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM3" base ad:0x56004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U595*")) tree "LPTIM4" base ad:0x46004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM4" base ad:0x56004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U599*")) tree "LPTIM1" base ad:0x46004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM1" base ad:0x56004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U599*")) tree "LPTIM2" base ad:0x40009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM2" base ad:0x50009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U599*")) tree "LPTIM3" base ad:0x46004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM3" base ad:0x56004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U599*")) tree "LPTIM4" base ad:0x46004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM4" base ad:0x56004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5A5*")) tree "LPTIM1" base ad:0x46004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM1" base ad:0x56004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5A5*")) tree "LPTIM2" base ad:0x40009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM2" base ad:0x50009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5A5*")) tree "LPTIM3" base ad:0x46004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM3" base ad:0x56004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5A5*")) tree "LPTIM4" base ad:0x46004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM4" base ad:0x56004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5A9*")) tree "LPTIM1" base ad:0x46004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM1" base ad:0x56004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5A9*")) tree "LPTIM2" base ad:0x40009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM2" base ad:0x50009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5A9*")) tree "LPTIM3" base ad:0x46004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM3" base ad:0x56004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5A9*")) tree "LPTIM4" base ad:0x46004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM4" base ad:0x56004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5F*")) tree "LPTIM1" base ad:0x46004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM1" base ad:0x56004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5F*")) tree "LPTIM2" base ad:0x40009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM2" base ad:0x50009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5F*")) tree "LPTIM3" base ad:0x46004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM3" base ad:0x56004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5F*")) tree "LPTIM4" base ad:0x46004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM4" base ad:0x56004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5G*")) tree "LPTIM1" base ad:0x46004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM1" base ad:0x56004400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5G*")) tree "LPTIM2" base ad:0x40009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM2" base ad:0x50009400 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5G*")) tree "LPTIM3" base ad:0x46004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM3" base ad:0x56004800 rgroup.long 0x0++0x3 line.long 0x0 "ISR_output,Interrupt and Status Register (output mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" rgroup.long 0x0++0x3 line.long 0x0 "ISR_input,Interrupt and Status Register (intput mode)" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0,1" bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0,1" bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_output,Interrupt Clear Register (output mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR_input,Interrupt Clear Register (intput mode)" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "DIER_output,LPTIM interrupt Enable Register (output mode)" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0,1" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER_input,LPTIM interrupt Enable Register (intput mode)" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0,1" bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0,1" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0,1" bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0,1" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0,1" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32U5G*")) tree "LPTIM4" base ad:0x46004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "SEC_LPTIM4" base ad:0x56004C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "DIER,LPTIM interrupt Enable Register" bitfld.long 0x0 8. "REPOKIE,REPOKIE" "0,1" bitfld.long 0x0 7. "UEIE,Update event interrupt" "0,1" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CC1IF,Capture/compare 1 clear flag" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CCR1,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0,1,2,3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0,1,2,3" line.long 0x4 "RCR,LPTIM repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "CCMR1,LPTIM capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0,1,2,3" bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity" "0,1,2,3" bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable" "0,1" bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0,1" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0,1,2,3" bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity" "0,1,2,3" bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable" "0,1" bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0,1" group.long 0x34++0x3 line.long 0x0 "CCR2,LPTIM Compare Register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif tree.end tree "LPUART (Low-power Universal Asynchronous Receiver Transmitter)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "LPUART1" base ad:0x46002400 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" newline bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" newline bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" newline bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" newline bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" newline bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" newline bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0xB line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x0 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x4 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.tbyte 0x8 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" sif (cpuis("STM32U575*")) bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" endif hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_LPUART1" base ad:0x56002400 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" newline bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" newline bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" newline bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32U575*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" newline bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" newline bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" newline bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0xB line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x0 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x4 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.tbyte 0x8 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" sif (cpuis("STM32U575*")) bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" endif hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U585*")) tree "LPUART1" base ad:0x46002400 group.long 0x0++0xF line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_LPUART1" base ad:0x56002400 group.long 0x0++0xF line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U595*")) tree "LPUART1" base ad:0x46002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_LPUART1" base ad:0x56002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U599*")) tree "LPUART1" base ad:0x46002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_LPUART1" base ad:0x56002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5A5*")) tree "LPUART1" base ad:0x46002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_LPUART1" base ad:0x56002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5A9*")) tree "LPUART1" base ad:0x46002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_LPUART1" base ad:0x56002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5F*")) tree "LPUART1" base ad:0x46002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_LPUART1" base ad:0x56002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5G*")) tree "LPUART1" base ad:0x46002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_LPUART1" base ad:0x56002400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0xF line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFNEIE" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" newline bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" newline bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFF,TXFF" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" newline bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt and status register" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,Autonomous mode control register" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif tree.end sif (cpuis("STM32U599*")||cpuis("STM32U5A9*")||cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "LTDC (LCD-TFT Display Controller)" base ad:0x0 tree "LTDC" base ad:0x40016800 group.long 0x8++0x13 line.long 0x0 "LTDC_SSCR,LTDC synchronization size configuration register" hexmask.long.word 0x0 16.--27. 1. "HSW,horizontal synchronization width (in units of pixel clock period)" hexmask.long.word 0x0 0.--10. 1. "VSH,vertical synchronization height (in units of horizontal scan line)" line.long 0x4 "LTDC_BPCR,LTDC back porch configuration register" hexmask.long.word 0x4 16.--27. 1. "AHBP,accumulated horizontal back porch (in units of pixel clock period)" hexmask.long.word 0x4 0.--10. 1. "AVBP,accumulated Vertical back porch (in units of horizontal scan line)" line.long 0x8 "LTDC_AWCR,LTDC active width configuration register" hexmask.long.word 0x8 16.--27. 1. "AAW,accumulated active width (in units of pixel clock period)" hexmask.long.word 0x8 0.--10. 1. "AAH,accumulated active height (in units of horizontal scan line)" line.long 0xC "LTDC_TWCR,LTDC total width configuration register" hexmask.long.word 0xC 16.--27. 1. "TOTALW,total width (in units of pixel clock period)" hexmask.long.word 0xC 0.--10. 1. "TOTALH,total height (in units of horizontal scan line)" line.long 0x10 "LTDC_GCR,LTDC global control register" bitfld.long 0x10 31. "HSPOL,horizontal synchronization polarity" "0: horizontal synchronization polarity is active low.,1: horizontal synchronization polarity is active.." bitfld.long 0x10 30. "VSPOL,vertical synchronization polarity" "0: vertical synchronization is active low.,1: vertical synchronization is active high." newline bitfld.long 0x10 29. "DEPOL,not data enable polarity" "0: not data enable polarity is active low.,1: not data enable polarity is active high." bitfld.long 0x10 28. "PCPOL,pixel clock polarity" "0: pixel clock polarity is active low.,1: pixel clock is active high." newline bitfld.long 0x10 16. "DEN,dither enable" "0: dither disabled,1: dither enabled" rbitfld.long 0x10 12.--14. "DRW,dither red width" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 8.--10. "DGW,dither green width" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 4.--6. "DBW,dither blue width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "LTDCEN,LCD-TFT controller enable" "0: LTDC disabled,1: LTDC enabled" group.long 0x24++0x3 line.long 0x0 "LTDC_SRCR,LTDC shadow reload configuration register" bitfld.long 0x0 1. "VBR,vertical blanking reload" "0: no effect,1: The shadow registers are reloaded during the.." bitfld.long 0x0 0. "IMR,immediate reload" "0: no effect,1: The shadow registers are reloaded immediately." group.long 0x2C++0x3 line.long 0x0 "LTDC_BCCR,LTDC background color configuration register" hexmask.long.byte 0x0 16.--23. 1. "BCRED,background color red value" hexmask.long.byte 0x0 8.--15. 1. "BCGREEN,background color green value" newline hexmask.long.byte 0x0 0.--7. 1. "BCBLUE,background color blue value" group.long 0x34++0x3 line.long 0x0 "LTDC_IER,LTDC interrupt enable register" bitfld.long 0x0 3. "RRIE,register reload interrupt enable" "0: register reload interrupt disable,1: register reload interrupt enable" bitfld.long 0x0 2. "TERRIE,transfer error interrupt enable" "0: transfer error interrupt disable,1: transfer error interrupt enable" newline bitfld.long 0x0 1. "FUIE,FIFO underrun interrupt enable" "0: FIFO underrun interrupt disable,1: FIFO underrun Interrupt enable" bitfld.long 0x0 0. "LIE,line interrupt enable" "0: line interrupt disable,1: line interrupt enable" rgroup.long 0x38++0x3 line.long 0x0 "LTDC_ISR,LTDC interrupt status register" bitfld.long 0x0 3. "RRIF,register reload interrupt flag" "0: no register reload interrupt generated,1: register reload interrupt generated when a.." bitfld.long 0x0 2. "TERRIF,transfer error interrupt flag" "0: no transfer error interrupt generated,1: transfer error interrupt generated when a bus.." newline bitfld.long 0x0 1. "FUIF,FIFO underrun interrupt flag" "0: no FIFO underrun interrupt generated.,1: FIFO underrun interrupt generated if one of the.." bitfld.long 0x0 0. "LIF,line interrupt flag" "0: no line interrupt generated,1: line interrupt generated when a programmed line.." wgroup.long 0x3C++0x3 line.long 0x0 "LTDC_ICR," bitfld.long 0x0 3. "CRRIF,clears register reload interrupt flag" "0: no effect,1: clears the RRIF flag in the LTDC_ISR register" bitfld.long 0x0 2. "CTERRIF,clears the transfer error interrupt flag" "0: no effect,1: clears the TERRIF flag in the LTDC_ISR register." newline bitfld.long 0x0 1. "CFUIF,clears the FIFO underrun interrupt flag" "0: no effect,1: clears the FUDERRIF flag in the LTDC_ISR register." bitfld.long 0x0 0. "CLIF,clears the line interrupt flag" "0: no effect,1: clears the LIF flag in the LTDC_ISR register." group.long 0x40++0x3 line.long 0x0 "LTDC_LIPCR,LTDC line interrupt position configuration register" hexmask.long.word 0x0 0.--10. 1. "LIPOS,line interrupt position" rgroup.long 0x44++0x7 line.long 0x0 "LTDC_CPSR," hexmask.long.word 0x0 16.--31. 1. "CXPOS,current X position" hexmask.long.word 0x0 0.--15. 1. "CYPOS,current Y position" line.long 0x4 "LTDC_CDSR,LTDC current display status register" bitfld.long 0x4 3. "HSYNCS,horizontal synchronization display status" "0: active low,1: active high" bitfld.long 0x4 2. "VSYNCS,vertical synchronization display status" "0: active low,1: active high" newline bitfld.long 0x4 1. "HDES,horizontal data enable display status" "0: active low,1: active high" bitfld.long 0x4 0. "VDES,vertical data enable display status" "0: active low,1: active high" group.long 0x84++0x1F line.long 0x0 "LTDC_L1CR," bitfld.long 0x0 4. "CLUTEN,color look-up table enable" "0: color look-up table disable,1: color look-up table enable" bitfld.long 0x0 1. "COLKEN,color keying enable" "0: color keying disable,1: color keying enable" newline bitfld.long 0x0 0. "LEN,layer enable" "0: layer disable,1: layer enable" line.long 0x4 "LTDC_L1WHPCR,LTDC layer 1 window horizontal position configuration register" hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,window horizontal start position" line.long 0x8 "LTDC_L1WVPCR,LTDC layer 1 window vertical position configuration register" hexmask.long.word 0x8 16.--26. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x8 0.--10. 1. "WVSTPOS,window vertical start position" line.long 0xC "LTDC_L1CKCR,LTDC layer 1 color keying configuration register" hexmask.long.byte 0xC 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,color key blue value" line.long 0x10 "LTDC_L1PFCR,LTDC layer 1 pixel format configuration register" bitfld.long 0x10 0.--2. "PF,pixel format" "0: ARGB8888,1: RGB888,2: RGB565,3: ARGB1555,4: ARGB4444,5: L8 (8-bit luminance),6: AL44 (4-bit alpha 4-bit luminance),7: AL88 (8-bit alpha 8-bit luminance)" line.long 0x14 "LTDC_L1CACR,LTDC layer 1 constant alpha configuration register" hexmask.long.byte 0x14 0.--7. 1. "CONSTA,constant alpha" line.long 0x18 "LTDC_L1DCCR,LTDC layer 1 default color configuration register" hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x18 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,default color blue" line.long 0x1C "LTDC_L1BFCR,LTDC layer 1 blending factors configuration register" bitfld.long 0x1C 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" bitfld.long 0x1C 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" group.long 0xAC++0xB line.long 0x0 "LTDC_L1CFBAR,LTDC layer 1 color frame buffer address register" hexmask.long 0x0 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x4 "LTDC_L1CFBLR,LTDC layer 1 color frame buffer length register" hexmask.long.word 0x4 16.--28. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x4 0.--12. 1. "CFBLL,color frame buffer line length" line.long 0x8 "LTDC_L1CFBLNR,LTDC layer 1 color frame buffer line number register" hexmask.long.word 0x8 0.--10. 1. "CFBLNBR,frame buffer line number" wgroup.long 0xC4++0x3 line.long 0x0 "LTDC_L1CLUTWR,LTDC layer 1 CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" group.long 0x104++0x1F line.long 0x0 "LTDC_L2CR," bitfld.long 0x0 4. "CLUTEN,color look-up table enable" "0: color look-up table disable,1: color look-up table enable" bitfld.long 0x0 1. "COLKEN,color keying enable" "0: color keying disable,1: color keying enable" newline bitfld.long 0x0 0. "LEN,layer enable" "0: layer disable,1: layer enable" line.long 0x4 "LTDC_L2WHPCR,LTDC layer 2 window horizontal position configuration register" hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,window horizontal start position" line.long 0x8 "LTDC_L2WVPCR,LTDC layer 2 window vertical position configuration register" hexmask.long.word 0x8 16.--26. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x8 0.--10. 1. "WVSTPOS,window vertical start position" line.long 0xC "LTDC_L2CKCR,LTDC layer 2 color keying configuration register" hexmask.long.byte 0xC 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,color key blue value" line.long 0x10 "LTDC_L2PFCR,LTDC layer 2 pixel format configuration register" bitfld.long 0x10 0.--2. "PF,pixel format" "0: ARGB8888,1: RGB888,2: RGB565,3: ARGB1555,4: ARGB4444,5: L8 (8-bit luminance),6: AL44 (4-bit alpha 4-bit luminance),7: AL88 (8-bit alpha 8-bit luminance)" line.long 0x14 "LTDC_L2CACR,LTDC layer 2 constant alpha configuration register" hexmask.long.byte 0x14 0.--7. 1. "CONSTA,constant alpha" line.long 0x18 "LTDC_L2DCCR,LTDC layer 2 default color configuration register" hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x18 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,default color blue" line.long 0x1C "LTDC_L2BFCR,LTDC layer 2 blending factors configuration register" bitfld.long 0x1C 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" bitfld.long 0x1C 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" group.long 0x12C++0xB line.long 0x0 "LTDC_L2CFBAR,LTDC layer 2 color frame buffer address register" hexmask.long 0x0 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x4 "LTDC_L2CFBLR,LTDC layer 2 color frame buffer length register" hexmask.long.word 0x4 16.--28. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x4 0.--12. 1. "CFBLL,color frame buffer line length" line.long 0x8 "LTDC_L2CFBLNR,LTDC layer 2 color frame buffer line number register" hexmask.long.word 0x8 0.--10. 1. "CFBLNBR,frame buffer line number" wgroup.long 0x144++0x3 line.long 0x0 "LTDC_L2CLUTWR,LTDC layer 2 CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" tree.end tree "SEC_LTDC" base ad:0x50016800 group.long 0x8++0x13 line.long 0x0 "LTDC_SSCR,LTDC synchronization size configuration register" hexmask.long.word 0x0 16.--27. 1. "HSW,horizontal synchronization width (in units of pixel clock period)" hexmask.long.word 0x0 0.--10. 1. "VSH,vertical synchronization height (in units of horizontal scan line)" line.long 0x4 "LTDC_BPCR,LTDC back porch configuration register" hexmask.long.word 0x4 16.--27. 1. "AHBP,accumulated horizontal back porch (in units of pixel clock period)" hexmask.long.word 0x4 0.--10. 1. "AVBP,accumulated Vertical back porch (in units of horizontal scan line)" line.long 0x8 "LTDC_AWCR,LTDC active width configuration register" hexmask.long.word 0x8 16.--27. 1. "AAW,accumulated active width (in units of pixel clock period)" hexmask.long.word 0x8 0.--10. 1. "AAH,accumulated active height (in units of horizontal scan line)" line.long 0xC "LTDC_TWCR,LTDC total width configuration register" hexmask.long.word 0xC 16.--27. 1. "TOTALW,total width (in units of pixel clock period)" hexmask.long.word 0xC 0.--10. 1. "TOTALH,total height (in units of horizontal scan line)" line.long 0x10 "LTDC_GCR,LTDC global control register" bitfld.long 0x10 31. "HSPOL,horizontal synchronization polarity" "0: horizontal synchronization polarity is active low.,1: horizontal synchronization polarity is active.." bitfld.long 0x10 30. "VSPOL,vertical synchronization polarity" "0: vertical synchronization is active low.,1: vertical synchronization is active high." newline bitfld.long 0x10 29. "DEPOL,not data enable polarity" "0: not data enable polarity is active low.,1: not data enable polarity is active high." bitfld.long 0x10 28. "PCPOL,pixel clock polarity" "0: pixel clock polarity is active low.,1: pixel clock is active high." newline bitfld.long 0x10 16. "DEN,dither enable" "0: dither disabled,1: dither enabled" rbitfld.long 0x10 12.--14. "DRW,dither red width" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 8.--10. "DGW,dither green width" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 4.--6. "DBW,dither blue width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "LTDCEN,LCD-TFT controller enable" "0: LTDC disabled,1: LTDC enabled" group.long 0x24++0x3 line.long 0x0 "LTDC_SRCR,LTDC shadow reload configuration register" bitfld.long 0x0 1. "VBR,vertical blanking reload" "0: no effect,1: The shadow registers are reloaded during the.." bitfld.long 0x0 0. "IMR,immediate reload" "0: no effect,1: The shadow registers are reloaded immediately." group.long 0x2C++0x3 line.long 0x0 "LTDC_BCCR,LTDC background color configuration register" hexmask.long.byte 0x0 16.--23. 1. "BCRED,background color red value" hexmask.long.byte 0x0 8.--15. 1. "BCGREEN,background color green value" newline hexmask.long.byte 0x0 0.--7. 1. "BCBLUE,background color blue value" group.long 0x34++0x3 line.long 0x0 "LTDC_IER,LTDC interrupt enable register" bitfld.long 0x0 3. "RRIE,register reload interrupt enable" "0: register reload interrupt disable,1: register reload interrupt enable" bitfld.long 0x0 2. "TERRIE,transfer error interrupt enable" "0: transfer error interrupt disable,1: transfer error interrupt enable" newline bitfld.long 0x0 1. "FUIE,FIFO underrun interrupt enable" "0: FIFO underrun interrupt disable,1: FIFO underrun Interrupt enable" bitfld.long 0x0 0. "LIE,line interrupt enable" "0: line interrupt disable,1: line interrupt enable" rgroup.long 0x38++0x3 line.long 0x0 "LTDC_ISR,LTDC interrupt status register" bitfld.long 0x0 3. "RRIF,register reload interrupt flag" "0: no register reload interrupt generated,1: register reload interrupt generated when a.." bitfld.long 0x0 2. "TERRIF,transfer error interrupt flag" "0: no transfer error interrupt generated,1: transfer error interrupt generated when a bus.." newline bitfld.long 0x0 1. "FUIF,FIFO underrun interrupt flag" "0: no FIFO underrun interrupt generated.,1: FIFO underrun interrupt generated if one of the.." bitfld.long 0x0 0. "LIF,line interrupt flag" "0: no line interrupt generated,1: line interrupt generated when a programmed line.." wgroup.long 0x3C++0x3 line.long 0x0 "LTDC_ICR," bitfld.long 0x0 3. "CRRIF,clears register reload interrupt flag" "0: no effect,1: clears the RRIF flag in the LTDC_ISR register" bitfld.long 0x0 2. "CTERRIF,clears the transfer error interrupt flag" "0: no effect,1: clears the TERRIF flag in the LTDC_ISR register." newline bitfld.long 0x0 1. "CFUIF,clears the FIFO underrun interrupt flag" "0: no effect,1: clears the FUDERRIF flag in the LTDC_ISR register." bitfld.long 0x0 0. "CLIF,clears the line interrupt flag" "0: no effect,1: clears the LIF flag in the LTDC_ISR register." group.long 0x40++0x3 line.long 0x0 "LTDC_LIPCR,LTDC line interrupt position configuration register" hexmask.long.word 0x0 0.--10. 1. "LIPOS,line interrupt position" rgroup.long 0x44++0x7 line.long 0x0 "LTDC_CPSR," hexmask.long.word 0x0 16.--31. 1. "CXPOS,current X position" hexmask.long.word 0x0 0.--15. 1. "CYPOS,current Y position" line.long 0x4 "LTDC_CDSR,LTDC current display status register" bitfld.long 0x4 3. "HSYNCS,horizontal synchronization display status" "0: active low,1: active high" bitfld.long 0x4 2. "VSYNCS,vertical synchronization display status" "0: active low,1: active high" newline bitfld.long 0x4 1. "HDES,horizontal data enable display status" "0: active low,1: active high" bitfld.long 0x4 0. "VDES,vertical data enable display status" "0: active low,1: active high" group.long 0x84++0x1F line.long 0x0 "LTDC_L1CR," bitfld.long 0x0 4. "CLUTEN,color look-up table enable" "0: color look-up table disable,1: color look-up table enable" bitfld.long 0x0 1. "COLKEN,color keying enable" "0: color keying disable,1: color keying enable" newline bitfld.long 0x0 0. "LEN,layer enable" "0: layer disable,1: layer enable" line.long 0x4 "LTDC_L1WHPCR,LTDC layer 1 window horizontal position configuration register" hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,window horizontal start position" line.long 0x8 "LTDC_L1WVPCR,LTDC layer 1 window vertical position configuration register" hexmask.long.word 0x8 16.--26. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x8 0.--10. 1. "WVSTPOS,window vertical start position" line.long 0xC "LTDC_L1CKCR,LTDC layer 1 color keying configuration register" hexmask.long.byte 0xC 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,color key blue value" line.long 0x10 "LTDC_L1PFCR,LTDC layer 1 pixel format configuration register" bitfld.long 0x10 0.--2. "PF,pixel format" "0: ARGB8888,1: RGB888,2: RGB565,3: ARGB1555,4: ARGB4444,5: L8 (8-bit luminance),6: AL44 (4-bit alpha 4-bit luminance),7: AL88 (8-bit alpha 8-bit luminance)" line.long 0x14 "LTDC_L1CACR,LTDC layer 1 constant alpha configuration register" hexmask.long.byte 0x14 0.--7. 1. "CONSTA,constant alpha" line.long 0x18 "LTDC_L1DCCR,LTDC layer 1 default color configuration register" hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x18 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,default color blue" line.long 0x1C "LTDC_L1BFCR,LTDC layer 1 blending factors configuration register" bitfld.long 0x1C 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" bitfld.long 0x1C 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" group.long 0xAC++0xB line.long 0x0 "LTDC_L1CFBAR,LTDC layer 1 color frame buffer address register" hexmask.long 0x0 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x4 "LTDC_L1CFBLR,LTDC layer 1 color frame buffer length register" hexmask.long.word 0x4 16.--28. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x4 0.--12. 1. "CFBLL,color frame buffer line length" line.long 0x8 "LTDC_L1CFBLNR,LTDC layer 1 color frame buffer line number register" hexmask.long.word 0x8 0.--10. 1. "CFBLNBR,frame buffer line number" wgroup.long 0xC4++0x3 line.long 0x0 "LTDC_L1CLUTWR,LTDC layer 1 CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" group.long 0x104++0x1F line.long 0x0 "LTDC_L2CR," bitfld.long 0x0 4. "CLUTEN,color look-up table enable" "0: color look-up table disable,1: color look-up table enable" bitfld.long 0x0 1. "COLKEN,color keying enable" "0: color keying disable,1: color keying enable" newline bitfld.long 0x0 0. "LEN,layer enable" "0: layer disable,1: layer enable" line.long 0x4 "LTDC_L2WHPCR,LTDC layer 2 window horizontal position configuration register" hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,window horizontal start position" line.long 0x8 "LTDC_L2WVPCR,LTDC layer 2 window vertical position configuration register" hexmask.long.word 0x8 16.--26. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x8 0.--10. 1. "WVSTPOS,window vertical start position" line.long 0xC "LTDC_L2CKCR,LTDC layer 2 color keying configuration register" hexmask.long.byte 0xC 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,color key blue value" line.long 0x10 "LTDC_L2PFCR,LTDC layer 2 pixel format configuration register" bitfld.long 0x10 0.--2. "PF,pixel format" "0: ARGB8888,1: RGB888,2: RGB565,3: ARGB1555,4: ARGB4444,5: L8 (8-bit luminance),6: AL44 (4-bit alpha 4-bit luminance),7: AL88 (8-bit alpha 8-bit luminance)" line.long 0x14 "LTDC_L2CACR,LTDC layer 2 constant alpha configuration register" hexmask.long.byte 0x14 0.--7. 1. "CONSTA,constant alpha" line.long 0x18 "LTDC_L2DCCR,LTDC layer 2 default color configuration register" hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x18 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,default color blue" line.long 0x1C "LTDC_L2BFCR,LTDC layer 2 blending factors configuration register" bitfld.long 0x1C 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" bitfld.long 0x1C 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" group.long 0x12C++0xB line.long 0x0 "LTDC_L2CFBAR,LTDC layer 2 color frame buffer address register" hexmask.long 0x0 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x4 "LTDC_L2CFBLR,LTDC layer 2 color frame buffer length register" hexmask.long.word 0x4 16.--28. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x4 0.--12. 1. "CFBLL,color frame buffer line length" line.long 0x8 "LTDC_L2CFBLNR,LTDC layer 2 color frame buffer line number register" hexmask.long.word 0x8 0.--10. 1. "CFBLNBR,frame buffer line number" wgroup.long 0x144++0x3 line.long 0x0 "LTDC_L2CLUTWR,LTDC layer 2 CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" tree.end tree.end endif tree "MDF (Multi-function Digital Filter)" base ad:0x0 tree "MDF1" base ad:0x40025000 group.long 0x0++0x7 line.long 0x0 "GCR,MDF global control register" hexmask.long.byte 0x0 4.--7. 1. "ILVNB,ILVNB" bitfld.long 0x0 0. "TRGO,TRGO" "0,1" line.long 0x4 "CKGCR,MDF clock generator control register" bitfld.long 0x4 31. "CKGACTIVE,CKGACTIVE" "0,1" hexmask.long.byte 0x4 24.--30. 1. "PROCDIV,PROCDIV" newline hexmask.long.byte 0x4 16.--19. 1. "CCKDIV,CCKDIV" hexmask.long.byte 0x4 12.--15. 1. "TRGSRC,TRGSRC" newline bitfld.long 0x4 8. "TRGSENS,TRGSENS" "0,1" bitfld.long 0x4 6. "CCK1DIR,CCK1DIR" "0,1" newline bitfld.long 0x4 5. "CCK0DIR,CCK0DIR" "0,1" bitfld.long 0x4 4. "CKGMOD,CKGMOD" "0,1" newline bitfld.long 0x4 2. "CCK1EN,CCK1EN" "0,1" bitfld.long 0x4 1. "CCK0EN,CCK0EN" "0,1" newline bitfld.long 0x4 0. "CKGDEN,CKGDEN" "0,1" group.long 0x80++0x3 line.long 0x0 "MDF_SITF0CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated.." "0: The serial interface is not active,1: The serial interface is active" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x100++0x3 line.long 0x0 "MDF_SITF1CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag" "0,1" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x180++0x3 line.long 0x0 "MDF_SITF2CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag" "0,1" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x200++0x3 line.long 0x0 "MDF_SITF3CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated.." "0: The serial interface is not active,1: The serial interface is active" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x280++0x3 line.long 0x0 "MDF_SITF4CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated.." "0: The serial interface is not active,1: The serial interface is active" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x300++0x3 line.long 0x0 "MDF_SITF5CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated.." "0: The serial interface is not active,1: The serial interface is active" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x84++0x3 line.long 0x0 "MDF_BSMX0CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x104++0x3 line.long 0x0 "MDF_BSMX1CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x184++0x3 line.long 0x0 "MDF_BSMX2CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x204++0x3 line.long 0x0 "MDF_BSMX3CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x284++0x3 line.long 0x0 "MDF_BSMX4CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x304++0x3 line.long 0x0 "MDF_BSMX5CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x88++0x3 line.long 0x0 "MDF_DFLT0CR,This register is used to control the digital filter x." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software." "0,1" newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x108++0x3 line.long 0x0 "MDF_DFLT1CR,This register is used to control the digital filter x." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x188++0x3 line.long 0x0 "MDF_DFLT2CR,This register is used to control the digital filter 2." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x208++0x3 line.long 0x0 "MDF_DFLT3CR,This register is used to control the digital filter 3." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x288++0x3 line.long 0x0 "MDF_DFLT4CR,This register is used to control the digital filter 4." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x308++0x3 line.long 0x0 "MDF_DFLT5CR,This register is used to control the digital filter x." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x8C++0x3 line.long 0x0 "MDF_DFLT0CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x10C++0x3 line.long 0x0 "MDF_DFLT1CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x18C++0x3 line.long 0x0 "MDF_DFLT2CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x20C++0x3 line.long 0x0 "MDF_DFLT3CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x28C++0x3 line.long 0x0 "MDF_DFLT4CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x30C++0x3 line.long 0x0 "MDF_DFLT5CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x90++0x3 line.long 0x0 "MDF_DFLT0RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x110++0x3 line.long 0x0 "MDF_DFLT1RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x190++0x3 line.long 0x0 "MDF_DFLT2RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x210++0x3 line.long 0x0 "MDF_DFLT3RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x290++0x3 line.long 0x0 "MDF_DFLT4RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x310++0x3 line.long 0x0 "MDF_DFLT5RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x94++0x3 line.long 0x0 "MDF_DFLT0INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x114++0x3 line.long 0x0 "MDF_DFLT1INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x194++0x3 line.long 0x0 "MDF_DFLT2INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x214++0x3 line.long 0x0 "MDF_DFLT3INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x294++0x3 line.long 0x0 "MDF_DFLT4INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x314++0x3 line.long 0x0 "MDF_DFLT5INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x98++0x3 line.long 0x0 "MDF_OLD0CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x118++0x3 line.long 0x0 "MDF_OLD1CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x198++0x3 line.long 0x0 "MDF_OLD2CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x218++0x3 line.long 0x0 "MDF_OLD3CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x298++0x3 line.long 0x0 "MDF_OLD4CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x318++0x3 line.long 0x0 "MDF_OLD5CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x9C++0x3 line.long 0x0 "MDF_OLD0THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x11C++0x3 line.long 0x0 "MDF_OLD1THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x19C++0x3 line.long 0x0 "MDF_OLD2THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x21C++0x3 line.long 0x0 "MDF_OLD3THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x29C++0x3 line.long 0x0 "MDF_OLD4THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x31C++0x3 line.long 0x0 "MDF_OLD5THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0xA0++0x3 line.long 0x0 "MDF_OLD0THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x120++0x3 line.long 0x0 "MDF_OLD1THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x1A0++0x3 line.long 0x0 "MDF_OLD2THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x220++0x3 line.long 0x0 "MDF_OLD3THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x2A0++0x3 line.long 0x0 "MDF_OLD4THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x320++0x3 line.long 0x0 "MDF_OLD5THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0xA4++0x3 line.long 0x0 "MDF_DLY0CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x124++0x3 line.long 0x0 "MDF_DLY1CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x1A4++0x3 line.long 0x0 "MDF_DLY2CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x224++0x3 line.long 0x0 "MDF_DLY3CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x2A4++0x3 line.long 0x0 "MDF_DLY4CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x324++0x3 line.long 0x0 "MDF_DLY5CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0xA8++0x3 line.long 0x0 "MDF_SCD0CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x128++0x3 line.long 0x0 "MDF_SCD1CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x1A8++0x3 line.long 0x0 "MDF_SCD2CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x228++0x3 line.long 0x0 "MDF_SCD3CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x2A8++0x3 line.long 0x0 "MDF_SCD4CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x328++0x3 line.long 0x0 "MDF_SCD5CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0xAC++0x7 line.long 0x0 "MDF_DFLT0IER,This register is used for allowing or not the events to generate an interrupt." bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x4 "MDF_DFLT0ISR,MDF DFLT0 interrupt status register 0" bitfld.long 0x4 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x4 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x4 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x4 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x4 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x4 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing this bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x4 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing this bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x4 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x4 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x4 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on writing 0 has no effect. - 1: Reading 1 means that a new data is available on writing 1.." "0: Reading 0 means that no data is available on,1: Reading 1 means that a new data is available on" newline bitfld.long 0x4 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x4 0. "FTHF,FTHF" "0,1" group.long 0x12C++0x3 line.long 0x0 "MDF_DFLT1IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x1AC++0x3 line.long 0x0 "MDF_DFLT2IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x22C++0x3 line.long 0x0 "MDF_DFLT3IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x2AC++0x3 line.long 0x0 "MDF_DFLT4IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x32C++0x3 line.long 0x0 "MDF_DFLT5IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x130++0x3 line.long 0x0 "MDF_DFLT1ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0x1B0++0x3 line.long 0x0 "MDF_DFLT2ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0x230++0x3 line.long 0x0 "MDF_DFLT3ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0x2B0++0x3 line.long 0x0 "MDF_DFLT4ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0x330++0x3 line.long 0x0 "MDF_DFLT5ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0xB4++0x3 line.long 0x0 "MDF_OEC0CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x134++0x3 line.long 0x0 "MDF_OEC1CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x1B4++0x3 line.long 0x0 "MDF_OEC2CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x234++0x3 line.long 0x0 "MDF_OEC3CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x2B4++0x3 line.long 0x0 "MDF_OEC4CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x334++0x3 line.long 0x0 "MDF_OEC5CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." rgroup.long 0xEC++0x3 line.long 0x0 "MDF_SNPS0DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x16C++0x3 line.long 0x0 "MDF_SNPS1DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x1EC++0x3 line.long 0x0 "MDF_SNPS2DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x26C++0x3 line.long 0x0 "MDF_SNPS3DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x2EC++0x3 line.long 0x0 "MDF_SNPS4DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x36C++0x3 line.long 0x0 "MDF_SNPS5DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0xF0++0x3 line.long 0x0 "MDF_DFLT0DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x170++0x3 line.long 0x0 "MDF_DFLT1DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x1F0++0x3 line.long 0x0 "MDF_DFLT2DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x270++0x3 line.long 0x0 "MDF_DFLT3DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x2F0++0x3 line.long 0x0 "MDF_DFLT4DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x370++0x3 line.long 0x0 "MDF_DFLT5DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." tree.end tree "SEC_MDF1" base ad:0x50025000 group.long 0x0++0x7 line.long 0x0 "GCR,MDF global control register" hexmask.long.byte 0x0 4.--7. 1. "ILVNB,ILVNB" bitfld.long 0x0 0. "TRGO,TRGO" "0,1" line.long 0x4 "CKGCR,MDF clock generator control register" bitfld.long 0x4 31. "CKGACTIVE,CKGACTIVE" "0,1" hexmask.long.byte 0x4 24.--30. 1. "PROCDIV,PROCDIV" newline hexmask.long.byte 0x4 16.--19. 1. "CCKDIV,CCKDIV" hexmask.long.byte 0x4 12.--15. 1. "TRGSRC,TRGSRC" newline bitfld.long 0x4 8. "TRGSENS,TRGSENS" "0,1" bitfld.long 0x4 6. "CCK1DIR,CCK1DIR" "0,1" newline bitfld.long 0x4 5. "CCK0DIR,CCK0DIR" "0,1" bitfld.long 0x4 4. "CKGMOD,CKGMOD" "0,1" newline bitfld.long 0x4 2. "CCK1EN,CCK1EN" "0,1" bitfld.long 0x4 1. "CCK0EN,CCK0EN" "0,1" newline bitfld.long 0x4 0. "CKGDEN,CKGDEN" "0,1" group.long 0x80++0x3 line.long 0x0 "MDF_SITF0CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated.." "0: The serial interface is not active,1: The serial interface is active" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x100++0x3 line.long 0x0 "MDF_SITF1CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag" "0,1" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x180++0x3 line.long 0x0 "MDF_SITF2CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag" "0,1" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x200++0x3 line.long 0x0 "MDF_SITF3CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated.." "0: The serial interface is not active,1: The serial interface is active" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x280++0x3 line.long 0x0 "MDF_SITF4CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated.." "0: The serial interface is not active,1: The serial interface is active" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x300++0x3 line.long 0x0 "MDF_SITF5CR,This register is used to control the serial interfaces (SITFx)." rbitfld.long 0x0 31. "SITFACTIVE,Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated.." "0: The serial interface is not active,1: The serial interface is active" hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In.." newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0 falling edge = logic 1.." "0: LF_MASTER,1: Normal SPI mode,?,?" bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx not allowed in.." "0: Serial clock source is MDF_CCK0,1: Serial clock source is MDF_CCK1 1x: Serial clock..,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled" "0: Serial interface disabled,1: Serial interface enabled" group.long 0x84++0x3 line.long 0x0 "MDF_BSMX0CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x104++0x3 line.long 0x0 "MDF_BSMX1CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x184++0x3 line.long 0x0 "MDF_BSMX2CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x204++0x3 line.long 0x0 "MDF_BSMX3CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x284++0x3 line.long 0x0 "MDF_BSMX4CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x304++0x3 line.long 0x0 "MDF_BSMX5CR,This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD." rbitfld.long 0x0 31. "BSMXACTIVE,BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag.." "0: The BSMX is not active,1: The BSMX is active" hexmask.long.byte 0x0 0.--4. 1. "BSSEL,Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an.." group.long 0x88++0x3 line.long 0x0 "MDF_DFLT0CR,This register is used to control the digital filter x." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software." "0,1" newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x108++0x3 line.long 0x0 "MDF_DFLT1CR,This register is used to control the digital filter x." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x188++0x3 line.long 0x0 "MDF_DFLT2CR,This register is used to control the digital filter 2." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x208++0x3 line.long 0x0 "MDF_DFLT3CR,This register is used to control the digital filter 3." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x288++0x3 line.long 0x0 "MDF_DFLT4CR,This register is used to control the digital filter 4." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x308++0x3 line.long 0x0 "MDF_DFLT5CR,This register is used to control the digital filter x." rbitfld.long 0x0 31. "DFLTACTIVE,Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active and can be re-enabled again (via DFLTEN bit) if needed -.." "0: The digital filter is not active,1: The digital filter is active" rbitfld.long 0x0 30. "DFLTRUN,Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running and ready to accept a new trigger event - 1: The digital filter is running" "0: The digital filter is not running,1: The digital filter is running" newline hexmask.long.byte 0x0 20.--27. 1. "NBDIS,Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... -.." bitfld.long 0x0 16. "SNPSFMT,Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register leaving a data resolution of 23 bits. - 1:.." "0: The integrator counter,1: The integrator counter" newline hexmask.long.byte 0x0 12.--15. 1. "TRGSRC,Digital filter Trigger signal selection Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0].." bitfld.long 0x0 8. "TRGSENS,Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the.." "0: A rising edge event triggers the acquisition,1: A falling edge even triggers the acquisition.." newline bitfld.long 0x0 4.--6. "ACQMOD,Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous continuous acquisition mode - 001: Asynchronous single-shot acquisition mode - 010: Synchronous continuous.." "0: Asynchronous,1: Asynchronous,?,?,?,?,?,?" bitfld.long 0x0 2. "FTH,RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for.." "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x0 1. "DMAEN,DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The.." "0: The DMA interface for the corresponding digital..,1: The DMA interface for the corresponding digital.." bitfld.long 0x0 0. "DFLTEN,Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the.." "0: The acquisition is stopped immediately,1: The acquisition is immediately started if ACQMOD.." group.long 0x8C++0x3 line.long 0x0 "MDF_DFLT0CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x10C++0x3 line.long 0x0 "MDF_DFLT1CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x18C++0x3 line.long 0x0 "MDF_DFLT2CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x20C++0x3 line.long 0x0 "MDF_DFLT3CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x28C++0x3 line.long 0x0 "MDF_DFLT4CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x30C++0x3 line.long 0x0 "MDF_DFLT5CICR,This register is used to control the main CIC filter." hexmask.long.byte 0x0 20.--25. 1. "SCALE,Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new.." hexmask.long.word 0x0 8.--16. 1. "MCICD,CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0:.." newline bitfld.long 0x0 4.--6. "CICMOD,Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary.." "0: The CIC is split into 2 filters,1: The CIC is split into 2 filters,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "DATSRC,Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected please.." "?,?,?,?" group.long 0x90++0x3 line.long 0x0 "MDF_DFLT0RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x110++0x3 line.long 0x0 "MDF_DFLT1RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x190++0x3 line.long 0x0 "MDF_DFLT2RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x210++0x3 line.long 0x0 "MDF_DFLT3RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x290++0x3 line.long 0x0 "MDF_DFLT4RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x310++0x3 line.long 0x0 "MDF_DFLT5RSFR,This register is used to control the reshape and HPF filters." bitfld.long 0x0 8.--9. "HPFC,High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off.." "0: Cut-off frequency = 0,1: Cut-off frequency = 0,?,?" bitfld.long 0x0 7. "HPFBYP,High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected please refer.." "0: The high pass filter is not bypassed,1: The high pass filter is bypassed This field can.." newline bitfld.long 0x0 4. "RSFLTD,Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected please.." "0: Decimation ratio is 4,1: Decimation ratio is 1 This field can be.." bitfld.long 0x0 0. "RSFLTBYP,Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be.." "0: The reshape filter is not bypassed,1: The reshape filter is bypassed This field can be.." group.long 0x94++0x3 line.long 0x0 "MDF_DFLT0INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x114++0x3 line.long 0x0 "MDF_DFLT1INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x194++0x3 line.long 0x0 "MDF_DFLT2INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x214++0x3 line.long 0x0 "MDF_DFLT3INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x294++0x3 line.long 0x0 "MDF_DFLT4INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x314++0x3 line.long 0x0 "MDF_DFLT5INTR,This register is used to the integrator (INT) settings." hexmask.long.byte 0x0 4.--10. 1. "INTVAL,Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1 meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3.." bitfld.long 0x0 0.--1. "INTDIV,Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The.." "0: The integrator data outputs are divided by 128,1: The integrator data outputs are divided by 32,?,?" group.long 0x98++0x3 line.long 0x0 "MDF_OLD0CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x118++0x3 line.long 0x0 "MDF_OLD1CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x198++0x3 line.long 0x0 "MDF_OLD2CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x218++0x3 line.long 0x0 "MDF_OLD3CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x298++0x3 line.long 0x0 "MDF_OLD4CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x318++0x3 line.long 0x0 "MDF_OLD5CR,This register is used to configure the Out-of Limit Detector function." rbitfld.long 0x0 31. "OLDACTIVE,OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the.." "0: The OLD is not active,1: The OLD is active" hexmask.long.byte 0x0 17.--21. 1. "ACICD,OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio.." newline bitfld.long 0x0 12.--13. "ACICN,OLD CIC order selection Set and cleared by software. This field allows the application to select the type and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1.." "0: FastSinc filter type,1: Sinc1 filter type,?,?" hexmask.long.byte 0x0 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be.." newline bitfld.long 0x0 1. "THINB,Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This.." "0: The OLD generates an event if the signal is..,1: The OLD generates an event if the signal is.." bitfld.long 0x0 0. "OLDEN,Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled including the ACIC filter working in continuous mode." "0: The OLD is disabled,1: The OLD is enabled" group.long 0x9C++0x3 line.long 0x0 "MDF_OLD0THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x11C++0x3 line.long 0x0 "MDF_OLD1THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x19C++0x3 line.long 0x0 "MDF_OLD2THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x21C++0x3 line.long 0x0 "MDF_OLD3THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x29C++0x3 line.long 0x0 "MDF_OLD4THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x31C++0x3 line.long 0x0 "MDF_OLD5THLR,This register is used for the adjustment of the Out-off Limit low threshold." hexmask.long 0x0 0.--25. 1. "OLDTHL,OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0xA0++0x3 line.long 0x0 "MDF_OLD0THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x120++0x3 line.long 0x0 "MDF_OLD1THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x1A0++0x3 line.long 0x0 "MDF_OLD2THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x220++0x3 line.long 0x0 "MDF_OLD3THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x2A0++0x3 line.long 0x0 "MDF_OLD4THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0x320++0x3 line.long 0x0 "MDF_OLD5THHR,This register is used for the adjustment of the Out-off Limit high threshold." hexmask.long 0x0 0.--25. 1. "OLDTHH,OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected please refer to Section 1.4.15: Register.." group.long 0xA4++0x3 line.long 0x0 "MDF_DLY0CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x124++0x3 line.long 0x0 "MDF_DLY1CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x1A4++0x3 line.long 0x0 "MDF_DLY2CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x224++0x3 line.long 0x0 "MDF_DLY3CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x2A4++0x3 line.long 0x0 "MDF_DLY4CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0x324++0x3 line.long 0x0 "MDF_DLY5CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SKPBF,Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid.." "0: Reading 0 means that the MDF is ready to accept..,1: Reading 1 means that last valid SKPDLY[6:0] is.." hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field if SKPBF = 0 and the corresponding bit DFLTEN = 1 . If SKPBF = 1.." group.long 0xA8++0x3 line.long 0x0 "MDF_SCD0CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x128++0x3 line.long 0x0 "MDF_SCD1CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x1A8++0x3 line.long 0x0 "MDF_SCD2CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x228++0x3 line.long 0x0 "MDF_SCD3CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x2A8++0x3 line.long 0x0 "MDF_SCD4CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0x328++0x3 line.long 0x0 "MDF_SCD5CR,This register is used for the adjustment stream delays." rbitfld.long 0x0 31. "SCDACTIVE,SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to.." "0: The SCD is not active,1: The SCD is active" hexmask.long.byte 0x0 12.--19. 1. "SCDT,Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached then a short-circuit detector event occurs on a given input.." newline hexmask.long.byte 0x0 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be.." bitfld.long 0x0 0. "SCDEN,Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled - 1: The short circuit detector is enabled " "0: The short circuit detector is disabled,1: The short circuit detector is enabled" group.long 0xAC++0x7 line.long 0x0 "MDF_DFLT0IER,This register is used for allowing or not the events to generate an interrupt." bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x4 "MDF_DFLT0ISR,MDF DFLT0 interrupt status register 0" bitfld.long 0x4 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x4 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x4 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x4 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x4 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x4 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing this bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x4 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing this bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x4 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x4 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x4 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on writing 0 has no effect. - 1: Reading 1 means that a new data is available on writing 1.." "0: Reading 0 means that no data is available on,1: Reading 1 means that a new data is available on" newline bitfld.long 0x4 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x4 0. "FTHF,FTHF" "0,1" group.long 0x12C++0x3 line.long 0x0 "MDF_DFLT1IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x1AC++0x3 line.long 0x0 "MDF_DFLT2IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x22C++0x3 line.long 0x0 "MDF_DFLT3IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x2AC++0x3 line.long 0x0 "MDF_DFLT4IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x32C++0x3 line.long 0x0 "MDF_DFLT5IER,MDF DFLTx interrupt enable register x" bitfld.long 0x0 11. "RFOVRIE,Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 8. "SCDIE,Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled" "0: SCD interrupt disabled,1: SCD interrupt enabled" newline bitfld.long 0x0 7. "SSOVRIE,Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x0 4. "OLDIE,Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled" "0: OLD event interrupt disabled,1: OLD event interrupt enabled" newline bitfld.long 0x0 2. "SSDRIE,Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" group.long 0x130++0x3 line.long 0x0 "MDF_DFLT1ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0x1B0++0x3 line.long 0x0 "MDF_DFLT2ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0x230++0x3 line.long 0x0 "MDF_DFLT3ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0x2B0++0x3 line.long 0x0 "MDF_DFLT4ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0x330++0x3 line.long 0x0 "MDF_DFLT5ISR,This register contains the status flags for each digital filter path." bitfld.long 0x0 11. "RFOVRF,Reshape Filter Overrun detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected writing 0 has no effect. - 1: Reading 1 means that reshape filter.." "0: Reading 0 means that no reshape filter overrun..,1: Reading 1 means that reshape filter overrun is.." bitfld.long 0x0 10. "CKABF,Clock absence detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected writing.." "0: Reading 0 means that no clock absence is detected,1: Reading 1 means that a clock absence is detected" newline bitfld.long 0x0 9. "SATF,Saturation detection flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected writing 0 has no effect. - 1: Reading 1 means that a saturation is detected writing 1 clears.." "0: Reading 0 means that no saturation is detected,1: Reading 1 means that a saturation is detected" bitfld.long 0x0 8. "SCDF,Short-Circuit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected writing 1 clears.." "0: Reading 0 means that no SCD event is detected,1: Reading 1 means that a SCD event is detected" newline bitfld.long 0x0 7. "SSOVRF,Snapshot overrun flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is.." "0: Reading 0 means that no snapshot overrun event..,1: Reading 1 means that a snapshot overrun event is.." rbitfld.long 0x0 6. "THHF,High threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHH,1: The signal was higher than OLDTHH" newline rbitfld.long 0x0 5. "THLF,Low threshold status flag Set by hardware and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions.." "0: The signal was lower than OLDTHL,1: The signal was higher than OLDTHL" bitfld.long 0x0 4. "OLDF,Out-of Limit Detector flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected writing 1 clears.." "0: Reading 0 means that no OLD event is detected,1: Reading 1 means that an OLD event is detected" newline rbitfld.long 0x0 3. "RXNEF,RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty." "0: Reading 0 means that the RXFIFO is empty,1: Reading 1 means that the RXFIFO is not empty" bitfld.long 0x0 2. "SSDRF,Snapshot data ready flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR writing 0 has no effect. - 1: Reading 1 means that a new data is available on.." "0: Reading 0 means that no data is available on..,1: Reading 1 means that a new data is available on.." newline bitfld.long 0x0 1. "DOVRF,Data overflow flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected writing 0 has no effect. - 1: Reading 1 means that an overflow is detected writing 1 clears this flag." "0: Reading 0 means that no overflow is detected,1: Reading 1 means that an overflow is detected" rbitfld.long 0x0 0. "FTHF,RXFIFO threshold flag Set by hardware and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold .." "0: Reading 0 means that the RXFIFO threshold is not..,1: Reading 1 means that the RXFIFO reached the.." group.long 0xB4++0x3 line.long 0x0 "MDF_OEC0CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x134++0x3 line.long 0x0 "MDF_OEC1CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x1B4++0x3 line.long 0x0 "MDF_OEC2CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x234++0x3 line.long 0x0 "MDF_OEC3CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x2B4++0x3 line.long 0x0 "MDF_OEC4CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." group.long 0x334++0x3 line.long 0x0 "MDF_OEC5CR,This register contains the offset compensation value." hexmask.long 0x0 0.--25. 1. "OFFSET,Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the.." rgroup.long 0xEC++0x3 line.long 0x0 "MDF_SNPS0DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x16C++0x3 line.long 0x0 "MDF_SNPS1DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x1EC++0x3 line.long 0x0 "MDF_SNPS2DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x26C++0x3 line.long 0x0 "MDF_SNPS3DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x2EC++0x3 line.long 0x0 "MDF_SNPS4DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0x36C++0x3 line.long 0x0 "MDF_SNPS5DR,This register is used to read the data processed by each digital filter in snapshot mode." hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size If SNPSFMT = 0 EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter If SNPSFMT = 1 this field contains the INT accumulator counter value at the moment of the last trigger event occurs.." newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)" rgroup.long 0xF0++0x3 line.long 0x0 "MDF_DFLT0DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x170++0x3 line.long 0x0 "MDF_DFLT1DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x1F0++0x3 line.long 0x0 "MDF_DFLT2DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x270++0x3 line.long 0x0 "MDF_DFLT3DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x2F0++0x3 line.long 0x0 "MDF_DFLT4DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." rgroup.long 0x370++0x3 line.long 0x0 "MDF_DFLT5DR,This register is used to read the data processed by each digital filter." hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by digital filter." tree.end tree.end tree "OCTOSPI (Octo-SPI Interface)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "OCTOSPI1" base ad:0x420D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" sif (cpuis("STM32U575*")) bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline endif bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" sif (cpuis("STM32U575*")) bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" endif bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" sif (cpuis("STM32U575*")) bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" endif bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_OCTOSPI1" base ad:0x520D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" sif (cpuis("STM32U575*")) bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline endif bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" sif (cpuis("STM32U575*")) bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" endif bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" sif (cpuis("STM32U575*")) bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" endif bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U575*")) tree "OCTOSPI2" base ad:0x420D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI2" base ad:0x520D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U575*")) tree "OCTOSPIM" base ad:0x420C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end tree "SEC_OCTOSPIM" base ad:0x520C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "OCTOSPI1" base ad:0x420D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI1" base ad:0x520D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "OCTOSPI2" base ad:0x420D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI2" base ad:0x520D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "OCTOSPIM" base ad:0x420C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end tree "SEC_OCTOSPIM" base ad:0x520C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "OCTOSPI1" base ad:0x420D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI1" base ad:0x520D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "OCTOSPI2" base ad:0x420D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI2" base ad:0x520D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "OCTOSPIM" base ad:0x420C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end tree "SEC_OCTOSPIM" base ad:0x520C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "OCTOSPI1" base ad:0x420D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI1" base ad:0x520D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "OCTOSPI2" base ad:0x420D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI2" base ad:0x520D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "OCTOSPIM" base ad:0x420C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end tree "SEC_OCTOSPIM" base ad:0x520C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "OCTOSPI1" base ad:0x420D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI1" base ad:0x520D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "OCTOSPI2" base ad:0x420D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI2" base ad:0x520D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "OCTOSPIM" base ad:0x420C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end tree "SEC_OCTOSPIM" base ad:0x520C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "OCTOSPI1" base ad:0x420D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI1" base ad:0x520D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "OCTOSPI2" base ad:0x420D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI2" base ad:0x520D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "OCTOSPIM" base ad:0x420C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end tree "SEC_OCTOSPIM" base ad:0x520C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "OCTOSPI1" base ad:0x420D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI1" base ad:0x520D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "OCTOSPI2" base ad:0x420D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI2" base ad:0x520D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "OCTOSPIM" base ad:0x420C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end tree "SEC_OCTOSPIM" base ad:0x520C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "OCTOSPI1" base ad:0x420D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI1" base ad:0x520D1400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "OCTOSPI2" base ad:0x420D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end tree "SEC_OCTOSPI2" base ad:0x520D2400 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,timeout flag" "0,1" bitfld.long 0x0 3. "SMF,status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear Transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status MASK" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Status match" group.long 0x90++0x3 line.long 0x0 "PIR,polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,communication configuration" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,wrap communication configuration" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "WIR,write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,ALTERNATE" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBus latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "OCTOSPIM" base ad:0x420C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end tree "SEC_OCTOSPIM" base ad:0x520C4000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1" line.long 0x4 "P1CR,OCTOSPI I/O manager Port 1 configuration register" bitfld.long 0x4 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x4 0. "CLKEN,CLKEN" "0,1" line.long 0x8 "P2CR,OCTOSPI I/O manager Port 2 configuration register" bitfld.long 0x8 25.--26. "IOHSRC,IOHSR" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end endif tree.end tree "OPAMP (Operational Amplifiers)" base ad:0x0 tree "OPAMP" base ad:0x46005000 group.long 0x0++0xB line.long 0x0 "OPAMP1_CSR,OPAMP1 control/status register" bitfld.long 0x0 31. "OPA_RANGE,OPAMP range setting" "0: reserved,1: OPAMP range set" bitfld.long 0x0 30. "OPAHSM,OPAMP high-speed mode" "0: normal mode (standard slew rate),1: increased consumption to improve the slew rate" newline rbitfld.long 0x0 15. "CALOUT,OPAMP calibration output" "0,1" bitfld.long 0x0 14. "USERTRIM,'factory' or 'user' offset trimmed values selection" "0: 'factory' trim code used,1: 'user' trim code used" newline bitfld.long 0x0 13. "CALSEL,Calibration selection" "0: NMOS calibration (200mV applied on OPAMP..,1: PMOS calibration (VDDA -200 mV.." bitfld.long 0x0 12. "CALON,Calibration mode enable" "0: normal mode,1: calibration mode (all switches opened by hardware)" newline bitfld.long 0x0 10. "VP_SEL,Non-inverted input selection" "0: GPIO connected to VINP,1: DAC connected to VINP" bitfld.long 0x0 8.--9. "VM_SEL,Inverting input selection" "0: GPIO connected to VINM (valid also in PGA mode..,1: dedicated low-leakage input connected to VINM..,?,?" newline bitfld.long 0x0 4.--5. "PGA_GAIN,OPAMP programmable amplifier gain value" "0: internal PGA gain 2,1: internal PGA gain 4,2: internal PGA gain 8,3: internal PGA gain 16" bitfld.long 0x0 2.--3. "OPAMODE,OPAMP PGA mode" "?,1: internal PGA disabled,2: internal PGA enabled gain programmed in PGA_GAIN,3: internal follower" newline bitfld.long 0x0 1. "OPALPM,OPAMP low-power mode" "0: normal mode,1: low-power mode" bitfld.long 0x0 0. "OPAEN,OPAMP enable" "0: OPAMP disabled,1: OPAMP enabled" line.long 0x4 "OPAMP1_OTR,OPAMP1 offset trimming register in normal mode" hexmask.long.byte 0x4 8.--12. 1. "TRIMOFFSETP,Trim for PMOS differential pairs" hexmask.long.byte 0x4 0.--4. 1. "TRIMOFFSETN,Trim for NMOS differential pairs" line.long 0x8 "OPAMP1_LPOTR,OPAMP1 offset trimming register in low-power mode" hexmask.long.byte 0x8 8.--12. 1. "TRIMLPOFFSETP,Low-power mode trim for PMOS differential pairs" hexmask.long.byte 0x8 0.--4. 1. "TRIMLPOFFSETN,Low-power mode trim for NMOS differential pairs" group.long 0x10++0xB line.long 0x0 "OPAMP2_CRS,OPAMP2 control/status register" bitfld.long 0x0 30. "OPAHSM,OPAMP high-speed mode" "0: normal mode (standard slew rate),1: increased consumption to improve the slew rate" rbitfld.long 0x0 15. "CALOUT,OPAMP calibration output" "0,1" newline bitfld.long 0x0 14. "USERTRIM,'factory' or 'user' offset trimmed values selection" "0: 'factory' trim code used,1: 'user' trim code used" bitfld.long 0x0 13. "CALSEL,Calibration selection" "0: NMOS calibration (200 mV applied on OPAMP inputs),1: PMOS calibration (VDDA - 200 mV.." newline bitfld.long 0x0 12. "CALON,Calibration mode enable" "0: normal mode,1: calibration mode (all switches opened by hardware)" bitfld.long 0x0 10. "VP_SEL,Non inverted input selection" "0: GPIO connected to VINP,1: DAC connected to VINP" newline bitfld.long 0x0 8.--9. "VM_SEL,Inverting input selection" "0: GPIO connected to VINM (valid also in PGA mode..,1: dedicated low-leakage input connected to VINM..,?,?" bitfld.long 0x0 4.--5. "PGA_GAIN,OPAMP programmable amplifier gain value" "0: internal PGA gain 2,1: internal PGA gain 4,2: internal PGA gain 8,3: internal PGA gain 16" newline bitfld.long 0x0 2.--3. "OPAMODE,OPAMP PGA mode" "?,1: internal PGA disabled,2: internal PGA enabled gain programmed in PGA_GAIN,3: internal follower" bitfld.long 0x0 1. "OPALPM,OPAMP low-power mode" "0: normal mode,1: low-power mode" newline bitfld.long 0x0 0. "OPAEN,OPAMP enable" "0: OPAMP disabled,1: OPAMP enabled" line.long 0x4 "OPAMP2_OTR,OPAMP2 offset trimming register in normal mode" hexmask.long.byte 0x4 8.--12. 1. "TRIMOFFSETP,Trim for PMOS differential pairs" hexmask.long.byte 0x4 0.--4. 1. "TRIMOFFSETN,Trim for NMOS differential pairs" line.long 0x8 "OPAMP2_LPOTR,OPAMP2 offset trimming register in low-power mode" hexmask.long.byte 0x8 8.--12. 1. "TRIMLPOFFSETP,Low-power mode trim for PMOS differential pairs" hexmask.long.byte 0x8 0.--4. 1. "TRIMLPOFFSETN,Low-power mode trim for NMOS differential pairs" tree.end tree "SEC_OPAMP" base ad:0x56005000 group.long 0x0++0xB line.long 0x0 "OPAMP1_CSR,OPAMP1 control/status register" bitfld.long 0x0 31. "OPA_RANGE,OPAMP range setting" "0: reserved,1: OPAMP range set" bitfld.long 0x0 30. "OPAHSM,OPAMP high-speed mode" "0: normal mode (standard slew rate),1: increased consumption to improve the slew rate" newline rbitfld.long 0x0 15. "CALOUT,OPAMP calibration output" "0,1" bitfld.long 0x0 14. "USERTRIM,'factory' or 'user' offset trimmed values selection" "0: 'factory' trim code used,1: 'user' trim code used" newline bitfld.long 0x0 13. "CALSEL,Calibration selection" "0: NMOS calibration (200mV applied on OPAMP..,1: PMOS calibration (VDDA -200 mV.." bitfld.long 0x0 12. "CALON,Calibration mode enable" "0: normal mode,1: calibration mode (all switches opened by hardware)" newline bitfld.long 0x0 10. "VP_SEL,Non-inverted input selection" "0: GPIO connected to VINP,1: DAC connected to VINP" bitfld.long 0x0 8.--9. "VM_SEL,Inverting input selection" "0: GPIO connected to VINM (valid also in PGA mode..,1: dedicated low-leakage input connected to VINM..,?,?" newline bitfld.long 0x0 4.--5. "PGA_GAIN,OPAMP programmable amplifier gain value" "0: internal PGA gain 2,1: internal PGA gain 4,2: internal PGA gain 8,3: internal PGA gain 16" bitfld.long 0x0 2.--3. "OPAMODE,OPAMP PGA mode" "?,1: internal PGA disabled,2: internal PGA enabled gain programmed in PGA_GAIN,3: internal follower" newline bitfld.long 0x0 1. "OPALPM,OPAMP low-power mode" "0: normal mode,1: low-power mode" bitfld.long 0x0 0. "OPAEN,OPAMP enable" "0: OPAMP disabled,1: OPAMP enabled" line.long 0x4 "OPAMP1_OTR,OPAMP1 offset trimming register in normal mode" hexmask.long.byte 0x4 8.--12. 1. "TRIMOFFSETP,Trim for PMOS differential pairs" hexmask.long.byte 0x4 0.--4. 1. "TRIMOFFSETN,Trim for NMOS differential pairs" line.long 0x8 "OPAMP1_LPOTR,OPAMP1 offset trimming register in low-power mode" hexmask.long.byte 0x8 8.--12. 1. "TRIMLPOFFSETP,Low-power mode trim for PMOS differential pairs" hexmask.long.byte 0x8 0.--4. 1. "TRIMLPOFFSETN,Low-power mode trim for NMOS differential pairs" group.long 0x10++0xB line.long 0x0 "OPAMP2_CRS,OPAMP2 control/status register" bitfld.long 0x0 30. "OPAHSM,OPAMP high-speed mode" "0: normal mode (standard slew rate),1: increased consumption to improve the slew rate" rbitfld.long 0x0 15. "CALOUT,OPAMP calibration output" "0,1" newline bitfld.long 0x0 14. "USERTRIM,'factory' or 'user' offset trimmed values selection" "0: 'factory' trim code used,1: 'user' trim code used" bitfld.long 0x0 13. "CALSEL,Calibration selection" "0: NMOS calibration (200 mV applied on OPAMP inputs),1: PMOS calibration (VDDA - 200 mV.." newline bitfld.long 0x0 12. "CALON,Calibration mode enable" "0: normal mode,1: calibration mode (all switches opened by hardware)" bitfld.long 0x0 10. "VP_SEL,Non inverted input selection" "0: GPIO connected to VINP,1: DAC connected to VINP" newline bitfld.long 0x0 8.--9. "VM_SEL,Inverting input selection" "0: GPIO connected to VINM (valid also in PGA mode..,1: dedicated low-leakage input connected to VINM..,?,?" bitfld.long 0x0 4.--5. "PGA_GAIN,OPAMP programmable amplifier gain value" "0: internal PGA gain 2,1: internal PGA gain 4,2: internal PGA gain 8,3: internal PGA gain 16" newline bitfld.long 0x0 2.--3. "OPAMODE,OPAMP PGA mode" "?,1: internal PGA disabled,2: internal PGA enabled gain programmed in PGA_GAIN,3: internal follower" bitfld.long 0x0 1. "OPALPM,OPAMP low-power mode" "0: normal mode,1: low-power mode" newline bitfld.long 0x0 0. "OPAEN,OPAMP enable" "0: OPAMP disabled,1: OPAMP enabled" line.long 0x4 "OPAMP2_OTR,OPAMP2 offset trimming register in normal mode" hexmask.long.byte 0x4 8.--12. 1. "TRIMOFFSETP,Trim for PMOS differential pairs" hexmask.long.byte 0x4 0.--4. 1. "TRIMOFFSETN,Trim for NMOS differential pairs" line.long 0x8 "OPAMP2_LPOTR,OPAMP2 offset trimming register in low-power mode" hexmask.long.byte 0x8 8.--12. 1. "TRIMLPOFFSETP,Low-power mode trim for PMOS differential pairs" hexmask.long.byte 0x8 0.--4. 1. "TRIMLPOFFSETN,Low-power mode trim for NMOS differential pairs" tree.end tree.end sif (cpuis("STM32U545*")||cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U5A5*")||cpuis("STM32U5A9*")||cpuis("STM32U5G*")) tree "OTFDEC (On-the-fly Decryption Engine)" base ad:0x0 sif (cpuis("STM32U545*")||cpuis("STM32U575*")) tree "OTFDEC1" base ad:0x420C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" sif (cpuis("STM32U545*")) hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" endif hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" sif (cpuis("STM32U545*")) hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" endif hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" sif (cpuis("STM32U545*")) hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" endif hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" sif (cpuis("STM32U575*")) group.long 0x8C++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" sif (cpuis("STM32U545*")) hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" endif hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif sif (cpuis("STM32U545*")) group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" endif group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" endif group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" endif group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" endif wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_OTFDEC1" base ad:0x520C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" sif (cpuis("STM32U545*")) hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" endif hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" sif (cpuis("STM32U545*")) hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" endif hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" sif (cpuis("STM32U545*")) hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" endif hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" sif (cpuis("STM32U575*")) group.long 0x8C++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" sif (cpuis("STM32U545*")) hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" endif sif (cpuis("STM32U575*")) hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" endif hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif sif (cpuis("STM32U545*")) group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" endif group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" endif group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" endif group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" endif wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" sif (cpuis("STM32U545*")) hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" endif sif (cpuis("STM32U575*")) hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U575*")) tree "OTFDEC2" base ad:0x420C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "SEC_OTFDEC2" base ad:0x520C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "OTFDEC1" base ad:0x420C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "SEC_OTFDEC1" base ad:0x520C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "OTFDEC2" base ad:0x420C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "SEC_OTFDEC2" base ad:0x520C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "OTFDEC1" base ad:0x420C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "SEC_OTFDEC1" base ad:0x520C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "OTFDEC2" base ad:0x420C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "SEC_OTFDEC2" base ad:0x520C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "OTFDEC1" base ad:0x420C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "SEC_OTFDEC1" base ad:0x520C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "OTFDEC2" base ad:0x420C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "SEC_OTFDEC2" base ad:0x520C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "OTFDEC1" base ad:0x420C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "SEC_OTFDEC1" base ad:0x520C5000 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "OTFDEC2" base ad:0x420C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "SEC_OTFDEC2" base ad:0x520C5400 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x10++0x3 line.long 0x0 "PRIVCFGR,OTFDEC privileged access control configuration register" bitfld.long 0x0 0. "PRIV,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG1_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG2_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG3_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REG4_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG1_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG2_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG3_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REG4_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG1_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG2_END_ADDR,Region AXI end address" group.long 0x88++0x3 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG3_END_ADDR,Region AXI end address" group.long 0xB8++0x3 line.long 0x0 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REG4_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,REG1_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,REG2_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG1_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG2_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG3_NONCE,REG3_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REG4_NONCE,REG4_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG2_KEY_,REG2_KEY_" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG1_KEY,REG1_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG2_KEY,REG2_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG3_KEY,REG3_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REG4_KEY,REG4_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif tree.end endif sif (cpuis("STM32U575*")||cpuis("STM32U585*")) tree "OTG_FS (USB On-the-go Full-Speed)" base ad:0x0 tree "OTG_FS" base ad:0x42040000 group.long 0x0++0x1B line.long 0x0 "GOTGCTL,The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core." rbitfld.long 0x0 21. "CURMOD,CURMOD" "0,1" bitfld.long 0x0 20. "OTGVER,OTGVER" "0,1" rbitfld.long 0x0 19. "BSVLD,BSVLD" "0,1" rbitfld.long 0x0 18. "ASVLD,ASVLD" "0,1" rbitfld.long 0x0 17. "DBCT,DBCT" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,CIDSTS" "0,1" bitfld.long 0x0 12. "EHEN,EHEN" "0,1" bitfld.long 0x0 11. "DHNPEN,DHNPEN" "0,1" bitfld.long 0x0 10. "HSHNPEN,HSHNPEN" "0,1" bitfld.long 0x0 9. "HNPRQ,HNPRQ" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,HNGSCS" "0,1" bitfld.long 0x0 7. "BVALOVAL,BVALOVAL" "0,1" bitfld.long 0x0 6. "BVALOEN,BVALOEN" "0,1" bitfld.long 0x0 5. "AVALOVAL,AVALOVAL" "0,1" bitfld.long 0x0 4. "AVALOEN,AVALOEN" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBVALOVAL" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBVALOEN" "0,1" bitfld.long 0x0 1. "SRQ,SRQ" "0,1" rbitfld.long 0x0 0. "SRQSCS,SRQSCS" "0,1" line.long 0x4 "GOTGINT,The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt." bitfld.long 0x4 19. "DBCDNE,DBCDNE" "0,1" bitfld.long 0x4 18. "ADTOCHG,ADTOCHG" "0,1" bitfld.long 0x4 17. "HNGDET,HNGDET" "0,1" bitfld.long 0x4 9. "HNSSCHG,HNSSCHG" "0,1" bitfld.long 0x4 8. "SRSSCHG,SRSSCHG" "0,1" newline bitfld.long 0x4 2. "SEDET,SEDET" "0,1" line.long 0x8 "GAHBCFG,This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program.." bitfld.long 0x8 8. "PTXFELVL,PTXFELVL" "0,1" bitfld.long 0x8 7. "TXFELVL,TXFELVL" "0,1" bitfld.long 0x8 0. "GINTMSK,GINTMSK" "0,1" line.long 0xC "GUSBCFG,This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on.." bitfld.long 0xC 30. "FDMOD,FDMOD" "0,1" bitfld.long 0xC 29. "FHMOD,FHMOD" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,TRDT" bitfld.long 0xC 9. "HNPCAP,HNPCAP" "0,1" bitfld.long 0xC 8. "SRPCAP,SRPCAP" "0,1" newline rbitfld.long 0xC 6. "PHYSEL,PHYSEL" "0,1" bitfld.long 0xC 0.--2. "TOCAL,TOCAL" "0,1,2,3,4,5,6,7" line.long 0x10 "GRSTCTL,The application uses this register to reset various hardware features inside the core." rbitfld.long 0x10 31. "AHBIDL,AHBIDL" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TXFNUM" bitfld.long 0x10 5. "TXFFLSH,TXFFLSH" "0,1" bitfld.long 0x10 4. "RXFFLSH,RXFFLSH" "0,1" bitfld.long 0x10 2. "FSRST,FSRST" "0,1" newline bitfld.long 0x10 1. "PSRST,PSRST" "0,1" rbitfld.long 0x10 0. "CSRST,CSRST" "0,1" line.long 0x14 "GINTSTS,This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode. while others are valid in device mode only. This register also.." bitfld.long 0x14 31. "WKUPINT,WKUPINT" "0,1" bitfld.long 0x14 30. "SRQINT,SRQINT" "0,1" bitfld.long 0x14 29. "DISCINT,DISCINT" "0,1" bitfld.long 0x14 28. "CIDSCHG,CIDSCHG" "0,1" bitfld.long 0x14 27. "LPMINT,LPMINT" "0,1" newline rbitfld.long 0x14 26. "PTXFE,PTXFE" "0,1" rbitfld.long 0x14 25. "HCINT,HCINT" "0,1" rbitfld.long 0x14 24. "HPRTINT,HPRTINT" "0,1" bitfld.long 0x14 23. "RSTDET,RSTDET" "0,1" bitfld.long 0x14 21. "IPXFR,IPXFR" "0,1" newline bitfld.long 0x14 20. "IISOIXFR,IISOIXFR" "0,1" rbitfld.long 0x14 19. "OEPINT,OEPINT" "0,1" rbitfld.long 0x14 18. "IEPINT,IEPINT" "0,1" bitfld.long 0x14 15. "EOPF,EOPF" "0,1" bitfld.long 0x14 14. "ISOODRP,ISOODRP" "0,1" newline bitfld.long 0x14 13. "ENUMDNE,ENUMDNE" "0,1" bitfld.long 0x14 12. "USBRST,USBRST" "0,1" bitfld.long 0x14 11. "USBSUSP,USBSUSP" "0,1" bitfld.long 0x14 10. "ESUSP,ESUSP" "0,1" rbitfld.long 0x14 7. "GONAKEFF,GONAKEFF" "0,1" newline rbitfld.long 0x14 6. "GINAKEFF,GINAKEFF" "0,1" rbitfld.long 0x14 5. "NPTXFE,NPTXFE" "0,1" rbitfld.long 0x14 4. "RXFLVL,RXFLVL" "0,1" bitfld.long 0x14 3. "SOF,SOF" "0,1" rbitfld.long 0x14 2. "OTGINT,OTGINT" "0,1" newline bitfld.long 0x14 1. "MMIS,MMIS" "0,1" rbitfld.long 0x14 0. "CMOD,CMOD" "0,1" line.long 0x18 "GINTMSK,This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked. the interrupt associated with that bit is not generated. However. the core interrupt (GINTSTS) register bit corresponding to that.." bitfld.long 0x18 31. "WUIM,WUIM" "0,1" bitfld.long 0x18 30. "SRQIM,SRQIM" "0,1" bitfld.long 0x18 29. "DISCINT,DISCINT" "0,1" bitfld.long 0x18 28. "CIDSCHGM,CIDSCHGM" "0,1" bitfld.long 0x18 27. "LPMINTM,LPMINTM" "0,1" newline bitfld.long 0x18 26. "PTXFEM,PTXFEM" "0,1" bitfld.long 0x18 25. "HCIM,HCIM" "0,1" bitfld.long 0x18 24. "PRTIM,PRTIM" "0,1" bitfld.long 0x18 23. "RSTDETM,RSTDETM" "0,1" bitfld.long 0x18 21. "IPXFRM,IPXFRM" "0,1" newline bitfld.long 0x18 20. "IISOIXFRM,IISOIXFRM" "0,1" bitfld.long 0x18 19. "OEPINT,OEPINT" "0,1" bitfld.long 0x18 18. "IEPINT,IEPINT" "0,1" bitfld.long 0x18 15. "EOPFM,EOPFM" "0,1" bitfld.long 0x18 14. "ISOODRPM,ISOODRPM" "0,1" newline bitfld.long 0x18 13. "ENUMDNEM,ENUMDNEM" "0,1" bitfld.long 0x18 12. "USBRST,USBRST" "0,1" bitfld.long 0x18 11. "USBSUSPM,USBSUSPM" "0,1" bitfld.long 0x18 10. "ESUSPM,ESUSPM" "0,1" bitfld.long 0x18 7. "GONAKEFFM,GONAKEFFM" "0,1" newline bitfld.long 0x18 6. "GINAKEFFM,GINAKEFFM" "0,1" bitfld.long 0x18 5. "NPTXFEM,NPTXFEM" "0,1" bitfld.long 0x18 4. "RXFLVLM,RXFLVLM" "0,1" bitfld.long 0x18 3. "SOFM,SOFM" "0,1" bitfld.long 0x18 2. "OTGINT,OTGINT" "0,1" newline bitfld.long 0x18 1. "MMISM,MMISM" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "GRXSTSR_DEVICE,This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and.." bitfld.long 0x0 27. "STSPHST,STSPHST" "0,1" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x0 0.--3. 1. "EPNUM,EPNUM" rgroup.long 0x1C++0x7 line.long 0x0 "GRXSTSR_HOST,This description is for register GRXSTSR in Host mode" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,CHNUM" line.long 0x4 "GRXSTSP_DEVICE,This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO. a read to GRXSTSP (receive status read and pop register).." bitfld.long 0x4 27. "STSPHST,STSPHST" "0,1" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x4 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x4 0.--3. 1. "EPNUM,EPNUM" rgroup.long 0x20++0x3 line.long 0x0 "GRXSTSP_HOST,This description is for register GRXSTSP in HOST mode" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,CHNUM" group.long 0x24++0x7 line.long 0x0 "GRXFSIZ,The application can program the RAM size that must be allocated to the Rx FIFO." hexmask.long.word 0x0 0.--15. 1. "RXFD,RXFD" line.long 0x4 "HNPTXFSIZ,Host mode" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,NPTXFD" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,NPTXFSA" rgroup.long 0x2C++0x3 line.long 0x0 "HNPTXSTS,In device mode. this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue." hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,NPTXQTOP" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,NPTQXSAV" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,NPTXFSAV" group.long 0x38++0x7 line.long 0x0 "GCCFG,OTG general core configuration register" bitfld.long 0x0 21. "VBDEN,VBDEN" "0,1" bitfld.long 0x0 20. "SDEN,SDEN" "0,1" bitfld.long 0x0 19. "PDEN,PDEN" "0,1" bitfld.long 0x0 18. "DCDEN,DCDEN" "0,1" bitfld.long 0x0 17. "BCDEN,BCDEN" "0,1" newline bitfld.long 0x0 16. "PWRDWN,PWRDWN" "0,1" rbitfld.long 0x0 3. "PS2DET,PS2DET" "0,1" rbitfld.long 0x0 2. "SDET,SDET" "0,1" rbitfld.long 0x0 1. "PDET,PDET" "0,1" rbitfld.long 0x0 0. "DCDET,DCDET" "0,1" line.long 0x4 "CID,This is a register containing the Product ID as reset value." hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,PRODUCT_ID" group.long 0x54++0x3 line.long 0x0 "GLPMCFG,OTG core LPM configuration register" bitfld.long 0x0 28. "ENBESL,ENBESL" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPMRCNTSTS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,SNDLPM" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPMRCNT" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPMCHIDX" newline rbitfld.long 0x0 16. "L1RSMOK,L1RSMOK" "0,1" rbitfld.long 0x0 15. "SLPSTS,SLPSTS" "0,1" rbitfld.long 0x0 13.--14. "LPMRSP,LPMRSP" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1DSEN" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESLTHRS" newline bitfld.long 0x0 7. "L1SSEN,L1SSEN" "0,1" bitfld.long 0x0 6. "REMWAKE,REMWAKE" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,BESL" bitfld.long 0x0 1. "LPMACK,LPMACK" "0,1" bitfld.long 0x0 0. "LPMEN,LPMEN" "0,1" group.long 0x100++0x17 line.long 0x0 "HPTXFSIZ,OTG host periodic transmit FIFO size register" hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,PTXFSIZ" hexmask.long.word 0x0 0.--15. 1. "PTXSA,PTXSA" line.long 0x4 "DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x8 "DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0xC "DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x10 "DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x14 "DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,INEPTXSA" group.long 0x400++0x7 line.long 0x0 "HCFG,This register configures the core after power-on. Do not make changes to this register after initializing the host." rbitfld.long 0x0 2. "FSLSS,FSLSS" "0,1" bitfld.long 0x0 0.--1. "FSLSPCS,FSLSPCS" "0,1,2,3" line.long 0x4 "HFIR,This register stores the frame interval information for the current speed to which the OTG controller has enumerated." bitfld.long 0x4 16. "RLDCTRL,RLDCTRL" "0,1" hexmask.long.word 0x4 0.--15. 1. "FRIVL,FRIVL" rgroup.long 0x408++0x3 line.long 0x0 "HFNUM,This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame." hexmask.long.word 0x0 16.--31. 1. "FTREM,FTREM" hexmask.long.word 0x0 0.--15. 1. "FRNUM,FRNUM" rgroup.long 0x410++0x7 line.long 0x0 "HPTXSTS,This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue." hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,PTXQTOP" hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,PTXQSAV" hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,PTXFSAVL" line.long 0x4 "HAINT,When a significant event occurs on a channel. the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one.." hexmask.long.word 0x4 0.--15. 1. "HAINT,HAINT" group.long 0x418++0x3 line.long 0x0 "HAINTMSK,The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel. up to a maximum of 16 bits." hexmask.long.word 0x0 0.--15. 1. "HAINTM,HAINTM" group.long 0x440++0x3 line.long 0x0 "HPRT,This register is available only in host mode. Currently. the OTG host supports only one port. A single register holds USB port-related information such as USB reset. enable. suspend. resume. connect status. and test mode for each port. It is shown.." rbitfld.long 0x0 17.--18. "PSPD,PSPD" "0,1,2,3" hexmask.long.byte 0x0 13.--16. 1. "PTCTL,PTCTL" bitfld.long 0x0 12. "PPWR,PPWR" "0,1" rbitfld.long 0x0 10.--11. "PLSTS,PLSTS" "0,1,2,3" bitfld.long 0x0 8. "PRST,PRST" "0,1" newline bitfld.long 0x0 7. "PSUSP,PSUSP" "0,1" bitfld.long 0x0 6. "PRES,PRES" "0,1" bitfld.long 0x0 5. "POCCHNG,POCCHNG" "0,1" rbitfld.long 0x0 4. "POCA,POCA" "0,1" bitfld.long 0x0 3. "PENCHNG,PENCHNG" "0,1" newline bitfld.long 0x0 2. "PENA,PENA" "0,1" bitfld.long 0x0 1. "PCDET,PCDET" "0,1" rbitfld.long 0x0 0. "PCSTS,PCSTS" "0,1" group.long 0x500++0x3 line.long 0x0 "HCCHAR0,OTG host channel 0 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x508++0xB line.long 0x0 "HCINT0,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK0,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ0,OTG host channel 0 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x520++0x3 line.long 0x0 "HCCHAR1,OTG host channel 1 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x528++0xB line.long 0x0 "HCINT1,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK1,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ1,OTG host channel 1 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x540++0x3 line.long 0x0 "HCCHAR2,OTG host channel 2 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x548++0xB line.long 0x0 "HCINT2,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK2,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ2,OTG host channel 2 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x560++0x3 line.long 0x0 "HCCHAR3,OTG host channel 3 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x568++0xB line.long 0x0 "HCINT3,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK3,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ3,OTG host channel 3 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x580++0x3 line.long 0x0 "HCCHAR4,OTG host channel 4 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x588++0xB line.long 0x0 "HCINT4,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK4,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ4,OTG host channel 4 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5A0++0x3 line.long 0x0 "HCCHAR5,OTG host channel 5 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5A8++0xB line.long 0x0 "HCINT5,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK5,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ5,OTG host channel 5 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5C0++0x3 line.long 0x0 "HCCHAR6,OTG host channel 6 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5C8++0xB line.long 0x0 "HCINT6,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK6,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ6,OTG host channel 6 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5E0++0x3 line.long 0x0 "HCCHAR7,OTG host channel 7 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5E8++0xB line.long 0x0 "HCINT7,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK7,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ7,OTG host channel 7 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x600++0x3 line.long 0x0 "HCCHAR8,OTG host channel 8 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x608++0xB line.long 0x0 "HCINT8,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK8,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ8,OTG host channel 8 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x620++0x3 line.long 0x0 "HCCHAR9,OTG host channel 9 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x628++0xB line.long 0x0 "HCINT9,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK9,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ9,OTG host channel 9 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x640++0x3 line.long 0x0 "HCCHAR10,OTG host channel 10 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x648++0xB line.long 0x0 "HCINT10,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK10,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ10,OTG host channel 10 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x660++0x3 line.long 0x0 "HCCHAR11,OTG host channel 11 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x668++0xB line.long 0x0 "HCINT11,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK11,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ11,OTG host channel 11 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x800++0x7 line.long 0x0 "DCFG,This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming." bitfld.long 0x0 15. "ERRATIM,ERRATIM" "0,1" bitfld.long 0x0 11.--12. "PFIVL,PFIVL" "0,1,2,3" hexmask.long.byte 0x0 4.--10. 1. "DAD,DAD" bitfld.long 0x0 2. "NZLSOHSK,NZLSOHSK" "0,1" bitfld.long 0x0 0.--1. "DSPD,DSPD" "0,1,2,3" line.long 0x4 "DCTL,OTG device control register" bitfld.long 0x4 18. "DSBESLRJCT,DSBESLRJCT" "0,1" bitfld.long 0x4 11. "POPRGDNE,POPRGDNE" "0,1" bitfld.long 0x4 10. "CGONAK,CGONAK" "0,1" bitfld.long 0x4 9. "SGONAK,SGONAK" "0,1" bitfld.long 0x4 8. "CGINAK,CGINAK" "0,1" newline bitfld.long 0x4 7. "SGINAK,SGINAK" "0,1" bitfld.long 0x4 4.--6. "TCTL,TCTL" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "GONSTS,GONSTS" "0,1" rbitfld.long 0x4 2. "GINSTS,GINSTS" "0,1" bitfld.long 0x4 1. "SDIS,SDIS" "0,1" newline bitfld.long 0x4 0. "RWUSIG,RWUSIG" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "DSTS,This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register." bitfld.long 0x0 22.--23. "DEVLNSTS,DEVLNSTS" "0,1,2,3" hexmask.long.word 0x0 8.--21. 1. "FNSOF,FNSOF" bitfld.long 0x0 3. "EERR,EERR" "0,1" bitfld.long 0x0 1.--2. "ENUMSPD,ENUMSPD" "0,1,2,3" bitfld.long 0x0 0. "SUSPSTS,SUSPSTS" "0,1" group.long 0x810++0x7 line.long 0x0 "DIEPMSK,This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this.." bitfld.long 0x0 13. "NAKM,NAKM" "0,1" bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" bitfld.long 0x0 5. "INEPNMM,INEPNMM" "0,1" bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" bitfld.long 0x0 3. "TOM,TOM" "0,1" newline bitfld.long 0x0 1. "EPDM,EPDM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" line.long 0x4 "DOEPMSK,This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in.." bitfld.long 0x4 13. "NAKMSK,NAKMSK" "0,1" bitfld.long 0x4 12. "BERRM,BERRM" "0,1" bitfld.long 0x4 8. "OUTPKTERRM,OUTPKTERRM" "0,1" bitfld.long 0x4 5. "STSPHSRXM,STSPHSRXM" "0,1" bitfld.long 0x4 4. "OTEPDM,OTEPDM" "0,1" newline bitfld.long 0x4 3. "STUPM,STUPM" "0,1" bitfld.long 0x4 1. "EPDM,EPDM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" rgroup.long 0x818++0x3 line.long 0x0 "DAINT,When a significant event occurs on an endpoint. a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS. respectively). There.." hexmask.long.word 0x0 16.--31. 1. "OEPINT,OEPINT" hexmask.long.word 0x0 0.--15. 1. "IEPINT,IEPINT" group.long 0x81C++0x3 line.long 0x0 "DAINTMSK,The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However. the DAINT register bit corresponding to that interrupt is still set." hexmask.long.word 0x0 16.--31. 1. "OEPM,OEPM" hexmask.long.word 0x0 0.--15. 1. "IEPM,IEPM" group.long 0x828++0x7 line.long 0x0 "DVBUSDIS,This register specifies the VBUS discharge time after VBUS pulsing during SRP." hexmask.long.word 0x0 0.--15. 1. "VBUSDT,VBUSDT" line.long 0x4 "DVBUSPULSE,This register specifies the VBUS pulsing time during SRP." hexmask.long.word 0x4 0.--15. 1. "DVBUSP,DVBUSP" group.long 0x834++0x3 line.long 0x0 "DIEPEMPMSK,This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx)." hexmask.long.word 0x0 0.--15. 1. "INEPTXFEM,INEPTXFEM" group.long 0x900++0x3 line.long 0x0 "DIEPCTL0,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" bitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" group.long 0x908++0x3 line.long 0x0 "DIEPINT0,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x910++0x3 line.long 0x0 "DIEPTSIZ0,The application must modify this register before enabling endpoint 0." bitfld.long 0x0 19.--20. "PKTCNT,PKTCNT" "0,1,2,3" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x918++0x3 line.long 0x0 "DTXFSTS0,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x920++0x3 line.long 0x0 "DIEPCTL1,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x928++0x3 line.long 0x0 "DIEPINT1,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x930++0x3 line.long 0x0 "DIEPTSIZ1,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x938++0x3 line.long 0x0 "DTXFSTS1,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x940++0x3 line.long 0x0 "DIEPCTL2,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x948++0x3 line.long 0x0 "DIEPINT2,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x950++0x3 line.long 0x0 "DIEPTSIZ2,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x958++0x3 line.long 0x0 "DTXFSTS2,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x960++0x3 line.long 0x0 "DIEPCTL3,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x968++0x3 line.long 0x0 "DIEPINT3,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x970++0x3 line.long 0x0 "DIEPTSIZ3,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x978++0x3 line.long 0x0 "DTXFSTS3,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x980++0x3 line.long 0x0 "DIEPCTL4,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x988++0x3 line.long 0x0 "DIEPINT4,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x990++0x3 line.long 0x0 "DIEPTSIZ4,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x998++0x3 line.long 0x0 "DTXFSTS4,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x9A0++0x3 line.long 0x0 "DIEPCTL5,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x9A8++0x3 line.long 0x0 "DIEPINT5,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x9B0++0x3 line.long 0x0 "DIEPTSIZ5,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x9B8++0x3 line.long 0x0 "DTXFSTS5,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0xB00++0x3 line.long 0x0 "DOEPCTL0,This section describes the DOEPCTL0 register." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" rbitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" newline bitfld.long 0x0 20. "SNPM,SNPM" "0,1" rbitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" rbitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" group.long 0xB08++0x3 line.long 0x0 "DOEPINT0,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB10++0x3 line.long 0x0 "DOEPTSIZ0,The application must modify this register before enabling endpoint 0." bitfld.long 0x0 29.--30. "STUPCNT,STUPCNT" "0,1,2,3" bitfld.long 0x0 19. "PKTCNT,PKTCNT" "0,1" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,XFRSIZ" group.long 0xB20++0x3 line.long 0x0 "DOEPCTL1,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB28++0x3 line.long 0x0 "DOEPINT1,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB30++0x3 line.long 0x0 "DOEPTSIZ1,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xB40++0x3 line.long 0x0 "DOEPCTL2,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB48++0x3 line.long 0x0 "DOEPINT2,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB50++0x3 line.long 0x0 "DOEPTSIZ2,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xB60++0x3 line.long 0x0 "DOEPCTL3,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB68++0x3 line.long 0x0 "DOEPINT3,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB70++0x3 line.long 0x0 "DOEPTSIZ3,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xB80++0x3 line.long 0x0 "DOEPCTL4,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB88++0x3 line.long 0x0 "DOEPINT4,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB90++0x3 line.long 0x0 "DOEPTSIZ4,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xBA0++0x3 line.long 0x0 "DOEPCTL5,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xBA8++0x3 line.long 0x0 "DOEPINT5,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xBB0++0x3 line.long 0x0 "DOEPTSIZ5,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xE00++0x3 line.long 0x0 "PCGCCTL,This register is available in host and device modes." rbitfld.long 0x0 7. "SUSP,SUSP" "0,1" rbitfld.long 0x0 6. "PHYSLEEP,PHYSLEEP" "0,1" bitfld.long 0x0 5. "ENL1GTG,ENL1GTG" "0,1" rbitfld.long 0x0 4. "PHYSUSP,PHYSUSP" "0,1" bitfld.long 0x0 1. "GATEHCLK,GATEHCLK" "0,1" newline bitfld.long 0x0 0. "STPPCLK,STPPCLK" "0,1" tree.end tree "SEC_OTG_FS" base ad:0x52040000 group.long 0x0++0x1B line.long 0x0 "GOTGCTL,The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core." rbitfld.long 0x0 21. "CURMOD,CURMOD" "0,1" bitfld.long 0x0 20. "OTGVER,OTGVER" "0,1" rbitfld.long 0x0 19. "BSVLD,BSVLD" "0,1" rbitfld.long 0x0 18. "ASVLD,ASVLD" "0,1" rbitfld.long 0x0 17. "DBCT,DBCT" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,CIDSTS" "0,1" bitfld.long 0x0 12. "EHEN,EHEN" "0,1" bitfld.long 0x0 11. "DHNPEN,DHNPEN" "0,1" bitfld.long 0x0 10. "HSHNPEN,HSHNPEN" "0,1" bitfld.long 0x0 9. "HNPRQ,HNPRQ" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,HNGSCS" "0,1" bitfld.long 0x0 7. "BVALOVAL,BVALOVAL" "0,1" bitfld.long 0x0 6. "BVALOEN,BVALOEN" "0,1" bitfld.long 0x0 5. "AVALOVAL,AVALOVAL" "0,1" bitfld.long 0x0 4. "AVALOEN,AVALOEN" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBVALOVAL" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBVALOEN" "0,1" bitfld.long 0x0 1. "SRQ,SRQ" "0,1" rbitfld.long 0x0 0. "SRQSCS,SRQSCS" "0,1" line.long 0x4 "GOTGINT,The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt." bitfld.long 0x4 19. "DBCDNE,DBCDNE" "0,1" bitfld.long 0x4 18. "ADTOCHG,ADTOCHG" "0,1" bitfld.long 0x4 17. "HNGDET,HNGDET" "0,1" bitfld.long 0x4 9. "HNSSCHG,HNSSCHG" "0,1" bitfld.long 0x4 8. "SRSSCHG,SRSSCHG" "0,1" newline bitfld.long 0x4 2. "SEDET,SEDET" "0,1" line.long 0x8 "GAHBCFG,This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program.." bitfld.long 0x8 8. "PTXFELVL,PTXFELVL" "0,1" bitfld.long 0x8 7. "TXFELVL,TXFELVL" "0,1" bitfld.long 0x8 0. "GINTMSK,GINTMSK" "0,1" line.long 0xC "GUSBCFG,This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on.." bitfld.long 0xC 30. "FDMOD,FDMOD" "0,1" bitfld.long 0xC 29. "FHMOD,FHMOD" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,TRDT" bitfld.long 0xC 9. "HNPCAP,HNPCAP" "0,1" bitfld.long 0xC 8. "SRPCAP,SRPCAP" "0,1" newline rbitfld.long 0xC 6. "PHYSEL,PHYSEL" "0,1" bitfld.long 0xC 0.--2. "TOCAL,TOCAL" "0,1,2,3,4,5,6,7" line.long 0x10 "GRSTCTL,The application uses this register to reset various hardware features inside the core." rbitfld.long 0x10 31. "AHBIDL,AHBIDL" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TXFNUM" bitfld.long 0x10 5. "TXFFLSH,TXFFLSH" "0,1" bitfld.long 0x10 4. "RXFFLSH,RXFFLSH" "0,1" bitfld.long 0x10 2. "FSRST,FSRST" "0,1" newline bitfld.long 0x10 1. "PSRST,PSRST" "0,1" rbitfld.long 0x10 0. "CSRST,CSRST" "0,1" line.long 0x14 "GINTSTS,This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode. while others are valid in device mode only. This register also.." bitfld.long 0x14 31. "WKUPINT,WKUPINT" "0,1" bitfld.long 0x14 30. "SRQINT,SRQINT" "0,1" bitfld.long 0x14 29. "DISCINT,DISCINT" "0,1" bitfld.long 0x14 28. "CIDSCHG,CIDSCHG" "0,1" bitfld.long 0x14 27. "LPMINT,LPMINT" "0,1" newline rbitfld.long 0x14 26. "PTXFE,PTXFE" "0,1" rbitfld.long 0x14 25. "HCINT,HCINT" "0,1" rbitfld.long 0x14 24. "HPRTINT,HPRTINT" "0,1" bitfld.long 0x14 23. "RSTDET,RSTDET" "0,1" bitfld.long 0x14 21. "IPXFR,IPXFR" "0,1" newline bitfld.long 0x14 20. "IISOIXFR,IISOIXFR" "0,1" rbitfld.long 0x14 19. "OEPINT,OEPINT" "0,1" rbitfld.long 0x14 18. "IEPINT,IEPINT" "0,1" bitfld.long 0x14 15. "EOPF,EOPF" "0,1" bitfld.long 0x14 14. "ISOODRP,ISOODRP" "0,1" newline bitfld.long 0x14 13. "ENUMDNE,ENUMDNE" "0,1" bitfld.long 0x14 12. "USBRST,USBRST" "0,1" bitfld.long 0x14 11. "USBSUSP,USBSUSP" "0,1" bitfld.long 0x14 10. "ESUSP,ESUSP" "0,1" rbitfld.long 0x14 7. "GONAKEFF,GONAKEFF" "0,1" newline rbitfld.long 0x14 6. "GINAKEFF,GINAKEFF" "0,1" rbitfld.long 0x14 5. "NPTXFE,NPTXFE" "0,1" rbitfld.long 0x14 4. "RXFLVL,RXFLVL" "0,1" bitfld.long 0x14 3. "SOF,SOF" "0,1" rbitfld.long 0x14 2. "OTGINT,OTGINT" "0,1" newline bitfld.long 0x14 1. "MMIS,MMIS" "0,1" rbitfld.long 0x14 0. "CMOD,CMOD" "0,1" line.long 0x18 "GINTMSK,This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked. the interrupt associated with that bit is not generated. However. the core interrupt (GINTSTS) register bit corresponding to that.." bitfld.long 0x18 31. "WUIM,WUIM" "0,1" bitfld.long 0x18 30. "SRQIM,SRQIM" "0,1" bitfld.long 0x18 29. "DISCINT,DISCINT" "0,1" bitfld.long 0x18 28. "CIDSCHGM,CIDSCHGM" "0,1" bitfld.long 0x18 27. "LPMINTM,LPMINTM" "0,1" newline bitfld.long 0x18 26. "PTXFEM,PTXFEM" "0,1" bitfld.long 0x18 25. "HCIM,HCIM" "0,1" bitfld.long 0x18 24. "PRTIM,PRTIM" "0,1" bitfld.long 0x18 23. "RSTDETM,RSTDETM" "0,1" bitfld.long 0x18 21. "IPXFRM,IPXFRM" "0,1" newline bitfld.long 0x18 20. "IISOIXFRM,IISOIXFRM" "0,1" bitfld.long 0x18 19. "OEPINT,OEPINT" "0,1" bitfld.long 0x18 18. "IEPINT,IEPINT" "0,1" bitfld.long 0x18 15. "EOPFM,EOPFM" "0,1" bitfld.long 0x18 14. "ISOODRPM,ISOODRPM" "0,1" newline bitfld.long 0x18 13. "ENUMDNEM,ENUMDNEM" "0,1" bitfld.long 0x18 12. "USBRST,USBRST" "0,1" bitfld.long 0x18 11. "USBSUSPM,USBSUSPM" "0,1" bitfld.long 0x18 10. "ESUSPM,ESUSPM" "0,1" bitfld.long 0x18 7. "GONAKEFFM,GONAKEFFM" "0,1" newline bitfld.long 0x18 6. "GINAKEFFM,GINAKEFFM" "0,1" bitfld.long 0x18 5. "NPTXFEM,NPTXFEM" "0,1" bitfld.long 0x18 4. "RXFLVLM,RXFLVLM" "0,1" bitfld.long 0x18 3. "SOFM,SOFM" "0,1" bitfld.long 0x18 2. "OTGINT,OTGINT" "0,1" newline bitfld.long 0x18 1. "MMISM,MMISM" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "GRXSTSR_DEVICE,This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and.." bitfld.long 0x0 27. "STSPHST,STSPHST" "0,1" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x0 0.--3. 1. "EPNUM,EPNUM" rgroup.long 0x1C++0x7 line.long 0x0 "GRXSTSR_HOST,This description is for register GRXSTSR in Host mode" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,CHNUM" line.long 0x4 "GRXSTSP_DEVICE,This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO. a read to GRXSTSP (receive status read and pop register).." bitfld.long 0x4 27. "STSPHST,STSPHST" "0,1" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x4 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x4 0.--3. 1. "EPNUM,EPNUM" rgroup.long 0x20++0x3 line.long 0x0 "GRXSTSP_HOST,This description is for register GRXSTSP in HOST mode" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,CHNUM" group.long 0x24++0x7 line.long 0x0 "GRXFSIZ,The application can program the RAM size that must be allocated to the Rx FIFO." hexmask.long.word 0x0 0.--15. 1. "RXFD,RXFD" line.long 0x4 "HNPTXFSIZ,Host mode" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,NPTXFD" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,NPTXFSA" rgroup.long 0x2C++0x3 line.long 0x0 "HNPTXSTS,In device mode. this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue." hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,NPTXQTOP" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,NPTQXSAV" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,NPTXFSAV" group.long 0x38++0x7 line.long 0x0 "GCCFG,OTG general core configuration register" bitfld.long 0x0 21. "VBDEN,VBDEN" "0,1" bitfld.long 0x0 20. "SDEN,SDEN" "0,1" bitfld.long 0x0 19. "PDEN,PDEN" "0,1" bitfld.long 0x0 18. "DCDEN,DCDEN" "0,1" bitfld.long 0x0 17. "BCDEN,BCDEN" "0,1" newline bitfld.long 0x0 16. "PWRDWN,PWRDWN" "0,1" rbitfld.long 0x0 3. "PS2DET,PS2DET" "0,1" rbitfld.long 0x0 2. "SDET,SDET" "0,1" rbitfld.long 0x0 1. "PDET,PDET" "0,1" rbitfld.long 0x0 0. "DCDET,DCDET" "0,1" line.long 0x4 "CID,This is a register containing the Product ID as reset value." hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,PRODUCT_ID" group.long 0x54++0x3 line.long 0x0 "GLPMCFG,OTG core LPM configuration register" bitfld.long 0x0 28. "ENBESL,ENBESL" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPMRCNTSTS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,SNDLPM" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPMRCNT" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPMCHIDX" newline rbitfld.long 0x0 16. "L1RSMOK,L1RSMOK" "0,1" rbitfld.long 0x0 15. "SLPSTS,SLPSTS" "0,1" rbitfld.long 0x0 13.--14. "LPMRSP,LPMRSP" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1DSEN" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESLTHRS" newline bitfld.long 0x0 7. "L1SSEN,L1SSEN" "0,1" bitfld.long 0x0 6. "REMWAKE,REMWAKE" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,BESL" bitfld.long 0x0 1. "LPMACK,LPMACK" "0,1" bitfld.long 0x0 0. "LPMEN,LPMEN" "0,1" group.long 0x100++0x17 line.long 0x0 "HPTXFSIZ,OTG host periodic transmit FIFO size register" hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,PTXFSIZ" hexmask.long.word 0x0 0.--15. 1. "PTXSA,PTXSA" line.long 0x4 "DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x8 "DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0xC "DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x10 "DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x14 "DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,INEPTXSA" group.long 0x400++0x7 line.long 0x0 "HCFG,This register configures the core after power-on. Do not make changes to this register after initializing the host." rbitfld.long 0x0 2. "FSLSS,FSLSS" "0,1" bitfld.long 0x0 0.--1. "FSLSPCS,FSLSPCS" "0,1,2,3" line.long 0x4 "HFIR,This register stores the frame interval information for the current speed to which the OTG controller has enumerated." bitfld.long 0x4 16. "RLDCTRL,RLDCTRL" "0,1" hexmask.long.word 0x4 0.--15. 1. "FRIVL,FRIVL" rgroup.long 0x408++0x3 line.long 0x0 "HFNUM,This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame." hexmask.long.word 0x0 16.--31. 1. "FTREM,FTREM" hexmask.long.word 0x0 0.--15. 1. "FRNUM,FRNUM" rgroup.long 0x410++0x7 line.long 0x0 "HPTXSTS,This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue." hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,PTXQTOP" hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,PTXQSAV" hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,PTXFSAVL" line.long 0x4 "HAINT,When a significant event occurs on a channel. the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one.." hexmask.long.word 0x4 0.--15. 1. "HAINT,HAINT" group.long 0x418++0x3 line.long 0x0 "HAINTMSK,The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel. up to a maximum of 16 bits." hexmask.long.word 0x0 0.--15. 1. "HAINTM,HAINTM" group.long 0x440++0x3 line.long 0x0 "HPRT,This register is available only in host mode. Currently. the OTG host supports only one port. A single register holds USB port-related information such as USB reset. enable. suspend. resume. connect status. and test mode for each port. It is shown.." rbitfld.long 0x0 17.--18. "PSPD,PSPD" "0,1,2,3" hexmask.long.byte 0x0 13.--16. 1. "PTCTL,PTCTL" bitfld.long 0x0 12. "PPWR,PPWR" "0,1" rbitfld.long 0x0 10.--11. "PLSTS,PLSTS" "0,1,2,3" bitfld.long 0x0 8. "PRST,PRST" "0,1" newline bitfld.long 0x0 7. "PSUSP,PSUSP" "0,1" bitfld.long 0x0 6. "PRES,PRES" "0,1" bitfld.long 0x0 5. "POCCHNG,POCCHNG" "0,1" rbitfld.long 0x0 4. "POCA,POCA" "0,1" bitfld.long 0x0 3. "PENCHNG,PENCHNG" "0,1" newline bitfld.long 0x0 2. "PENA,PENA" "0,1" bitfld.long 0x0 1. "PCDET,PCDET" "0,1" rbitfld.long 0x0 0. "PCSTS,PCSTS" "0,1" group.long 0x500++0x3 line.long 0x0 "HCCHAR0,OTG host channel 0 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x508++0xB line.long 0x0 "HCINT0,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK0,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ0,OTG host channel 0 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x520++0x3 line.long 0x0 "HCCHAR1,OTG host channel 1 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x528++0xB line.long 0x0 "HCINT1,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK1,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ1,OTG host channel 1 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x540++0x3 line.long 0x0 "HCCHAR2,OTG host channel 2 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x548++0xB line.long 0x0 "HCINT2,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK2,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ2,OTG host channel 2 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x560++0x3 line.long 0x0 "HCCHAR3,OTG host channel 3 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x568++0xB line.long 0x0 "HCINT3,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK3,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ3,OTG host channel 3 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x580++0x3 line.long 0x0 "HCCHAR4,OTG host channel 4 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x588++0xB line.long 0x0 "HCINT4,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK4,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ4,OTG host channel 4 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5A0++0x3 line.long 0x0 "HCCHAR5,OTG host channel 5 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5A8++0xB line.long 0x0 "HCINT5,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK5,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ5,OTG host channel 5 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5C0++0x3 line.long 0x0 "HCCHAR6,OTG host channel 6 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5C8++0xB line.long 0x0 "HCINT6,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK6,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ6,OTG host channel 6 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5E0++0x3 line.long 0x0 "HCCHAR7,OTG host channel 7 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5E8++0xB line.long 0x0 "HCINT7,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK7,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ7,OTG host channel 7 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x600++0x3 line.long 0x0 "HCCHAR8,OTG host channel 8 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x608++0xB line.long 0x0 "HCINT8,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK8,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ8,OTG host channel 8 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x620++0x3 line.long 0x0 "HCCHAR9,OTG host channel 9 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x628++0xB line.long 0x0 "HCINT9,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK9,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ9,OTG host channel 9 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x640++0x3 line.long 0x0 "HCCHAR10,OTG host channel 10 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x648++0xB line.long 0x0 "HCINT10,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK10,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ10,OTG host channel 10 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x660++0x3 line.long 0x0 "HCCHAR11,OTG host channel 11 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x668++0xB line.long 0x0 "HCINT11,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" newline bitfld.long 0x0 4. "NAK,NAK" "0,1" bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK11,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x4 4. "NAKM,NAKM" "0,1" bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ11,OTG host channel 11 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x800++0x7 line.long 0x0 "DCFG,This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming." bitfld.long 0x0 15. "ERRATIM,ERRATIM" "0,1" bitfld.long 0x0 11.--12. "PFIVL,PFIVL" "0,1,2,3" hexmask.long.byte 0x0 4.--10. 1. "DAD,DAD" bitfld.long 0x0 2. "NZLSOHSK,NZLSOHSK" "0,1" bitfld.long 0x0 0.--1. "DSPD,DSPD" "0,1,2,3" line.long 0x4 "DCTL,OTG device control register" bitfld.long 0x4 18. "DSBESLRJCT,DSBESLRJCT" "0,1" bitfld.long 0x4 11. "POPRGDNE,POPRGDNE" "0,1" bitfld.long 0x4 10. "CGONAK,CGONAK" "0,1" bitfld.long 0x4 9. "SGONAK,SGONAK" "0,1" bitfld.long 0x4 8. "CGINAK,CGINAK" "0,1" newline bitfld.long 0x4 7. "SGINAK,SGINAK" "0,1" bitfld.long 0x4 4.--6. "TCTL,TCTL" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "GONSTS,GONSTS" "0,1" rbitfld.long 0x4 2. "GINSTS,GINSTS" "0,1" bitfld.long 0x4 1. "SDIS,SDIS" "0,1" newline bitfld.long 0x4 0. "RWUSIG,RWUSIG" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "DSTS,This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register." bitfld.long 0x0 22.--23. "DEVLNSTS,DEVLNSTS" "0,1,2,3" hexmask.long.word 0x0 8.--21. 1. "FNSOF,FNSOF" bitfld.long 0x0 3. "EERR,EERR" "0,1" bitfld.long 0x0 1.--2. "ENUMSPD,ENUMSPD" "0,1,2,3" bitfld.long 0x0 0. "SUSPSTS,SUSPSTS" "0,1" group.long 0x810++0x7 line.long 0x0 "DIEPMSK,This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this.." bitfld.long 0x0 13. "NAKM,NAKM" "0,1" bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" bitfld.long 0x0 5. "INEPNMM,INEPNMM" "0,1" bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" bitfld.long 0x0 3. "TOM,TOM" "0,1" newline bitfld.long 0x0 1. "EPDM,EPDM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" line.long 0x4 "DOEPMSK,This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in.." bitfld.long 0x4 13. "NAKMSK,NAKMSK" "0,1" bitfld.long 0x4 12. "BERRM,BERRM" "0,1" bitfld.long 0x4 8. "OUTPKTERRM,OUTPKTERRM" "0,1" bitfld.long 0x4 5. "STSPHSRXM,STSPHSRXM" "0,1" bitfld.long 0x4 4. "OTEPDM,OTEPDM" "0,1" newline bitfld.long 0x4 3. "STUPM,STUPM" "0,1" bitfld.long 0x4 1. "EPDM,EPDM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" rgroup.long 0x818++0x3 line.long 0x0 "DAINT,When a significant event occurs on an endpoint. a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS. respectively). There.." hexmask.long.word 0x0 16.--31. 1. "OEPINT,OEPINT" hexmask.long.word 0x0 0.--15. 1. "IEPINT,IEPINT" group.long 0x81C++0x3 line.long 0x0 "DAINTMSK,The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However. the DAINT register bit corresponding to that interrupt is still set." hexmask.long.word 0x0 16.--31. 1. "OEPM,OEPM" hexmask.long.word 0x0 0.--15. 1. "IEPM,IEPM" group.long 0x828++0x7 line.long 0x0 "DVBUSDIS,This register specifies the VBUS discharge time after VBUS pulsing during SRP." hexmask.long.word 0x0 0.--15. 1. "VBUSDT,VBUSDT" line.long 0x4 "DVBUSPULSE,This register specifies the VBUS pulsing time during SRP." hexmask.long.word 0x4 0.--15. 1. "DVBUSP,DVBUSP" group.long 0x834++0x3 line.long 0x0 "DIEPEMPMSK,This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx)." hexmask.long.word 0x0 0.--15. 1. "INEPTXFEM,INEPTXFEM" group.long 0x900++0x3 line.long 0x0 "DIEPCTL0,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" bitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" group.long 0x908++0x3 line.long 0x0 "DIEPINT0,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x910++0x3 line.long 0x0 "DIEPTSIZ0,The application must modify this register before enabling endpoint 0." bitfld.long 0x0 19.--20. "PKTCNT,PKTCNT" "0,1,2,3" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x918++0x3 line.long 0x0 "DTXFSTS0,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x920++0x3 line.long 0x0 "DIEPCTL1,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x928++0x3 line.long 0x0 "DIEPINT1,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x930++0x3 line.long 0x0 "DIEPTSIZ1,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x938++0x3 line.long 0x0 "DTXFSTS1,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x940++0x3 line.long 0x0 "DIEPCTL2,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x948++0x3 line.long 0x0 "DIEPINT2,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x950++0x3 line.long 0x0 "DIEPTSIZ2,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x958++0x3 line.long 0x0 "DTXFSTS2,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x960++0x3 line.long 0x0 "DIEPCTL3,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x968++0x3 line.long 0x0 "DIEPINT3,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x970++0x3 line.long 0x0 "DIEPTSIZ3,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x978++0x3 line.long 0x0 "DTXFSTS3,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x980++0x3 line.long 0x0 "DIEPCTL4,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x988++0x3 line.long 0x0 "DIEPINT4,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x990++0x3 line.long 0x0 "DIEPTSIZ4,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x998++0x3 line.long 0x0 "DTXFSTS4,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x9A0++0x3 line.long 0x0 "DIEPCTL5,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x9A8++0x3 line.long 0x0 "DIEPINT5,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" newline bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x9B0++0x3 line.long 0x0 "DIEPTSIZ5,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x9B8++0x3 line.long 0x0 "DTXFSTS5,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0xB00++0x3 line.long 0x0 "DOEPCTL0,This section describes the DOEPCTL0 register." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" rbitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" newline bitfld.long 0x0 20. "SNPM,SNPM" "0,1" rbitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" rbitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" group.long 0xB08++0x3 line.long 0x0 "DOEPINT0,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB10++0x3 line.long 0x0 "DOEPTSIZ0,The application must modify this register before enabling endpoint 0." bitfld.long 0x0 29.--30. "STUPCNT,STUPCNT" "0,1,2,3" bitfld.long 0x0 19. "PKTCNT,PKTCNT" "0,1" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,XFRSIZ" group.long 0xB20++0x3 line.long 0x0 "DOEPCTL1,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB28++0x3 line.long 0x0 "DOEPINT1,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB30++0x3 line.long 0x0 "DOEPTSIZ1,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xB40++0x3 line.long 0x0 "DOEPCTL2,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB48++0x3 line.long 0x0 "DOEPINT2,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB50++0x3 line.long 0x0 "DOEPTSIZ2,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xB60++0x3 line.long 0x0 "DOEPCTL3,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB68++0x3 line.long 0x0 "DOEPINT3,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB70++0x3 line.long 0x0 "DOEPTSIZ3,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xB80++0x3 line.long 0x0 "DOEPCTL4,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB88++0x3 line.long 0x0 "DOEPINT4,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB90++0x3 line.long 0x0 "DOEPTSIZ4,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xBA0++0x3 line.long 0x0 "DOEPCTL5,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xBA8++0x3 line.long 0x0 "DOEPINT5,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" bitfld.long 0x0 3. "STUP,STUP" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xBB0++0x3 line.long 0x0 "DOEPTSIZ5,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0xE00++0x3 line.long 0x0 "PCGCCTL,This register is available in host and device modes." rbitfld.long 0x0 7. "SUSP,SUSP" "0,1" rbitfld.long 0x0 6. "PHYSLEEP,PHYSLEEP" "0,1" bitfld.long 0x0 5. "ENL1GTG,ENL1GTG" "0,1" rbitfld.long 0x0 4. "PHYSUSP,PHYSUSP" "0,1" bitfld.long 0x0 1. "GATEHCLK,GATEHCLK" "0,1" newline bitfld.long 0x0 0. "STPPCLK,STPPCLK" "0,1" tree.end tree.end endif sif (cpuis("STM32U595*")||cpuis("STM32U599*")||cpuis("STM32U5A5*")||cpuis("STM32U5A9*")||cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "OTG_HS (USB On-the-go High-Speed)" base ad:0x0 tree "OTG_HS" base ad:0x42040000 group.long 0x0++0x1B line.long 0x0 "GOTGCTL,The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core." rbitfld.long 0x0 21. "CURMOD,CURMOD" "0,1" bitfld.long 0x0 20. "OTGVER,OTGVER" "0,1" rbitfld.long 0x0 19. "BSVLD,BSVLD" "0,1" newline rbitfld.long 0x0 18. "ASVLD,ASVLD" "0,1" rbitfld.long 0x0 17. "DBCT,DBCT" "0,1" rbitfld.long 0x0 16. "CIDSTS,CIDSTS" "0,1" newline bitfld.long 0x0 12. "EHEN,EHEN" "0,1" bitfld.long 0x0 11. "DHNPEN,DHNPEN" "0,1" bitfld.long 0x0 10. "HSHNPEN,HSHNPEN" "0,1" newline bitfld.long 0x0 9. "HNPRQ,HNPRQ" "0,1" rbitfld.long 0x0 8. "HNGSCS,HNGSCS" "0,1" bitfld.long 0x0 7. "BVALOVAL,BVALOVAL" "0,1" newline bitfld.long 0x0 6. "BVALOEN,BVALOEN" "0,1" bitfld.long 0x0 5. "AVALOVAL,AVALOVAL" "0,1" bitfld.long 0x0 4. "AVALOEN,AVALOEN" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBVALOVAL" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBVALOEN" "0,1" bitfld.long 0x0 1. "SRQ,SRQ" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,SRQSCS" "0,1" line.long 0x4 "GOTGINT,The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt." bitfld.long 0x4 19. "DBCDNE,DBCDNE" "0,1" bitfld.long 0x4 18. "ADTOCHG,ADTOCHG" "0,1" bitfld.long 0x4 17. "HNGDET,HNGDET" "0,1" newline bitfld.long 0x4 9. "HNSSCHG,HNSSCHG" "0,1" bitfld.long 0x4 8. "SRSSCHG,SRSSCHG" "0,1" bitfld.long 0x4 2. "SEDET,SEDET" "0,1" line.long 0x8 "GAHBCFG,This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program.." bitfld.long 0x8 8. "PTXFELVL,PTXFELVL" "0,1" bitfld.long 0x8 7. "TXFELVL,TXFELVL" "0,1" bitfld.long 0x8 0. "GINTMSK,GINTMSK" "0,1" line.long 0xC "GUSBCFG,This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on.." bitfld.long 0xC 30. "FDMOD,FDMOD" "0,1" bitfld.long 0xC 29. "FHMOD,FHMOD" "0,1" bitfld.long 0xC 22. "TSDPS,TSDPS" "0,1" newline bitfld.long 0xC 15. "PHYLPC,PHYLPC" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,TRDT" bitfld.long 0xC 9. "HNPCAP,HNPCAP" "0,1" newline bitfld.long 0xC 8. "SRPCAP,SRPCAP" "0,1" rbitfld.long 0xC 6. "PHYSEL,PHYSEL" "0,1" bitfld.long 0xC 0.--2. "TOCAL,TOCAL" "0,1,2,3,4,5,6,7" line.long 0x10 "GRSTCTL,The application uses this register to reset various hardware features inside the core." rbitfld.long 0x10 31. "AHBIDL,AHBIDL" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMAREQ" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TXFNUM" newline bitfld.long 0x10 5. "TXFFLSH,TXFFLSH" "0,1" bitfld.long 0x10 4. "RXFFLSH,RXFFLSH" "0,1" bitfld.long 0x10 2. "FSRST,FSRST" "0,1" newline bitfld.long 0x10 1. "PSRST,PSRST" "0,1" rbitfld.long 0x10 0. "CSRST,CSRST" "0,1" line.long 0x14 "GINTSTS,This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode. while others are valid in device mode only. This register also.." bitfld.long 0x14 31. "WKUPINT,WKUPINT" "0,1" bitfld.long 0x14 30. "SRQINT,SRQINT" "0,1" bitfld.long 0x14 29. "DISCINT,DISCINT" "0,1" newline bitfld.long 0x14 28. "CIDSCHG,CIDSCHG" "0,1" bitfld.long 0x14 27. "LPMINT,LPMINT" "0,1" rbitfld.long 0x14 26. "PTXFE,PTXFE" "0,1" newline rbitfld.long 0x14 25. "HCINT,HCINT" "0,1" rbitfld.long 0x14 24. "HPRTINT,HPRTINT" "0,1" bitfld.long 0x14 23. "RSTDET,RSTDET" "0,1" newline bitfld.long 0x14 22. "DATAFSUSP,DATAFSUSP" "0,1" bitfld.long 0x14 21. "IPXFR,IPXFR" "0,1" bitfld.long 0x14 20. "IISOIXFR,IISOIXFR" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OEPINT" "0,1" rbitfld.long 0x14 18. "IEPINT,IEPINT" "0,1" bitfld.long 0x14 15. "EOPF,EOPF" "0,1" newline bitfld.long 0x14 14. "ISOODRP,ISOODRP" "0,1" bitfld.long 0x14 13. "ENUMDNE,ENUMDNE" "0,1" bitfld.long 0x14 12. "USBRST,USBRST" "0,1" newline bitfld.long 0x14 11. "USBSUSP,USBSUSP" "0,1" bitfld.long 0x14 10. "ESUSP,ESUSP" "0,1" rbitfld.long 0x14 7. "GONAKEFF,GONAKEFF" "0,1" newline rbitfld.long 0x14 6. "GINAKEFF,GINAKEFF" "0,1" rbitfld.long 0x14 5. "NPTXFE,NPTXFE" "0,1" rbitfld.long 0x14 4. "RXFLVL,RXFLVL" "0,1" newline bitfld.long 0x14 3. "SOF,SOF" "0,1" rbitfld.long 0x14 2. "OTGINT,OTGINT" "0,1" bitfld.long 0x14 1. "MMIS,MMIS" "0,1" newline rbitfld.long 0x14 0. "CMOD,CMOD" "0,1" line.long 0x18 "GINTMSK,This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked. the interrupt associated with that bit is not generated. However. the core interrupt (GINTSTS) register bit corresponding to that.." bitfld.long 0x18 31. "WUIM,WUIM" "0,1" bitfld.long 0x18 30. "SRQIM,SRQIM" "0,1" bitfld.long 0x18 29. "DISCINT,DISCINT" "0,1" newline bitfld.long 0x18 28. "CIDSCHGM,CIDSCHGM" "0,1" bitfld.long 0x18 27. "LPMINTM,LPMINTM" "0,1" bitfld.long 0x18 26. "PTXFEM,PTXFEM" "0,1" newline bitfld.long 0x18 25. "HCIM,HCIM" "0,1" bitfld.long 0x18 24. "PRTIM,PRTIM" "0,1" bitfld.long 0x18 23. "RSTDETM,RSTDETM" "0,1" newline bitfld.long 0x18 22. "FSUSPM,FSUSPM" "0,1" bitfld.long 0x18 21. "IPXFRM,IPXFRM" "0,1" bitfld.long 0x18 20. "IISOIXFRM,IISOIXFRM" "0,1" newline bitfld.long 0x18 19. "OEPINT,OEPINT" "0,1" bitfld.long 0x18 18. "IEPINT,IEPINT" "0,1" bitfld.long 0x18 15. "EOPFM,EOPFM" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,ISOODRPM" "0,1" bitfld.long 0x18 13. "ENUMDNEM,ENUMDNEM" "0,1" bitfld.long 0x18 12. "USBRST,USBRST" "0,1" newline bitfld.long 0x18 11. "USBSUSPM,USBSUSPM" "0,1" bitfld.long 0x18 10. "ESUSPM,ESUSPM" "0,1" bitfld.long 0x18 7. "GONAKEFFM,GONAKEFFM" "0,1" newline bitfld.long 0x18 6. "GINAKEFFM,GINAKEFFM" "0,1" bitfld.long 0x18 5. "NPTXFEM,NPTXFEM" "0,1" bitfld.long 0x18 4. "RXFLVLM,RXFLVLM" "0,1" newline bitfld.long 0x18 3. "SOFM,SOFM" "0,1" bitfld.long 0x18 2. "OTGINT,OTGINT" "0,1" bitfld.long 0x18 1. "MMISM,MMISM" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "GRXSTSR_DEVICE,This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and.." bitfld.long 0x0 27. "STSPHST,STSPHST" "0,1" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" newline bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,EPNUM" rgroup.long 0x1C++0x7 line.long 0x0 "GRXSTSR_HOST,This description is for register GRXSTSR in Host mode" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,CHNUM" line.long 0x4 "GRXSTSP_DEVICE,This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO. a read to GRXSTSP (receive status read and pop register).." bitfld.long 0x4 27. "STSPHST,STSPHST" "0,1" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,PKTSTS" newline bitfld.long 0x4 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,EPNUM" rgroup.long 0x20++0x3 line.long 0x0 "GRXSTSP_HOST,This description is for register GRXSTSP in HOST mode" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,CHNUM" group.long 0x24++0x7 line.long 0x0 "GRXFSIZ,The application can program the RAM size that must be allocated to the Rx FIFO." hexmask.long.word 0x0 0.--15. 1. "RXFD,RXFD" line.long 0x4 "HNPTXFSIZ,Host mode" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,NPTXFD" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,NPTXFSA" rgroup.long 0x2C++0x3 line.long 0x0 "HNPTXSTS,In device mode. this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue." hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,NPTXQTOP" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,NPTQXSAV" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,NPTXFSAV" group.long 0x38++0x7 line.long 0x0 "GCCFG,OTG general core configuration register" bitfld.long 0x0 21. "VBDEN,VBDEN" "0,1" bitfld.long 0x0 20. "SDEN,SDEN" "0,1" bitfld.long 0x0 19. "PDEN,PDEN" "0,1" newline bitfld.long 0x0 18. "DCDEN,DCDEN" "0,1" bitfld.long 0x0 17. "BCDEN,BCDEN" "0,1" bitfld.long 0x0 16. "PWRDWN,PWRDWN" "0,1" newline rbitfld.long 0x0 3. "PS2DET,PS2DET" "0,1" rbitfld.long 0x0 2. "SDET,SDET" "0,1" rbitfld.long 0x0 1. "PDET,PDET" "0,1" newline rbitfld.long 0x0 0. "DCDET,DCDET" "0,1" line.long 0x4 "CID,This is a register containing the Product ID as reset value." hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,PRODUCT_ID" group.long 0x54++0x3 line.long 0x0 "GLPMCFG,OTG core LPM configuration register" bitfld.long 0x0 28. "ENBESL,ENBESL" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPMRCNTSTS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,SNDLPM" "0,1" newline bitfld.long 0x0 21.--23. "LPMRCNT,LPMRCNT" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPMCHIDX" rbitfld.long 0x0 16. "L1RSMOK,L1RSMOK" "0,1" newline rbitfld.long 0x0 15. "SLPSTS,SLPSTS" "0,1" rbitfld.long 0x0 13.--14. "LPMRSP,LPMRSP" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1DSEN" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESLTHRS" bitfld.long 0x0 7. "L1SSEN,L1SSEN" "0,1" bitfld.long 0x0 6. "REMWAKE,REMWAKE" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "BESL,BESL" bitfld.long 0x0 1. "LPMACK,LPMACK" "0,1" bitfld.long 0x0 0. "LPMEN,LPMEN" "0,1" group.long 0x100++0x23 line.long 0x0 "HPTXFSIZ,OTG host periodic transmit FIFO size register" hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,PTXFSIZ" hexmask.long.word 0x0 0.--15. 1. "PTXSA,PTXSA" line.long 0x4 "DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x8 "DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0xC "DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x10 "DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x14 "DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x18 "DIEPTXF6,OTG device IN endpoint transmit FIFO 6 size register" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x1C "DIEPTXF7,OTG device IN endpoint transmit FIFO 7 size register" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x20 "DIEPTXF8,OTG device IN endpoint transmit FIFO 8 size register" hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,INEPTXSA" group.long 0x400++0x7 line.long 0x0 "HCFG,This register configures the core after power-on. Do not make changes to this register after initializing the host." rbitfld.long 0x0 2. "FSLSS,FSLSS" "0,1" bitfld.long 0x0 0.--1. "FSLSPCS,FSLSPCS" "0,1,2,3" line.long 0x4 "HFIR,This register stores the frame interval information for the current speed to which the OTG controller has enumerated." bitfld.long 0x4 16. "RLDCTRL,RLDCTRL" "0,1" hexmask.long.word 0x4 0.--15. 1. "FRIVL,FRIVL" rgroup.long 0x408++0x3 line.long 0x0 "HFNUM,This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame." hexmask.long.word 0x0 16.--31. 1. "FTREM,FTREM" hexmask.long.word 0x0 0.--15. 1. "FRNUM,FRNUM" rgroup.long 0x410++0x7 line.long 0x0 "HPTXSTS,This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue." hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,PTXQTOP" hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,PTXQSAV" hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,PTXFSAVL" line.long 0x4 "HAINT,When a significant event occurs on a channel. the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one.." hexmask.long.word 0x4 0.--15. 1. "HAINT,HAINT" group.long 0x418++0x3 line.long 0x0 "HAINTMSK,The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel. up to a maximum of 16 bits." hexmask.long.word 0x0 0.--15. 1. "HAINTM,HAINTM" group.long 0x440++0x3 line.long 0x0 "HPRT,This register is available only in host mode. Currently. the OTG host supports only one port. A single register holds USB port-related information such as USB reset. enable. suspend. resume. connect status. and test mode for each port. It is shown.." rbitfld.long 0x0 17.--18. "PSPD,PSPD" "0,1,2,3" hexmask.long.byte 0x0 13.--16. 1. "PTCTL,PTCTL" bitfld.long 0x0 12. "PPWR,PPWR" "0,1" newline rbitfld.long 0x0 10.--11. "PLSTS,PLSTS" "0,1,2,3" bitfld.long 0x0 8. "PRST,PRST" "0,1" bitfld.long 0x0 7. "PSUSP,PSUSP" "0,1" newline bitfld.long 0x0 6. "PRES,PRES" "0,1" bitfld.long 0x0 5. "POCCHNG,POCCHNG" "0,1" rbitfld.long 0x0 4. "POCA,POCA" "0,1" newline bitfld.long 0x0 3. "PENCHNG,PENCHNG" "0,1" bitfld.long 0x0 2. "PENA,PENA" "0,1" bitfld.long 0x0 1. "PCDET,PCDET" "0,1" newline rbitfld.long 0x0 0. "PCSTS,PCSTS" "0,1" group.long 0x500++0x7 line.long 0x0 "HCCHAR0,OTG host channel 0 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" line.long 0x4 "HCSPLT0,OTG host channel 0 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" group.long 0x524++0x3 line.long 0x0 "HCSPLT1,OTG host channel 1 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x544++0x3 line.long 0x0 "HCSPLT2,OTG host channel 2 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x564++0x3 line.long 0x0 "HCSPLT3,OTG host channel 3 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x584++0x3 line.long 0x0 "HCSPLT4,OTG host channel 4 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x5A4++0x3 line.long 0x0 "HCSPLT5,OTG host channel 5 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x5C4++0x3 line.long 0x0 "HCSPLT6,OTG host channel 6 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x5E4++0x3 line.long 0x0 "HCSPLT7,OTG host channel 7 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x604++0x3 line.long 0x0 "HCSPLT8,OTG host channel 8 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x624++0x3 line.long 0x0 "HCSPLT9,OTG host channel 9 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x644++0x3 line.long 0x0 "HCSPLT10,OTG host channel 10 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x664++0x3 line.long 0x0 "HCSPLT11,OTG host channel 11 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x684++0x3 line.long 0x0 "HCSPLT12,OTG host channel 0 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x6A4++0x3 line.long 0x0 "HCSPLT13,OTG host channel 13 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x6C4++0x3 line.long 0x0 "HCSPLT14,OTG host channel 14 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x6E4++0x3 line.long 0x0 "HCSPLT15,OTG host channel 15 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x508++0xF line.long 0x0 "HCINT0,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK0,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ0,OTG host channel 0 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0xC "HCDMA0,OTG host channel 0 DMA address register" hexmask.long 0xC 0.--31. 1. "DMAADDR,DMA address" group.long 0x534++0x3 line.long 0x0 "HCDMA1,OTG host channel 1 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x554++0x3 line.long 0x0 "HCDMA2,OTG host channel 2 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x574++0x3 line.long 0x0 "HCDMA3,OTG host channel 3 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x594++0x3 line.long 0x0 "HCDMA4,OTG host channel 4 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x5B4++0x3 line.long 0x0 "HCDMA5,OTG host channel 5 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x5D4++0x3 line.long 0x0 "HCDMA6,OTG host channel 6 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x5F4++0x3 line.long 0x0 "HCDMA7,OTG host channel 7 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x614++0x3 line.long 0x0 "HCDMA8,OTG host channel 8 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x634++0x3 line.long 0x0 "HCDMA9,OTG host channel 9 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x654++0x3 line.long 0x0 "HCDMA10,OTG host channel 10 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x674++0x3 line.long 0x0 "HCDMA11,OTG host channel 11 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x694++0x3 line.long 0x0 "HCDMA12,OTG host channel 12 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x6B4++0x3 line.long 0x0 "HCDMA13,OTG host channel 13 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x6D4++0x3 line.long 0x0 "HCDMA14,OTG host channel 14 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x6F4++0x3 line.long 0x0 "HCDMA15,OTG host channel 15 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x520++0x3 line.long 0x0 "HCCHAR1,OTG host channel 1 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x528++0xB line.long 0x0 "HCINT1_DEVICE,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK1,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ1,OTG host channel 1 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x540++0x3 line.long 0x0 "HCCHAR2,OTG host channel 2 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x548++0xB line.long 0x0 "HCINT2,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK2,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ2,OTG host channel 2 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x560++0x3 line.long 0x0 "HCCHAR3,OTG host channel 3 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x568++0xB line.long 0x0 "HCINT3,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK3,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ3,OTG host channel 3 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x580++0x3 line.long 0x0 "HCCHAR4,OTG host channel 4 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x588++0xB line.long 0x0 "HCINT4,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK4,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ4,OTG host channel 4 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5A0++0x3 line.long 0x0 "HCCHAR5,OTG host channel 5 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5A8++0xB line.long 0x0 "HCINT5,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK5,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ5,OTG host channel 5 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5C0++0x3 line.long 0x0 "HCCHAR6,OTG host channel 6 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5C8++0xB line.long 0x0 "HCINT6,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK6,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ6,OTG host channel 6 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5E0++0x3 line.long 0x0 "HCCHAR7,OTG host channel 7 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5E8++0xB line.long 0x0 "HCINT7,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK7,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ7,OTG host channel 7 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x600++0x3 line.long 0x0 "HCCHAR8,OTG host channel 8 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x608++0xB line.long 0x0 "HCINT8,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK8,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ8,OTG host channel 8 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x620++0x3 line.long 0x0 "HCCHAR9,OTG host channel 9 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x628++0xB line.long 0x0 "HCINT9,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK9,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ9,OTG host channel 9 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x640++0x3 line.long 0x0 "HCCHAR10,OTG host channel 10 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x648++0xB line.long 0x0 "HCINT10,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK10,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ10,OTG host channel 10 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x660++0x3 line.long 0x0 "HCCHAR11,OTG host channel 11 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x680++0x3 line.long 0x0 "HCCHAR12,OTG host channel 12 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x6A0++0x3 line.long 0x0 "HCCHAR13,OTG host channel 13 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x6C0++0x3 line.long 0x0 "HCCHAR14,OTG host channel 14 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x6E0++0x3 line.long 0x0 "HCCHAR15,OTG host channel 15 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x668++0x3 line.long 0x0 "HCINT11,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x688++0x3 line.long 0x0 "HCINT12,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x6A8++0x3 line.long 0x0 "HCINT13,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x6C8++0x3 line.long 0x0 "HCINT14,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x6E8++0x3 line.long 0x0 "HCINT15,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x66C++0x3 line.long 0x0 "HCINTMSK11,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x68C++0x3 line.long 0x0 "HCINTMSK12,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x6AC++0x3 line.long 0x0 "HCINTMSK13,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x6CC++0x3 line.long 0x0 "HCINTMSK14,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x6EC++0x3 line.long 0x0 "HCINTMSK15,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x670++0x3 line.long 0x0 "HCTSIZ11,OTG host channel 11 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x690++0x3 line.long 0x0 "HCTSIZ12,OTG host channel 12 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x6B0++0x3 line.long 0x0 "HCTSIZ13,OTG host channel 13 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x6D0++0x3 line.long 0x0 "HCTSIZ14,OTG host channel 14 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x6F0++0x3 line.long 0x0 "HCTSIZ15,OTG host channel 15 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x800++0x7 line.long 0x0 "DCFG,This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming." bitfld.long 0x0 15. "ERRATIM,ERRATIM" "0,1" bitfld.long 0x0 11.--12. "PFIVL,PFIVL" "0,1,2,3" hexmask.long.byte 0x0 4.--10. 1. "DAD,DAD" newline bitfld.long 0x0 2. "NZLSOHSK,NZLSOHSK" "0,1" bitfld.long 0x0 0.--1. "DSPD,DSPD" "0,1,2,3" line.long 0x4 "DCTL,OTG device control register" bitfld.long 0x4 18. "DSBESLRJCT,DSBESLRJCT" "0,1" bitfld.long 0x4 11. "POPRGDNE,POPRGDNE" "0,1" bitfld.long 0x4 10. "CGONAK,CGONAK" "0,1" newline bitfld.long 0x4 9. "SGONAK,SGONAK" "0,1" bitfld.long 0x4 8. "CGINAK,CGINAK" "0,1" bitfld.long 0x4 7. "SGINAK,SGINAK" "0,1" newline bitfld.long 0x4 4.--6. "TCTL,TCTL" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "GONSTS,GONSTS" "0,1" rbitfld.long 0x4 2. "GINSTS,GINSTS" "0,1" newline bitfld.long 0x4 1. "SDIS,SDIS" "0,1" bitfld.long 0x4 0. "RWUSIG,RWUSIG" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "DSTS,This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register." bitfld.long 0x0 22.--23. "DEVLNSTS,DEVLNSTS" "0,1,2,3" hexmask.long.word 0x0 8.--21. 1. "FNSOF,FNSOF" bitfld.long 0x0 3. "EERR,EERR" "0,1" newline bitfld.long 0x0 1.--2. "ENUMSPD,ENUMSPD" "0,1,2,3" bitfld.long 0x0 0. "SUSPSTS,SUSPSTS" "0,1" group.long 0x810++0x7 line.long 0x0 "DIEPMSK,This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this.." bitfld.long 0x0 13. "NAKM,NAKM" "0,1" bitfld.long 0x0 8. "TXFURM,TXFURM" "0,1" bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" newline bitfld.long 0x0 5. "INEPNMM,INEPNMM" "0,1" bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" bitfld.long 0x0 3. "TOM,TOM" "0,1" newline bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x0 1. "EPDM,EPDM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" line.long 0x4 "DOEPMSK,This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in.." bitfld.long 0x4 14. "NYETMSK,NYETMSK" "0,1" bitfld.long 0x4 13. "NAKMSK,NAKMSK" "0,1" bitfld.long 0x4 12. "BERRM,BERRM" "0,1" newline bitfld.long 0x4 8. "OUTPKTERRM,OUTPKTERRM" "0,1" bitfld.long 0x4 6. "B2BSTUPM,B2BSTUPM" "0,1" bitfld.long 0x4 5. "STSPHSRXM,STSPHSRXM" "0,1" newline bitfld.long 0x4 4. "OTEPDM,OTEPDM" "0,1" bitfld.long 0x4 3. "STUPM,STUPM" "0,1" bitfld.long 0x4 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x4 1. "EPDM,EPDM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" rgroup.long 0x818++0x3 line.long 0x0 "DAINT,When a significant event occurs on an endpoint. a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS. respectively). There.." hexmask.long.word 0x0 16.--31. 1. "OEPINT,OEPINT" hexmask.long.word 0x0 0.--15. 1. "IEPINT,IEPINT" group.long 0x81C++0x3 line.long 0x0 "DAINTMSK,The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However. the DAINT register bit corresponding to that interrupt is still set." hexmask.long.word 0x0 16.--31. 1. "OEPM,OEPM" hexmask.long.word 0x0 0.--15. 1. "IEPM,IEPM" group.long 0x828++0xF line.long 0x0 "DVBUSDIS,This register specifies the VBUS discharge time after VBUS pulsing during SRP." hexmask.long.word 0x0 0.--15. 1. "VBUSDT,VBUSDT" line.long 0x4 "DVBUSPULSE,This register specifies the VBUS pulsing time during SRP." hexmask.long.word 0x4 0.--15. 1. "DVBUSP,DVBUSP" line.long 0x8 "DTHRCTL,OTG device threshold control register" bitfld.long 0x8 27. "ARPEN,Arbiter parking enable" "0,1" hexmask.long.word 0x8 17.--25. 1. "RXTHRLEN,Receive threshold length" bitfld.long 0x8 16. "RXTHREN,Receive threshold enable" "0,1" newline hexmask.long.word 0x8 2.--10. 1. "TXTHRLEN,Transmit threshold length" bitfld.long 0x8 1. "ISOTHREN,ISO IN endpoint threshold enable" "0,1" bitfld.long 0x8 0. "NONISOTHREN,Nonisochronous IN endpoints threshold enable" "0,1" line.long 0xC "DIEPEMPMSK,This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx)." hexmask.long.word 0xC 0.--15. 1. "INEPTXFEM,INEPTXFEM" group.long 0x884++0x3 line.long 0x0 "HS_DOEPEACHMSK1,OTG device each OUT endpoint-1 interrupt mask register" bitfld.long 0x0 14. "NYETMSK,NYETMSK" "0,1" bitfld.long 0x0 13. "NAKMSK,NAKMSK" "0,1" bitfld.long 0x0 12. "BERRM,BERRM" "0,1" newline bitfld.long 0x0 9. "BNAM,BNAM" "0,1" bitfld.long 0x0 8. "OUTPKTERRM,OUTPKTERRM" "0,1" bitfld.long 0x0 6. "B2BSTUPM,B2BSTUPM" "0,1" newline bitfld.long 0x0 4. "OTEPDM,OTEPDM" "0,1" bitfld.long 0x0 3. "STUPM,STUPM" "0,1" bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x0 1. "EPDM,EPDM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x900++0x3 line.long 0x0 "DIEPCTL0,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline bitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" group.long 0x908++0x3 line.long 0x0 "DIEPINT0,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x910++0x3 line.long 0x0 "DIEPTSIZ0,The application must modify this register before enabling endpoint 0." bitfld.long 0x0 19.--20. "PKTCNT,PKTCNT" "0,1,2,3" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x918++0x3 line.long 0x0 "DTXFSTS0,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x920++0x3 line.long 0x0 "DIEPCTL1,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x928++0x3 line.long 0x0 "DIEPINT1,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x930++0x7 line.long 0x0 "DIEPTSIZ1,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA1,OTG device IN endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x938++0x3 line.long 0x0 "DTXFSTS1,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x940++0x3 line.long 0x0 "DIEPCTL2,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x948++0x3 line.long 0x0 "DIEPINT2,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x950++0x7 line.long 0x0 "DIEPTSIZ2,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA2,OTG device IN endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x958++0x3 line.long 0x0 "DTXFSTS2,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x960++0x3 line.long 0x0 "DIEPCTL3,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x968++0x3 line.long 0x0 "DIEPINT3,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x970++0x7 line.long 0x0 "DIEPTSIZ3,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA3,OTG device IN endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x978++0x3 line.long 0x0 "DTXFSTS3,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x980++0x3 line.long 0x0 "DIEPCTL4,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x988++0x3 line.long 0x0 "DIEPINT4,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x990++0x7 line.long 0x0 "DIEPTSIZ4,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA4,OTG device IN endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x998++0x3 line.long 0x0 "DTXFSTS4,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x9A0++0x3 line.long 0x0 "DIEPCTL5,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x9A8++0x3 line.long 0x0 "DIEPINT5,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x9B0++0x7 line.long 0x0 "DIEPTSIZ5,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA5,OTG device IN endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x9B8++0x3 line.long 0x0 "DTXFSTS5,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x9C8++0x3 line.long 0x0 "DIEPINT6,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,TXFIFOUDRN" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x9D0++0x7 line.long 0x0 "DIEPTSIZ6,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA6,OTG device IN endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0x9E8++0x3 line.long 0x0 "DIEPINT7,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,TXFIFOUDRN" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x9F0++0x7 line.long 0x0 "DIEPTSIZ7,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA7,OTG device IN endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xA08++0x3 line.long 0x0 "DIEPINT8,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,TXFIFOUDRN" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xA10++0x7 line.long 0x0 "DIEPTSIZ8,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA8,OTG device IN endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB00++0x3 line.long 0x0 "DOEPCTL0,This section describes the DOEPCTL0 register." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" rbitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" newline rbitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline rbitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" group.long 0xB08++0x3 line.long 0x0 "DOEPINT0,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB10++0x7 line.long 0x0 "DOEPTSIZ0,The application must modify this register before enabling endpoint 0." bitfld.long 0x0 29.--30. "STUPCNT,STUPCNT" "0,1,2,3" bitfld.long 0x0 19. "PKTCNT,PKTCNT" "0,1" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA0,OTG device OUT endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB20++0x3 line.long 0x0 "DOEPCTL1,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB28++0x3 line.long 0x0 "DOEPINT1,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB30++0x7 line.long 0x0 "DOEPTSIZ1,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA1,OTG device OUT endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB40++0x3 line.long 0x0 "DOEPCTL2,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB48++0x3 line.long 0x0 "DOEPINT2,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB50++0x7 line.long 0x0 "DOEPTSIZ2,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA2,OTG device OUT endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB60++0x3 line.long 0x0 "DOEPCTL3,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB68++0x3 line.long 0x0 "DOEPINT3,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB70++0x7 line.long 0x0 "DOEPTSIZ3,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA3,OTG device OUT endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB80++0x3 line.long 0x0 "DOEPCTL4,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB88++0x3 line.long 0x0 "DOEPINT4,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB90++0x7 line.long 0x0 "DOEPTSIZ4,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA4,OTG device OUT endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xBA0++0x3 line.long 0x0 "DOEPCTL5,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xBA8++0x3 line.long 0x0 "DOEPINT5,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xBB0++0x7 line.long 0x0 "DOEPTSIZ5,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA5,OTG device OUT endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xBC0++0x3 line.long 0x0 "DOEPCTL6,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xBC8++0x3 line.long 0x0 "DOEPINT6,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xBD0++0x7 line.long 0x0 "DOEPTSIZ6,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA6,OTG device OUT endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xBE0++0x3 line.long 0x0 "DOEPCTL7,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xBE8++0x3 line.long 0x0 "DOEPINT7,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xBF0++0x7 line.long 0x0 "DOEPTSIZ7,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA7,OTG device OUT endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xC00++0x3 line.long 0x0 "DOEPCTL8,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xC08++0x3 line.long 0x0 "DOEPINT8,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xC10++0x7 line.long 0x0 "DOEPTSIZ8,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA8,OTG device OUT endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xE00++0x3 line.long 0x0 "PCGCCTL,This register is available in host and device modes." rbitfld.long 0x0 7. "SUSP,SUSP" "0,1" rbitfld.long 0x0 6. "PHYSLEEP,PHYSLEEP" "0,1" bitfld.long 0x0 5. "ENL1GTG,ENL1GTG" "0,1" newline rbitfld.long 0x0 4. "PHYSUSP,PHYSUSP" "0,1" bitfld.long 0x0 1. "GATEHCLK,GATEHCLK" "0,1" bitfld.long 0x0 0. "STPPCLK,STPPCLK" "0,1" tree.end tree "SEC_OTG_HS" base ad:0x52040000 group.long 0x0++0x1B line.long 0x0 "GOTGCTL,The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core." rbitfld.long 0x0 21. "CURMOD,CURMOD" "0,1" bitfld.long 0x0 20. "OTGVER,OTGVER" "0,1" rbitfld.long 0x0 19. "BSVLD,BSVLD" "0,1" newline rbitfld.long 0x0 18. "ASVLD,ASVLD" "0,1" rbitfld.long 0x0 17. "DBCT,DBCT" "0,1" rbitfld.long 0x0 16. "CIDSTS,CIDSTS" "0,1" newline bitfld.long 0x0 12. "EHEN,EHEN" "0,1" bitfld.long 0x0 11. "DHNPEN,DHNPEN" "0,1" bitfld.long 0x0 10. "HSHNPEN,HSHNPEN" "0,1" newline bitfld.long 0x0 9. "HNPRQ,HNPRQ" "0,1" rbitfld.long 0x0 8. "HNGSCS,HNGSCS" "0,1" bitfld.long 0x0 7. "BVALOVAL,BVALOVAL" "0,1" newline bitfld.long 0x0 6. "BVALOEN,BVALOEN" "0,1" bitfld.long 0x0 5. "AVALOVAL,AVALOVAL" "0,1" bitfld.long 0x0 4. "AVALOEN,AVALOEN" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBVALOVAL" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBVALOEN" "0,1" bitfld.long 0x0 1. "SRQ,SRQ" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,SRQSCS" "0,1" line.long 0x4 "GOTGINT,The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt." bitfld.long 0x4 19. "DBCDNE,DBCDNE" "0,1" bitfld.long 0x4 18. "ADTOCHG,ADTOCHG" "0,1" bitfld.long 0x4 17. "HNGDET,HNGDET" "0,1" newline bitfld.long 0x4 9. "HNSSCHG,HNSSCHG" "0,1" bitfld.long 0x4 8. "SRSSCHG,SRSSCHG" "0,1" bitfld.long 0x4 2. "SEDET,SEDET" "0,1" line.long 0x8 "GAHBCFG,This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program.." bitfld.long 0x8 8. "PTXFELVL,PTXFELVL" "0,1" bitfld.long 0x8 7. "TXFELVL,TXFELVL" "0,1" bitfld.long 0x8 0. "GINTMSK,GINTMSK" "0,1" line.long 0xC "GUSBCFG,This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on.." bitfld.long 0xC 30. "FDMOD,FDMOD" "0,1" bitfld.long 0xC 29. "FHMOD,FHMOD" "0,1" bitfld.long 0xC 22. "TSDPS,TSDPS" "0,1" newline bitfld.long 0xC 15. "PHYLPC,PHYLPC" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,TRDT" bitfld.long 0xC 9. "HNPCAP,HNPCAP" "0,1" newline bitfld.long 0xC 8. "SRPCAP,SRPCAP" "0,1" rbitfld.long 0xC 6. "PHYSEL,PHYSEL" "0,1" bitfld.long 0xC 0.--2. "TOCAL,TOCAL" "0,1,2,3,4,5,6,7" line.long 0x10 "GRSTCTL,The application uses this register to reset various hardware features inside the core." rbitfld.long 0x10 31. "AHBIDL,AHBIDL" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMAREQ" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TXFNUM" newline bitfld.long 0x10 5. "TXFFLSH,TXFFLSH" "0,1" bitfld.long 0x10 4. "RXFFLSH,RXFFLSH" "0,1" bitfld.long 0x10 2. "FSRST,FSRST" "0,1" newline bitfld.long 0x10 1. "PSRST,PSRST" "0,1" rbitfld.long 0x10 0. "CSRST,CSRST" "0,1" line.long 0x14 "GINTSTS,This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode. while others are valid in device mode only. This register also.." bitfld.long 0x14 31. "WKUPINT,WKUPINT" "0,1" bitfld.long 0x14 30. "SRQINT,SRQINT" "0,1" bitfld.long 0x14 29. "DISCINT,DISCINT" "0,1" newline bitfld.long 0x14 28. "CIDSCHG,CIDSCHG" "0,1" bitfld.long 0x14 27. "LPMINT,LPMINT" "0,1" rbitfld.long 0x14 26. "PTXFE,PTXFE" "0,1" newline rbitfld.long 0x14 25. "HCINT,HCINT" "0,1" rbitfld.long 0x14 24. "HPRTINT,HPRTINT" "0,1" bitfld.long 0x14 23. "RSTDET,RSTDET" "0,1" newline bitfld.long 0x14 22. "DATAFSUSP,DATAFSUSP" "0,1" bitfld.long 0x14 21. "IPXFR,IPXFR" "0,1" bitfld.long 0x14 20. "IISOIXFR,IISOIXFR" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OEPINT" "0,1" rbitfld.long 0x14 18. "IEPINT,IEPINT" "0,1" bitfld.long 0x14 15. "EOPF,EOPF" "0,1" newline bitfld.long 0x14 14. "ISOODRP,ISOODRP" "0,1" bitfld.long 0x14 13. "ENUMDNE,ENUMDNE" "0,1" bitfld.long 0x14 12. "USBRST,USBRST" "0,1" newline bitfld.long 0x14 11. "USBSUSP,USBSUSP" "0,1" bitfld.long 0x14 10. "ESUSP,ESUSP" "0,1" rbitfld.long 0x14 7. "GONAKEFF,GONAKEFF" "0,1" newline rbitfld.long 0x14 6. "GINAKEFF,GINAKEFF" "0,1" rbitfld.long 0x14 5. "NPTXFE,NPTXFE" "0,1" rbitfld.long 0x14 4. "RXFLVL,RXFLVL" "0,1" newline bitfld.long 0x14 3. "SOF,SOF" "0,1" rbitfld.long 0x14 2. "OTGINT,OTGINT" "0,1" bitfld.long 0x14 1. "MMIS,MMIS" "0,1" newline rbitfld.long 0x14 0. "CMOD,CMOD" "0,1" line.long 0x18 "GINTMSK,This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked. the interrupt associated with that bit is not generated. However. the core interrupt (GINTSTS) register bit corresponding to that.." bitfld.long 0x18 31. "WUIM,WUIM" "0,1" bitfld.long 0x18 30. "SRQIM,SRQIM" "0,1" bitfld.long 0x18 29. "DISCINT,DISCINT" "0,1" newline bitfld.long 0x18 28. "CIDSCHGM,CIDSCHGM" "0,1" bitfld.long 0x18 27. "LPMINTM,LPMINTM" "0,1" bitfld.long 0x18 26. "PTXFEM,PTXFEM" "0,1" newline bitfld.long 0x18 25. "HCIM,HCIM" "0,1" bitfld.long 0x18 24. "PRTIM,PRTIM" "0,1" bitfld.long 0x18 23. "RSTDETM,RSTDETM" "0,1" newline bitfld.long 0x18 22. "FSUSPM,FSUSPM" "0,1" bitfld.long 0x18 21. "IPXFRM,IPXFRM" "0,1" bitfld.long 0x18 20. "IISOIXFRM,IISOIXFRM" "0,1" newline bitfld.long 0x18 19. "OEPINT,OEPINT" "0,1" bitfld.long 0x18 18. "IEPINT,IEPINT" "0,1" bitfld.long 0x18 15. "EOPFM,EOPFM" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,ISOODRPM" "0,1" bitfld.long 0x18 13. "ENUMDNEM,ENUMDNEM" "0,1" bitfld.long 0x18 12. "USBRST,USBRST" "0,1" newline bitfld.long 0x18 11. "USBSUSPM,USBSUSPM" "0,1" bitfld.long 0x18 10. "ESUSPM,ESUSPM" "0,1" bitfld.long 0x18 7. "GONAKEFFM,GONAKEFFM" "0,1" newline bitfld.long 0x18 6. "GINAKEFFM,GINAKEFFM" "0,1" bitfld.long 0x18 5. "NPTXFEM,NPTXFEM" "0,1" bitfld.long 0x18 4. "RXFLVLM,RXFLVLM" "0,1" newline bitfld.long 0x18 3. "SOFM,SOFM" "0,1" bitfld.long 0x18 2. "OTGINT,OTGINT" "0,1" bitfld.long 0x18 1. "MMISM,MMISM" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "GRXSTSR_DEVICE,This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and.." bitfld.long 0x0 27. "STSPHST,STSPHST" "0,1" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" newline bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,EPNUM" rgroup.long 0x1C++0x7 line.long 0x0 "GRXSTSR_HOST,This description is for register GRXSTSR in Host mode" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,CHNUM" line.long 0x4 "GRXSTSP_DEVICE,This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO. a read to GRXSTSP (receive status read and pop register).." bitfld.long 0x4 27. "STSPHST,STSPHST" "0,1" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,PKTSTS" newline bitfld.long 0x4 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,EPNUM" rgroup.long 0x20++0x3 line.long 0x0 "GRXSTSP_HOST,This description is for register GRXSTSP in HOST mode" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x0 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,CHNUM" group.long 0x24++0x7 line.long 0x0 "GRXFSIZ,The application can program the RAM size that must be allocated to the Rx FIFO." hexmask.long.word 0x0 0.--15. 1. "RXFD,RXFD" line.long 0x4 "HNPTXFSIZ,Host mode" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,NPTXFD" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,NPTXFSA" rgroup.long 0x2C++0x3 line.long 0x0 "HNPTXSTS,In device mode. this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue." hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,NPTXQTOP" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,NPTQXSAV" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,NPTXFSAV" group.long 0x38++0x7 line.long 0x0 "GCCFG,OTG general core configuration register" bitfld.long 0x0 21. "VBDEN,VBDEN" "0,1" bitfld.long 0x0 20. "SDEN,SDEN" "0,1" bitfld.long 0x0 19. "PDEN,PDEN" "0,1" newline bitfld.long 0x0 18. "DCDEN,DCDEN" "0,1" bitfld.long 0x0 17. "BCDEN,BCDEN" "0,1" bitfld.long 0x0 16. "PWRDWN,PWRDWN" "0,1" newline rbitfld.long 0x0 3. "PS2DET,PS2DET" "0,1" rbitfld.long 0x0 2. "SDET,SDET" "0,1" rbitfld.long 0x0 1. "PDET,PDET" "0,1" newline rbitfld.long 0x0 0. "DCDET,DCDET" "0,1" line.long 0x4 "CID,This is a register containing the Product ID as reset value." hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,PRODUCT_ID" group.long 0x54++0x3 line.long 0x0 "GLPMCFG,OTG core LPM configuration register" bitfld.long 0x0 28. "ENBESL,ENBESL" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPMRCNTSTS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,SNDLPM" "0,1" newline bitfld.long 0x0 21.--23. "LPMRCNT,LPMRCNT" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPMCHIDX" rbitfld.long 0x0 16. "L1RSMOK,L1RSMOK" "0,1" newline rbitfld.long 0x0 15. "SLPSTS,SLPSTS" "0,1" rbitfld.long 0x0 13.--14. "LPMRSP,LPMRSP" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1DSEN" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESLTHRS" bitfld.long 0x0 7. "L1SSEN,L1SSEN" "0,1" bitfld.long 0x0 6. "REMWAKE,REMWAKE" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "BESL,BESL" bitfld.long 0x0 1. "LPMACK,LPMACK" "0,1" bitfld.long 0x0 0. "LPMEN,LPMEN" "0,1" group.long 0x100++0x23 line.long 0x0 "HPTXFSIZ,OTG host periodic transmit FIFO size register" hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,PTXFSIZ" hexmask.long.word 0x0 0.--15. 1. "PTXSA,PTXSA" line.long 0x4 "DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x8 "DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0xC "DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x10 "DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x14 "DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x18 "DIEPTXF6,OTG device IN endpoint transmit FIFO 6 size register" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x1C "DIEPTXF7,OTG device IN endpoint transmit FIFO 7 size register" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,INEPTXSA" line.long 0x20 "DIEPTXF8,OTG device IN endpoint transmit FIFO 8 size register" hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,INEPTXFD" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,INEPTXSA" group.long 0x400++0x7 line.long 0x0 "HCFG,This register configures the core after power-on. Do not make changes to this register after initializing the host." rbitfld.long 0x0 2. "FSLSS,FSLSS" "0,1" bitfld.long 0x0 0.--1. "FSLSPCS,FSLSPCS" "0,1,2,3" line.long 0x4 "HFIR,This register stores the frame interval information for the current speed to which the OTG controller has enumerated." bitfld.long 0x4 16. "RLDCTRL,RLDCTRL" "0,1" hexmask.long.word 0x4 0.--15. 1. "FRIVL,FRIVL" rgroup.long 0x408++0x3 line.long 0x0 "HFNUM,This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame." hexmask.long.word 0x0 16.--31. 1. "FTREM,FTREM" hexmask.long.word 0x0 0.--15. 1. "FRNUM,FRNUM" rgroup.long 0x410++0x7 line.long 0x0 "HPTXSTS,This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue." hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,PTXQTOP" hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,PTXQSAV" hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,PTXFSAVL" line.long 0x4 "HAINT,When a significant event occurs on a channel. the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one.." hexmask.long.word 0x4 0.--15. 1. "HAINT,HAINT" group.long 0x418++0x3 line.long 0x0 "HAINTMSK,The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel. up to a maximum of 16 bits." hexmask.long.word 0x0 0.--15. 1. "HAINTM,HAINTM" group.long 0x440++0x3 line.long 0x0 "HPRT,This register is available only in host mode. Currently. the OTG host supports only one port. A single register holds USB port-related information such as USB reset. enable. suspend. resume. connect status. and test mode for each port. It is shown.." rbitfld.long 0x0 17.--18. "PSPD,PSPD" "0,1,2,3" hexmask.long.byte 0x0 13.--16. 1. "PTCTL,PTCTL" bitfld.long 0x0 12. "PPWR,PPWR" "0,1" newline rbitfld.long 0x0 10.--11. "PLSTS,PLSTS" "0,1,2,3" bitfld.long 0x0 8. "PRST,PRST" "0,1" bitfld.long 0x0 7. "PSUSP,PSUSP" "0,1" newline bitfld.long 0x0 6. "PRES,PRES" "0,1" bitfld.long 0x0 5. "POCCHNG,POCCHNG" "0,1" rbitfld.long 0x0 4. "POCA,POCA" "0,1" newline bitfld.long 0x0 3. "PENCHNG,PENCHNG" "0,1" bitfld.long 0x0 2. "PENA,PENA" "0,1" bitfld.long 0x0 1. "PCDET,PCDET" "0,1" newline rbitfld.long 0x0 0. "PCSTS,PCSTS" "0,1" group.long 0x500++0x7 line.long 0x0 "HCCHAR0,OTG host channel 0 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" line.long 0x4 "HCSPLT0,OTG host channel 0 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" group.long 0x524++0x3 line.long 0x0 "HCSPLT1,OTG host channel 1 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x544++0x3 line.long 0x0 "HCSPLT2,OTG host channel 2 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x564++0x3 line.long 0x0 "HCSPLT3,OTG host channel 3 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x584++0x3 line.long 0x0 "HCSPLT4,OTG host channel 4 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x5A4++0x3 line.long 0x0 "HCSPLT5,OTG host channel 5 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x5C4++0x3 line.long 0x0 "HCSPLT6,OTG host channel 6 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x5E4++0x3 line.long 0x0 "HCSPLT7,OTG host channel 7 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x604++0x3 line.long 0x0 "HCSPLT8,OTG host channel 8 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x624++0x3 line.long 0x0 "HCSPLT9,OTG host channel 9 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x644++0x3 line.long 0x0 "HCSPLT10,OTG host channel 10 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x664++0x3 line.long 0x0 "HCSPLT11,OTG host channel 11 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x684++0x3 line.long 0x0 "HCSPLT12,OTG host channel 0 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x6A4++0x3 line.long 0x0 "HCSPLT13,OTG host channel 13 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x6C4++0x3 line.long 0x0 "HCSPLT14,OTG host channel 14 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x6E4++0x3 line.long 0x0 "HCSPLT15,OTG host channel 15 split control register" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x508++0xF line.long 0x0 "HCINT0,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK0,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ0,OTG host channel 0 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0xC "HCDMA0,OTG host channel 0 DMA address register" hexmask.long 0xC 0.--31. 1. "DMAADDR,DMA address" group.long 0x534++0x3 line.long 0x0 "HCDMA1,OTG host channel 1 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x554++0x3 line.long 0x0 "HCDMA2,OTG host channel 2 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x574++0x3 line.long 0x0 "HCDMA3,OTG host channel 3 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x594++0x3 line.long 0x0 "HCDMA4,OTG host channel 4 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x5B4++0x3 line.long 0x0 "HCDMA5,OTG host channel 5 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x5D4++0x3 line.long 0x0 "HCDMA6,OTG host channel 6 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x5F4++0x3 line.long 0x0 "HCDMA7,OTG host channel 7 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x614++0x3 line.long 0x0 "HCDMA8,OTG host channel 8 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x634++0x3 line.long 0x0 "HCDMA9,OTG host channel 9 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x654++0x3 line.long 0x0 "HCDMA10,OTG host channel 10 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x674++0x3 line.long 0x0 "HCDMA11,OTG host channel 11 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x694++0x3 line.long 0x0 "HCDMA12,OTG host channel 12 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x6B4++0x3 line.long 0x0 "HCDMA13,OTG host channel 13 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x6D4++0x3 line.long 0x0 "HCDMA14,OTG host channel 14 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x6F4++0x3 line.long 0x0 "HCDMA15,OTG host channel 15 DMA address register" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x520++0x3 line.long 0x0 "HCCHAR1,OTG host channel 1 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x528++0xB line.long 0x0 "HCINT1_DEVICE,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK1,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ1,OTG host channel 1 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x540++0x3 line.long 0x0 "HCCHAR2,OTG host channel 2 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x548++0xB line.long 0x0 "HCINT2,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK2,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ2,OTG host channel 2 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x560++0x3 line.long 0x0 "HCCHAR3,OTG host channel 3 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x568++0xB line.long 0x0 "HCINT3,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK3,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ3,OTG host channel 3 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x580++0x3 line.long 0x0 "HCCHAR4,OTG host channel 4 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x588++0xB line.long 0x0 "HCINT4,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK4,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ4,OTG host channel 4 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5A0++0x3 line.long 0x0 "HCCHAR5,OTG host channel 5 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5A8++0xB line.long 0x0 "HCINT5,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK5,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ5,OTG host channel 5 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5C0++0x3 line.long 0x0 "HCCHAR6,OTG host channel 6 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5C8++0xB line.long 0x0 "HCINT6,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK6,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ6,OTG host channel 6 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x5E0++0x3 line.long 0x0 "HCCHAR7,OTG host channel 7 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x5E8++0xB line.long 0x0 "HCINT7,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK7,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ7,OTG host channel 7 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x600++0x3 line.long 0x0 "HCCHAR8,OTG host channel 8 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x608++0xB line.long 0x0 "HCINT8,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK8,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ8,OTG host channel 8 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x620++0x3 line.long 0x0 "HCCHAR9,OTG host channel 9 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x628++0xB line.long 0x0 "HCINT9,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK9,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ9,OTG host channel 9 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x640++0x3 line.long 0x0 "HCCHAR10,OTG host channel 10 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x648++0xB line.long 0x0 "HCINT10,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" line.long 0x4 "HCINTMSK10,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x4 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x4 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x4 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x4 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x4 5. "ACKM,ACKM" "0,1" bitfld.long 0x4 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x4 3. "STALLM,STALLM" "0,1" bitfld.long 0x4 1. "CHHM,CHHM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" line.long 0x8 "HCTSIZ10,OTG host channel 10 transfer size register" bitfld.long 0x8 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x8 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x660++0x3 line.long 0x0 "HCCHAR11,OTG host channel 11 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x680++0x3 line.long 0x0 "HCCHAR12,OTG host channel 12 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x6A0++0x3 line.long 0x0 "HCCHAR13,OTG host channel 13 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x6C0++0x3 line.long 0x0 "HCCHAR14,OTG host channel 14 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x6E0++0x3 line.long 0x0 "HCCHAR15,OTG host channel 15 characteristics register" bitfld.long 0x0 31. "CHENA,CHENA" "0,1" bitfld.long 0x0 30. "CHDIS,CHDIS" "0,1" bitfld.long 0x0 29. "ODDFRM,ODDFRM" "0,1" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,DAD" bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline bitfld.long 0x0 17. "LSDEV,LSDEV" "0,1" bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,EPNUM" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x668++0x3 line.long 0x0 "HCINT11,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x688++0x3 line.long 0x0 "HCINT12,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x6A8++0x3 line.long 0x0 "HCINT13,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x6C8++0x3 line.long 0x0 "HCINT14,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x6E8++0x3 line.long 0x0 "HCINT15,This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in.." bitfld.long 0x0 10. "DTERR,DTERR" "0,1" bitfld.long 0x0 9. "FRMOR,FRMOR" "0,1" bitfld.long 0x0 8. "BBERR,BBERR" "0,1" newline bitfld.long 0x0 7. "TXERR,TXERR" "0,1" bitfld.long 0x0 5. "ACK,ACK" "0,1" bitfld.long 0x0 4. "NAK,NAK" "0,1" newline bitfld.long 0x0 3. "STALL,STALL" "0,1" bitfld.long 0x0 1. "CHH,CHH" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x66C++0x3 line.long 0x0 "HCINTMSK11,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x68C++0x3 line.long 0x0 "HCINTMSK12,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x6AC++0x3 line.long 0x0 "HCINTMSK13,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x6CC++0x3 line.long 0x0 "HCINTMSK14,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x6EC++0x3 line.long 0x0 "HCINTMSK15,This register reflects the mask for each channel status described in the previous section." bitfld.long 0x0 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x0 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x0 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x0 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x0 5. "ACKM,ACKM" "0,1" bitfld.long 0x0 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x0 3. "STALLM,STALLM" "0,1" bitfld.long 0x0 1. "CHHM,CHHM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x670++0x3 line.long 0x0 "HCTSIZ11,OTG host channel 11 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x690++0x3 line.long 0x0 "HCTSIZ12,OTG host channel 12 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x6B0++0x3 line.long 0x0 "HCTSIZ13,OTG host channel 13 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x6D0++0x3 line.long 0x0 "HCTSIZ14,OTG host channel 14 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x6F0++0x3 line.long 0x0 "HCTSIZ15,OTG host channel 15 transfer size register" bitfld.long 0x0 31. "DOPNG,DOPNG" "0,1" bitfld.long 0x0 29.--30. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" group.long 0x800++0x7 line.long 0x0 "DCFG,This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming." bitfld.long 0x0 15. "ERRATIM,ERRATIM" "0,1" bitfld.long 0x0 11.--12. "PFIVL,PFIVL" "0,1,2,3" hexmask.long.byte 0x0 4.--10. 1. "DAD,DAD" newline bitfld.long 0x0 2. "NZLSOHSK,NZLSOHSK" "0,1" bitfld.long 0x0 0.--1. "DSPD,DSPD" "0,1,2,3" line.long 0x4 "DCTL,OTG device control register" bitfld.long 0x4 18. "DSBESLRJCT,DSBESLRJCT" "0,1" bitfld.long 0x4 11. "POPRGDNE,POPRGDNE" "0,1" bitfld.long 0x4 10. "CGONAK,CGONAK" "0,1" newline bitfld.long 0x4 9. "SGONAK,SGONAK" "0,1" bitfld.long 0x4 8. "CGINAK,CGINAK" "0,1" bitfld.long 0x4 7. "SGINAK,SGINAK" "0,1" newline bitfld.long 0x4 4.--6. "TCTL,TCTL" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "GONSTS,GONSTS" "0,1" rbitfld.long 0x4 2. "GINSTS,GINSTS" "0,1" newline bitfld.long 0x4 1. "SDIS,SDIS" "0,1" bitfld.long 0x4 0. "RWUSIG,RWUSIG" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "DSTS,This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register." bitfld.long 0x0 22.--23. "DEVLNSTS,DEVLNSTS" "0,1,2,3" hexmask.long.word 0x0 8.--21. 1. "FNSOF,FNSOF" bitfld.long 0x0 3. "EERR,EERR" "0,1" newline bitfld.long 0x0 1.--2. "ENUMSPD,ENUMSPD" "0,1,2,3" bitfld.long 0x0 0. "SUSPSTS,SUSPSTS" "0,1" group.long 0x810++0x7 line.long 0x0 "DIEPMSK,This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this.." bitfld.long 0x0 13. "NAKM,NAKM" "0,1" bitfld.long 0x0 8. "TXFURM,TXFURM" "0,1" bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" newline bitfld.long 0x0 5. "INEPNMM,INEPNMM" "0,1" bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" bitfld.long 0x0 3. "TOM,TOM" "0,1" newline bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x0 1. "EPDM,EPDM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" line.long 0x4 "DOEPMSK,This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in.." bitfld.long 0x4 14. "NYETMSK,NYETMSK" "0,1" bitfld.long 0x4 13. "NAKMSK,NAKMSK" "0,1" bitfld.long 0x4 12. "BERRM,BERRM" "0,1" newline bitfld.long 0x4 8. "OUTPKTERRM,OUTPKTERRM" "0,1" bitfld.long 0x4 6. "B2BSTUPM,B2BSTUPM" "0,1" bitfld.long 0x4 5. "STSPHSRXM,STSPHSRXM" "0,1" newline bitfld.long 0x4 4. "OTEPDM,OTEPDM" "0,1" bitfld.long 0x4 3. "STUPM,STUPM" "0,1" bitfld.long 0x4 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x4 1. "EPDM,EPDM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" rgroup.long 0x818++0x3 line.long 0x0 "DAINT,When a significant event occurs on an endpoint. a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS. respectively). There.." hexmask.long.word 0x0 16.--31. 1. "OEPINT,OEPINT" hexmask.long.word 0x0 0.--15. 1. "IEPINT,IEPINT" group.long 0x81C++0x3 line.long 0x0 "DAINTMSK,The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However. the DAINT register bit corresponding to that interrupt is still set." hexmask.long.word 0x0 16.--31. 1. "OEPM,OEPM" hexmask.long.word 0x0 0.--15. 1. "IEPM,IEPM" group.long 0x828++0xF line.long 0x0 "DVBUSDIS,This register specifies the VBUS discharge time after VBUS pulsing during SRP." hexmask.long.word 0x0 0.--15. 1. "VBUSDT,VBUSDT" line.long 0x4 "DVBUSPULSE,This register specifies the VBUS pulsing time during SRP." hexmask.long.word 0x4 0.--15. 1. "DVBUSP,DVBUSP" line.long 0x8 "DTHRCTL,OTG device threshold control register" bitfld.long 0x8 27. "ARPEN,Arbiter parking enable" "0,1" hexmask.long.word 0x8 17.--25. 1. "RXTHRLEN,Receive threshold length" bitfld.long 0x8 16. "RXTHREN,Receive threshold enable" "0,1" newline hexmask.long.word 0x8 2.--10. 1. "TXTHRLEN,Transmit threshold length" bitfld.long 0x8 1. "ISOTHREN,ISO IN endpoint threshold enable" "0,1" bitfld.long 0x8 0. "NONISOTHREN,Nonisochronous IN endpoints threshold enable" "0,1" line.long 0xC "DIEPEMPMSK,This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx)." hexmask.long.word 0xC 0.--15. 1. "INEPTXFEM,INEPTXFEM" group.long 0x884++0x3 line.long 0x0 "HS_DOEPEACHMSK1,OTG device each OUT endpoint-1 interrupt mask register" bitfld.long 0x0 14. "NYETMSK,NYETMSK" "0,1" bitfld.long 0x0 13. "NAKMSK,NAKMSK" "0,1" bitfld.long 0x0 12. "BERRM,BERRM" "0,1" newline bitfld.long 0x0 9. "BNAM,BNAM" "0,1" bitfld.long 0x0 8. "OUTPKTERRM,OUTPKTERRM" "0,1" bitfld.long 0x0 6. "B2BSTUPM,B2BSTUPM" "0,1" newline bitfld.long 0x0 4. "OTEPDM,OTEPDM" "0,1" bitfld.long 0x0 3. "STUPM,STUPM" "0,1" bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x0 1. "EPDM,EPDM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x900++0x3 line.long 0x0 "DIEPCTL0,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline bitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" group.long 0x908++0x3 line.long 0x0 "DIEPINT0,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x910++0x3 line.long 0x0 "DIEPTSIZ0,The application must modify this register before enabling endpoint 0." bitfld.long 0x0 19.--20. "PKTCNT,PKTCNT" "0,1,2,3" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,XFRSIZ" rgroup.long 0x918++0x3 line.long 0x0 "DTXFSTS0,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x920++0x3 line.long 0x0 "DIEPCTL1,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x928++0x3 line.long 0x0 "DIEPINT1,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x930++0x7 line.long 0x0 "DIEPTSIZ1,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA1,OTG device IN endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x938++0x3 line.long 0x0 "DTXFSTS1,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x940++0x3 line.long 0x0 "DIEPCTL2,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x948++0x3 line.long 0x0 "DIEPINT2,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x950++0x7 line.long 0x0 "DIEPTSIZ2,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA2,OTG device IN endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x958++0x3 line.long 0x0 "DTXFSTS2,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x960++0x3 line.long 0x0 "DIEPCTL3,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x968++0x3 line.long 0x0 "DIEPINT3,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x970++0x7 line.long 0x0 "DIEPTSIZ3,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA3,OTG device IN endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x978++0x3 line.long 0x0 "DTXFSTS3,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x980++0x3 line.long 0x0 "DIEPCTL4,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x988++0x3 line.long 0x0 "DIEPINT4,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x990++0x7 line.long 0x0 "DIEPTSIZ4,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA4,OTG device IN endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x998++0x3 line.long 0x0 "DTXFSTS4,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x9A0++0x3 line.long 0x0 "DIEPCTL5,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SODDFRM,SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TXFNUM" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0x9A8++0x3 line.long 0x0 "DIEPINT5,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" newline rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" newline bitfld.long 0x0 3. "TOC,TOC" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x9B0++0x7 line.long 0x0 "DIEPTSIZ5,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA5,OTG device IN endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" rgroup.long 0x9B8++0x3 line.long 0x0 "DTXFSTS5,This read-only register contains the free space information for the device IN endpoint Tx FIFO." hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,INEPTFSAV" group.long 0x9C8++0x3 line.long 0x0 "DIEPINT6,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,TXFIFOUDRN" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x9D0++0x7 line.long 0x0 "DIEPTSIZ6,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA6,OTG device IN endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0x9E8++0x3 line.long 0x0 "DIEPINT7,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,TXFIFOUDRN" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0x9F0++0x7 line.long 0x0 "DIEPTSIZ7,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA7,OTG device IN endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xA08++0x3 line.long 0x0 "DIEPINT8,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in.." bitfld.long 0x0 13. "NAK,NAK" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,PKTDRPSTS" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,TXFIFOUDRN" "0,1" rbitfld.long 0x0 7. "TXFE,TXFE" "0,1" rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline bitfld.long 0x0 5. "INEPNM,INEPNM" "0,1" bitfld.long 0x0 4. "ITTXFE,ITTXFE" "0,1" bitfld.long 0x0 3. "TOC,TOC" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xA10++0x7 line.long 0x0 "DIEPTSIZ8,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DIEPDMA8,OTG device IN endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB00++0x3 line.long 0x0 "DOEPCTL0,This section describes the DOEPCTL0 register." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" rbitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" newline bitfld.long 0x0 26. "CNAK,CNAK" "0,1" bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" newline rbitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline rbitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" group.long 0xB08++0x3 line.long 0x0 "DOEPINT0,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB10++0x7 line.long 0x0 "DOEPTSIZ0,The application must modify this register before enabling endpoint 0." bitfld.long 0x0 29.--30. "STUPCNT,STUPCNT" "0,1,2,3" bitfld.long 0x0 19. "PKTCNT,PKTCNT" "0,1" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA0,OTG device OUT endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB20++0x3 line.long 0x0 "DOEPCTL1,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB28++0x3 line.long 0x0 "DOEPINT1,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB30++0x7 line.long 0x0 "DOEPTSIZ1,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA1,OTG device OUT endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB40++0x3 line.long 0x0 "DOEPCTL2,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB48++0x3 line.long 0x0 "DOEPINT2,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB50++0x7 line.long 0x0 "DOEPTSIZ2,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA2,OTG device OUT endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB60++0x3 line.long 0x0 "DOEPCTL3,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB68++0x3 line.long 0x0 "DOEPINT3,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB70++0x7 line.long 0x0 "DOEPTSIZ3,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA3,OTG device OUT endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xB80++0x3 line.long 0x0 "DOEPCTL4,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xB88++0x3 line.long 0x0 "DOEPINT4,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xB90++0x7 line.long 0x0 "DOEPTSIZ4,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA4,OTG device OUT endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xBA0++0x3 line.long 0x0 "DOEPCTL5,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xBA8++0x3 line.long 0x0 "DOEPINT5,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xBB0++0x7 line.long 0x0 "DOEPTSIZ5,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA5,OTG device OUT endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xBC0++0x3 line.long 0x0 "DOEPCTL6,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xBC8++0x3 line.long 0x0 "DOEPINT6,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xBD0++0x7 line.long 0x0 "DOEPTSIZ6,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA6,OTG device OUT endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xBE0++0x3 line.long 0x0 "DOEPCTL7,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xBE8++0x3 line.long 0x0 "DOEPINT7,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xBF0++0x7 line.long 0x0 "DOEPTSIZ7,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA7,OTG device OUT endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xC00++0x3 line.long 0x0 "DOEPCTL8,The application uses this register to control the behavior of each logical endpoint other than endpoint 0." bitfld.long 0x0 31. "EPENA,EPENA" "0,1" bitfld.long 0x0 30. "EPDIS,EPDIS" "0,1" bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" bitfld.long 0x0 27. "SNAK,SNAK" "0,1" bitfld.long 0x0 26. "CNAK,CNAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL" "0,1" bitfld.long 0x0 20. "SNPM,SNPM" "0,1" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" bitfld.long 0x0 15. "USBAEP,USBAEP" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,MPSIZ" group.long 0xC08++0x3 line.long 0x0 "DOEPINT8,This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS).." bitfld.long 0x0 15. "STPKTRX,STPKTRX" "0,1" bitfld.long 0x0 14. "NYET,NYET" "0,1" bitfld.long 0x0 13. "NAK,NAK" "0,1" newline bitfld.long 0x0 12. "BERR,BERR" "0,1" bitfld.long 0x0 9. "BNA,BNA" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUTPKTERR" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,B2BSTUP" "0,1" bitfld.long 0x0 5. "STSPHSRX,STSPHSRX" "0,1" bitfld.long 0x0 4. "OTEPDIS,OTEPDIS" "0,1" newline bitfld.long 0x0 3. "STUP,STUP" "0,1" bitfld.long 0x0 2. "AHBERR,AHBERR" "0,1" bitfld.long 0x0 1. "EPDISD,EPDISD" "0,1" newline bitfld.long 0x0 0. "XFRC,XFRC" "0,1" group.long 0xC10++0x7 line.long 0x0 "DOEPTSIZ8,The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx). the core modifies this register. The application can only read.." bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,PKTCNT" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,XFRSIZ" line.long 0x4 "DOEPDMA8,OTG device OUT endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMAADDR" group.long 0xE00++0x3 line.long 0x0 "PCGCCTL,This register is available in host and device modes." rbitfld.long 0x0 7. "SUSP,SUSP" "0,1" rbitfld.long 0x0 6. "PHYSLEEP,PHYSLEEP" "0,1" bitfld.long 0x0 5. "ENL1GTG,ENL1GTG" "0,1" newline rbitfld.long 0x0 4. "PHYSUSP,PHYSUSP" "0,1" bitfld.long 0x0 1. "GATEHCLK,GATEHCLK" "0,1" bitfld.long 0x0 0. "STPPCLK,STPPCLK" "0,1" tree.end tree.end endif sif (cpuis("STM32U545*")||cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U5A5*")||cpuis("STM32U5A9*")||cpuis("STM32U5G*")) tree "PKA (Private Key Accelerator)" base ad:0x0 tree "PKA" base ad:0x420C2000 group.long 0x0++0x3 line.long 0x0 "CR,Control register" bitfld.long 0x0 21. "OPERRIE,Operation error interrupt enable" "0,1" bitfld.long 0x0 20. "ADDRERRIE,Address error interrupt" "0,1" bitfld.long 0x0 19. "RAMERRIE,RAM error interrupt enable" "0,1" bitfld.long 0x0 17. "PROCENDIE,End of operation interrupt" "0,1" hexmask.long.byte 0x0 8.--13. 1. "MODE,PKA Operation Mode" bitfld.long 0x0 1. "START,Start the operation" "0,1" bitfld.long 0x0 0. "EN,Peripheral Enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,PKA status register" bitfld.long 0x0 21. "OPERRF,OPERRF" "0,1" bitfld.long 0x0 20. "ADDRERRF,ADDRERRF" "0,1" bitfld.long 0x0 19. "RAMERRF,RAMERRF" "0,1" bitfld.long 0x0 17. "PROCENDF,PKA End of Operation flag" "0,1" bitfld.long 0x0 16. "BUSY,PKA operation is in" "0,1" bitfld.long 0x0 0. "INITOK,INITOK" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "CLRFR,PKA clear flag register" bitfld.long 0x0 21. "OPERRFC,OPERRFC" "0,1" bitfld.long 0x0 20. "ADDRERRFC,ADDRERRFC" "0,1" bitfld.long 0x0 19. "RAMERRFC,RAMERRFC" "0,1" bitfld.long 0x0 17. "PROCENDFC,Clear PKA End of Operation" "0,1" tree.end tree "SEC_PKA" base ad:0x520C2000 group.long 0x0++0x3 line.long 0x0 "CR,Control register" bitfld.long 0x0 21. "OPERRIE,Operation error interrupt enable" "0,1" bitfld.long 0x0 20. "ADDRERRIE,Address error interrupt" "0,1" bitfld.long 0x0 19. "RAMERRIE,RAM error interrupt enable" "0,1" bitfld.long 0x0 17. "PROCENDIE,End of operation interrupt" "0,1" hexmask.long.byte 0x0 8.--13. 1. "MODE,PKA Operation Mode" bitfld.long 0x0 1. "START,Start the operation" "0,1" bitfld.long 0x0 0. "EN,Peripheral Enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,PKA status register" bitfld.long 0x0 21. "OPERRF,OPERRF" "0,1" bitfld.long 0x0 20. "ADDRERRF,ADDRERRF" "0,1" bitfld.long 0x0 19. "RAMERRF,RAMERRF" "0,1" bitfld.long 0x0 17. "PROCENDF,PKA End of Operation flag" "0,1" bitfld.long 0x0 16. "BUSY,PKA operation is in" "0,1" bitfld.long 0x0 0. "INITOK,INITOK" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "CLRFR,PKA clear flag register" bitfld.long 0x0 21. "OPERRFC,OPERRFC" "0,1" bitfld.long 0x0 20. "ADDRERRFC,ADDRERRFC" "0,1" bitfld.long 0x0 19. "RAMERRFC,RAMERRFC" "0,1" bitfld.long 0x0 17. "PROCENDFC,Clear PKA End of Operation" "0,1" tree.end tree.end endif tree "PSSI (Parallel Synchronous Slave Interface)" base ad:0x0 tree "PSSI" base ad:0x4202C400 group.long 0x0++0x3 line.long 0x0 "CR,PSSI control register" bitfld.long 0x0 31. "OUTEN,Data direction selection bit" "0,1" bitfld.long 0x0 30. "DMAEN,DMA enable bit" "0,1" bitfld.long 0x0 18.--20. "DERDYCFG,Data enable and ready configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x0 14. "ENABLE,PSSI enable" "0,1" bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0,1,2,3" bitfld.long 0x0 8. "RDYPOL,Ready (PSSI_RDY) polarity" "0,1" bitfld.long 0x0 6. "DEPOL,Data enable (PSSI_DE) polarity" "0,1" bitfld.long 0x0 5. "CKPOL,Parallel data clock polarity" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "SR,PSSI status register" bitfld.long 0x0 3. "RTT1B,RTT1B" "0,1" bitfld.long 0x0 2. "RTT4B,RTT4B" "0,1" line.long 0x4 "RIS,PSSI raw interrupt status register" bitfld.long 0x4 1. "OVR_RIS,OVR_RIS" "0,1" group.long 0xC++0x3 line.long 0x0 "IER,PSSI interrupt enable register" bitfld.long 0x0 1. "OVR_IE,OVR_IE" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MIS,PSSI masked interrupt status register" bitfld.long 0x0 1. "OVR_MIS,OVR_MIS" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "ICR,PSSI interrupt clear register" bitfld.long 0x0 1. "OVR_ISC,OVR_ISC" "0,1" group.long 0x28++0x3 line.long 0x0 "DR,PSSI data register" hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0" tree.end tree "SEC_PSSI" base ad:0x5202C400 group.long 0x0++0x3 line.long 0x0 "CR,PSSI control register" bitfld.long 0x0 31. "OUTEN,Data direction selection bit" "0,1" bitfld.long 0x0 30. "DMAEN,DMA enable bit" "0,1" bitfld.long 0x0 18.--20. "DERDYCFG,Data enable and ready configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x0 14. "ENABLE,PSSI enable" "0,1" bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0,1,2,3" bitfld.long 0x0 8. "RDYPOL,Ready (PSSI_RDY) polarity" "0,1" bitfld.long 0x0 6. "DEPOL,Data enable (PSSI_DE) polarity" "0,1" bitfld.long 0x0 5. "CKPOL,Parallel data clock polarity" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "SR,PSSI status register" bitfld.long 0x0 3. "RTT1B,RTT1B" "0,1" bitfld.long 0x0 2. "RTT4B,RTT4B" "0,1" line.long 0x4 "RIS,PSSI raw interrupt status register" bitfld.long 0x4 1. "OVR_RIS,OVR_RIS" "0,1" group.long 0xC++0x3 line.long 0x0 "IER,PSSI interrupt enable register" bitfld.long 0x0 1. "OVR_IE,OVR_IE" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MIS,PSSI masked interrupt status register" bitfld.long 0x0 1. "OVR_MIS,OVR_MIS" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "ICR,PSSI interrupt clear register" bitfld.long 0x0 1. "OVR_ISC,OVR_ISC" "0,1" group.long 0x28++0x3 line.long 0x0 "DR,PSSI data register" hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0" tree.end tree.end tree "PWR (Power Control)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "PWR" base ad:0x46020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" newline bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." newline bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." sif (cpuis("STM32U545*")) bitfld.long 0x4 12. "PKARAMPDS,PKA32 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" endif newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" newline bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" newline bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" newline bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" newline bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 8. "SRAM1PDS12," "0,1" newline bitfld.long 0x0 7. "SRAM1PDS11," "0,1" bitfld.long 0x0 6. "SRAM1PDS10," "0,1" newline bitfld.long 0x0 5. "SRAM1PDS9," "0,1" bitfld.long 0x0 4. "SRAM1PDS8," "0,1" newline bitfld.long 0x0 3. "SRAM1PDS7," "0,1" bitfld.long 0x0 2. "SRAM1PDS6," "0,1" newline bitfld.long 0x0 1. "SRAM1PDS5," "0,1" bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "SEC_PWR" base ad:0x56020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" newline bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." newline bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." sif (cpuis("STM32U545*")) bitfld.long 0x4 12. "PKARAMPDS,PKA32 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" endif newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" newline bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" newline bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" newline bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" newline bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 8. "SRAM1PDS12," "0,1" newline bitfld.long 0x0 7. "SRAM1PDS11," "0,1" bitfld.long 0x0 6. "SRAM1PDS10," "0,1" newline bitfld.long 0x0 5. "SRAM1PDS9," "0,1" bitfld.long 0x0 4. "SRAM1PDS8," "0,1" newline bitfld.long 0x0 3. "SRAM1PDS7," "0,1" bitfld.long 0x0 2. "SRAM1PDS6," "0,1" newline bitfld.long 0x0 1. "SRAM1PDS5," "0,1" bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end endif sif (cpuis("STM32U575*")) tree "PWR" base ad:0x46020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" newline bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" newline bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." newline bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA SRAM power-down" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR," bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x4B line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13,Port A pull-up bit" "0,1" newline bitfld.long 0x4 12. "PU12,Port A pull-up bit" "0,1" bitfld.long 0x4 11. "PU11,Port A pull-up bit" "0,1" newline bitfld.long 0x4 10. "PU10,Port A pull-up bit" "0,1" bitfld.long 0x4 9. "PU9,Port A pull-up bit" "0,1" newline bitfld.long 0x4 8. "PU8,Port A pull-up bit" "0,1" bitfld.long 0x4 7. "PU7,Port A pull-up bit" "0,1" newline bitfld.long 0x4 6. "PU6,Port A pull-up bit" "0,1" bitfld.long 0x4 5. "PU5,Port A pull-up bit" "0,1" newline bitfld.long 0x4 4. "PU4,Port A pull-up bit" "0,1" bitfld.long 0x4 3. "PU3,Port A pull-up bit" "0,1" newline bitfld.long 0x4 2. "PU2,Port A pull-up bit" "0,1" bitfld.long 0x4 1. "PU1,Port A pull-up bit" "0,1" newline bitfld.long 0x4 0. "PU0,Port A pull-up bit" "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit" "0,1" bitfld.long 0x8 12. "PD12,Port A pull-down bit" "0,1" newline bitfld.long 0x8 11. "PD11,Port A pull-down bit" "0,1" bitfld.long 0x8 10. "PD10,Port A pull-down bit" "0,1" newline bitfld.long 0x8 9. "PD9,Port A pull-down bit" "0,1" bitfld.long 0x8 8. "PD8,Port A pull-down bit" "0,1" newline bitfld.long 0x8 7. "PD7,Port A pull-down bit" "0,1" bitfld.long 0x8 6. "PD6,Port A pull-down bit" "0,1" newline bitfld.long 0x8 5. "PD5,Port A pull-down bit" "0,1" bitfld.long 0x8 4. "PD4,Port A pull-down bit" "0,1" newline bitfld.long 0x8 3. "PD3,Port A pull-down bit" "0,1" bitfld.long 0x8 2. "PD2,Port A pull-down bit" "0,1" newline bitfld.long 0x8 1. "PD1,Port A pull-down bit" "0,1" bitfld.long 0x8 0. "PD0,Port A pull-down bit" "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15,Port B pull-up bit" "0,1" bitfld.long 0xC 14. "PU14,Port B pull-up bit" "0,1" newline bitfld.long 0xC 13. "PU13,Port B pull-up bit" "0,1" bitfld.long 0xC 12. "PU12,Port B pull-up bit" "0,1" newline bitfld.long 0xC 11. "PU11,Port B pull-up bit" "0,1" bitfld.long 0xC 10. "PU10,Port B pull-up bit" "0,1" newline bitfld.long 0xC 9. "PU9,Port B pull-up bit" "0,1" bitfld.long 0xC 8. "PU8,Port B pull-up bit" "0,1" newline bitfld.long 0xC 7. "PU7,Port B pull-up bit" "0,1" bitfld.long 0xC 6. "PU6,Port B pull-up bit" "0,1" newline bitfld.long 0xC 5. "PU5,Port B pull-up bit" "0,1" bitfld.long 0xC 4. "PU4,Port B pull-up bit" "0,1" newline bitfld.long 0xC 3. "PU3,Port B pull-up bit" "0,1" bitfld.long 0xC 2. "PU2,Port B pull-up bit" "0,1" newline bitfld.long 0xC 1. "PU1,Port B pull-up bit" "0,1" bitfld.long 0xC 0. "PU0,Port B pull-up bit" "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15,Port B pull-down bit" "0,1" bitfld.long 0x10 14. "PD14,Port B pull-down bit" "0,1" newline bitfld.long 0x10 13. "PD13,Port B pull-down bit" "0,1" bitfld.long 0x10 12. "PD12,Port B pull-down bit" "0,1" newline bitfld.long 0x10 11. "PD11,Port B pull-down bit" "0,1" bitfld.long 0x10 10. "PD10,Port B pull-down bit" "0,1" newline bitfld.long 0x10 9. "PD9,Port B pull-down bit" "0,1" bitfld.long 0x10 8. "PD8,Port B pull-down bit" "0,1" newline bitfld.long 0x10 7. "PD7,Port B pull-down bit" "0,1" bitfld.long 0x10 6. "PD6,Port B pull-down bit" "0,1" newline bitfld.long 0x10 5. "PD5,Port B pull-down bit" "0,1" bitfld.long 0x10 3. "PD3,Port B pull-down bit" "0,1" newline bitfld.long 0x10 2. "PD2,Port B pull-down bit" "0,1" bitfld.long 0x10 1. "PD1,Port B pull-down bit" "0,1" newline bitfld.long 0x10 0. "PD0,Port B pull-down bit" "0,1" line.long 0x14 "PWR_PUCRC,PWR port C pull-up control register" bitfld.long 0x14 15. "PU15,Port C pull-up bit" "0,1" bitfld.long 0x14 14. "PU14,Port C pull-up bit" "0,1" newline bitfld.long 0x14 13. "PU13,Port C pull-up bit" "0,1" bitfld.long 0x14 12. "PU12,Port C pull-up bit" "0,1" newline bitfld.long 0x14 11. "PU11,Port C pull-up bit" "0,1" bitfld.long 0x14 10. "PU10,Port C pull-up bit" "0,1" newline bitfld.long 0x14 9. "PU9,Port C pull-up bit" "0,1" bitfld.long 0x14 8. "PU8,Port C pull-up bit" "0,1" newline bitfld.long 0x14 7. "PU7,Port C pull-up bit" "0,1" bitfld.long 0x14 6. "PU6,Port C pull-up bit" "0,1" newline bitfld.long 0x14 5. "PU5,Port C pull-up bit" "0,1" bitfld.long 0x14 4. "PU4,Port C pull-up bit" "0,1" newline bitfld.long 0x14 3. "PU3,Port C pull-up bit" "0,1" bitfld.long 0x14 2. "PU2,Port C pull-up bit" "0,1" newline bitfld.long 0x14 1. "PU1,Port C pull-up bit" "0,1" bitfld.long 0x14 0. "PU0,Port C pull-up bit" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15,Port C pull-down bit" "0,1" bitfld.long 0x18 14. "PD14,Port C pull-down bit" "0,1" newline bitfld.long 0x18 13. "PD13,Port C pull-down bit" "0,1" bitfld.long 0x18 12. "PD12,Port C pull-down bit" "0,1" newline bitfld.long 0x18 11. "PD11,Port C pull-down bit" "0,1" bitfld.long 0x18 10. "PD10,Port C pull-down bit" "0,1" newline bitfld.long 0x18 9. "PD9,Port C pull-down bit" "0,1" bitfld.long 0x18 8. "PD8,Port C pull-down bit" "0,1" newline bitfld.long 0x18 7. "PD7,Port C pull-down bit" "0,1" bitfld.long 0x18 6. "PD6,Port C pull-down bit" "0,1" newline bitfld.long 0x18 5. "PD5,Port C pull-down bit" "0,1" bitfld.long 0x18 4. "PD4,Port C pull-down bit" "0,1" newline bitfld.long 0x18 3. "PD3,Port C pull-down bit" "0,1" bitfld.long 0x18 2. "PD2,Port C pull-down bit" "0,1" newline bitfld.long 0x18 1. "PD1,Port C pull-down bit" "0,1" bitfld.long 0x18 0. "PD0,Port C pull-down bit" "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15,Port D pull-up bit" "0,1" bitfld.long 0x1C 14. "PU14,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 13. "PU13,Port D pull-up bit" "0,1" bitfld.long 0x1C 12. "PU12,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 11. "PU11,Port D pull-up bit" "0,1" bitfld.long 0x1C 10. "PU10,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 9. "PU9,Port D pull-up bit" "0,1" bitfld.long 0x1C 8. "PU8,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 7. "PU7,Port D pull-up bit" "0,1" bitfld.long 0x1C 6. "PU6,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 5. "PU5,Port D pull-up bit" "0,1" bitfld.long 0x1C 4. "PU4,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 3. "PU3,Port D pull-up bit" "0,1" bitfld.long 0x1C 2. "PU2,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 1. "PU1,Port D pull-up bit" "0,1" bitfld.long 0x1C 0. "PU0,Port D pull-up bit" "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15,Port D pull-down bit" "0,1" bitfld.long 0x20 14. "PD14,Port D pull-down bit" "0,1" newline bitfld.long 0x20 13. "PD13,Port D pull-down bit" "0,1" bitfld.long 0x20 12. "PD12,Port D pull-down bit" "0,1" newline bitfld.long 0x20 11. "PD11,Port D pull-down bit" "0,1" bitfld.long 0x20 10. "PD10,Port D pull-down bit" "0,1" newline bitfld.long 0x20 9. "PD9,Port D pull-down bit" "0,1" bitfld.long 0x20 8. "PD8,Port D pull-down bit" "0,1" newline bitfld.long 0x20 7. "PD7,Port D pull-down bit" "0,1" bitfld.long 0x20 6. "PD6,Port D pull-down bit" "0,1" newline bitfld.long 0x20 5. "PD5,Port D pull-down bit" "0,1" bitfld.long 0x20 4. "PD4,Port D pull-down bit" "0,1" newline bitfld.long 0x20 3. "PD3,Port D pull-down bit" "0,1" bitfld.long 0x20 2. "PD2,Port D pull-down bit" "0,1" newline bitfld.long 0x20 1. "PD1,Port D pull-down bit" "0,1" bitfld.long 0x20 0. "PD0,Port D pull-down bit" "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15,Port E pull-up bit" "0,1" bitfld.long 0x24 14. "PU14,Port E pull-up bit" "0,1" newline bitfld.long 0x24 13. "PU13,Port E pull-up bit" "0,1" bitfld.long 0x24 12. "PU12,Port E pull-up bit" "0,1" newline bitfld.long 0x24 11. "PU11,Port E pull-up bit" "0,1" bitfld.long 0x24 10. "PU10,Port E pull-up bit" "0,1" newline bitfld.long 0x24 9. "PU9,Port E pull-up bit" "0,1" bitfld.long 0x24 8. "PU8,Port E pull-up bit" "0,1" newline bitfld.long 0x24 7. "PU7,Port E pull-up bit" "0,1" bitfld.long 0x24 6. "PU6,Port E pull-up bit" "0,1" newline bitfld.long 0x24 5. "PU5,Port E pull-up bit" "0,1" bitfld.long 0x24 4. "PU4,Port E pull-up bit" "0,1" newline bitfld.long 0x24 3. "PU3,Port E pull-up bit" "0,1" bitfld.long 0x24 2. "PU2,Port E pull-up bit" "0,1" newline bitfld.long 0x24 1. "PU1,Port E pull-up bit" "0,1" bitfld.long 0x24 0. "PU0,Port E pull-up bit" "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15,Port E pull-down bit" "0,1" bitfld.long 0x28 14. "PD14,Port E pull-down bit" "0,1" newline bitfld.long 0x28 13. "PD13,Port E pull-down bit" "0,1" bitfld.long 0x28 12. "PD12,Port E pull-down bit" "0,1" newline bitfld.long 0x28 11. "PD11,Port E pull-down bit" "0,1" bitfld.long 0x28 10. "PD10,Port E pull-down bit" "0,1" newline bitfld.long 0x28 9. "PD9,Port E pull-down bit" "0,1" bitfld.long 0x28 8. "PD8,Port E pull-down bit" "0,1" newline bitfld.long 0x28 7. "PD7,Port E pull-down bit" "0,1" bitfld.long 0x28 6. "PD6,Port E pull-down bit" "0,1" newline bitfld.long 0x28 5. "PD5,Port E pull-down bit" "0,1" bitfld.long 0x28 4. "PD4,Port E pull-down bit" "0,1" newline bitfld.long 0x28 3. "PD3,Port E pull-down bit" "0,1" bitfld.long 0x28 2. "PD2,Port E pull-down bit" "0,1" newline bitfld.long 0x28 1. "PD1,Port E pull-down bit" "0,1" bitfld.long 0x28 0. "PD0,Port E pull-down bit" "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15,Port F pull-up bit" "0,1" bitfld.long 0x2C 14. "PU14,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 13. "PU13,Port F pull-up bit" "0,1" bitfld.long 0x2C 12. "PU12,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 11. "PU11,Port F pull-up bit" "0,1" bitfld.long 0x2C 10. "PU10,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 9. "PU9,Port F pull-up bit" "0,1" bitfld.long 0x2C 8. "PU8,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 7. "PU7,Port F pull-up bit" "0,1" bitfld.long 0x2C 6. "PU6,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 5. "PU5,Port F pull-up bit" "0,1" bitfld.long 0x2C 4. "PU4,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 3. "PU3,Port F pull-up bit" "0,1" bitfld.long 0x2C 2. "PU2,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 1. "PU1,Port F pull-up bit" "0,1" bitfld.long 0x2C 0. "PU0,Port F pull-up bit" "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15,Port F pull-down bit" "0,1" bitfld.long 0x30 14. "PD14,Port F pull-down bit" "0,1" newline bitfld.long 0x30 13. "PD13,Port F pull-down bit" "0,1" bitfld.long 0x30 12. "PD12,Port F pull-down bit" "0,1" newline bitfld.long 0x30 11. "PD11,Port F pull-down bit" "0,1" bitfld.long 0x30 10. "PD10,Port F pull-down bit" "0,1" newline bitfld.long 0x30 9. "PD9,Port F pull-down bit" "0,1" bitfld.long 0x30 8. "PD8,Port F pull-down bit" "0,1" newline bitfld.long 0x30 7. "PD7,Port F pull-down bit" "0,1" bitfld.long 0x30 6. "PD6,Port F pull-down bit" "0,1" newline bitfld.long 0x30 5. "PD5,Port F pull-down bit" "0,1" bitfld.long 0x30 4. "PD4,Port F pull-down bit" "0,1" newline bitfld.long 0x30 3. "PD3,Port F pull-down bit" "0,1" bitfld.long 0x30 2. "PD2,Port F pull-down bit" "0,1" newline bitfld.long 0x30 1. "PD1,Port F pull-down bit" "0,1" bitfld.long 0x30 0. "PD0,Port F pull-down bit" "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15,Port G pull-up bit" "0,1" bitfld.long 0x34 14. "PU14,Port G pull-up bit" "0,1" newline bitfld.long 0x34 13. "PU13,Port G pull-up bit" "0,1" bitfld.long 0x34 12. "PU12,Port G pull-up bit" "0,1" newline bitfld.long 0x34 11. "PU11,Port G pull-up bit" "0,1" bitfld.long 0x34 10. "PU10,Port G pull-up bit" "0,1" newline bitfld.long 0x34 9. "PU9,Port G pull-up bit" "0,1" bitfld.long 0x34 8. "PU8,Port G pull-up bit" "0,1" newline bitfld.long 0x34 7. "PU7,Port G pull-up bit" "0,1" bitfld.long 0x34 6. "PU6,Port G pull-up bit" "0,1" newline bitfld.long 0x34 5. "PU5,Port G pull-up bit" "0,1" bitfld.long 0x34 4. "PU4,Port G pull-up bit" "0,1" newline bitfld.long 0x34 3. "PU3,Port G pull-up bit" "0,1" bitfld.long 0x34 2. "PU2,Port G pull-up bit" "0,1" newline bitfld.long 0x34 1. "PU1,Port G pull-up bit" "0,1" bitfld.long 0x34 0. "PU0,Port G pull-up bit" "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15,Port G pull-down bit" "0,1" bitfld.long 0x38 14. "PD14,Port G pull-down bit" "0,1" newline bitfld.long 0x38 13. "PD13,Port G pull-down bit" "0,1" bitfld.long 0x38 12. "PD12,Port G pull-down bit" "0,1" newline bitfld.long 0x38 11. "PD11,Port G pull-down bit" "0,1" bitfld.long 0x38 10. "PD10,Port G pull-down bit" "0,1" newline bitfld.long 0x38 9. "PD9,Port G pull-down bit" "0,1" bitfld.long 0x38 8. "PD8,Port G pull-down bit" "0,1" newline bitfld.long 0x38 7. "PD7,Port G pull-down bit" "0,1" bitfld.long 0x38 6. "PD6,Port G pull-down bit" "0,1" newline bitfld.long 0x38 5. "PD5,Port G pull-down bit" "0,1" bitfld.long 0x38 4. "PD4,Port G pull-down bit" "0,1" newline bitfld.long 0x38 3. "PD3,Port G pull-down bit" "0,1" bitfld.long 0x38 2. "PD2,Port G pull-down bit" "0,1" newline bitfld.long 0x38 1. "PD1,Port G pull-down bit" "0,1" bitfld.long 0x38 0. "PD0,Port G pull-down bit" "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15,Port H pull-up bit" "0,1" bitfld.long 0x3C 14. "PU14,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 13. "PU13,Port H pull-up bit" "0,1" bitfld.long 0x3C 12. "PU12,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 11. "PU11,Port H pull-up bit" "0,1" bitfld.long 0x3C 10. "PU10,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 9. "PU9,Port H pull-up bit" "0,1" bitfld.long 0x3C 8. "PU8,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 7. "PU7,Port H pull-up bit" "0,1" bitfld.long 0x3C 6. "PU6,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 5. "PU5,Port H pull-up bit" "0,1" bitfld.long 0x3C 4. "PU4,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 3. "PU3,Port H pull-up bit" "0,1" bitfld.long 0x3C 2. "PU2,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 1. "PU1,Port H pull-up bit" "0,1" bitfld.long 0x3C 0. "PU0,Port H pull-up bit" "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15,Port H pull-down bit" "0,1" bitfld.long 0x40 14. "PD14,Port H pull-down bit" "0,1" newline bitfld.long 0x40 13. "PD13,Port H pull-down bit" "0,1" bitfld.long 0x40 12. "PD12,Port H pull-down bit" "0,1" newline bitfld.long 0x40 11. "PD11,Port H pull-down bit" "0,1" bitfld.long 0x40 10. "PD10,Port H pull-down bit" "0,1" newline bitfld.long 0x40 9. "PD9,Port H pull-down bit" "0,1" bitfld.long 0x40 8. "PD8,Port H pull-down bit" "0,1" newline bitfld.long 0x40 7. "PD7,Port H pull-down bit" "0,1" bitfld.long 0x40 6. "PD6,Port H pull-down bit" "0,1" newline bitfld.long 0x40 5. "PD5,Port H pull-down bit" "0,1" bitfld.long 0x40 4. "PD4,Port H pull-down bit" "0,1" newline bitfld.long 0x40 3. "PD3,Port H pull-down bit" "0,1" bitfld.long 0x40 2. "PD2,Port H pull-down bit" "0,1" newline bitfld.long 0x40 1. "PD1,Port H pull-down bit" "0,1" bitfld.long 0x40 0. "PD0,Port H pull-down bit" "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 7. "PU7,Port I pull-up bit" "0,1" bitfld.long 0x44 6. "PU6,Port I pull-up bit" "0,1" newline bitfld.long 0x44 5. "PU5,Port I pull-up bit" "0,1" bitfld.long 0x44 4. "PU4,Port I pull-up bit" "0,1" newline bitfld.long 0x44 3. "PU3,Port I pull-up bit" "0,1" bitfld.long 0x44 2. "PU2,Port I pull-up bit" "0,1" newline bitfld.long 0x44 1. "PU1,Port I pull-up bit" "0,1" bitfld.long 0x44 0. "PU0,Port I pull-up bit" "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 7. "PD7,Port I pull-down bit" "0,1" bitfld.long 0x48 6. "PD6,Port I pull-down bit" "0,1" newline bitfld.long 0x48 5. "PD5,Port I pull-down bit" "0,1" bitfld.long 0x48 4. "PD4,Port I pull-down bit" "0,1" newline bitfld.long 0x48 3. "PD3,Port I pull-down bit" "0,1" bitfld.long 0x48 2. "PD2,Port I pull-down bit" "0,1" newline bitfld.long 0x48 1. "PD1,Port I pull-down bit" "0,1" bitfld.long 0x48 0. "PD0,Port I pull-down bit" "0,1" tree.end tree "SEC_PWR" base ad:0x56020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" newline bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" newline bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." newline bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA SRAM power-down" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR," bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x4B line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13,Port A pull-up bit" "0,1" newline bitfld.long 0x4 12. "PU12,Port A pull-up bit" "0,1" bitfld.long 0x4 11. "PU11,Port A pull-up bit" "0,1" newline bitfld.long 0x4 10. "PU10,Port A pull-up bit" "0,1" bitfld.long 0x4 9. "PU9,Port A pull-up bit" "0,1" newline bitfld.long 0x4 8. "PU8,Port A pull-up bit" "0,1" bitfld.long 0x4 7. "PU7,Port A pull-up bit" "0,1" newline bitfld.long 0x4 6. "PU6,Port A pull-up bit" "0,1" bitfld.long 0x4 5. "PU5,Port A pull-up bit" "0,1" newline bitfld.long 0x4 4. "PU4,Port A pull-up bit" "0,1" bitfld.long 0x4 3. "PU3,Port A pull-up bit" "0,1" newline bitfld.long 0x4 2. "PU2,Port A pull-up bit" "0,1" bitfld.long 0x4 1. "PU1,Port A pull-up bit" "0,1" newline bitfld.long 0x4 0. "PU0,Port A pull-up bit" "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit" "0,1" bitfld.long 0x8 12. "PD12,Port A pull-down bit" "0,1" newline bitfld.long 0x8 11. "PD11,Port A pull-down bit" "0,1" bitfld.long 0x8 10. "PD10,Port A pull-down bit" "0,1" newline bitfld.long 0x8 9. "PD9,Port A pull-down bit" "0,1" bitfld.long 0x8 8. "PD8,Port A pull-down bit" "0,1" newline bitfld.long 0x8 7. "PD7,Port A pull-down bit" "0,1" bitfld.long 0x8 6. "PD6,Port A pull-down bit" "0,1" newline bitfld.long 0x8 5. "PD5,Port A pull-down bit" "0,1" bitfld.long 0x8 4. "PD4,Port A pull-down bit" "0,1" newline bitfld.long 0x8 3. "PD3,Port A pull-down bit" "0,1" bitfld.long 0x8 2. "PD2,Port A pull-down bit" "0,1" newline bitfld.long 0x8 1. "PD1,Port A pull-down bit" "0,1" bitfld.long 0x8 0. "PD0,Port A pull-down bit" "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15,Port B pull-up bit" "0,1" bitfld.long 0xC 14. "PU14,Port B pull-up bit" "0,1" newline bitfld.long 0xC 13. "PU13,Port B pull-up bit" "0,1" bitfld.long 0xC 12. "PU12,Port B pull-up bit" "0,1" newline bitfld.long 0xC 11. "PU11,Port B pull-up bit" "0,1" bitfld.long 0xC 10. "PU10,Port B pull-up bit" "0,1" newline bitfld.long 0xC 9. "PU9,Port B pull-up bit" "0,1" bitfld.long 0xC 8. "PU8,Port B pull-up bit" "0,1" newline bitfld.long 0xC 7. "PU7,Port B pull-up bit" "0,1" bitfld.long 0xC 6. "PU6,Port B pull-up bit" "0,1" newline bitfld.long 0xC 5. "PU5,Port B pull-up bit" "0,1" bitfld.long 0xC 4. "PU4,Port B pull-up bit" "0,1" newline bitfld.long 0xC 3. "PU3,Port B pull-up bit" "0,1" bitfld.long 0xC 2. "PU2,Port B pull-up bit" "0,1" newline bitfld.long 0xC 1. "PU1,Port B pull-up bit" "0,1" bitfld.long 0xC 0. "PU0,Port B pull-up bit" "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15,Port B pull-down bit" "0,1" bitfld.long 0x10 14. "PD14,Port B pull-down bit" "0,1" newline bitfld.long 0x10 13. "PD13,Port B pull-down bit" "0,1" bitfld.long 0x10 12. "PD12,Port B pull-down bit" "0,1" newline bitfld.long 0x10 11. "PD11,Port B pull-down bit" "0,1" bitfld.long 0x10 10. "PD10,Port B pull-down bit" "0,1" newline bitfld.long 0x10 9. "PD9,Port B pull-down bit" "0,1" bitfld.long 0x10 8. "PD8,Port B pull-down bit" "0,1" newline bitfld.long 0x10 7. "PD7,Port B pull-down bit" "0,1" bitfld.long 0x10 6. "PD6,Port B pull-down bit" "0,1" newline bitfld.long 0x10 5. "PD5,Port B pull-down bit" "0,1" bitfld.long 0x10 3. "PD3,Port B pull-down bit" "0,1" newline bitfld.long 0x10 2. "PD2,Port B pull-down bit" "0,1" bitfld.long 0x10 1. "PD1,Port B pull-down bit" "0,1" newline bitfld.long 0x10 0. "PD0,Port B pull-down bit" "0,1" line.long 0x14 "PWR_PUCRC,PWR port C pull-up control register" bitfld.long 0x14 15. "PU15,Port C pull-up bit" "0,1" bitfld.long 0x14 14. "PU14,Port C pull-up bit" "0,1" newline bitfld.long 0x14 13. "PU13,Port C pull-up bit" "0,1" bitfld.long 0x14 12. "PU12,Port C pull-up bit" "0,1" newline bitfld.long 0x14 11. "PU11,Port C pull-up bit" "0,1" bitfld.long 0x14 10. "PU10,Port C pull-up bit" "0,1" newline bitfld.long 0x14 9. "PU9,Port C pull-up bit" "0,1" bitfld.long 0x14 8. "PU8,Port C pull-up bit" "0,1" newline bitfld.long 0x14 7. "PU7,Port C pull-up bit" "0,1" bitfld.long 0x14 6. "PU6,Port C pull-up bit" "0,1" newline bitfld.long 0x14 5. "PU5,Port C pull-up bit" "0,1" bitfld.long 0x14 4. "PU4,Port C pull-up bit" "0,1" newline bitfld.long 0x14 3. "PU3,Port C pull-up bit" "0,1" bitfld.long 0x14 2. "PU2,Port C pull-up bit" "0,1" newline bitfld.long 0x14 1. "PU1,Port C pull-up bit" "0,1" bitfld.long 0x14 0. "PU0,Port C pull-up bit" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15,Port C pull-down bit" "0,1" bitfld.long 0x18 14. "PD14,Port C pull-down bit" "0,1" newline bitfld.long 0x18 13. "PD13,Port C pull-down bit" "0,1" bitfld.long 0x18 12. "PD12,Port C pull-down bit" "0,1" newline bitfld.long 0x18 11. "PD11,Port C pull-down bit" "0,1" bitfld.long 0x18 10. "PD10,Port C pull-down bit" "0,1" newline bitfld.long 0x18 9. "PD9,Port C pull-down bit" "0,1" bitfld.long 0x18 8. "PD8,Port C pull-down bit" "0,1" newline bitfld.long 0x18 7. "PD7,Port C pull-down bit" "0,1" bitfld.long 0x18 6. "PD6,Port C pull-down bit" "0,1" newline bitfld.long 0x18 5. "PD5,Port C pull-down bit" "0,1" bitfld.long 0x18 4. "PD4,Port C pull-down bit" "0,1" newline bitfld.long 0x18 3. "PD3,Port C pull-down bit" "0,1" bitfld.long 0x18 2. "PD2,Port C pull-down bit" "0,1" newline bitfld.long 0x18 1. "PD1,Port C pull-down bit" "0,1" bitfld.long 0x18 0. "PD0,Port C pull-down bit" "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15,Port D pull-up bit" "0,1" bitfld.long 0x1C 14. "PU14,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 13. "PU13,Port D pull-up bit" "0,1" bitfld.long 0x1C 12. "PU12,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 11. "PU11,Port D pull-up bit" "0,1" bitfld.long 0x1C 10. "PU10,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 9. "PU9,Port D pull-up bit" "0,1" bitfld.long 0x1C 8. "PU8,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 7. "PU7,Port D pull-up bit" "0,1" bitfld.long 0x1C 6. "PU6,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 5. "PU5,Port D pull-up bit" "0,1" bitfld.long 0x1C 4. "PU4,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 3. "PU3,Port D pull-up bit" "0,1" bitfld.long 0x1C 2. "PU2,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 1. "PU1,Port D pull-up bit" "0,1" bitfld.long 0x1C 0. "PU0,Port D pull-up bit" "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15,Port D pull-down bit" "0,1" bitfld.long 0x20 14. "PD14,Port D pull-down bit" "0,1" newline bitfld.long 0x20 13. "PD13,Port D pull-down bit" "0,1" bitfld.long 0x20 12. "PD12,Port D pull-down bit" "0,1" newline bitfld.long 0x20 11. "PD11,Port D pull-down bit" "0,1" bitfld.long 0x20 10. "PD10,Port D pull-down bit" "0,1" newline bitfld.long 0x20 9. "PD9,Port D pull-down bit" "0,1" bitfld.long 0x20 8. "PD8,Port D pull-down bit" "0,1" newline bitfld.long 0x20 7. "PD7,Port D pull-down bit" "0,1" bitfld.long 0x20 6. "PD6,Port D pull-down bit" "0,1" newline bitfld.long 0x20 5. "PD5,Port D pull-down bit" "0,1" bitfld.long 0x20 4. "PD4,Port D pull-down bit" "0,1" newline bitfld.long 0x20 3. "PD3,Port D pull-down bit" "0,1" bitfld.long 0x20 2. "PD2,Port D pull-down bit" "0,1" newline bitfld.long 0x20 1. "PD1,Port D pull-down bit" "0,1" bitfld.long 0x20 0. "PD0,Port D pull-down bit" "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15,Port E pull-up bit" "0,1" bitfld.long 0x24 14. "PU14,Port E pull-up bit" "0,1" newline bitfld.long 0x24 13. "PU13,Port E pull-up bit" "0,1" bitfld.long 0x24 12. "PU12,Port E pull-up bit" "0,1" newline bitfld.long 0x24 11. "PU11,Port E pull-up bit" "0,1" bitfld.long 0x24 10. "PU10,Port E pull-up bit" "0,1" newline bitfld.long 0x24 9. "PU9,Port E pull-up bit" "0,1" bitfld.long 0x24 8. "PU8,Port E pull-up bit" "0,1" newline bitfld.long 0x24 7. "PU7,Port E pull-up bit" "0,1" bitfld.long 0x24 6. "PU6,Port E pull-up bit" "0,1" newline bitfld.long 0x24 5. "PU5,Port E pull-up bit" "0,1" bitfld.long 0x24 4. "PU4,Port E pull-up bit" "0,1" newline bitfld.long 0x24 3. "PU3,Port E pull-up bit" "0,1" bitfld.long 0x24 2. "PU2,Port E pull-up bit" "0,1" newline bitfld.long 0x24 1. "PU1,Port E pull-up bit" "0,1" bitfld.long 0x24 0. "PU0,Port E pull-up bit" "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15,Port E pull-down bit" "0,1" bitfld.long 0x28 14. "PD14,Port E pull-down bit" "0,1" newline bitfld.long 0x28 13. "PD13,Port E pull-down bit" "0,1" bitfld.long 0x28 12. "PD12,Port E pull-down bit" "0,1" newline bitfld.long 0x28 11. "PD11,Port E pull-down bit" "0,1" bitfld.long 0x28 10. "PD10,Port E pull-down bit" "0,1" newline bitfld.long 0x28 9. "PD9,Port E pull-down bit" "0,1" bitfld.long 0x28 8. "PD8,Port E pull-down bit" "0,1" newline bitfld.long 0x28 7. "PD7,Port E pull-down bit" "0,1" bitfld.long 0x28 6. "PD6,Port E pull-down bit" "0,1" newline bitfld.long 0x28 5. "PD5,Port E pull-down bit" "0,1" bitfld.long 0x28 4. "PD4,Port E pull-down bit" "0,1" newline bitfld.long 0x28 3. "PD3,Port E pull-down bit" "0,1" bitfld.long 0x28 2. "PD2,Port E pull-down bit" "0,1" newline bitfld.long 0x28 1. "PD1,Port E pull-down bit" "0,1" bitfld.long 0x28 0. "PD0,Port E pull-down bit" "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15,Port F pull-up bit" "0,1" bitfld.long 0x2C 14. "PU14,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 13. "PU13,Port F pull-up bit" "0,1" bitfld.long 0x2C 12. "PU12,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 11. "PU11,Port F pull-up bit" "0,1" bitfld.long 0x2C 10. "PU10,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 9. "PU9,Port F pull-up bit" "0,1" bitfld.long 0x2C 8. "PU8,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 7. "PU7,Port F pull-up bit" "0,1" bitfld.long 0x2C 6. "PU6,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 5. "PU5,Port F pull-up bit" "0,1" bitfld.long 0x2C 4. "PU4,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 3. "PU3,Port F pull-up bit" "0,1" bitfld.long 0x2C 2. "PU2,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 1. "PU1,Port F pull-up bit" "0,1" bitfld.long 0x2C 0. "PU0,Port F pull-up bit" "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15,Port F pull-down bit" "0,1" bitfld.long 0x30 14. "PD14,Port F pull-down bit" "0,1" newline bitfld.long 0x30 13. "PD13,Port F pull-down bit" "0,1" bitfld.long 0x30 12. "PD12,Port F pull-down bit" "0,1" newline bitfld.long 0x30 11. "PD11,Port F pull-down bit" "0,1" bitfld.long 0x30 10. "PD10,Port F pull-down bit" "0,1" newline bitfld.long 0x30 9. "PD9,Port F pull-down bit" "0,1" bitfld.long 0x30 8. "PD8,Port F pull-down bit" "0,1" newline bitfld.long 0x30 7. "PD7,Port F pull-down bit" "0,1" bitfld.long 0x30 6. "PD6,Port F pull-down bit" "0,1" newline bitfld.long 0x30 5. "PD5,Port F pull-down bit" "0,1" bitfld.long 0x30 4. "PD4,Port F pull-down bit" "0,1" newline bitfld.long 0x30 3. "PD3,Port F pull-down bit" "0,1" bitfld.long 0x30 2. "PD2,Port F pull-down bit" "0,1" newline bitfld.long 0x30 1. "PD1,Port F pull-down bit" "0,1" bitfld.long 0x30 0. "PD0,Port F pull-down bit" "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15,Port G pull-up bit" "0,1" bitfld.long 0x34 14. "PU14,Port G pull-up bit" "0,1" newline bitfld.long 0x34 13. "PU13,Port G pull-up bit" "0,1" bitfld.long 0x34 12. "PU12,Port G pull-up bit" "0,1" newline bitfld.long 0x34 11. "PU11,Port G pull-up bit" "0,1" bitfld.long 0x34 10. "PU10,Port G pull-up bit" "0,1" newline bitfld.long 0x34 9. "PU9,Port G pull-up bit" "0,1" bitfld.long 0x34 8. "PU8,Port G pull-up bit" "0,1" newline bitfld.long 0x34 7. "PU7,Port G pull-up bit" "0,1" bitfld.long 0x34 6. "PU6,Port G pull-up bit" "0,1" newline bitfld.long 0x34 5. "PU5,Port G pull-up bit" "0,1" bitfld.long 0x34 4. "PU4,Port G pull-up bit" "0,1" newline bitfld.long 0x34 3. "PU3,Port G pull-up bit" "0,1" bitfld.long 0x34 2. "PU2,Port G pull-up bit" "0,1" newline bitfld.long 0x34 1. "PU1,Port G pull-up bit" "0,1" bitfld.long 0x34 0. "PU0,Port G pull-up bit" "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15,Port G pull-down bit" "0,1" bitfld.long 0x38 14. "PD14,Port G pull-down bit" "0,1" newline bitfld.long 0x38 13. "PD13,Port G pull-down bit" "0,1" bitfld.long 0x38 12. "PD12,Port G pull-down bit" "0,1" newline bitfld.long 0x38 11. "PD11,Port G pull-down bit" "0,1" bitfld.long 0x38 10. "PD10,Port G pull-down bit" "0,1" newline bitfld.long 0x38 9. "PD9,Port G pull-down bit" "0,1" bitfld.long 0x38 8. "PD8,Port G pull-down bit" "0,1" newline bitfld.long 0x38 7. "PD7,Port G pull-down bit" "0,1" bitfld.long 0x38 6. "PD6,Port G pull-down bit" "0,1" newline bitfld.long 0x38 5. "PD5,Port G pull-down bit" "0,1" bitfld.long 0x38 4. "PD4,Port G pull-down bit" "0,1" newline bitfld.long 0x38 3. "PD3,Port G pull-down bit" "0,1" bitfld.long 0x38 2. "PD2,Port G pull-down bit" "0,1" newline bitfld.long 0x38 1. "PD1,Port G pull-down bit" "0,1" bitfld.long 0x38 0. "PD0,Port G pull-down bit" "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15,Port H pull-up bit" "0,1" bitfld.long 0x3C 14. "PU14,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 13. "PU13,Port H pull-up bit" "0,1" bitfld.long 0x3C 12. "PU12,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 11. "PU11,Port H pull-up bit" "0,1" bitfld.long 0x3C 10. "PU10,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 9. "PU9,Port H pull-up bit" "0,1" bitfld.long 0x3C 8. "PU8,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 7. "PU7,Port H pull-up bit" "0,1" bitfld.long 0x3C 6. "PU6,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 5. "PU5,Port H pull-up bit" "0,1" bitfld.long 0x3C 4. "PU4,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 3. "PU3,Port H pull-up bit" "0,1" bitfld.long 0x3C 2. "PU2,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 1. "PU1,Port H pull-up bit" "0,1" bitfld.long 0x3C 0. "PU0,Port H pull-up bit" "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15,Port H pull-down bit" "0,1" bitfld.long 0x40 14. "PD14,Port H pull-down bit" "0,1" newline bitfld.long 0x40 13. "PD13,Port H pull-down bit" "0,1" bitfld.long 0x40 12. "PD12,Port H pull-down bit" "0,1" newline bitfld.long 0x40 11. "PD11,Port H pull-down bit" "0,1" bitfld.long 0x40 10. "PD10,Port H pull-down bit" "0,1" newline bitfld.long 0x40 9. "PD9,Port H pull-down bit" "0,1" bitfld.long 0x40 8. "PD8,Port H pull-down bit" "0,1" newline bitfld.long 0x40 7. "PD7,Port H pull-down bit" "0,1" bitfld.long 0x40 6. "PD6,Port H pull-down bit" "0,1" newline bitfld.long 0x40 5. "PD5,Port H pull-down bit" "0,1" bitfld.long 0x40 4. "PD4,Port H pull-down bit" "0,1" newline bitfld.long 0x40 3. "PD3,Port H pull-down bit" "0,1" bitfld.long 0x40 2. "PD2,Port H pull-down bit" "0,1" newline bitfld.long 0x40 1. "PD1,Port H pull-down bit" "0,1" bitfld.long 0x40 0. "PD0,Port H pull-down bit" "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 7. "PU7,Port I pull-up bit" "0,1" bitfld.long 0x44 6. "PU6,Port I pull-up bit" "0,1" newline bitfld.long 0x44 5. "PU5,Port I pull-up bit" "0,1" bitfld.long 0x44 4. "PU4,Port I pull-up bit" "0,1" newline bitfld.long 0x44 3. "PU3,Port I pull-up bit" "0,1" bitfld.long 0x44 2. "PU2,Port I pull-up bit" "0,1" newline bitfld.long 0x44 1. "PU1,Port I pull-up bit" "0,1" bitfld.long 0x44 0. "PU0,Port I pull-up bit" "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 7. "PD7,Port I pull-down bit" "0,1" bitfld.long 0x48 6. "PD6,Port I pull-down bit" "0,1" newline bitfld.long 0x48 5. "PD5,Port I pull-down bit" "0,1" bitfld.long 0x48 4. "PD4,Port I pull-down bit" "0,1" newline bitfld.long 0x48 3. "PD3,Port I pull-down bit" "0,1" bitfld.long 0x48 2. "PD2,Port I pull-down bit" "0,1" newline bitfld.long 0x48 1. "PD1,Port I pull-down bit" "0,1" bitfld.long 0x48 0. "PD0,Port I pull-down bit" "0,1" tree.end endif sif (cpuis("STM32U585*")) tree "PWR" base ad:0x46020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" newline bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" newline bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." newline bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA SRAM power-down" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR," bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x4B line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13,Port A pull-up bit" "0,1" newline bitfld.long 0x4 12. "PU12,Port A pull-up bit" "0,1" bitfld.long 0x4 11. "PU11,Port A pull-up bit" "0,1" newline bitfld.long 0x4 10. "PU10,Port A pull-up bit" "0,1" bitfld.long 0x4 9. "PU9,Port A pull-up bit" "0,1" newline bitfld.long 0x4 8. "PU8,Port A pull-up bit" "0,1" bitfld.long 0x4 7. "PU7,Port A pull-up bit" "0,1" newline bitfld.long 0x4 6. "PU6,Port A pull-up bit" "0,1" bitfld.long 0x4 5. "PU5,Port A pull-up bit" "0,1" newline bitfld.long 0x4 4. "PU4,Port A pull-up bit" "0,1" bitfld.long 0x4 3. "PU3,Port A pull-up bit" "0,1" newline bitfld.long 0x4 2. "PU2,Port A pull-up bit" "0,1" bitfld.long 0x4 1. "PU1,Port A pull-up bit" "0,1" newline bitfld.long 0x4 0. "PU0,Port A pull-up bit" "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit" "0,1" bitfld.long 0x8 12. "PD12,Port A pull-down bit" "0,1" newline bitfld.long 0x8 11. "PD11,Port A pull-down bit" "0,1" bitfld.long 0x8 10. "PD10,Port A pull-down bit" "0,1" newline bitfld.long 0x8 9. "PD9,Port A pull-down bit" "0,1" bitfld.long 0x8 8. "PD8,Port A pull-down bit" "0,1" newline bitfld.long 0x8 7. "PD7,Port A pull-down bit" "0,1" bitfld.long 0x8 6. "PD6,Port A pull-down bit" "0,1" newline bitfld.long 0x8 5. "PD5,Port A pull-down bit" "0,1" bitfld.long 0x8 4. "PD4,Port A pull-down bit" "0,1" newline bitfld.long 0x8 3. "PD3,Port A pull-down bit" "0,1" bitfld.long 0x8 2. "PD2,Port A pull-down bit" "0,1" newline bitfld.long 0x8 1. "PD1,Port A pull-down bit" "0,1" bitfld.long 0x8 0. "PD0,Port A pull-down bit" "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15,Port B pull-up bit" "0,1" bitfld.long 0xC 14. "PU14,Port B pull-up bit" "0,1" newline bitfld.long 0xC 13. "PU13,Port B pull-up bit" "0,1" bitfld.long 0xC 12. "PU12,Port B pull-up bit" "0,1" newline bitfld.long 0xC 11. "PU11,Port B pull-up bit" "0,1" bitfld.long 0xC 10. "PU10,Port B pull-up bit" "0,1" newline bitfld.long 0xC 9. "PU9,Port B pull-up bit" "0,1" bitfld.long 0xC 8. "PU8,Port B pull-up bit" "0,1" newline bitfld.long 0xC 7. "PU7,Port B pull-up bit" "0,1" bitfld.long 0xC 6. "PU6,Port B pull-up bit" "0,1" newline bitfld.long 0xC 5. "PU5,Port B pull-up bit" "0,1" bitfld.long 0xC 4. "PU4,Port B pull-up bit" "0,1" newline bitfld.long 0xC 3. "PU3,Port B pull-up bit" "0,1" bitfld.long 0xC 2. "PU2,Port B pull-up bit" "0,1" newline bitfld.long 0xC 1. "PU1,Port B pull-up bit" "0,1" bitfld.long 0xC 0. "PU0,Port B pull-up bit" "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15,Port B pull-down bit" "0,1" bitfld.long 0x10 14. "PD14,Port B pull-down bit" "0,1" newline bitfld.long 0x10 13. "PD13,Port B pull-down bit" "0,1" bitfld.long 0x10 12. "PD12,Port B pull-down bit" "0,1" newline bitfld.long 0x10 11. "PD11,Port B pull-down bit" "0,1" bitfld.long 0x10 10. "PD10,Port B pull-down bit" "0,1" newline bitfld.long 0x10 9. "PD9,Port B pull-down bit" "0,1" bitfld.long 0x10 8. "PD8,Port B pull-down bit" "0,1" newline bitfld.long 0x10 7. "PD7,Port B pull-down bit" "0,1" bitfld.long 0x10 6. "PD6,Port B pull-down bit" "0,1" newline bitfld.long 0x10 5. "PD5,Port B pull-down bit" "0,1" bitfld.long 0x10 3. "PD3,Port B pull-down bit" "0,1" newline bitfld.long 0x10 2. "PD2,Port B pull-down bit" "0,1" bitfld.long 0x10 1. "PD1,Port B pull-down bit" "0,1" newline bitfld.long 0x10 0. "PD0,Port B pull-down bit" "0,1" line.long 0x14 "PWR_PUCRC,PWR port C pull-up control register" bitfld.long 0x14 15. "PU15,Port C pull-up bit" "0,1" bitfld.long 0x14 14. "PU14,Port C pull-up bit" "0,1" newline bitfld.long 0x14 13. "PU13,Port C pull-up bit" "0,1" bitfld.long 0x14 12. "PU12,Port C pull-up bit" "0,1" newline bitfld.long 0x14 11. "PU11,Port C pull-up bit" "0,1" bitfld.long 0x14 10. "PU10,Port C pull-up bit" "0,1" newline bitfld.long 0x14 9. "PU9,Port C pull-up bit" "0,1" bitfld.long 0x14 8. "PU8,Port C pull-up bit" "0,1" newline bitfld.long 0x14 7. "PU7,Port C pull-up bit" "0,1" bitfld.long 0x14 6. "PU6,Port C pull-up bit" "0,1" newline bitfld.long 0x14 5. "PU5,Port C pull-up bit" "0,1" bitfld.long 0x14 4. "PU4,Port C pull-up bit" "0,1" newline bitfld.long 0x14 3. "PU3,Port C pull-up bit" "0,1" bitfld.long 0x14 2. "PU2,Port C pull-up bit" "0,1" newline bitfld.long 0x14 1. "PU1,Port C pull-up bit" "0,1" bitfld.long 0x14 0. "PU0,Port C pull-up bit" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15,Port C pull-down bit" "0,1" bitfld.long 0x18 14. "PD14,Port C pull-down bit" "0,1" newline bitfld.long 0x18 13. "PD13,Port C pull-down bit" "0,1" bitfld.long 0x18 12. "PD12,Port C pull-down bit" "0,1" newline bitfld.long 0x18 11. "PD11,Port C pull-down bit" "0,1" bitfld.long 0x18 10. "PD10,Port C pull-down bit" "0,1" newline bitfld.long 0x18 9. "PD9,Port C pull-down bit" "0,1" bitfld.long 0x18 8. "PD8,Port C pull-down bit" "0,1" newline bitfld.long 0x18 7. "PD7,Port C pull-down bit" "0,1" bitfld.long 0x18 6. "PD6,Port C pull-down bit" "0,1" newline bitfld.long 0x18 5. "PD5,Port C pull-down bit" "0,1" bitfld.long 0x18 4. "PD4,Port C pull-down bit" "0,1" newline bitfld.long 0x18 3. "PD3,Port C pull-down bit" "0,1" bitfld.long 0x18 2. "PD2,Port C pull-down bit" "0,1" newline bitfld.long 0x18 1. "PD1,Port C pull-down bit" "0,1" bitfld.long 0x18 0. "PD0,Port C pull-down bit" "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15,Port D pull-up bit" "0,1" bitfld.long 0x1C 14. "PU14,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 13. "PU13,Port D pull-up bit" "0,1" bitfld.long 0x1C 12. "PU12,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 11. "PU11,Port D pull-up bit" "0,1" bitfld.long 0x1C 10. "PU10,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 9. "PU9,Port D pull-up bit" "0,1" bitfld.long 0x1C 8. "PU8,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 7. "PU7,Port D pull-up bit" "0,1" bitfld.long 0x1C 6. "PU6,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 5. "PU5,Port D pull-up bit" "0,1" bitfld.long 0x1C 4. "PU4,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 3. "PU3,Port D pull-up bit" "0,1" bitfld.long 0x1C 2. "PU2,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 1. "PU1,Port D pull-up bit" "0,1" bitfld.long 0x1C 0. "PU0,Port D pull-up bit" "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15,Port D pull-down bit" "0,1" bitfld.long 0x20 14. "PD14,Port D pull-down bit" "0,1" newline bitfld.long 0x20 13. "PD13,Port D pull-down bit" "0,1" bitfld.long 0x20 12. "PD12,Port D pull-down bit" "0,1" newline bitfld.long 0x20 11. "PD11,Port D pull-down bit" "0,1" bitfld.long 0x20 10. "PD10,Port D pull-down bit" "0,1" newline bitfld.long 0x20 9. "PD9,Port D pull-down bit" "0,1" bitfld.long 0x20 8. "PD8,Port D pull-down bit" "0,1" newline bitfld.long 0x20 7. "PD7,Port D pull-down bit" "0,1" bitfld.long 0x20 6. "PD6,Port D pull-down bit" "0,1" newline bitfld.long 0x20 5. "PD5,Port D pull-down bit" "0,1" bitfld.long 0x20 4. "PD4,Port D pull-down bit" "0,1" newline bitfld.long 0x20 3. "PD3,Port D pull-down bit" "0,1" bitfld.long 0x20 2. "PD2,Port D pull-down bit" "0,1" newline bitfld.long 0x20 1. "PD1,Port D pull-down bit" "0,1" bitfld.long 0x20 0. "PD0,Port D pull-down bit" "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15,Port E pull-up bit" "0,1" bitfld.long 0x24 14. "PU14,Port E pull-up bit" "0,1" newline bitfld.long 0x24 13. "PU13,Port E pull-up bit" "0,1" bitfld.long 0x24 12. "PU12,Port E pull-up bit" "0,1" newline bitfld.long 0x24 11. "PU11,Port E pull-up bit" "0,1" bitfld.long 0x24 10. "PU10,Port E pull-up bit" "0,1" newline bitfld.long 0x24 9. "PU9,Port E pull-up bit" "0,1" bitfld.long 0x24 8. "PU8,Port E pull-up bit" "0,1" newline bitfld.long 0x24 7. "PU7,Port E pull-up bit" "0,1" bitfld.long 0x24 6. "PU6,Port E pull-up bit" "0,1" newline bitfld.long 0x24 5. "PU5,Port E pull-up bit" "0,1" bitfld.long 0x24 4. "PU4,Port E pull-up bit" "0,1" newline bitfld.long 0x24 3. "PU3,Port E pull-up bit" "0,1" bitfld.long 0x24 2. "PU2,Port E pull-up bit" "0,1" newline bitfld.long 0x24 1. "PU1,Port E pull-up bit" "0,1" bitfld.long 0x24 0. "PU0,Port E pull-up bit" "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15,Port E pull-down bit" "0,1" bitfld.long 0x28 14. "PD14,Port E pull-down bit" "0,1" newline bitfld.long 0x28 13. "PD13,Port E pull-down bit" "0,1" bitfld.long 0x28 12. "PD12,Port E pull-down bit" "0,1" newline bitfld.long 0x28 11. "PD11,Port E pull-down bit" "0,1" bitfld.long 0x28 10. "PD10,Port E pull-down bit" "0,1" newline bitfld.long 0x28 9. "PD9,Port E pull-down bit" "0,1" bitfld.long 0x28 8. "PD8,Port E pull-down bit" "0,1" newline bitfld.long 0x28 7. "PD7,Port E pull-down bit" "0,1" bitfld.long 0x28 6. "PD6,Port E pull-down bit" "0,1" newline bitfld.long 0x28 5. "PD5,Port E pull-down bit" "0,1" bitfld.long 0x28 4. "PD4,Port E pull-down bit" "0,1" newline bitfld.long 0x28 3. "PD3,Port E pull-down bit" "0,1" bitfld.long 0x28 2. "PD2,Port E pull-down bit" "0,1" newline bitfld.long 0x28 1. "PD1,Port E pull-down bit" "0,1" bitfld.long 0x28 0. "PD0,Port E pull-down bit" "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15,Port F pull-up bit" "0,1" bitfld.long 0x2C 14. "PU14,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 13. "PU13,Port F pull-up bit" "0,1" bitfld.long 0x2C 12. "PU12,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 11. "PU11,Port F pull-up bit" "0,1" bitfld.long 0x2C 10. "PU10,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 9. "PU9,Port F pull-up bit" "0,1" bitfld.long 0x2C 8. "PU8,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 7. "PU7,Port F pull-up bit" "0,1" bitfld.long 0x2C 6. "PU6,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 5. "PU5,Port F pull-up bit" "0,1" bitfld.long 0x2C 4. "PU4,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 3. "PU3,Port F pull-up bit" "0,1" bitfld.long 0x2C 2. "PU2,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 1. "PU1,Port F pull-up bit" "0,1" bitfld.long 0x2C 0. "PU0,Port F pull-up bit" "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15,Port F pull-down bit" "0,1" bitfld.long 0x30 14. "PD14,Port F pull-down bit" "0,1" newline bitfld.long 0x30 13. "PD13,Port F pull-down bit" "0,1" bitfld.long 0x30 12. "PD12,Port F pull-down bit" "0,1" newline bitfld.long 0x30 11. "PD11,Port F pull-down bit" "0,1" bitfld.long 0x30 10. "PD10,Port F pull-down bit" "0,1" newline bitfld.long 0x30 9. "PD9,Port F pull-down bit" "0,1" bitfld.long 0x30 8. "PD8,Port F pull-down bit" "0,1" newline bitfld.long 0x30 7. "PD7,Port F pull-down bit" "0,1" bitfld.long 0x30 6. "PD6,Port F pull-down bit" "0,1" newline bitfld.long 0x30 5. "PD5,Port F pull-down bit" "0,1" bitfld.long 0x30 4. "PD4,Port F pull-down bit" "0,1" newline bitfld.long 0x30 3. "PD3,Port F pull-down bit" "0,1" bitfld.long 0x30 2. "PD2,Port F pull-down bit" "0,1" newline bitfld.long 0x30 1. "PD1,Port F pull-down bit" "0,1" bitfld.long 0x30 0. "PD0,Port F pull-down bit" "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15,Port G pull-up bit" "0,1" bitfld.long 0x34 14. "PU14,Port G pull-up bit" "0,1" newline bitfld.long 0x34 13. "PU13,Port G pull-up bit" "0,1" bitfld.long 0x34 12. "PU12,Port G pull-up bit" "0,1" newline bitfld.long 0x34 11. "PU11,Port G pull-up bit" "0,1" bitfld.long 0x34 10. "PU10,Port G pull-up bit" "0,1" newline bitfld.long 0x34 9. "PU9,Port G pull-up bit" "0,1" bitfld.long 0x34 8. "PU8,Port G pull-up bit" "0,1" newline bitfld.long 0x34 7. "PU7,Port G pull-up bit" "0,1" bitfld.long 0x34 6. "PU6,Port G pull-up bit" "0,1" newline bitfld.long 0x34 5. "PU5,Port G pull-up bit" "0,1" bitfld.long 0x34 4. "PU4,Port G pull-up bit" "0,1" newline bitfld.long 0x34 3. "PU3,Port G pull-up bit" "0,1" bitfld.long 0x34 2. "PU2,Port G pull-up bit" "0,1" newline bitfld.long 0x34 1. "PU1,Port G pull-up bit" "0,1" bitfld.long 0x34 0. "PU0,Port G pull-up bit" "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15,Port G pull-down bit" "0,1" bitfld.long 0x38 14. "PD14,Port G pull-down bit" "0,1" newline bitfld.long 0x38 13. "PD13,Port G pull-down bit" "0,1" bitfld.long 0x38 12. "PD12,Port G pull-down bit" "0,1" newline bitfld.long 0x38 11. "PD11,Port G pull-down bit" "0,1" bitfld.long 0x38 10. "PD10,Port G pull-down bit" "0,1" newline bitfld.long 0x38 9. "PD9,Port G pull-down bit" "0,1" bitfld.long 0x38 8. "PD8,Port G pull-down bit" "0,1" newline bitfld.long 0x38 7. "PD7,Port G pull-down bit" "0,1" bitfld.long 0x38 6. "PD6,Port G pull-down bit" "0,1" newline bitfld.long 0x38 5. "PD5,Port G pull-down bit" "0,1" bitfld.long 0x38 4. "PD4,Port G pull-down bit" "0,1" newline bitfld.long 0x38 3. "PD3,Port G pull-down bit" "0,1" bitfld.long 0x38 2. "PD2,Port G pull-down bit" "0,1" newline bitfld.long 0x38 1. "PD1,Port G pull-down bit" "0,1" bitfld.long 0x38 0. "PD0,Port G pull-down bit" "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15,Port H pull-up bit" "0,1" bitfld.long 0x3C 14. "PU14,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 13. "PU13,Port H pull-up bit" "0,1" bitfld.long 0x3C 12. "PU12,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 11. "PU11,Port H pull-up bit" "0,1" bitfld.long 0x3C 10. "PU10,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 9. "PU9,Port H pull-up bit" "0,1" bitfld.long 0x3C 8. "PU8,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 7. "PU7,Port H pull-up bit" "0,1" bitfld.long 0x3C 6. "PU6,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 5. "PU5,Port H pull-up bit" "0,1" bitfld.long 0x3C 4. "PU4,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 3. "PU3,Port H pull-up bit" "0,1" bitfld.long 0x3C 2. "PU2,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 1. "PU1,Port H pull-up bit" "0,1" bitfld.long 0x3C 0. "PU0,Port H pull-up bit" "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15,Port H pull-down bit" "0,1" bitfld.long 0x40 14. "PD14,Port H pull-down bit" "0,1" newline bitfld.long 0x40 13. "PD13,Port H pull-down bit" "0,1" bitfld.long 0x40 12. "PD12,Port H pull-down bit" "0,1" newline bitfld.long 0x40 11. "PD11,Port H pull-down bit" "0,1" bitfld.long 0x40 10. "PD10,Port H pull-down bit" "0,1" newline bitfld.long 0x40 9. "PD9,Port H pull-down bit" "0,1" bitfld.long 0x40 8. "PD8,Port H pull-down bit" "0,1" newline bitfld.long 0x40 7. "PD7,Port H pull-down bit" "0,1" bitfld.long 0x40 6. "PD6,Port H pull-down bit" "0,1" newline bitfld.long 0x40 5. "PD5,Port H pull-down bit" "0,1" bitfld.long 0x40 4. "PD4,Port H pull-down bit" "0,1" newline bitfld.long 0x40 3. "PD3,Port H pull-down bit" "0,1" bitfld.long 0x40 2. "PD2,Port H pull-down bit" "0,1" newline bitfld.long 0x40 1. "PD1,Port H pull-down bit" "0,1" bitfld.long 0x40 0. "PD0,Port H pull-down bit" "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 7. "PU7,Port I pull-up bit" "0,1" bitfld.long 0x44 6. "PU6,Port I pull-up bit" "0,1" newline bitfld.long 0x44 5. "PU5,Port I pull-up bit" "0,1" bitfld.long 0x44 4. "PU4,Port I pull-up bit" "0,1" newline bitfld.long 0x44 3. "PU3,Port I pull-up bit" "0,1" bitfld.long 0x44 2. "PU2,Port I pull-up bit" "0,1" newline bitfld.long 0x44 1. "PU1,Port I pull-up bit" "0,1" bitfld.long 0x44 0. "PU0,Port I pull-up bit" "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 7. "PD7,Port I pull-down bit" "0,1" bitfld.long 0x48 6. "PD6,Port I pull-down bit" "0,1" newline bitfld.long 0x48 5. "PD5,Port I pull-down bit" "0,1" bitfld.long 0x48 4. "PD4,Port I pull-down bit" "0,1" newline bitfld.long 0x48 3. "PD3,Port I pull-down bit" "0,1" bitfld.long 0x48 2. "PD2,Port I pull-down bit" "0,1" newline bitfld.long 0x48 1. "PD1,Port I pull-down bit" "0,1" bitfld.long 0x48 0. "PD0,Port I pull-down bit" "0,1" tree.end tree "SEC_PWR" base ad:0x56020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" newline bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" newline bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." newline bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA SRAM power-down" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR," bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x4B line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13,Port A pull-up bit" "0,1" newline bitfld.long 0x4 12. "PU12,Port A pull-up bit" "0,1" bitfld.long 0x4 11. "PU11,Port A pull-up bit" "0,1" newline bitfld.long 0x4 10. "PU10,Port A pull-up bit" "0,1" bitfld.long 0x4 9. "PU9,Port A pull-up bit" "0,1" newline bitfld.long 0x4 8. "PU8,Port A pull-up bit" "0,1" bitfld.long 0x4 7. "PU7,Port A pull-up bit" "0,1" newline bitfld.long 0x4 6. "PU6,Port A pull-up bit" "0,1" bitfld.long 0x4 5. "PU5,Port A pull-up bit" "0,1" newline bitfld.long 0x4 4. "PU4,Port A pull-up bit" "0,1" bitfld.long 0x4 3. "PU3,Port A pull-up bit" "0,1" newline bitfld.long 0x4 2. "PU2,Port A pull-up bit" "0,1" bitfld.long 0x4 1. "PU1,Port A pull-up bit" "0,1" newline bitfld.long 0x4 0. "PU0,Port A pull-up bit" "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit" "0,1" bitfld.long 0x8 12. "PD12,Port A pull-down bit" "0,1" newline bitfld.long 0x8 11. "PD11,Port A pull-down bit" "0,1" bitfld.long 0x8 10. "PD10,Port A pull-down bit" "0,1" newline bitfld.long 0x8 9. "PD9,Port A pull-down bit" "0,1" bitfld.long 0x8 8. "PD8,Port A pull-down bit" "0,1" newline bitfld.long 0x8 7. "PD7,Port A pull-down bit" "0,1" bitfld.long 0x8 6. "PD6,Port A pull-down bit" "0,1" newline bitfld.long 0x8 5. "PD5,Port A pull-down bit" "0,1" bitfld.long 0x8 4. "PD4,Port A pull-down bit" "0,1" newline bitfld.long 0x8 3. "PD3,Port A pull-down bit" "0,1" bitfld.long 0x8 2. "PD2,Port A pull-down bit" "0,1" newline bitfld.long 0x8 1. "PD1,Port A pull-down bit" "0,1" bitfld.long 0x8 0. "PD0,Port A pull-down bit" "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15,Port B pull-up bit" "0,1" bitfld.long 0xC 14. "PU14,Port B pull-up bit" "0,1" newline bitfld.long 0xC 13. "PU13,Port B pull-up bit" "0,1" bitfld.long 0xC 12. "PU12,Port B pull-up bit" "0,1" newline bitfld.long 0xC 11. "PU11,Port B pull-up bit" "0,1" bitfld.long 0xC 10. "PU10,Port B pull-up bit" "0,1" newline bitfld.long 0xC 9. "PU9,Port B pull-up bit" "0,1" bitfld.long 0xC 8. "PU8,Port B pull-up bit" "0,1" newline bitfld.long 0xC 7. "PU7,Port B pull-up bit" "0,1" bitfld.long 0xC 6. "PU6,Port B pull-up bit" "0,1" newline bitfld.long 0xC 5. "PU5,Port B pull-up bit" "0,1" bitfld.long 0xC 4. "PU4,Port B pull-up bit" "0,1" newline bitfld.long 0xC 3. "PU3,Port B pull-up bit" "0,1" bitfld.long 0xC 2. "PU2,Port B pull-up bit" "0,1" newline bitfld.long 0xC 1. "PU1,Port B pull-up bit" "0,1" bitfld.long 0xC 0. "PU0,Port B pull-up bit" "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15,Port B pull-down bit" "0,1" bitfld.long 0x10 14. "PD14,Port B pull-down bit" "0,1" newline bitfld.long 0x10 13. "PD13,Port B pull-down bit" "0,1" bitfld.long 0x10 12. "PD12,Port B pull-down bit" "0,1" newline bitfld.long 0x10 11. "PD11,Port B pull-down bit" "0,1" bitfld.long 0x10 10. "PD10,Port B pull-down bit" "0,1" newline bitfld.long 0x10 9. "PD9,Port B pull-down bit" "0,1" bitfld.long 0x10 8. "PD8,Port B pull-down bit" "0,1" newline bitfld.long 0x10 7. "PD7,Port B pull-down bit" "0,1" bitfld.long 0x10 6. "PD6,Port B pull-down bit" "0,1" newline bitfld.long 0x10 5. "PD5,Port B pull-down bit" "0,1" bitfld.long 0x10 3. "PD3,Port B pull-down bit" "0,1" newline bitfld.long 0x10 2. "PD2,Port B pull-down bit" "0,1" bitfld.long 0x10 1. "PD1,Port B pull-down bit" "0,1" newline bitfld.long 0x10 0. "PD0,Port B pull-down bit" "0,1" line.long 0x14 "PWR_PUCRC,PWR port C pull-up control register" bitfld.long 0x14 15. "PU15,Port C pull-up bit" "0,1" bitfld.long 0x14 14. "PU14,Port C pull-up bit" "0,1" newline bitfld.long 0x14 13. "PU13,Port C pull-up bit" "0,1" bitfld.long 0x14 12. "PU12,Port C pull-up bit" "0,1" newline bitfld.long 0x14 11. "PU11,Port C pull-up bit" "0,1" bitfld.long 0x14 10. "PU10,Port C pull-up bit" "0,1" newline bitfld.long 0x14 9. "PU9,Port C pull-up bit" "0,1" bitfld.long 0x14 8. "PU8,Port C pull-up bit" "0,1" newline bitfld.long 0x14 7. "PU7,Port C pull-up bit" "0,1" bitfld.long 0x14 6. "PU6,Port C pull-up bit" "0,1" newline bitfld.long 0x14 5. "PU5,Port C pull-up bit" "0,1" bitfld.long 0x14 4. "PU4,Port C pull-up bit" "0,1" newline bitfld.long 0x14 3. "PU3,Port C pull-up bit" "0,1" bitfld.long 0x14 2. "PU2,Port C pull-up bit" "0,1" newline bitfld.long 0x14 1. "PU1,Port C pull-up bit" "0,1" bitfld.long 0x14 0. "PU0,Port C pull-up bit" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15,Port C pull-down bit" "0,1" bitfld.long 0x18 14. "PD14,Port C pull-down bit" "0,1" newline bitfld.long 0x18 13. "PD13,Port C pull-down bit" "0,1" bitfld.long 0x18 12. "PD12,Port C pull-down bit" "0,1" newline bitfld.long 0x18 11. "PD11,Port C pull-down bit" "0,1" bitfld.long 0x18 10. "PD10,Port C pull-down bit" "0,1" newline bitfld.long 0x18 9. "PD9,Port C pull-down bit" "0,1" bitfld.long 0x18 8. "PD8,Port C pull-down bit" "0,1" newline bitfld.long 0x18 7. "PD7,Port C pull-down bit" "0,1" bitfld.long 0x18 6. "PD6,Port C pull-down bit" "0,1" newline bitfld.long 0x18 5. "PD5,Port C pull-down bit" "0,1" bitfld.long 0x18 4. "PD4,Port C pull-down bit" "0,1" newline bitfld.long 0x18 3. "PD3,Port C pull-down bit" "0,1" bitfld.long 0x18 2. "PD2,Port C pull-down bit" "0,1" newline bitfld.long 0x18 1. "PD1,Port C pull-down bit" "0,1" bitfld.long 0x18 0. "PD0,Port C pull-down bit" "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15,Port D pull-up bit" "0,1" bitfld.long 0x1C 14. "PU14,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 13. "PU13,Port D pull-up bit" "0,1" bitfld.long 0x1C 12. "PU12,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 11. "PU11,Port D pull-up bit" "0,1" bitfld.long 0x1C 10. "PU10,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 9. "PU9,Port D pull-up bit" "0,1" bitfld.long 0x1C 8. "PU8,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 7. "PU7,Port D pull-up bit" "0,1" bitfld.long 0x1C 6. "PU6,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 5. "PU5,Port D pull-up bit" "0,1" bitfld.long 0x1C 4. "PU4,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 3. "PU3,Port D pull-up bit" "0,1" bitfld.long 0x1C 2. "PU2,Port D pull-up bit" "0,1" newline bitfld.long 0x1C 1. "PU1,Port D pull-up bit" "0,1" bitfld.long 0x1C 0. "PU0,Port D pull-up bit" "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15,Port D pull-down bit" "0,1" bitfld.long 0x20 14. "PD14,Port D pull-down bit" "0,1" newline bitfld.long 0x20 13. "PD13,Port D pull-down bit" "0,1" bitfld.long 0x20 12. "PD12,Port D pull-down bit" "0,1" newline bitfld.long 0x20 11. "PD11,Port D pull-down bit" "0,1" bitfld.long 0x20 10. "PD10,Port D pull-down bit" "0,1" newline bitfld.long 0x20 9. "PD9,Port D pull-down bit" "0,1" bitfld.long 0x20 8. "PD8,Port D pull-down bit" "0,1" newline bitfld.long 0x20 7. "PD7,Port D pull-down bit" "0,1" bitfld.long 0x20 6. "PD6,Port D pull-down bit" "0,1" newline bitfld.long 0x20 5. "PD5,Port D pull-down bit" "0,1" bitfld.long 0x20 4. "PD4,Port D pull-down bit" "0,1" newline bitfld.long 0x20 3. "PD3,Port D pull-down bit" "0,1" bitfld.long 0x20 2. "PD2,Port D pull-down bit" "0,1" newline bitfld.long 0x20 1. "PD1,Port D pull-down bit" "0,1" bitfld.long 0x20 0. "PD0,Port D pull-down bit" "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15,Port E pull-up bit" "0,1" bitfld.long 0x24 14. "PU14,Port E pull-up bit" "0,1" newline bitfld.long 0x24 13. "PU13,Port E pull-up bit" "0,1" bitfld.long 0x24 12. "PU12,Port E pull-up bit" "0,1" newline bitfld.long 0x24 11. "PU11,Port E pull-up bit" "0,1" bitfld.long 0x24 10. "PU10,Port E pull-up bit" "0,1" newline bitfld.long 0x24 9. "PU9,Port E pull-up bit" "0,1" bitfld.long 0x24 8. "PU8,Port E pull-up bit" "0,1" newline bitfld.long 0x24 7. "PU7,Port E pull-up bit" "0,1" bitfld.long 0x24 6. "PU6,Port E pull-up bit" "0,1" newline bitfld.long 0x24 5. "PU5,Port E pull-up bit" "0,1" bitfld.long 0x24 4. "PU4,Port E pull-up bit" "0,1" newline bitfld.long 0x24 3. "PU3,Port E pull-up bit" "0,1" bitfld.long 0x24 2. "PU2,Port E pull-up bit" "0,1" newline bitfld.long 0x24 1. "PU1,Port E pull-up bit" "0,1" bitfld.long 0x24 0. "PU0,Port E pull-up bit" "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15,Port E pull-down bit" "0,1" bitfld.long 0x28 14. "PD14,Port E pull-down bit" "0,1" newline bitfld.long 0x28 13. "PD13,Port E pull-down bit" "0,1" bitfld.long 0x28 12. "PD12,Port E pull-down bit" "0,1" newline bitfld.long 0x28 11. "PD11,Port E pull-down bit" "0,1" bitfld.long 0x28 10. "PD10,Port E pull-down bit" "0,1" newline bitfld.long 0x28 9. "PD9,Port E pull-down bit" "0,1" bitfld.long 0x28 8. "PD8,Port E pull-down bit" "0,1" newline bitfld.long 0x28 7. "PD7,Port E pull-down bit" "0,1" bitfld.long 0x28 6. "PD6,Port E pull-down bit" "0,1" newline bitfld.long 0x28 5. "PD5,Port E pull-down bit" "0,1" bitfld.long 0x28 4. "PD4,Port E pull-down bit" "0,1" newline bitfld.long 0x28 3. "PD3,Port E pull-down bit" "0,1" bitfld.long 0x28 2. "PD2,Port E pull-down bit" "0,1" newline bitfld.long 0x28 1. "PD1,Port E pull-down bit" "0,1" bitfld.long 0x28 0. "PD0,Port E pull-down bit" "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15,Port F pull-up bit" "0,1" bitfld.long 0x2C 14. "PU14,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 13. "PU13,Port F pull-up bit" "0,1" bitfld.long 0x2C 12. "PU12,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 11. "PU11,Port F pull-up bit" "0,1" bitfld.long 0x2C 10. "PU10,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 9. "PU9,Port F pull-up bit" "0,1" bitfld.long 0x2C 8. "PU8,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 7. "PU7,Port F pull-up bit" "0,1" bitfld.long 0x2C 6. "PU6,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 5. "PU5,Port F pull-up bit" "0,1" bitfld.long 0x2C 4. "PU4,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 3. "PU3,Port F pull-up bit" "0,1" bitfld.long 0x2C 2. "PU2,Port F pull-up bit" "0,1" newline bitfld.long 0x2C 1. "PU1,Port F pull-up bit" "0,1" bitfld.long 0x2C 0. "PU0,Port F pull-up bit" "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15,Port F pull-down bit" "0,1" bitfld.long 0x30 14. "PD14,Port F pull-down bit" "0,1" newline bitfld.long 0x30 13. "PD13,Port F pull-down bit" "0,1" bitfld.long 0x30 12. "PD12,Port F pull-down bit" "0,1" newline bitfld.long 0x30 11. "PD11,Port F pull-down bit" "0,1" bitfld.long 0x30 10. "PD10,Port F pull-down bit" "0,1" newline bitfld.long 0x30 9. "PD9,Port F pull-down bit" "0,1" bitfld.long 0x30 8. "PD8,Port F pull-down bit" "0,1" newline bitfld.long 0x30 7. "PD7,Port F pull-down bit" "0,1" bitfld.long 0x30 6. "PD6,Port F pull-down bit" "0,1" newline bitfld.long 0x30 5. "PD5,Port F pull-down bit" "0,1" bitfld.long 0x30 4. "PD4,Port F pull-down bit" "0,1" newline bitfld.long 0x30 3. "PD3,Port F pull-down bit" "0,1" bitfld.long 0x30 2. "PD2,Port F pull-down bit" "0,1" newline bitfld.long 0x30 1. "PD1,Port F pull-down bit" "0,1" bitfld.long 0x30 0. "PD0,Port F pull-down bit" "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15,Port G pull-up bit" "0,1" bitfld.long 0x34 14. "PU14,Port G pull-up bit" "0,1" newline bitfld.long 0x34 13. "PU13,Port G pull-up bit" "0,1" bitfld.long 0x34 12. "PU12,Port G pull-up bit" "0,1" newline bitfld.long 0x34 11. "PU11,Port G pull-up bit" "0,1" bitfld.long 0x34 10. "PU10,Port G pull-up bit" "0,1" newline bitfld.long 0x34 9. "PU9,Port G pull-up bit" "0,1" bitfld.long 0x34 8. "PU8,Port G pull-up bit" "0,1" newline bitfld.long 0x34 7. "PU7,Port G pull-up bit" "0,1" bitfld.long 0x34 6. "PU6,Port G pull-up bit" "0,1" newline bitfld.long 0x34 5. "PU5,Port G pull-up bit" "0,1" bitfld.long 0x34 4. "PU4,Port G pull-up bit" "0,1" newline bitfld.long 0x34 3. "PU3,Port G pull-up bit" "0,1" bitfld.long 0x34 2. "PU2,Port G pull-up bit" "0,1" newline bitfld.long 0x34 1. "PU1,Port G pull-up bit" "0,1" bitfld.long 0x34 0. "PU0,Port G pull-up bit" "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15,Port G pull-down bit" "0,1" bitfld.long 0x38 14. "PD14,Port G pull-down bit" "0,1" newline bitfld.long 0x38 13. "PD13,Port G pull-down bit" "0,1" bitfld.long 0x38 12. "PD12,Port G pull-down bit" "0,1" newline bitfld.long 0x38 11. "PD11,Port G pull-down bit" "0,1" bitfld.long 0x38 10. "PD10,Port G pull-down bit" "0,1" newline bitfld.long 0x38 9. "PD9,Port G pull-down bit" "0,1" bitfld.long 0x38 8. "PD8,Port G pull-down bit" "0,1" newline bitfld.long 0x38 7. "PD7,Port G pull-down bit" "0,1" bitfld.long 0x38 6. "PD6,Port G pull-down bit" "0,1" newline bitfld.long 0x38 5. "PD5,Port G pull-down bit" "0,1" bitfld.long 0x38 4. "PD4,Port G pull-down bit" "0,1" newline bitfld.long 0x38 3. "PD3,Port G pull-down bit" "0,1" bitfld.long 0x38 2. "PD2,Port G pull-down bit" "0,1" newline bitfld.long 0x38 1. "PD1,Port G pull-down bit" "0,1" bitfld.long 0x38 0. "PD0,Port G pull-down bit" "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15,Port H pull-up bit" "0,1" bitfld.long 0x3C 14. "PU14,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 13. "PU13,Port H pull-up bit" "0,1" bitfld.long 0x3C 12. "PU12,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 11. "PU11,Port H pull-up bit" "0,1" bitfld.long 0x3C 10. "PU10,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 9. "PU9,Port H pull-up bit" "0,1" bitfld.long 0x3C 8. "PU8,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 7. "PU7,Port H pull-up bit" "0,1" bitfld.long 0x3C 6. "PU6,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 5. "PU5,Port H pull-up bit" "0,1" bitfld.long 0x3C 4. "PU4,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 3. "PU3,Port H pull-up bit" "0,1" bitfld.long 0x3C 2. "PU2,Port H pull-up bit" "0,1" newline bitfld.long 0x3C 1. "PU1,Port H pull-up bit" "0,1" bitfld.long 0x3C 0. "PU0,Port H pull-up bit" "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15,Port H pull-down bit" "0,1" bitfld.long 0x40 14. "PD14,Port H pull-down bit" "0,1" newline bitfld.long 0x40 13. "PD13,Port H pull-down bit" "0,1" bitfld.long 0x40 12. "PD12,Port H pull-down bit" "0,1" newline bitfld.long 0x40 11. "PD11,Port H pull-down bit" "0,1" bitfld.long 0x40 10. "PD10,Port H pull-down bit" "0,1" newline bitfld.long 0x40 9. "PD9,Port H pull-down bit" "0,1" bitfld.long 0x40 8. "PD8,Port H pull-down bit" "0,1" newline bitfld.long 0x40 7. "PD7,Port H pull-down bit" "0,1" bitfld.long 0x40 6. "PD6,Port H pull-down bit" "0,1" newline bitfld.long 0x40 5. "PD5,Port H pull-down bit" "0,1" bitfld.long 0x40 4. "PD4,Port H pull-down bit" "0,1" newline bitfld.long 0x40 3. "PD3,Port H pull-down bit" "0,1" bitfld.long 0x40 2. "PD2,Port H pull-down bit" "0,1" newline bitfld.long 0x40 1. "PD1,Port H pull-down bit" "0,1" bitfld.long 0x40 0. "PD0,Port H pull-down bit" "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 7. "PU7,Port I pull-up bit" "0,1" bitfld.long 0x44 6. "PU6,Port I pull-up bit" "0,1" newline bitfld.long 0x44 5. "PU5,Port I pull-up bit" "0,1" bitfld.long 0x44 4. "PU4,Port I pull-up bit" "0,1" newline bitfld.long 0x44 3. "PU3,Port I pull-up bit" "0,1" bitfld.long 0x44 2. "PU2,Port I pull-up bit" "0,1" newline bitfld.long 0x44 1. "PU1,Port I pull-up bit" "0,1" bitfld.long 0x44 0. "PU0,Port I pull-up bit" "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 7. "PD7,Port I pull-down bit" "0,1" bitfld.long 0x48 6. "PD6,Port I pull-down bit" "0,1" newline bitfld.long 0x48 5. "PD5,Port I pull-down bit" "0,1" bitfld.long 0x48 4. "PD4,Port I pull-down bit" "0,1" newline bitfld.long 0x48 3. "PD3,Port I pull-down bit" "0,1" bitfld.long 0x48 2. "PD2,Port I pull-down bit" "0,1" newline bitfld.long 0x48 1. "PD1,Port I pull-down bit" "0,1" bitfld.long 0x48 0. "PD0,Port I pull-down bit" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "PWR" base ad:0x46020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." newline bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" newline bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" newline bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" newline bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" newline bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end tree "SEC_PWR" base ad:0x56020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." newline bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" newline bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" newline bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" newline bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" newline bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "PWR" base ad:0x46020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 25. "DSIRAMPDS,DSI SRAM power-down in Stop modes (Stop 0 1)" "0: DSI SRAM content retained in Stop 0 and Stop 1..,1: DSI SRAM content lost in Stop 0 and Stop 1 modes" newline bitfld.long 0x4 24. "GPRAMPDS,Graphic peripherals (LTDC/GFXMMU) SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: Graphic peripherals SRAM content retained in..,1: Graphic peripherals SRAM content lost in Stop.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." newline bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" newline bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" bitfld.long 0x4 7. "DC2RAMPDS,DCACHE2 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE2 SRAM content retained in Stop modes,1: DCACHE2 SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end tree "SEC_PWR" base ad:0x56020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 25. "DSIRAMPDS,DSI SRAM power-down in Stop modes (Stop 0 1)" "0: DSI SRAM content retained in Stop 0 and Stop 1..,1: DSI SRAM content lost in Stop 0 and Stop 1 modes" newline bitfld.long 0x4 24. "GPRAMPDS,Graphic peripherals (LTDC/GFXMMU) SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: Graphic peripherals SRAM content retained in..,1: Graphic peripherals SRAM content lost in Stop.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." newline bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" newline bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" bitfld.long 0x4 7. "DC2RAMPDS,DCACHE2 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE2 SRAM content retained in Stop modes,1: DCACHE2 SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "PWR" base ad:0x46020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA32 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end tree "SEC_PWR" base ad:0x56020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA32 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "PWR" base ad:0x46020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 25. "DSIRAMPDS,DSI SRAM power-down in Stop modes (Stop 0 1)" "0: DSI SRAM content retained in Stop 0 and Stop 1..,1: DSI SRAM content lost in Stop 0 and Stop 1 modes" newline bitfld.long 0x4 24. "GPRAMPDS,Graphic peripherals (LTDC/GFXMMU) SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: Graphic peripherals SRAM content retained in..,1: Graphic peripherals SRAM content lost in Stop.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA32 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 7. "DC2RAMPDS,DCACHE2 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE2 SRAM content retained in Stop modes,1: DCACHE2 SRAM content lost in Stop modes" bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" newline bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" newline bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" newline bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end tree "SEC_PWR" base ad:0x56020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 25. "DSIRAMPDS,DSI SRAM power-down in Stop modes (Stop 0 1)" "0: DSI SRAM content retained in Stop 0 and Stop 1..,1: DSI SRAM content lost in Stop 0 and Stop 1 modes" newline bitfld.long 0x4 24. "GPRAMPDS,Graphic peripherals (LTDC/GFXMMU) SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: Graphic peripherals SRAM content retained in..,1: Graphic peripherals SRAM content lost in Stop.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA32 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 7. "DC2RAMPDS,DCACHE2 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE2 SRAM content retained in Stop modes,1: DCACHE2 SRAM content lost in Stop modes" bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" newline bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" newline bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" newline bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "PWR" base ad:0x46020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 25. "DSIRAMPDS,DSI SRAM power-down in Stop modes (Stop 0 1)" "0: DSI SRAM content retained in Stop 0 and Stop 1..,1: DSI SRAM content lost in Stop 0 and Stop 1 modes" newline bitfld.long 0x4 24. "GPRAMPDS,Graphic peripherals (LTDC/GFXMMU) SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: Graphic peripherals SRAM content retained in..,1: Graphic peripherals SRAM content lost in Stop.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." newline bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" newline bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" bitfld.long 0x4 7. "DC2RAMPDS,DCACHE2 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE2 SRAM content retained in Stop modes,1: DCACHE2 SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end tree "SEC_PWR" base ad:0x56020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 25. "DSIRAMPDS,DSI SRAM power-down in Stop modes (Stop 0 1)" "0: DSI SRAM content retained in Stop 0 and Stop 1..,1: DSI SRAM content lost in Stop 0 and Stop 1 modes" newline bitfld.long 0x4 24. "GPRAMPDS,Graphic peripherals (LTDC/GFXMMU) SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: Graphic peripherals SRAM content retained in..,1: Graphic peripherals SRAM content lost in Stop.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." newline bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" newline bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" bitfld.long 0x4 7. "DC2RAMPDS,DCACHE2 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE2 SRAM content retained in Stop modes,1: DCACHE2 SRAM content lost in Stop modes" newline bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" newline bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" newline bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "PWR" base ad:0x46020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 25. "DSIRAMPDS,DSI SRAM power-down in Stop modes (Stop 0 1)" "0: DSI SRAM content retained in Stop 0 and Stop 1..,1: DSI SRAM content lost in Stop 0 and Stop 1 modes" newline bitfld.long 0x4 24. "GPRAMPDS,Graphic peripherals (LTDC/GFXMMU) SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: Graphic peripherals SRAM content retained in..,1: Graphic peripherals SRAM content lost in Stop.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA32 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 7. "DC2RAMPDS,DCACHE2 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE2 SRAM content retained in Stop modes,1: DCACHE2 SRAM content lost in Stop modes" bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" newline bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" newline bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" newline bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end tree "SEC_PWR" base ad:0x56020800 group.long 0x0++0x3B line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 12. "SRAM5PD,SRAM5 power down" "0: SRAM5 powered on,1: SRAM5 powered off" bitfld.long 0x0 11. "SRAM4PD,SRAM4 power down" "0: SRAM4 powered on,1: SRAM4 powered off" newline bitfld.long 0x0 10. "SRAM3PD,SRAM3 power down" "0: SRAM3 powered on,1: SRAM3 powered off" bitfld.long 0x0 9. "SRAM2PD,SRAM2 power down" "0: SRAM2 powered on,1: SRAM2 powered off" newline bitfld.long 0x0 8. "SRAM1PD,SRAM1 power down" "0: SRAM1 powered on,1: SRAM1 powered off" bitfld.long 0x0 7. "ULPMEN,BOR ultra-low power mode" "0: BOR operating in continuous (normal) mode in..,1: BOR operating in discontinuous (ultra-low power).." newline bitfld.long 0x0 6. "RRSB2,SRAM2 page 2 retention in Stop 3 and Standby modes" "0: SRAM2 page2 content not retained in Stop3 and..,1: SRAM2 page2 content retained in Stop 3 and.." bitfld.long 0x0 5. "RRSB1,SRAM2 page 1 retention in Stop 3 and Standby modes" "0: SRAM2 page1 content not retained in Stop 3 and..,1: SRAM2 page1 content retained in Stop 3 and.." newline bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Stop 3 mode,?,?,?,?" line.long 0x4 "PWR_CR2,PWR control register 2" bitfld.long 0x4 31. "SRDRUN,SmartRun domain in Run mode" "0: SmartRun domain AHB3 and APB3 clocks disabled by..,1: SmartRun domain AHB3 and APB3 clocks kept.." bitfld.long 0x4 25. "DSIRAMPDS,DSI SRAM power-down in Stop modes (Stop 0 1)" "0: DSI SRAM content retained in Stop 0 and Stop 1..,1: DSI SRAM content lost in Stop 0 and Stop 1 modes" newline bitfld.long 0x4 24. "GPRAMPDS,Graphic peripherals (LTDC/GFXMMU) SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: Graphic peripherals SRAM content retained in..,1: Graphic peripherals SRAM content lost in Stop.." bitfld.long 0x4 23. "SRAM3PDS8,SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 8 content retained in Stop modes,1: SRAM3 page 8 content lost in Stop modes" newline bitfld.long 0x4 22. "SRAM3PDS7,SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 7 content retained in Stop modes,1: SRAM3 page 7 content lost in Stop modes" bitfld.long 0x4 21. "SRAM3PDS6,SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 6 content retained in Stop modes,1: SRAM3 page 6 content lost in Stop modes" newline bitfld.long 0x4 20. "SRAM3PDS5,SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 5 content retained in Stop modes,1: SRAM3 page 5 content lost in Stop modes" bitfld.long 0x4 19. "SRAM3PDS4,SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 4 content retained in Stop modes,1: SRAM3 page 4 content lost in Stop modes" newline bitfld.long 0x4 18. "SRAM3PDS3,SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 3 content retained in Stop modes,1: SRAM3 page 3 content lost in Stop modes" bitfld.long 0x4 17. "SRAM3PDS2,SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 2 content retained in Stop modes,1: SRAM3 page 2 content lost in Stop modes" newline bitfld.long 0x4 16. "SRAM3PDS1,SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM3 page 1 content retained in Stop modes,1: SRAM3 page 1 content lost in Stop modes" bitfld.long 0x4 14. "FLASHFWU,Flash memory fast wakeup from Stop 0 and Stop 1 modes" "0: Flash memory enters low-power mode in Stop 0 and..,1: Flash memory remains in normal mode in Stop 0.." newline bitfld.long 0x4 13. "SRAM4FWU,SRAM4 fast wakeup from Stop 0 Stop 1 and Stop 2 modes" "0: SRAM4 enters low-power mode in Stop 0 1 and 2..,1: SRAM4 remains in normal mode in Stop 0 1 and 2.." bitfld.long 0x4 12. "PKARAMPDS,PKA32 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: PKA SRAM content retained in Stop modes,1: PKA SRAM content lost in Stop modes" newline bitfld.long 0x4 11. "PRAMPDS,FMAC FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0/1/2/3)" "0: FMAC FDCAN and USB peripherals SRAM content..,1: FMAC FDCAN and USB peripherals SRAM content lost.." bitfld.long 0x4 10. "DMA2DRAMPDS,DMA2D SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DMA2D SRAM content retained in Stop modes,1: DMA2D SRAM content lost in Stop modes" newline bitfld.long 0x4 9. "DC1RAMPDS,DCACHE1 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE1 SRAM content retained in Stop modes,1: DCACHE1 SRAM content lost in Stop modes" bitfld.long 0x4 8. "ICRAMPDS,ICACHE SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: ICACHE SRAM content retained in Stop modes,1: ICACHE SRAM content lost in Stop modes" newline bitfld.long 0x4 7. "DC2RAMPDS,DCACHE2 SRAM power-down in Stop modes (Stop 0 1 2 3)" "0: DCACHE2 SRAM content retained in Stop modes,1: DCACHE2 SRAM content lost in Stop modes" bitfld.long 0x4 6. "SRAM4PDS,SRAM4 power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM4 content retained in Stop modes,1: SRAM4 content lost in Stop modes" newline bitfld.long 0x4 5. "SRAM2PDS2,SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 2 content retained in Stop modes,1: SRAM2 page 2 content lost in Stop modes" bitfld.long 0x4 4. "SRAM2PDS1,SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0 1 2)" "0: SRAM2 page 1 content retained in Stop modes,1: SRAM2 page 1 content lost in Stop modes" newline bitfld.long 0x4 2. "SRAM1PDS3,SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 3 content retained in Stop modes,1: SRAM1 page 3 content lost in Stop modes" bitfld.long 0x4 1. "SRAM1PDS2,SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 2 content retained in Stop modes,1: SRAM1 page 2 content lost in Stop modes" newline bitfld.long 0x4 0. "SRAM1PDS1,SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0 1 2 3)" "0: SRAM1 page 1 content retained in Stop modes,1: SRAM1 page 1 content lost in Stop modes" line.long 0x8 "PWR_CR3,PWR control register 3" bitfld.long 0x8 2. "FSTEN,Fast soft start" "0: LDO/SMPS fast startup disabled (limited inrush..,1: LDO/SMPS fast startup enabled" bitfld.long 0x8 1. "REGSEL,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0xC "PWR_VOSR,PWR voltage scaling register" bitfld.long 0xC 20. "USBBOOSTEN,USB EPOD booster enable" "0: USB booster disabled,1: USB booster enabled" bitfld.long 0xC 19. "USBPWREN,USB power enable" "0: USB power disabled,1: USB power enabled" newline bitfld.long 0xC 18. "BOOSTEN,EPOD booster enable" "0: Booster disabled,1: Booster enabled" bitfld.long 0xC 16.--17. "VOS,Voltage scaling range selection" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency). This value cannot.." newline rbitfld.long 0xC 15. "VOSRDY,Ready bit for VCORE voltage scaling output selection" "0: Not ready voltage level < VOS selected level,1: Ready voltage level >= VOS selected level" rbitfld.long 0xC 14. "BOOSTRDY,EPOD booster ready" "0: Power booster not ready,1: Power booster ready" newline rbitfld.long 0xC 13. "USBBOOSTRDY,USB EPOD booster ready" "0: USB power booster not ready,1: USB power booster ready" line.long 0x10 "PWR_SVMCR,PWR supply voltage monitoring control register" bitfld.long 0x10 30. "ASV,VDDA independent analog supply valid" "0: VDDA not present: logical and electrical..,1: VDDA valid" bitfld.long 0x10 29. "IO2SV,VDDIO2 independent I/Os supply valid" "0: VDDIO2 not present: logical and electrical..,1: VDDIO2 valid" newline bitfld.long 0x10 28. "USV,VDDUSB independent USB supply valid" "0: VDDUSB not present: logical and electrical..,1: VDDUSB valid" bitfld.long 0x10 27. "AVM2EN,VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)" "0: VDDA voltage monitor 2 disabled,1: VDDA voltage monitor 2 enabled" newline bitfld.long 0x10 26. "AVM1EN,VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)" "0: VDDA voltage monitor 1 disabled,1: VDDA voltage monitor 1 enabled" bitfld.long 0x10 25. "IO2VMEN,VDDIO2 independent I/Os voltage monitor enable" "0: VDDIO2 voltage monitor disabled,1: VDDIO2 voltage monitor enabled" newline bitfld.long 0x10 24. "UVMEN,VDDUSB independent USB voltage monitor enable" "0: VDDUSB voltage monitor disabled,1: VDDUSB voltage monitor enabled" bitfld.long 0x10 5.--7. "PVDLS,Power voltage detector level selection" "0: VPVD0 around 2.0 V,1: VPVD1 around 2.2 V,2: VPVD2 around 2.4 V,3: VPVD3 around 2.5 V,4: VPVD4 around 2.6 V,5: VPVD5 around 2.8 V,6: VPVD6 around 2.9 V,7: External input analog voltage PVD_IN (compared.." newline bitfld.long 0x10 4. "PVDE,Power voltage detector enable" "0: Power voltage detector disabled,1: Power voltage detector enabled" line.long 0x14 "PWR_WUCR1,PWR wakeup control register 1" bitfld.long 0x14 7. "WUPEN8,Wakeup pin WKUP8 enable" "0: Wakeup pin WKUP8 disabled,1: Wakeup pin WKUP8 enabled" bitfld.long 0x14 6. "WUPEN7,Wakeup pin WKUP7 enable" "0: Wakeup pin WKUP7 disabled,1: Wakeup pin WKUP7 enabled" newline bitfld.long 0x14 5. "WUPEN6,Wakeup pin WKUP6 enable" "0: Wakeup pin WKUP6 disabled,1: Wakeup pin WKUP6 enabled" bitfld.long 0x14 4. "WUPEN5,Wakeup pin WKUP5 enable" "0: Wakeup pin WKUP5 disabled,1: Wakeup pin WKUP5 enabled" newline bitfld.long 0x14 3. "WUPEN4,Wakeup pin WKUP4 enable" "0: Wakeup pin WKUP4 disabled,1: Wakeup pin WKUP4 enabled" bitfld.long 0x14 2. "WUPEN3,Wakeup pin WKUP3 enable" "0: Wakeup pin WKUP3 disabled,1: Wakeup pin WKUP3 enabled" newline bitfld.long 0x14 1. "WUPEN2,Wakeup pin WKUP2 enable" "0: Wakeup pin WKUP2 disabled,1: Wakeup pin WKUP2 enabled" bitfld.long 0x14 0. "WUPEN1,Wakeup pin WKUP1 enable" "0: Wakeup pin WKUP1 disabled,1: Wakeup pin WKUP1 enabled" line.long 0x18 "PWR_WUCR2,PWR wakeup control register 2" bitfld.long 0x18 7. "WUPP8,Wakeup pin WKUP8 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 6. "WUPP7,Wakeup pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 5. "WUPP6,Wakeup pin WKUP6 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 4. "WUPP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 3. "WUPP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 2. "WUPP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x18 1. "WUPP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x18 0. "WUPP1,Wakeup pin WKUP1 polarity." "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" line.long 0x1C "PWR_WUCR3,PWR wakeup control register 3" bitfld.long 0x1C 14.--15. "WUSEL8,Wakeup pin WKUP8 selection" "0: WKUP8_0,1: WKUP8_1,2: WKUP8_2,3: WKUP8_3" bitfld.long 0x1C 12.--13. "WUSEL7,Wakeup pin WKUP7 selection" "0: WKUP7_0,1: WKUP7_1,2: WKUP7_2,3: WKUP7_3" newline bitfld.long 0x1C 10.--11. "WUSEL6,Wakeup pin WKUP6 selection" "0: WKUP6_0,1: WKUP6_1,2: WKUP6_2,3: WKUP6_3" bitfld.long 0x1C 8.--9. "WUSEL5,Wakeup pin WKUP5 selection" "0: WKUP5_0,1: WKUP5_1,2: WKUP5_2,3: WKUP5_3" newline bitfld.long 0x1C 6.--7. "WUSEL4,Wakeup pin WKUP4 selection" "0: WKUP4_0,1: WKUP4_1,2: WKUP4_2,3: WKUP4_3" bitfld.long 0x1C 4.--5. "WUSEL3,Wakeup pin WKUP3 selection" "0: WKUP3_0,1: WKUP3_1,2: WKUP3_2,3: WKUP3_3" newline bitfld.long 0x1C 2.--3. "WUSEL2,Wakeup pin WKUP2 selection" "0: WKUP2_0,1: WKUP2_1,2: WKUP2_2,3: WKUP2_3" bitfld.long 0x1C 0.--1. "WUSEL1,Wakeup pin WKUP1 selection" "0: WKUP0_0,1: WKUP0_1,2: WKUP0_2,3: WKUP0_3" line.long 0x20 "PWR_BDCR1,PWR Backup domain control register 1" bitfld.long 0x20 4. "MONEN,Backup domain voltage and temperature monitoring enable" "0: Backup domain voltage and temperature monitoring..,1: Backup domain voltage and temperature monitoring.." bitfld.long 0x20 0. "BREN,Backup RAM retention in Standby and VBAT modes" "0: Backup RAM content lost in Standby and VBAT modes,1: Backup RAM content preserved in Standby and VBAT.." line.long 0x24 "PWR_BDCR2,PWR Backup domain control register 2" bitfld.long 0x24 1. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 kOhm resistor,1: Charge VBAT through a 1.5 kOhm resistor" bitfld.long 0x24 0. "VBE,VBAT charging enable" "0: VBAT battery charging disabled,1: VBAT battery charging enabled" line.long 0x28 "PWR_DBPR,PWR disable Backup domain register" bitfld.long 0x28 0. "DBP,Disable Backup domain write protection" "0: Write access to Backup domain disabled,1: Write access to Backup domain enabled" line.long 0x2C "PWR_UCPDR,PWR USB Type-C and Power Delivery register" bitfld.long 0x2C 1. "UCPD_STBY,UCPD Standby mode" "0,1" bitfld.long 0x2C 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled on.." line.long 0x30 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x30 15. "APCSEC,Pull-up/pull-down secure protection" "0: PWR_APCR can be read and written with secure or..,1: PWR_APCR can be read and written only with.." bitfld.long 0x30 14. "VBSEC,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPR can be read and.." newline bitfld.long 0x30 13. "VDMSEC,Voltage detection and monitoring secure protection" "0: PWR_SVMCR and PWR_CR3 can be read and written..,1: PWR_SVMCR and PWR_CR3 can be read and written.." bitfld.long 0x30 12. "LPMSEC,Low-power modes secure protection" "0: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be..,1: PWR_CR1 PWR_CR2 and CSSF in the PWR_SR can be.." newline bitfld.long 0x30 7. "WUP8SEC,WUP8 secure protection" "0: Bits related to the WKUP8 pin in PWR_WUCR1..,1: Bits related to the WKUP8 pin in PWR_WUCR1.." bitfld.long 0x30 6. "WUP7SEC,WUP7 secure protection" "0: Bits related to the WKUP7 pin in PWR_WUCR1..,1: Bits related to the WKUP7 pin in PWR_WUCR1.." newline bitfld.long 0x30 5. "WUP6SEC,WUP6 secure protection" "0: Bits related to the WKUP6 pin in PWR_WUCR1..,1: Bits related to the WKUP6 pin in PWR_WUCR1.." bitfld.long 0x30 4. "WUP5SEC,WUP5 secure protection" "0: Bits related to the WKUP5 pin in PWR_WUCR1..,1: Bits related to the WKUP5 pin in PWR_WUCR1.." newline bitfld.long 0x30 3. "WUP4SEC,WUP4 secure protection" "0: Bits related to the WKUP4 pin in PWR_WUCR1..,1: Bits related to the WKUP4 pin in PWR_WUCR1.." bitfld.long 0x30 2. "WUP3SEC,WUP3 secure protection" "0: Bits related to the WKUP3 pin in PWR_WUCR1..,1: Bits related to the WKUP3 pin in PWR_WUCR1.." newline bitfld.long 0x30 1. "WUP2SEC,WUP2 secure protection" "0: Bits related to the WKUP2 pin in PWR_WUCR1..,1: Bits related to the WKUP2 pin in PWR_WUCR1.." bitfld.long 0x30 0. "WUP1SEC,WUP1 secure protection" "0: Bits related to the WKUP1 pin in PWR_WUCR1..,1: Bits related to the WKUP1 pin in PWR_WUCR1.." line.long 0x34 "PWR_PRIVCFGR,PWR privilege control register" bitfld.long 0x34 1. "NSPRIV,PWR non-secure functions privilege configuration" "0: Read and write to PWR non-secure functions can..,1: Read and write to PWR non-secure functions can.." bitfld.long 0x34 0. "SPRIV,PWR secure functions privilege configuration" "0: Read and write to PWR secure functions can be..,1: Read and write to PWR secure functions can be.." line.long 0x38 "PWR_SR,PWR status register" rbitfld.long 0x38 2. "SBF,Standby flag" "0: The device did not enter Standby mode.,1: The device entered Standby mode." rbitfld.long 0x38 1. "STOPF,Stop flag" "0: The device did not enter any Stop mode.,1: The device entered a Stop mode." newline bitfld.long 0x38 0. "CSSF,Clear Stop and Standby flags" "0,1" rgroup.long 0x3C++0xB line.long 0x0 "PWR_SVMSR,PWR supply voltage monitoring status register" bitfld.long 0x0 27. "VDDA2RDY,VDDA ready versus 1.8V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." bitfld.long 0x0 26. "VDDA1RDY,VDDA ready versus 1.6V voltage monitor" "0: VDDA is below the threshold of the VDDA voltage..,1: VDDA is equal or above the threshold of the VDDA.." newline bitfld.long 0x0 25. "VDDIO2RDY,VDDIO2 ready" "0: VDDIO2 is below the threshold of the VDDIO2..,1: VDDIO2 is equal or above the threshold of the.." bitfld.long 0x0 24. "VDDUSBRDY,VDDUSB ready" "0: VDDUSB is below the threshold of the VDDUSB..,1: VDDUSB is equal or above the threshold of the.." newline bitfld.long 0x0 16.--17. "ACTVOS,VOS currently applied to VCORE" "0: Range 4 (lowest power),1: Range 3,2: Range 2,3: Range 1 (highest frequency)" bitfld.long 0x0 15. "ACTVOSRDY,Voltage level ready for currently used VOS" "0: VCORE is above or below the current voltage..,1: VCORE is equal to the current voltage scaling.." newline bitfld.long 0x0 4. "PVDO,VDD voltage detector output" "0: VDD is equal or above the PVD threshold selected..,1: VDD is below the PVD threshold selected by.." bitfld.long 0x0 1. "REGS,Regulator selection" "0: LDO selected,1: SMPS selected" line.long 0x4 "PWR_BDSR,PWR Backup domain status register" bitfld.long 0x4 3. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature < high threshold,1: Temperature >= low threshold" bitfld.long 0x4 2. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature > low threshold,1: Temperature <= low threshold" newline bitfld.long 0x4 1. "VBATH,Backup domain voltage level monitoring versus high threshold" "0: Backup domain voltage level < high threshold,1: Backup domain voltage level >= low threshold" line.long 0x8 "PWR_WUSR,PWR wakeup status register" bitfld.long 0x8 7. "WUF8,Wakeup flag 8" "0,1" bitfld.long 0x8 6. "WUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x8 5. "WUF6,Wakeup flag 6" "0,1" bitfld.long 0x8 4. "WUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x8 3. "WUF4,Wakeup flag 4" "0,1" bitfld.long 0x8 2. "WUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x8 1. "WUF2,Wakeup flag 2" "0,1" bitfld.long 0x8 0. "WUF1,Wakeup flag 1" "0,1" wgroup.long 0x48++0x3 line.long 0x0 "PWR_WUSCR,PWR wakeup status clear register" bitfld.long 0x0 7. "CWUF8,Wakeup flag 8" "0,1" bitfld.long 0x0 6. "CWUF7,Wakeup flag 7" "0,1" newline bitfld.long 0x0 5. "CWUF6,Wakeup flag 6" "0,1" bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1" newline bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1" bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1" newline bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1" bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1" group.long 0x4C++0x53 line.long 0x0 "PWR_APCR,PWR apply pull configuration register" bitfld.long 0x0 0. "APC,Apply pull-up and pull-down configuration" "0,1" line.long 0x4 "PWR_PUCRA,PWR port A pull-up control register" bitfld.long 0x4 15. "PU15,Port A pull-up bit 15" "0,1" bitfld.long 0x4 13. "PU13," "0,1" newline bitfld.long 0x4 12. "PU12," "0,1" bitfld.long 0x4 11. "PU11," "0,1" newline bitfld.long 0x4 10. "PU10," "0,1" bitfld.long 0x4 9. "PU9," "0,1" newline bitfld.long 0x4 8. "PU8," "0,1" bitfld.long 0x4 7. "PU7," "0,1" newline bitfld.long 0x4 6. "PU6," "0,1" bitfld.long 0x4 5. "PU5," "0,1" newline bitfld.long 0x4 4. "PU4," "0,1" bitfld.long 0x4 3. "PU3," "0,1" newline bitfld.long 0x4 2. "PU2," "0,1" bitfld.long 0x4 1. "PU1," "0,1" newline bitfld.long 0x4 0. "PU0," "0,1" line.long 0x8 "PWR_PDCRA,PWR port A pull-down control register" bitfld.long 0x8 14. "PD14,Port A pull-down bit 14" "0,1" bitfld.long 0x8 12. "PD12," "0,1" newline bitfld.long 0x8 11. "PD11," "0,1" bitfld.long 0x8 10. "PD10," "0,1" newline bitfld.long 0x8 9. "PD9," "0,1" bitfld.long 0x8 8. "PD8," "0,1" newline bitfld.long 0x8 7. "PD7," "0,1" bitfld.long 0x8 6. "PD6," "0,1" newline bitfld.long 0x8 5. "PD5," "0,1" bitfld.long 0x8 4. "PD4," "0,1" newline bitfld.long 0x8 3. "PD3," "0,1" bitfld.long 0x8 2. "PD2," "0,1" newline bitfld.long 0x8 1. "PD1," "0,1" bitfld.long 0x8 0. "PD0," "0,1" line.long 0xC "PWR_PUCRB,PWR port B pull-up control register" bitfld.long 0xC 15. "PU15," "0,1" bitfld.long 0xC 14. "PU14," "0,1" newline bitfld.long 0xC 13. "PU13," "0,1" bitfld.long 0xC 12. "PU12," "0,1" newline bitfld.long 0xC 11. "PU11," "0,1" bitfld.long 0xC 10. "PU10," "0,1" newline bitfld.long 0xC 9. "PU9," "0,1" bitfld.long 0xC 8. "PU8," "0,1" newline bitfld.long 0xC 7. "PU7," "0,1" bitfld.long 0xC 6. "PU6," "0,1" newline bitfld.long 0xC 5. "PU5," "0,1" bitfld.long 0xC 4. "PU4," "0,1" newline bitfld.long 0xC 3. "PU3," "0,1" bitfld.long 0xC 2. "PU2," "0,1" newline bitfld.long 0xC 1. "PU1," "0,1" bitfld.long 0xC 0. "PU0," "0,1" line.long 0x10 "PWR_PDCRB,PWR port B pull-down control register" bitfld.long 0x10 15. "PD15," "0,1" bitfld.long 0x10 14. "PD14," "0,1" newline bitfld.long 0x10 13. "PD13," "0,1" bitfld.long 0x10 12. "PD12," "0,1" newline bitfld.long 0x10 11. "PD11," "0,1" bitfld.long 0x10 10. "PD10," "0,1" newline bitfld.long 0x10 9. "PD9," "0,1" bitfld.long 0x10 8. "PD8," "0,1" newline bitfld.long 0x10 7. "PD7," "0,1" bitfld.long 0x10 6. "PD6," "0,1" newline bitfld.long 0x10 5. "PD5," "0,1" bitfld.long 0x10 3. "PD3," "0,1" newline bitfld.long 0x10 2. "PD2," "0,1" bitfld.long 0x10 1. "PD1," "0,1" newline bitfld.long 0x10 0. "PD0," "0,1" line.long 0x14 "PWR_PUCRC,Power port C pull up control register" bitfld.long 0x14 15. "PU15,PU15" "0,1" bitfld.long 0x14 14. "PU14,PU14" "0,1" newline bitfld.long 0x14 13. "PU13,PU13" "0,1" bitfld.long 0x14 12. "PU12,PU12" "0,1" newline bitfld.long 0x14 11. "PU11,PU11" "0,1" bitfld.long 0x14 10. "PU10,PU10" "0,1" newline bitfld.long 0x14 9. "PU9,PU9" "0,1" bitfld.long 0x14 8. "PU8,PU8" "0,1" newline bitfld.long 0x14 7. "PU7,PU7" "0,1" bitfld.long 0x14 6. "PU6,PU6" "0,1" newline bitfld.long 0x14 5. "PU5,PU5" "0,1" bitfld.long 0x14 4. "PU4,PU4" "0,1" newline bitfld.long 0x14 3. "PU3,PU3" "0,1" bitfld.long 0x14 2. "PU2,PU2" "0,1" newline bitfld.long 0x14 1. "PU1,PU1" "0,1" bitfld.long 0x14 0. "PU0,PU0" "0,1" line.long 0x18 "PWR_PDCRC,PWR port C pull-down control register" bitfld.long 0x18 15. "PD15," "0,1" bitfld.long 0x18 14. "PD14," "0,1" newline bitfld.long 0x18 13. "PD13," "0,1" bitfld.long 0x18 12. "PD12," "0,1" newline bitfld.long 0x18 11. "PD11," "0,1" bitfld.long 0x18 10. "PD10," "0,1" newline bitfld.long 0x18 9. "PD9," "0,1" bitfld.long 0x18 8. "PD8," "0,1" newline bitfld.long 0x18 7. "PD7," "0,1" bitfld.long 0x18 6. "PD6," "0,1" newline bitfld.long 0x18 5. "PD5," "0,1" bitfld.long 0x18 4. "PD4," "0,1" newline bitfld.long 0x18 3. "PD3," "0,1" bitfld.long 0x18 2. "PD2," "0,1" newline bitfld.long 0x18 1. "PD1," "0,1" bitfld.long 0x18 0. "PD0," "0,1" line.long 0x1C "PWR_PUCRD,PWR port D pull-up control register" bitfld.long 0x1C 15. "PU15," "0,1" bitfld.long 0x1C 14. "PU14," "0,1" newline bitfld.long 0x1C 13. "PU13," "0,1" bitfld.long 0x1C 12. "PU12," "0,1" newline bitfld.long 0x1C 11. "PU11," "0,1" bitfld.long 0x1C 10. "PU10," "0,1" newline bitfld.long 0x1C 9. "PU9," "0,1" bitfld.long 0x1C 8. "PU8," "0,1" newline bitfld.long 0x1C 7. "PU7," "0,1" bitfld.long 0x1C 6. "PU6," "0,1" newline bitfld.long 0x1C 5. "PU5," "0,1" bitfld.long 0x1C 4. "PU4," "0,1" newline bitfld.long 0x1C 3. "PU3," "0,1" bitfld.long 0x1C 2. "PU2," "0,1" newline bitfld.long 0x1C 1. "PU1," "0,1" bitfld.long 0x1C 0. "PU0," "0,1" line.long 0x20 "PWR_PDCRD,PWR port D pull-down control register" bitfld.long 0x20 15. "PD15," "0,1" bitfld.long 0x20 14. "PD14," "0,1" newline bitfld.long 0x20 13. "PD13," "0,1" bitfld.long 0x20 12. "PD12," "0,1" newline bitfld.long 0x20 11. "PD11," "0,1" bitfld.long 0x20 10. "PD10," "0,1" newline bitfld.long 0x20 9. "PD9," "0,1" bitfld.long 0x20 8. "PD8," "0,1" newline bitfld.long 0x20 7. "PD7," "0,1" bitfld.long 0x20 6. "PD6," "0,1" newline bitfld.long 0x20 5. "PD5," "0,1" bitfld.long 0x20 4. "PD4," "0,1" newline bitfld.long 0x20 3. "PD3," "0,1" bitfld.long 0x20 2. "PD2," "0,1" newline bitfld.long 0x20 1. "PD1," "0,1" bitfld.long 0x20 0. "PD0," "0,1" line.long 0x24 "PWR_PUCRE,PWR port E pull-up control register" bitfld.long 0x24 15. "PU15," "0,1" bitfld.long 0x24 14. "PU14," "0,1" newline bitfld.long 0x24 13. "PU13," "0,1" bitfld.long 0x24 12. "PU12," "0,1" newline bitfld.long 0x24 11. "PU11," "0,1" bitfld.long 0x24 10. "PU10," "0,1" newline bitfld.long 0x24 9. "PU9," "0,1" bitfld.long 0x24 8. "PU8," "0,1" newline bitfld.long 0x24 7. "PU7," "0,1" bitfld.long 0x24 6. "PU6," "0,1" newline bitfld.long 0x24 5. "PU5," "0,1" bitfld.long 0x24 4. "PU4," "0,1" newline bitfld.long 0x24 3. "PU3," "0,1" bitfld.long 0x24 2. "PU2," "0,1" newline bitfld.long 0x24 1. "PU1," "0,1" bitfld.long 0x24 0. "PU0," "0,1" line.long 0x28 "PWR_PDCRE,PWR port E pull-down control register" bitfld.long 0x28 15. "PD15," "0,1" bitfld.long 0x28 14. "PD14," "0,1" newline bitfld.long 0x28 13. "PD13," "0,1" bitfld.long 0x28 12. "PD12," "0,1" newline bitfld.long 0x28 11. "PD11," "0,1" bitfld.long 0x28 10. "PD10," "0,1" newline bitfld.long 0x28 9. "PD9," "0,1" bitfld.long 0x28 8. "PD8," "0,1" newline bitfld.long 0x28 7. "PD7," "0,1" bitfld.long 0x28 6. "PD6," "0,1" newline bitfld.long 0x28 5. "PD5," "0,1" bitfld.long 0x28 4. "PD4," "0,1" newline bitfld.long 0x28 3. "PD3," "0,1" bitfld.long 0x28 2. "PD2," "0,1" newline bitfld.long 0x28 1. "PD1," "0,1" bitfld.long 0x28 0. "PD0," "0,1" line.long 0x2C "PWR_PUCRF,PWR port F pull-up control register" bitfld.long 0x2C 15. "PU15," "0,1" bitfld.long 0x2C 14. "PU14," "0,1" newline bitfld.long 0x2C 13. "PU13," "0,1" bitfld.long 0x2C 12. "PU12," "0,1" newline bitfld.long 0x2C 11. "PU11," "0,1" bitfld.long 0x2C 10. "PU10," "0,1" newline bitfld.long 0x2C 9. "PU9," "0,1" bitfld.long 0x2C 8. "PU8," "0,1" newline bitfld.long 0x2C 7. "PU7," "0,1" bitfld.long 0x2C 6. "PU6," "0,1" newline bitfld.long 0x2C 5. "PU5," "0,1" bitfld.long 0x2C 4. "PU4," "0,1" newline bitfld.long 0x2C 3. "PU3," "0,1" bitfld.long 0x2C 2. "PU2," "0,1" newline bitfld.long 0x2C 1. "PU1," "0,1" bitfld.long 0x2C 0. "PU0," "0,1" line.long 0x30 "PWR_PDCRF,PWR port F pull-down control register" bitfld.long 0x30 15. "PD15," "0,1" bitfld.long 0x30 14. "PD14," "0,1" newline bitfld.long 0x30 13. "PD13," "0,1" bitfld.long 0x30 12. "PD12," "0,1" newline bitfld.long 0x30 11. "PD11," "0,1" bitfld.long 0x30 10. "PD10," "0,1" newline bitfld.long 0x30 9. "PD9," "0,1" bitfld.long 0x30 8. "PD8," "0,1" newline bitfld.long 0x30 7. "PD7," "0,1" bitfld.long 0x30 6. "PD6," "0,1" newline bitfld.long 0x30 5. "PD5," "0,1" bitfld.long 0x30 4. "PD4," "0,1" newline bitfld.long 0x30 3. "PD3," "0,1" bitfld.long 0x30 2. "PD2," "0,1" newline bitfld.long 0x30 1. "PD1," "0,1" bitfld.long 0x30 0. "PD0," "0,1" line.long 0x34 "PWR_PUCRG,PWR port G pull-up control register" bitfld.long 0x34 15. "PU15," "0,1" bitfld.long 0x34 14. "PU14," "0,1" newline bitfld.long 0x34 13. "PU13," "0,1" bitfld.long 0x34 12. "PU12," "0,1" newline bitfld.long 0x34 11. "PU11," "0,1" bitfld.long 0x34 10. "PU10," "0,1" newline bitfld.long 0x34 9. "PU9," "0,1" bitfld.long 0x34 8. "PU8," "0,1" newline bitfld.long 0x34 7. "PU7," "0,1" bitfld.long 0x34 6. "PU6," "0,1" newline bitfld.long 0x34 5. "PU5," "0,1" bitfld.long 0x34 4. "PU4," "0,1" newline bitfld.long 0x34 3. "PU3," "0,1" bitfld.long 0x34 2. "PU2," "0,1" newline bitfld.long 0x34 1. "PU1," "0,1" bitfld.long 0x34 0. "PU0," "0,1" line.long 0x38 "PWR_PDCRG,PWR port G pull-down control register" bitfld.long 0x38 15. "PD15," "0,1" bitfld.long 0x38 14. "PD14," "0,1" newline bitfld.long 0x38 13. "PD13," "0,1" bitfld.long 0x38 12. "PD12," "0,1" newline bitfld.long 0x38 11. "PD11," "0,1" bitfld.long 0x38 10. "PD10," "0,1" newline bitfld.long 0x38 9. "PD9," "0,1" bitfld.long 0x38 8. "PD8," "0,1" newline bitfld.long 0x38 7. "PD7," "0,1" bitfld.long 0x38 6. "PD6," "0,1" newline bitfld.long 0x38 5. "PD5," "0,1" bitfld.long 0x38 4. "PD4," "0,1" newline bitfld.long 0x38 3. "PD3," "0,1" bitfld.long 0x38 2. "PD2," "0,1" newline bitfld.long 0x38 1. "PD1," "0,1" bitfld.long 0x38 0. "PD0," "0,1" line.long 0x3C "PWR_PUCRH,PWR port H pull-up control register" bitfld.long 0x3C 15. "PU15," "0,1" bitfld.long 0x3C 14. "PU14," "0,1" newline bitfld.long 0x3C 13. "PU13," "0,1" bitfld.long 0x3C 12. "PU12," "0,1" newline bitfld.long 0x3C 11. "PU11," "0,1" bitfld.long 0x3C 10. "PU10," "0,1" newline bitfld.long 0x3C 9. "PU9," "0,1" bitfld.long 0x3C 8. "PU8," "0,1" newline bitfld.long 0x3C 7. "PU7," "0,1" bitfld.long 0x3C 6. "PU6," "0,1" newline bitfld.long 0x3C 5. "PU5," "0,1" bitfld.long 0x3C 4. "PU4," "0,1" newline bitfld.long 0x3C 3. "PU3," "0,1" bitfld.long 0x3C 2. "PU2," "0,1" newline bitfld.long 0x3C 1. "PU1," "0,1" bitfld.long 0x3C 0. "PU0," "0,1" line.long 0x40 "PWR_PDCRH,PWR port H pull-down control register" bitfld.long 0x40 15. "PD15," "0,1" bitfld.long 0x40 14. "PD14," "0,1" newline bitfld.long 0x40 13. "PD13," "0,1" bitfld.long 0x40 12. "PD12," "0,1" newline bitfld.long 0x40 11. "PD11," "0,1" bitfld.long 0x40 10. "PD10," "0,1" newline bitfld.long 0x40 9. "PD9," "0,1" bitfld.long 0x40 8. "PD8," "0,1" newline bitfld.long 0x40 7. "PD7," "0,1" bitfld.long 0x40 6. "PD6," "0,1" newline bitfld.long 0x40 5. "PD5," "0,1" bitfld.long 0x40 4. "PD4," "0,1" newline bitfld.long 0x40 3. "PD3," "0,1" bitfld.long 0x40 2. "PD2," "0,1" newline bitfld.long 0x40 1. "PD1," "0,1" bitfld.long 0x40 0. "PD0," "0,1" line.long 0x44 "PWR_PUCRI,PWR port I pull-up control register" bitfld.long 0x44 15. "PU15," "0,1" bitfld.long 0x44 14. "PU14," "0,1" newline bitfld.long 0x44 13. "PU13," "0,1" bitfld.long 0x44 12. "PU12," "0,1" newline bitfld.long 0x44 11. "PU11," "0,1" bitfld.long 0x44 10. "PU10," "0,1" newline bitfld.long 0x44 9. "PU9," "0,1" bitfld.long 0x44 8. "PU8," "0,1" newline bitfld.long 0x44 7. "PU7," "0,1" bitfld.long 0x44 6. "PU6," "0,1" newline bitfld.long 0x44 5. "PU5," "0,1" bitfld.long 0x44 4. "PU4," "0,1" newline bitfld.long 0x44 3. "PU3," "0,1" bitfld.long 0x44 2. "PU2," "0,1" newline bitfld.long 0x44 1. "PU1," "0,1" bitfld.long 0x44 0. "PU0," "0,1" line.long 0x48 "PWR_PDCRI,PWR port I pull-down control register" bitfld.long 0x48 15. "PD15," "0,1" bitfld.long 0x48 14. "PD14," "0,1" newline bitfld.long 0x48 13. "PD13," "0,1" bitfld.long 0x48 12. "PD12," "0,1" newline bitfld.long 0x48 11. "PD11," "0,1" bitfld.long 0x48 10. "PD10," "0,1" newline bitfld.long 0x48 9. "PD9," "0,1" bitfld.long 0x48 8. "PD8," "0,1" newline bitfld.long 0x48 7. "PD7," "0,1" bitfld.long 0x48 6. "PD6," "0,1" newline bitfld.long 0x48 5. "PD5," "0,1" bitfld.long 0x48 4. "PD4," "0,1" newline bitfld.long 0x48 3. "PD3," "0,1" bitfld.long 0x48 2. "PD2," "0,1" newline bitfld.long 0x48 1. "PD1," "0,1" bitfld.long 0x48 0. "PD0," "0,1" line.long 0x4C "PWR_PUCRJ,PWR port J pull-up control register" bitfld.long 0x4C 11. "PU11," "0,1" bitfld.long 0x4C 10. "PU10," "0,1" newline bitfld.long 0x4C 9. "PU9," "0,1" bitfld.long 0x4C 8. "PU8," "0,1" newline bitfld.long 0x4C 7. "PU7," "0,1" bitfld.long 0x4C 6. "PU6," "0,1" newline bitfld.long 0x4C 5. "PU5," "0,1" bitfld.long 0x4C 4. "PU4," "0,1" newline bitfld.long 0x4C 3. "PU3," "0,1" bitfld.long 0x4C 2. "PU2," "0,1" newline bitfld.long 0x4C 1. "PU1," "0,1" bitfld.long 0x4C 0. "PU0," "0,1" line.long 0x50 "PWR_PDCRJ,PWR port J pull-down control register" bitfld.long 0x50 11. "PD11," "0,1" bitfld.long 0x50 10. "PD10," "0,1" newline bitfld.long 0x50 9. "PD9," "0,1" bitfld.long 0x50 8. "PD8," "0,1" newline bitfld.long 0x50 7. "PD7," "0,1" bitfld.long 0x50 6. "PD6," "0,1" newline bitfld.long 0x50 5. "PD5," "0,1" bitfld.long 0x50 4. "PD4," "0,1" newline bitfld.long 0x50 3. "PD3," "0,1" bitfld.long 0x50 2. "PD2," "0,1" newline bitfld.long 0x50 1. "PD1," "0,1" bitfld.long 0x50 0. "PD0," "0,1" group.long 0xA8++0x3 line.long 0x0 "PWR_CR4,PWR control register 4" bitfld.long 0x0 28. "SRAM5PDS13," "0,1" bitfld.long 0x0 27. "SRAM5PDS12," "0,1" newline bitfld.long 0x0 26. "SRAM5PDS11," "0,1" bitfld.long 0x0 25. "SRAM5PDS10," "0,1" newline bitfld.long 0x0 24. "SRAM5PDS9," "0,1" bitfld.long 0x0 23. "SRAM5PDS8," "0,1" newline bitfld.long 0x0 22. "SRAM5PDS7," "0,1" bitfld.long 0x0 21. "SRAM5PDS6," "0,1" newline bitfld.long 0x0 20. "SRAM5PDS5," "0,1" bitfld.long 0x0 19. "SRAM5PDS4," "0,1" newline bitfld.long 0x0 18. "SRAM5PDS3," "0,1" bitfld.long 0x0 17. "SRAM5PDS2," "0,1" newline bitfld.long 0x0 16. "SRAM5PDS1," "0,1" bitfld.long 0x0 14. "SRAM3PDS13," "0,1" newline bitfld.long 0x0 13. "SRAM3PDS12," "0,1" bitfld.long 0x0 12. "SRAM3PDS11," "0,1" newline bitfld.long 0x0 11. "SRAM3PDS10," "0,1" bitfld.long 0x0 10. "SRAM3PDS9," "0,1" newline bitfld.long 0x0 8. "SRAM1PDS12," "0,1" bitfld.long 0x0 7. "SRAM1PDS11," "0,1" newline bitfld.long 0x0 6. "SRAM1PDS10," "0,1" bitfld.long 0x0 5. "SRAM1PDS9," "0,1" newline bitfld.long 0x0 4. "SRAM1PDS8," "0,1" bitfld.long 0x0 3. "SRAM1PDS7," "0,1" newline bitfld.long 0x0 2. "SRAM1PDS6," "0,1" bitfld.long 0x0 1. "SRAM1PDS5," "0,1" newline bitfld.long 0x0 0. "SRAM1PDS4," "0,1" tree.end endif tree.end tree "RAMCFG (RAM Configuration Controller)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "RAMCFG" base ad:0x40026000 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" newline bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" newline bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" newline bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" newline bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" newline bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" newline bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" newline bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" newline bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" newline bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" newline bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" newline bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" newline bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" newline bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" newline bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" newline bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" newline bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" newline bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" endif sif (cpuis("STM32U575*")) group.long 0x0++0x3 line.long 0x0 "RAM1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RAM1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" endif wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" sif (cpuis("STM32U575*")) group.long 0x40++0x7 line.long 0x0 "RAM2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "RAM2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "RAM2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "RAM2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" newline bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" newline bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" newline bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" newline bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" newline bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" newline bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" newline bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" newline bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "RAM2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" newline bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" newline bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" newline bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" newline bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" newline bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" newline bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" newline bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" newline bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "RAM2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "RAM2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "RAM3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "RAM3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "RAM3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "RAM3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "RAM3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "RAM4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "RAM4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "RAM4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "RAM5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "RAM5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "RAM5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_RAMCFG" base ad:0x50026000 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" newline bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" newline bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" newline bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" newline bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" newline bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" newline bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" newline bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" newline bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" newline bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" newline bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" newline bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" newline bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" newline bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" newline bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" newline bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" newline bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" newline bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" endif sif (cpuis("STM32U575*")) group.long 0x0++0x3 line.long 0x0 "RAM1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RAM1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" endif wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" sif (cpuis("STM32U575*")) group.long 0x40++0x7 line.long 0x0 "RAM2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "RAM2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "RAM2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "RAM2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" newline bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" newline bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" newline bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" newline bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" newline bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" newline bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" newline bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" newline bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "RAM2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" newline bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" newline bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" newline bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" newline bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" newline bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" newline bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" newline bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" newline bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "RAM2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "RAM2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "RAM3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "RAM3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "RAM3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "RAM3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "RAM3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "RAM4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "RAM4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "RAM4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "RAM5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" newline bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" newline bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "RAM5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" newline bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "RAM5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" endif tree.end endif sif (cpuis("STM32U585*")) tree "RAMCFG" base ad:0x40026000 group.long 0x0++0x3 line.long 0x0 "RAM1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RAM1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "RAM2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "RAM2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "RAM2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "RAM2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" newline bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" newline bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "RAM2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" newline bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" newline bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "RAM2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "RAM2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "RAM3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "RAM3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "RAM3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "RAM3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "RAM3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "RAM4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "RAM4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "RAM4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "RAM5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "RAM5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "RAM5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" tree.end tree "SEC_RAMCFG" base ad:0x50026000 group.long 0x0++0x3 line.long 0x0 "RAM1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RAM1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "RAM2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "RAM2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "RAM2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "RAM2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" newline bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" newline bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "RAM2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" newline bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" newline bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "RAM2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "RAM2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "RAM3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "RAM3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "RAM3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "RAM3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "RAM3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "RAM4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "RAM4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "RAM4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "RAM5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "RAM5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "RAM5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "RAM5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "RAM5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "RAM5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "RAMCFG" base ad:0x40026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end tree "SEC_RAMCFG" base ad:0x50026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end endif sif (cpuis("STM32U599*")) tree "RAMCFG" base ad:0x40026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end tree "SEC_RAMCFG" base ad:0x50026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end endif sif (cpuis("STM32U5A5*")) tree "RAMCFG" base ad:0x40026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end tree "SEC_RAMCFG" base ad:0x50026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end endif sif (cpuis("STM32U5A9*")) tree "RAMCFG" base ad:0x40026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end tree "SEC_RAMCFG" base ad:0x50026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end endif sif (cpuis("STM32U5F*")) tree "RAMCFG" base ad:0x40026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end tree "SEC_RAMCFG" base ad:0x50026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end endif sif (cpuis("STM32U5G*")) tree "RAMCFG" base ad:0x40026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end tree "SEC_RAMCFG" base ad:0x50026000 group.long 0x0++0x3 line.long 0x0 "M1CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "M1ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "RAM1ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x40++0x7 line.long 0x0 "M2CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M2IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x48++0xB line.long 0x0 "M2ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M2SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M2DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x54++0xB line.long 0x0 "M2ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" line.long 0x4 "M2WPR1,RAMCFG SRAM2 write protection register 1" bitfld.long 0x4 31. "P31WP,P31WP" "0,1" bitfld.long 0x4 30. "P30WP,P30WP" "0,1" bitfld.long 0x4 29. "P29WP,P29WP" "0,1" bitfld.long 0x4 28. "P28WP,P28WP" "0,1" newline bitfld.long 0x4 27. "P27WP,P27WP" "0,1" bitfld.long 0x4 26. "P26WP,P26WP" "0,1" bitfld.long 0x4 25. "P25WP,P25WP" "0,1" bitfld.long 0x4 24. "P24WP,P24WP" "0,1" newline bitfld.long 0x4 23. "P23WP,P23WP" "0,1" bitfld.long 0x4 22. "P22WP,P22WP" "0,1" bitfld.long 0x4 21. "P21WP,P21WP" "0,1" bitfld.long 0x4 20. "P20WP,P20WP" "0,1" newline bitfld.long 0x4 19. "P19WP,P19WP" "0,1" bitfld.long 0x4 18. "P18WP,P18WP" "0,1" bitfld.long 0x4 17. "P17WP,P17WP" "0,1" bitfld.long 0x4 16. "P16WP,P16WP" "0,1" newline bitfld.long 0x4 15. "P15WP,P15WP" "0,1" bitfld.long 0x4 14. "P14WP,P14WP" "0,1" bitfld.long 0x4 13. "P13WP,P13WP" "0,1" bitfld.long 0x4 12. "P12WP,P12WP" "0,1" newline bitfld.long 0x4 11. "P11WP,P11WP" "0,1" bitfld.long 0x4 10. "P10WP,P10WP" "0,1" bitfld.long 0x4 9. "P9WP,P9WP" "0,1" bitfld.long 0x4 8. "P8WP,P8WP" "0,1" newline bitfld.long 0x4 7. "P7WP,P7WP" "0,1" bitfld.long 0x4 6. "P6WP,P6WP" "0,1" bitfld.long 0x4 5. "P5WP,P5WP" "0,1" bitfld.long 0x4 4. "P4WP,P4WP" "0,1" newline bitfld.long 0x4 3. "P3WP,P3WP" "0,1" bitfld.long 0x4 2. "P2WP,P2WP" "0,1" bitfld.long 0x4 1. "P1WP,P1WP" "0,1" bitfld.long 0x4 0. "P0WP,P0WP" "0,1" line.long 0x8 "M2WPR2,RAMCFG SRAM2 write protection register 2" bitfld.long 0x8 31. "P63WP,P63WP" "0,1" bitfld.long 0x8 30. "P62WP,P62WP" "0,1" bitfld.long 0x8 29. "P61WP,P61WP" "0,1" bitfld.long 0x8 28. "P60WP,P60WP" "0,1" newline bitfld.long 0x8 27. "P59WP,P59WP" "0,1" bitfld.long 0x8 26. "P58WP,P58WP" "0,1" bitfld.long 0x8 25. "P57WP,P57WP" "0,1" bitfld.long 0x8 24. "P56WP,P56WP" "0,1" newline bitfld.long 0x8 23. "P55WP,P55WP" "0,1" bitfld.long 0x8 22. "P54WP,P54WP" "0,1" bitfld.long 0x8 21. "P53WP,P53WP" "0,1" bitfld.long 0x8 20. "P52WP,P52WP" "0,1" newline bitfld.long 0x8 19. "P51WP,P51WP" "0,1" bitfld.long 0x8 18. "P50WP,P50WP" "0,1" bitfld.long 0x8 17. "P49WP,P49WP" "0,1" bitfld.long 0x8 16. "P48WP,P48WP" "0,1" newline bitfld.long 0x8 15. "P47WP,P47WP" "0,1" bitfld.long 0x8 14. "P46WP,P46WP" "0,1" bitfld.long 0x8 13. "P45WP,P45WP" "0,1" bitfld.long 0x8 12. "P44WP,P44WP" "0,1" newline bitfld.long 0x8 11. "P43WP,P43WP" "0,1" bitfld.long 0x8 10. "P42WP,P42WP" "0,1" bitfld.long 0x8 9. "P41WP,P41WP" "0,1" bitfld.long 0x8 8. "P40WP,P40WP" "0,1" newline bitfld.long 0x8 7. "P39WP,P39WP" "0,1" bitfld.long 0x8 6. "P38WP,P38WP" "0,1" bitfld.long 0x8 5. "P37WP,P37WP" "0,1" bitfld.long 0x8 4. "P36WP,P36WP" "0,1" newline bitfld.long 0x8 3. "P35WP,P35WP" "0,1" bitfld.long 0x8 2. "P34WP,P34WP" "0,1" bitfld.long 0x8 1. "P33WP,P33WP" "0,1" bitfld.long 0x8 0. "P32WP,P32WP" "0,1" wgroup.long 0x64++0x7 line.long 0x0 "M2ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M2ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x80++0x7 line.long 0x0 "M3CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M3IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x88++0xB line.long 0x0 "M3ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M3SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M3DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x94++0x3 line.long 0x0 "M3ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" wgroup.long 0xA4++0x7 line.long 0x0 "M3ECCKEYR,RAMCFG SRAM x ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" line.long 0x4 "M3ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0xC0++0x3 line.long 0x0 "M4CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "M4ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" wgroup.long 0xE8++0x3 line.long 0x0 "M4ERKEYR,RAMCFG SRAM x erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,ERASEKEY" group.long 0x100++0x7 line.long 0x0 "M5CR,RAMCFG SRAM x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" line.long 0x4 "M5IER,RAMCFG SRAM x interrupt enable register" bitfld.long 0x4 3. "ECCNMI,ECCNMI" "0,1" bitfld.long 0x4 1. "DEIE,DEIE" "0,1" bitfld.long 0x4 0. "SEIE,SEIE" "0,1" rgroup.long 0x108++0xB line.long 0x0 "M5ISR,RAMCFG RAMx interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAMBUSY" "0,1" bitfld.long 0x0 1. "DED,DED" "0,1" bitfld.long 0x0 0. "SEDC,SEDC" "0,1" line.long 0x4 "M5SEAR,RAMCFG RAM x ECC single error address register" hexmask.long 0x4 0.--31. 1. "ESEA,ESEA" line.long 0x8 "M5DEAR,RAMCFG RAM x ECC double error address register" hexmask.long 0x8 0.--31. 1. "EDEA,EDEA" group.long 0x114++0x3 line.long 0x0 "M5ICR,RAMCFG RAM x interrupt clear register x" bitfld.long 0x0 1. "CDED,CDED" "0,1" bitfld.long 0x0 0. "CSEDC,CSEDC" "0,1" group.long 0x124++0x3 line.long 0x0 "M5ECCKEYR,RAMCFG RAM x interrupt clear register x" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECCKEY" wgroup.long 0x128++0x3 line.long 0x0 "M5ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x140++0x3 line.long 0x0 "M6CR,memory x control register" bitfld.long 0x0 16.--18. "WSC,WSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SRAMER,SRAMER" "0,1" bitfld.long 0x0 4. "ALE,ALE" "0,1" bitfld.long 0x0 0. "ECCE,ECCE" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "M6ISR," bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation on going,1: Erase operation on going" bitfld.long 0x0 1. "DED,ECC double error detected" "0: No double error,1: Double error detected" bitfld.long 0x0 0. "SEDC,ECC single error detected and corrected" "0: No single error,1: Single error detected and corrected" wgroup.long 0x168++0x3 line.long 0x0 "M6ERKEYR," hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end endif tree.end tree "RCC (Reset and Clock Control)" base ad:0x0 tree "RCC" base ad:0x46020C00 group.long 0x0++0x3 line.long 0x0 "RCC_CR,RCC clock control register" rbitfld.long 0x0 29. "PLL3RDY,PLL3 clock ready flag" "0: PLL3 unlocked,1: PLL3 locked" bitfld.long 0x0 28. "PLL3ON,PLL3 enable" "0: PLL3 OFF,1: PLL3 ON" newline rbitfld.long 0x0 27. "PLL2RDY,PLL2 clock ready flag" "0: PLL2 unlocked,1: PLL2 locked" bitfld.long 0x0 26. "PLL2ON,PLL2 enable" "0: PLL2 OFF,1: PLL2 ON" newline rbitfld.long 0x0 25. "PLL1RDY,PLL1 clock ready flag" "0: PLL1 unlocked,1: PLL1 locked" bitfld.long 0x0 24. "PLL1ON,PLL1 enable" "0: PLL1 OFF,1: PLL1 ON" newline bitfld.long 0x0 20. "HSEEXT,HSE external clock bypass mode" "0: external HSE clock analog mode,1: external HSE clock digital mode (through I/O.." bitfld.long 0x0 19. "CSSON,Clock security system enable" "0: clock security system OFF (clock detector OFF),1: clock security system ON (clock detector ON if.." newline bitfld.long 0x0 18. "HSEBYP,HSE crystal oscillator bypass" "0: HSE crystal oscillator not bypassed,1: HSE crystal oscillator bypassed with external.." rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0: HSE oscillator not ready,1: HSE oscillator ready" newline bitfld.long 0x0 16. "HSEON,HSE clock enable" "0: HSE oscillator off,1: HSE oscillator on" rbitfld.long 0x0 15. "SHSIRDY,SHSI clock ready flag" "0: SHSI oscillator not ready,1: SHSI oscillator ready" newline bitfld.long 0x0 14. "SHSION,SHSI clock enable" "0: SHSI oscillator off,1: SHSI oscillator on" rbitfld.long 0x0 13. "HSI48RDY,HSI48 clock ready flag" "0: HSI48 oscillator not ready,1: HSI48 oscillator ready" newline bitfld.long 0x0 12. "HSI48ON,HSI48 clock enable" "0: HSI48 oscillator off,1: HSI48 oscillator on" rbitfld.long 0x0 10. "HSIRDY,HSI16 clock ready flag" "0: HSI16 oscillator not ready,1: HSI16 oscillator ready" newline bitfld.long 0x0 9. "HSIKERON,HSI16 enable for some peripheral kernels" "0: No effect on HSI16 oscillator,1: HSI16 oscillator forced on even in Stop mode" bitfld.long 0x0 8. "HSION,HSI16 clock enable" "0: HSI16 oscillator off,1: HSI16 oscillator on" newline bitfld.long 0x0 7. "MSIPLLFAST,MSI PLL mode fast startup" "0: MSI PLL normal start-up,1: MSI PLL fast start-up" bitfld.long 0x0 6. "MSIPLLSEL,MSI clock with PLL mode selection" "0: PLL mode applied to MSIK (MSI kernel) clock output,1: PLL mode applied to MSIS (MSI system) clock output" newline rbitfld.long 0x0 5. "MSIKRDY,MSIK clock ready flag" "0: MSIK (MSI kernel) oscillator not ready,1: MSIK (MSI kernel) oscillator ready" bitfld.long 0x0 4. "MSIKON,MSIK clock enable" "0: MSIK (MSI kernel) oscillator disabled,1: MSIK (MSI kernel) oscillator enabled" newline bitfld.long 0x0 3. "MSIPLLEN,MSI clock PLL-mode enable" "0: MSI PLL-mode OFF,1: MSI PLL-mode ON" rbitfld.long 0x0 2. "MSISRDY,MSIS clock ready flag" "0: MSIS (MSI system) oscillator not ready,1: MSIS (MSI system) oscillator ready" newline bitfld.long 0x0 1. "MSIKERON,MSI enable for some peripheral kernels" "0: No effect on MSI oscillator,1: MSI oscillator forced ON even in Stop mode" bitfld.long 0x0 0. "MSISON,MSIS clock enable" "0: MSIS (MSI system) oscillator off,1: MSIS (MSI system) oscillator on" group.long 0x8++0xB line.long 0x0 "RCC_ICSCR1,RCC internal clock sources calibration register 1" hexmask.long.byte 0x0 28.--31. 1. "MSISRANGE,MSIS clock ranges" hexmask.long.byte 0x0 24.--27. 1. "MSIKRANGE,MSIK clock ranges" newline bitfld.long 0x0 23. "MSIRGSEL,MSI clock range selection" "0: MSIS/MSIK ranges provided by MSISSRANGE[3:0] and..,1: MSIS/MSIK ranges provided by MSISRANGE[3:0] and.." bitfld.long 0x0 22. "MSIBIAS,MSI bias mode selection" "0: MSI bias continuous mode (clock accuracy fast..,1: MSI bias sampling mode when the regulator is in.." newline hexmask.long.byte 0x0 15.--19. 1. "MSICAL0,MSIRC0 clock calibration for MSI ranges 0 to 3" hexmask.long.byte 0x0 10.--14. 1. "MSICAL1,MSIRC1 clock calibration for MSI ranges 4 to 7" newline hexmask.long.byte 0x0 5.--9. 1. "MSICAL2,MSIRC2 clock calibration for MSI ranges 8 to 11" hexmask.long.byte 0x0 0.--4. 1. "MSICAL3,MSIRC3 clock calibration for MSI ranges 12 to 15" line.long 0x4 "RCC_ICSCR2,RCC internal clock sources calibration register 2" hexmask.long.byte 0x4 15.--19. 1. "MSITRIM0,MSI clock trimming for ranges 0 to 3" hexmask.long.byte 0x4 10.--14. 1. "MSITRIM1,MSI clock trimming for ranges 4 to 7" newline hexmask.long.byte 0x4 5.--9. 1. "MSITRIM2,MSI clock trimming for ranges 8 to 11" hexmask.long.byte 0x4 0.--4. 1. "MSITRIM3,MSI clock trimming for ranges 12 to 15" line.long 0x8 "RCC_ICSCR3,RCC internal clock sources calibration register 3" hexmask.long.byte 0x8 16.--20. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x8 0.--11. 1. "HSICAL,HSI clock calibration" rgroup.long 0x14++0x3 line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register" hexmask.long.word 0x0 0.--8. 1. "HSI48CAL,HSI48 clock calibration" group.long 0x1C++0x2F line.long 0x0 "RCC_CFGR1,RCC clock configuration register 1" bitfld.long 0x0 28.--30. "MCOPRE,microcontroller clock output prescaler" "0: MCO divided by 1,1: MCO divided by 2,2: MCO divided by 4,3: MCO divided by 8,4: MCO divided by 16,?,?,?" hexmask.long.byte 0x0 24.--27. 1. "MCOSEL,microcontroller clock output" newline bitfld.long 0x0 5. "STOPKERWUCK,wake-up from Stop kernel clock automatic enable selection" "0: MSIK oscillator automatically enabled when..,1: HSI16 oscillator automatically enabled when.." bitfld.long 0x0 4. "STOPWUCK,wake-up from Stop and CSS backup clock selection" "0: MSIS oscillator selected as wake-up from stop..,1: HSI16 oscillator selected as wake-up from stop.." newline rbitfld.long 0x0 2.--3. "SWS,system clock switch status" "0: MSIS oscillator used as system clock,1: HSI16 oscillator used as system clock,2: HSE used as system clock,3: PLL pll1_r_ck used as system clock" bitfld.long 0x0 0.--1. "SW,system clock switch" "0: MSIS selected as system clock,1: HSI16 selected as system clock,2: HSE selected as system clock,3: PLL pll1_r_ck selected as system clock" line.long 0x4 "RCC_CFGR2,RCC clock configuration register 2" bitfld.long 0x4 20. "APB2DIS,APB2 clock disable" "0: APB2 clock enabled distributed to peripherals..,1: APB2 clock disabled" bitfld.long 0x4 19. "APB1DIS,APB1 clock disable" "0: APB1 clock enabled distributed to peripherals..,1: APB1 clock disabled" newline bitfld.long 0x4 18. "AHB2DIS2,AHB2_2 clock disable" "0: AHB2_2 clock enabled distributed to peripherals..,1: AHB2_2 clock disabled" bitfld.long 0x4 17. "AHB2DIS1,AHB2_1 clock disable" "0: AHB2_1 clock enabled distributed to peripherals..,1: AHB2_1 clock disabled" newline bitfld.long 0x4 16. "AHB1DIS,AHB1 clock disable" "0: AHB1 clock enabled distributed to peripherals..,1: AHB1 clock disabled" bitfld.long 0x4 12.--14. "DPRE,DSI PHY prescaler" "?,?,?,?,4: DCLK divided by 2,5: DCLK divided by 4,6: DCLK divided by 8,7: DCLK divided by 16" newline bitfld.long 0x4 8.--10. "PPRE2,APB2 prescaler" "?,?,?,?,4: PCLK2 divided by 2,5: PCLK2 divided by 4,6: PCLK2 divided by 8,7: PCLK2 divided by 16" bitfld.long 0x4 4.--6. "PPRE1,APB1 prescaler" "?,?,?,?,4: PCLK1 divided by 2,5: PCLK1 divided by 4,6: PCLK1 divided by 8,7: PCLK1 divided by 16" newline hexmask.long.byte 0x4 0.--3. 1. "HPRE,AHB prescaler" line.long 0x8 "RCC_CFGR3,RCC clock configuration register 3" bitfld.long 0x8 17. "APB3DIS,APB3 clock disable" "0: APB3 clock enabled distributed to peripherals..,1: APB3 clock disabled" bitfld.long 0x8 16. "AHB3DIS,AHB3 clock disable" "0: AHB3 clock enabled distributed to peripherals..,1: AHB3 clock disabled" newline bitfld.long 0x8 4.--6. "PPRE3,APB3 prescaler" "?,?,?,?,4: HCLK divided by 2,5: HCLK divided by 4,6: HCLK divided by 8,7: HCLK divided by 16" line.long 0xC "RCC_PLL1CFGR,RCC PLL1 configuration register" bitfld.long 0xC 18. "PLL1REN,PLL1 DIVR divider output enable" "0: pll1_r_ck output disabled,1: pll1_r_ck output enabled" bitfld.long 0xC 17. "PLL1QEN,PLL1 DIVQ divider output enable" "0: pll1_q_ck output disabled,1: pll1_q_ck output enabled" newline bitfld.long 0xC 16. "PLL1PEN,PLL1 DIVP divider output enable" "0: pll1_p_ck output disabled,1: pll1_p_ck output enabled" hexmask.long.byte 0xC 12.--15. 1. "PLL1MBOOST,Prescaler for EPOD booster input clock" newline hexmask.long.byte 0xC 8.--11. 1. "PLL1M,Prescaler for PLL1" bitfld.long 0xC 4. "PLL1FRACEN,PLL1 fractional latch enable" "?,1: the transition 0 to 1 transfers the content of.." newline bitfld.long 0xC 2.--3. "PLL1RGE,PLL1 input frequency range" "?,?,?,3: PLL1 input (ref1_ck) clock range frequency.." bitfld.long 0xC 0.--1. "PLL1SRC,PLL1 entry clock source" "0: No clock sent to PLL1,1: MSIS clock selected as PLL1 clock entry,2: HSI16 clock selected as PLL1 clock entry,3: HSE clock selected as PLL1 clock entry" line.long 0x10 "RCC_PLL2CFGR,RCC PLL2 configuration register" bitfld.long 0x10 18. "PLL2REN,PLL2 DIVR divider output enable" "0: pll2_r_ck output disabled,1: pll2_r_ck output enabled" bitfld.long 0x10 17. "PLL2QEN,PLL2 DIVQ divider output enable" "0: pll2_q_ck output disabled,1: pll2_q_ck output enabled" newline bitfld.long 0x10 16. "PLL2PEN,PLL2 DIVP divider output enable" "0: pll2_p_ck output disabled,1: pll2_p_ck output enabled" hexmask.long.byte 0x10 8.--11. 1. "PLL2M,Prescaler for PLL2" newline bitfld.long 0x10 4. "PLL2FRACEN,PLL2 fractional latch enable" "?,1: the transition 0 to 1 transfers the content of.." bitfld.long 0x10 2.--3. "PLL2RGE,PLL2 input frequency range" "?,?,?,3: PLL2 input (ref2_ck) clock range frequency.." newline bitfld.long 0x10 0.--1. "PLL2SRC,PLL2 entry clock source" "0: No clock sent to PLL2,1: MSIS clock selected as PLL2 clock entry,2: HSI16 clock selected as PLL2 clock entry,3: HSE clock selected as PLL2 clock entry" line.long 0x14 "RCC_PLL3CFGR,RCC PLL3 configuration register" bitfld.long 0x14 18. "PLL3REN,PLL3 DIVR divider output enable" "0: pll3_r_ck output disabled,1: pll3_r_ck output enabled" bitfld.long 0x14 17. "PLL3QEN,PLL3 DIVQ divider output enable" "0: pll3_q_ck output disabled,1: pll3_q_ck output enabled" newline bitfld.long 0x14 16. "PLL3PEN,PLL3 DIVP divider output enable" "0: pll3_p_ck output disabled,1: pll3_p_ck output enabled" hexmask.long.byte 0x14 8.--11. 1. "PLL3M,Prescaler for PLL3" newline bitfld.long 0x14 4. "PLL3FRACEN,PLL3 fractional latch enable" "?,1: the transition 0 to 1 transfers the content of.." bitfld.long 0x14 2.--3. "PLL3RGE,PLL3 input frequency range" "?,?,?,3: PLL3 input (ref3_ck) clock range frequency.." newline bitfld.long 0x14 0.--1. "PLL3SRC,PLL3 entry clock source" "0: No clock sent to PLL3,1: MSIS clock selected as PLL3 clock entry,2: HSI16 clock selected as PLL3 clock entry,3: HSE clock selected as PLL3 clock entry" line.long 0x18 "RCC_PLL1DIVR,RCC PLL1 dividers register" hexmask.long.byte 0x18 24.--30. 1. "PLL1R,PLL1 DIVR division factor" hexmask.long.byte 0x18 16.--22. 1. "PLL1Q,PLL1 DIVQ division factor" newline hexmask.long.byte 0x18 9.--15. 1. "PLL1P,PLL1 DIVP division factor" hexmask.long.word 0x18 0.--8. 1. "PLL1N,Multiplication factor for PLL1 VCO" line.long 0x1C "RCC_PLL1FRACR,RCC PLL1 fractional divider register" hexmask.long.word 0x1C 3.--15. 1. "PLL1FRACN,Fractional part of the multiplication factor for PLL1 VCO" line.long 0x20 "RCC_PLL2DIVR,RCC PLL2 dividers configuration register" hexmask.long.byte 0x20 24.--30. 1. "PLL2R,PLL2 DIVR division factor" hexmask.long.byte 0x20 16.--22. 1. "PLL2Q,PLL2 DIVQ division factor" newline hexmask.long.byte 0x20 9.--15. 1. "PLL2P,PLL2 DIVP division factor" hexmask.long.word 0x20 0.--8. 1. "PLL2N,Multiplication factor for PLL2 VCO" line.long 0x24 "RCC_PLL2FRACR,RCC PLL2 fractional divider register" hexmask.long.word 0x24 3.--15. 1. "PLL2FRACN,Fractional part of the multiplication factor for PLL2 VCO" line.long 0x28 "RCC_PLL3DIVR,RCC PLL3 dividers configuration register" hexmask.long.byte 0x28 24.--30. 1. "PLL3R,PLL3 DIVR division factor" hexmask.long.byte 0x28 16.--22. 1. "PLL3Q,PLL3 DIVQ division factor" newline hexmask.long.byte 0x28 9.--15. 1. "PLL3P,PLL3 DIVP division factor" hexmask.long.word 0x28 0.--8. 1. "PLL3N,Multiplication factor for PLL3 VCO" line.long 0x2C "RCC_PLL3FRACR,RCC PLL3 fractional divider register" hexmask.long.word 0x2C 3.--15. 1. "PLL3FRACN,Fractional part of the multiplication factor for PLL3 VCO" group.long 0x50++0x3 line.long 0x0 "RCC_CIER,RCC clock interrupt enable register" bitfld.long 0x0 12. "SHSIRDYIE,SHSI ready interrupt enable" "0: SHSI ready interrupt disabled,1: SHSI ready interrupt enabled" bitfld.long 0x0 11. "MSIKRDYIE,MSIK ready interrupt enable" "0: MSIK ready interrupt disabled,1: MSIK ready interrupt enabled" newline bitfld.long 0x0 8. "PLL3RDYIE,PLL3 ready interrupt enable" "0: PLL3 lock interrupt disabled,1: PLL3 lock interrupt enabled" bitfld.long 0x0 7. "PLL2RDYIE,PLL2 ready interrupt enable" "0: PLL2 lock interrupt disabled,1: PLL2 lock interrupt enabled" newline bitfld.long 0x0 6. "PLL1RDYIE,PLL ready interrupt enable" "0: PLL1 lock interrupt disabled,1: PLL1 lock interrupt enabled" bitfld.long 0x0 5. "HSI48RDYIE,HSI48 ready interrupt enable" "0: HSI48 ready interrupt disabled,1: HSI48 ready interrupt enabled" newline bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0: HSE ready interrupt disabled,1: HSE ready interrupt enabled" bitfld.long 0x0 3. "HSIRDYIE,HSI16 ready interrupt enable" "0: HSI16 ready interrupt disabled,1: HSI16 ready interrupt enabled" newline bitfld.long 0x0 2. "MSISRDYIE,MSIS ready interrupt enable" "0: MSIS ready interrupt disabled,1: MSIS ready interrupt enabled" bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: LSE ready interrupt disabled,1: LSE ready interrupt enabled" newline bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: LSI ready interrupt disabled,1: LSI ready interrupt enabled" rgroup.long 0x54++0x3 line.long 0x0 "RCC_CIFR,RCC clock interrupt flag register" bitfld.long 0x0 12. "SHSIRDYF,SHSI ready interrupt flag" "0: No clock ready interrupt caused by the SHSI..,1: Clock ready interrupt caused by the SHSI.." bitfld.long 0x0 11. "MSIKRDYF,MSIK ready interrupt flag" "0: No clock ready interrupt caused by the MSIK..,1: Clock ready interrupt caused by the MSIK.." newline bitfld.long 0x0 10. "CSSF,Clock security system interrupt flag" "0: No clock security interrupt caused by HSE clock..,1: Clock security interrupt caused by HSE clock.." bitfld.long 0x0 8. "PLL3RDYF,PLL3 ready interrupt flag" "0: No clock ready interrupt caused by PLL3 lock,1: Clock ready interrupt caused by PLL3 lock" newline bitfld.long 0x0 7. "PLL2RDYF,PLL2 ready interrupt flag" "0: No clock ready interrupt caused by PLL2 lock,1: Clock ready interrupt caused by PLL2 lock" bitfld.long 0x0 6. "PLL1RDYF,PLL1 ready interrupt flag" "0: No clock ready interrupt caused by PLL1 lock,1: Clock ready interrupt caused by PLL1 lock" newline bitfld.long 0x0 5. "HSI48RDYF,HSI48 ready interrupt flag" "0: No clock ready interrupt caused by the HSI48..,1: Clock ready interrupt caused by the HSI48.." bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: No clock ready interrupt caused by the HSE..,1: Clock ready interrupt caused by the HSE oscillator" newline bitfld.long 0x0 3. "HSIRDYF,HSI16 ready interrupt flag" "0: No clock ready interrupt caused by the HSI16..,1: Clock ready interrupt caused by the HSI16.." bitfld.long 0x0 2. "MSISRDYF,MSIS ready interrupt flag" "0: No clock ready interrupt caused by the MSIS..,1: Clock ready interrupt caused by the MSIS.." newline bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: No clock ready interrupt caused by the LSE..,1: Clock ready interrupt caused by the LSE oscillator" bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: No clock ready interrupt caused by the LSI..,1: Clock ready interrupt caused by the LSI oscillator" wgroup.long 0x58++0x3 line.long 0x0 "RCC_CICR,RCC clock interrupt clear register" bitfld.long 0x0 12. "SHSIRDYC,SHSI oscillator ready interrupt clear" "0,1" bitfld.long 0x0 11. "MSIKRDYC,MSIK oscillator ready interrupt clear" "0,1" newline bitfld.long 0x0 10. "CSSC,Clock security system interrupt clear" "0,1" bitfld.long 0x0 8. "PLL3RDYC,PLL3 ready interrupt clear" "0,1" newline bitfld.long 0x0 7. "PLL2RDYC,PLL2 ready interrupt clear" "0,1" bitfld.long 0x0 6. "PLL1RDYC,PLL1 ready interrupt clear" "0,1" newline bitfld.long 0x0 5. "HSI48RDYC,HSI48 ready interrupt clear" "0,1" bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0,1" newline bitfld.long 0x0 3. "HSIRDYC,HSI16 ready interrupt clear" "0,1" bitfld.long 0x0 2. "MSISRDYC,MSIS ready interrupt clear" "0,1" newline bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0,1" bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0,1" group.long 0x60++0xF line.long 0x0 "RCC_AHB1RSTR,RCC AHB1 peripheral reset register" bitfld.long 0x0 20. "GPU2DRST,GPU2D reset" "0: No effect,1: Reset the GPU2D." bitfld.long 0x0 19. "GFXMMURST,GFXMMU reset" "0: No effect,1: Reset the GFXMMU." newline bitfld.long 0x0 18. "DMA2DRST,DMA2D reset" "0: No effect,1: Reset the DMA2D." bitfld.long 0x0 17. "RAMCFGRST,RAMCFG reset" "0: No effect,1: Reset the RAMCFG." newline bitfld.long 0x0 16. "TSCRST,TSC reset" "0: No effect,1: Reset the TSC." bitfld.long 0x0 15. "JPEGRST,JPEG reset" "0: No effect,1: Reset the JPEG." newline bitfld.long 0x0 12. "CRCRST,CRC reset" "0: No effect,1: Reset the CRC." bitfld.long 0x0 3. "MDF1RST,MDF1 reset" "0: No effect,1: Reset the MDF1." newline bitfld.long 0x0 2. "FMACRST,FMAC reset" "0: No effect,1: Reset the FMAC." bitfld.long 0x0 1. "CORDICRST,CORDIC reset" "0: No effect,1: Reset the CORDIC." newline bitfld.long 0x0 0. "GPDMA1RST,GPDMA1 reset" "0: No effect,1: Reset the GPDMA1." line.long 0x4 "RCC_AHB2RSTR1,RCC AHB2 peripheral reset register 1" bitfld.long 0x4 28. "SDMMC2RST,SDMMC2 reset" "0: No effect,1: Reset the SDMMC2." bitfld.long 0x4 27. "SDMMC1RST,SDMMC1 reset" "0: No effect,1: Reset the SDMMC1." newline bitfld.long 0x4 24. "OTFDEC2RST,OTFDEC2 reset" "0: No effect,1: Reset the OTFDEC2." bitfld.long 0x4 23. "OTFDEC1RST,OTFDEC1 reset" "0: No effect,1: Reset the OTFDEC1." newline bitfld.long 0x4 21. "OCTOSPIMRST,OCTOSPIM reset" "0: No effect,1: Reset the OCTOSPIM." bitfld.long 0x4 20. "SAESRST,SAES hardware accelerator reset" "0: No effect,1: Reset the SAES." newline bitfld.long 0x4 19. "PKARST,PKA reset" "0: No effect,1: Reset the PKA." bitfld.long 0x4 18. "RNGRST,RNG reset" "0: No effect,1: Reset the RNG." newline bitfld.long 0x4 17. "HASHRST,HASH reset" "0: No effect,1: Reset the HASH." bitfld.long 0x4 16. "AESRST,AES hardware accelerator reset" "0: No effect,1: Reset the AES." newline bitfld.long 0x4 14. "OTGRST,OTG_FS or OTG_HS reset" "0: No effect,1: Reset the OTG_FS or OTG_HS." bitfld.long 0x4 12. "DCMI_PSSIRST,DCMI and PSSI reset" "0: No effect,1: Reset the DCMI and PSSI." newline bitfld.long 0x4 10. "ADC12RST,ADC1 and ADC2 reset" "0: No effect,1: Reset the ADC1 and ADC2." bitfld.long 0x4 9. "GPIOJRST,I/O port J reset" "0: No effect,1: Reset the I/O port J." newline bitfld.long 0x4 8. "GPIOIRST,I/O port I reset" "0: No effect,1: Reset the I/O port .I" bitfld.long 0x4 7. "GPIOHRST,I/O port H reset" "0: No effect,1: Reset the I/O port H." newline bitfld.long 0x4 6. "GPIOGRST,I/O port G reset" "0: No effect,1: Reset the I/O port G." bitfld.long 0x4 5. "GPIOFRST,I/O port F reset" "0: No effect,1: Reset I/O port F" newline bitfld.long 0x4 4. "GPIOERST,I/O port E reset" "0: No effect,1: Reset the I/O port E." bitfld.long 0x4 3. "GPIODRST,I/O port D reset" "0: No effect,1: Reset the I/O port D." newline bitfld.long 0x4 2. "GPIOCRST,I/O port C reset" "0: No effect,1: Reset the I/O port C." bitfld.long 0x4 1. "GPIOBRST,I/O port B reset" "0: No effect,1: Reset the I/O port B." newline bitfld.long 0x4 0. "GPIOARST,I/O port A reset" "0: No effect,1: Reset the I/O port A." line.long 0x8 "RCC_AHB2RSTR2,RCC AHB2 peripheral reset register 2" bitfld.long 0x8 12. "HSPI1RST,HSPI1 reset" "0: No effect,1: Reset the HSPI1." bitfld.long 0x8 8. "OCTOSPI2RST,OCTOSPI2 reset" "0: No effect,1: Reset the OCTOSPI2." newline bitfld.long 0x8 4. "OCTOSPI1RST,OCTOSPI1 reset" "0: No effect,1: Reset the OCTOSPI1." bitfld.long 0x8 0. "FSMCRST,Flexible memory controller reset" "0: No effect,1: Reset the FSMC" line.long 0xC "RCC_AHB3RSTR,RCC AHB3 peripheral reset register" bitfld.long 0xC 10. "ADF1RST,ADF1 reset" "0: No effect,1: Reset the ADF1." bitfld.long 0xC 9. "LPDMA1RST,LPDMA1 reset" "0: No effect,1: Reset the LPDMA1." newline bitfld.long 0xC 6. "DAC1RST,DAC1 reset" "0: No effect,1: Reset the DAC1." bitfld.long 0xC 5. "ADC4RST,ADC4 reset" "0: No effect,1: Reset the ADC4 interface." newline bitfld.long 0xC 0. "LPGPIO1RST,LPGPIO1 reset" "0: No effect,1: Reset the LPGPIO1." group.long 0x74++0xF line.long 0x0 "RCC_APB1RSTR1,RCC APB1 peripheral reset register 1" bitfld.long 0x0 25. "USART6RST,USART6 reset" "0: No effect,1: Reset the USART6." bitfld.long 0x0 24. "CRSRST,CRS reset" "0: No effect,1: Reset the CRS." newline bitfld.long 0x0 22. "I2C2RST,I2C2 reset" "0: No effect,1: Reset the I2C2." bitfld.long 0x0 21. "I2C1RST,I2C1 reset" "0: No effect,1: Reset the I2C1." newline bitfld.long 0x0 20. "UART5RST,UART5 reset" "0: No effect,1: Reset the UART5." bitfld.long 0x0 19. "UART4RST,UART4 reset" "0: No effect,1: Reset the UART4." newline bitfld.long 0x0 18. "USART3RST,USART3 reset" "0: No effect,1: Reset the USART3." bitfld.long 0x0 17. "USART2RST,USART2 reset" "0: No effect,1: Reset the USART2" newline bitfld.long 0x0 14. "SPI2RST,SPI2 reset" "0: No effect,1: Reset the SPI2." bitfld.long 0x0 5. "TIM7RST,TIM7 reset" "0: No effect,1: Reset the TIM7." newline bitfld.long 0x0 4. "TIM6RST,TIM6 reset" "0: No effect,1: Reset the TIM6." bitfld.long 0x0 3. "TIM5RST,TIM5 reset" "0: No effect,1: Reset the TIM5." newline bitfld.long 0x0 2. "TIM4RST,TIM4 reset" "0: No effect,1: Reset the TIM4." bitfld.long 0x0 1. "TIM3RST,TIM3 reset" "0: No effect,1: Reset the TIM3." newline bitfld.long 0x0 0. "TIM2RST,TIM2 reset" "0: No effect,1: Reset the TIM2." line.long 0x4 "RCC_APB1RSTR2,RCC APB1 peripheral reset register 2" bitfld.long 0x4 23. "UCPD1RST,UCPD1 reset" "0: No effect,1: Reset the UCPD1." bitfld.long 0x4 9. "FDCAN1RST,FDCAN1 reset" "0: No effect,1: Reset the FDCAN1." newline bitfld.long 0x4 7. "I2C6RST,I2C6 reset" "0: No effect,1: Reset the I2C6." bitfld.long 0x4 6. "I2C5RST,I2C5 reset" "0: No effect,1: Reset the I2C5." newline bitfld.long 0x4 5. "LPTIM2RST,LPTIM2 reset" "0: No effect,1: Reset the LPTIM2." bitfld.long 0x4 1. "I2C4RST,I2C4 reset" "0: No effect,1: Reset the I2C4." line.long 0x8 "RCC_APB2RSTR,RCC APB2 peripheral reset register" bitfld.long 0x8 27. "DSIRST,DSI reset" "0: No effect,1: Reset the DSI." bitfld.long 0x8 26. "LTDCRST,LTDC reset" "0: No effect,1: Reset the LTDC." newline bitfld.long 0x8 25. "GFXTIMRST,GFXTIM reset" "0: No effect,1: Reset the GFXTIM." bitfld.long 0x8 24. "USBRST,USB reset" "0: No effect,1: Reset the USB." newline bitfld.long 0x8 22. "SAI2RST,SAI2 reset" "0: No effect,1: Reset the SAI2." bitfld.long 0x8 21. "SAI1RST,SAI1 reset" "0: No effect,1: Reset the SAI1." newline bitfld.long 0x8 18. "TIM17RST,TIM17 reset" "0: No effect,1: Reset the TIM17." bitfld.long 0x8 17. "TIM16RST,TIM16 reset" "0: No effect,1: Reset the TIM16." newline bitfld.long 0x8 16. "TIM15RST,TIM15 reset" "0: No effect,1: Reset the TIM15." bitfld.long 0x8 14. "USART1RST,USART1 reset" "0: No effect,1: Reset the USART1." newline bitfld.long 0x8 13. "TIM8RST,TIM8 reset" "0: No effect,1: Reset the TIM8." bitfld.long 0x8 12. "SPI1RST,SPI1 reset" "0: No effect,1: Reset the SPI1." newline bitfld.long 0x8 11. "TIM1RST,TIM1 reset" "0: No effect,1: Reset the TIM1." line.long 0xC "RCC_APB3RSTR,RCC APB3 peripheral reset register" bitfld.long 0xC 20. "VREFRST,VREFBUF reset" "0: No effect,1: Reset the VREFBUF." bitfld.long 0xC 15. "COMPRST,COMP reset" "0: No effect,1: Reset the COMP." newline bitfld.long 0xC 14. "OPAMPRST,OPAMP reset" "0: No effect,1: Reset the OPAMP." bitfld.long 0xC 13. "LPTIM4RST,LPTIM4 reset" "0: No effect,1: Reset the LPTIM4." newline bitfld.long 0xC 12. "LPTIM3RST,LPTIM3 reset" "0: No effect,1: Reset the LPTIM3." bitfld.long 0xC 11. "LPTIM1RST,LPTIM1 reset" "0: No effect,1: Reset the LPTIM1." newline bitfld.long 0xC 7. "I2C3RST,I2C3 reset" "0: No effect,1: Reset the I2C3." bitfld.long 0xC 6. "LPUART1RST,LPUART1 reset" "0: No effect,1: Reset the LPUART1." newline bitfld.long 0xC 5. "SPI3RST,SPI3 reset" "0: No effect,1: Reset the SPI3." bitfld.long 0xC 1. "SYSCFGRST,SYSCFG reset" "0: No effect,1: Reset the SYSCFG." group.long 0x88++0xF line.long 0x0 "RCC_AHB1ENR,RCC AHB1 peripheral clock enable register" bitfld.long 0x0 31. "SRAM1EN,SRAM1 clock enable" "0: SRAM1 clock disabled,1: SRAM1 clock enabled" bitfld.long 0x0 30. "DCACHE1EN,DCACHE1 clock enable" "0: DCACHE1 clock disabled,1: DCACHE1 clock enabled" newline bitfld.long 0x0 28. "BKPSRAMEN,BKPSRAM clock enable" "0: BKPSRAM clock disabled,1: BKPSRAM clock enabled" bitfld.long 0x0 24. "GTZC1EN,GTZC1 clock enable" "0: GTZC1 clock disabled,1: GTZC1 clock enabled" newline bitfld.long 0x0 21. "DCACHE2EN,DCACHE2 clock enable" "0: DCACHE2 clock disabled,1: DCACHE2 clock enabled" bitfld.long 0x0 20. "GPU2DEN,GPU2D clock enable" "0: GPU2D clock disabled,1: GPU2D clock enabled" newline bitfld.long 0x0 19. "GFXMMUEN,GFXMMU clock enable" "0: GFXMMU clock disabled,1: GFXMMU clock enabled" bitfld.long 0x0 18. "DMA2DEN,DMA2D clock enable" "0: DMA2D clock disabled,1: DMA2D clock enabled" newline bitfld.long 0x0 17. "RAMCFGEN,RAMCFG clock enable" "0: RAMCFG clock disabled,1: RAMCFG clock enabled" bitfld.long 0x0 16. "TSCEN,Touch sensing controller clock enable" "0: TSC clock disabled,1: TSC clock enabled" newline bitfld.long 0x0 15. "JPEGEN,JPEG clock enable" "0: JPEG clock disabled,1: JPEG clock enabled" bitfld.long 0x0 12. "CRCEN,CRC clock enable" "0: CRC clock disabled,1: CRC clock enabled" newline bitfld.long 0x0 8. "FLASHEN,FLASH clock enable" "0: FLASH clock disabled,1: FLASH clock enabled" bitfld.long 0x0 3. "MDF1EN,MDF1 clock enable" "0: MDF1 clock disabled,1: MDF1 clock enabled" newline bitfld.long 0x0 2. "FMACEN,FMAC clock enable" "0: FMAC clock disabled,1: FMAC clock enabled" bitfld.long 0x0 1. "CORDICEN,CORDIC clock enable" "0: CORDIC clock disabled,1: CORDIC clock enabled" newline bitfld.long 0x0 0. "GPDMA1EN,GPDMA1 clock enable" "0: GPDMA1 clock disabled,1: GPDMA1 clock enabled" line.long 0x4 "RCC_AHB2ENR1,RCC AHB2 peripheral clock enable register 1" bitfld.long 0x4 31. "SRAM3EN,SRAM3 clock enable" "0: SRAM3 clock disabled,1: SRAM3 clock enabled" bitfld.long 0x4 30. "SRAM2EN,SRAM2 clock enable" "0: SRAM2 clock disabled,1: SRAM2 clock enabled" newline bitfld.long 0x4 28. "SDMMC2EN,SDMMC2 clock enable" "0: SDMMC2 clock disabled,1: SDMMC2 clock enabled" bitfld.long 0x4 27. "SDMMC1EN,SDMMC1 clock enable" "0: SDMMC1 clock disabled,1: SDMMC1 clock enabled" newline bitfld.long 0x4 24. "OTFDEC2EN,OTFDEC2 clock enable" "0: OTFDEC2 clock disabled,1: OTFDEC2 clock enabled" bitfld.long 0x4 23. "OTFDEC1EN,OTFDEC1 clock enable" "0: OTFDEC1 clock disabled,1: OTFDEC1 clock enabled" newline bitfld.long 0x4 21. "OCTOSPIMEN,OCTOSPIM clock enable" "0: OCTOSPIM clock disabled,1: OCTOSPIM clock enabled" bitfld.long 0x4 20. "SAESEN,SAES clock enable" "0: SAES clock disabled,1: SAES clock enabled" newline bitfld.long 0x4 19. "PKAEN,PKA clock enable" "0: PKA clock disabled,1: PKA clock enabled" bitfld.long 0x4 18. "RNGEN,RNG clock enable" "0: RNG clock disabled,1: RNG clock enabled" newline bitfld.long 0x4 17. "HASHEN,HASH clock enable" "0: HASH clock disabled,1: HASH clock enabled" bitfld.long 0x4 16. "AESEN,AES clock enable" "0: AES clock disabled,1: AES clock enabled" newline bitfld.long 0x4 15. "OTGHSPHYEN,OTG_HS PHY clock enable" "0: OTG_HS PHY clock disabled,1: OTG_HS PHY clock enabled" bitfld.long 0x4 14. "OTGEN,OTG_FS or OTG_HS clock enable" "0: OTG_FS or OTG_HS clock disabled,1: OTG_FS or OTG_HS clock enabled" newline bitfld.long 0x4 12. "DCMI_PSSIEN,DCMI and PSSI clock enable" "0: DCMI and PSSI clock disabled,1: DCMI and PSSI clock enabled" bitfld.long 0x4 10. "ADC12EN,ADC1 and ADC2 clock enable" "0: ADC1 and ADC2 clock disabled,1: ADC1 and ADC2 clock enabled" newline bitfld.long 0x4 9. "GPIOJEN,I/O port J clock enable" "0: I/O port J clock disabled,1: I/O port J clock enabled" bitfld.long 0x4 8. "GPIOIEN,I/O port I clock enable" "0: I/O port I clock disabled,1: I/O port I clock enabled" newline bitfld.long 0x4 7. "GPIOHEN,I/O port H clock enable" "0: I/O port H clock disabled,1: I/O port H clock enabled" bitfld.long 0x4 6. "GPIOGEN,I/O port G clock enable" "0: I/O port G clock disabled,1: I/O port G clock enabled" newline bitfld.long 0x4 5. "GPIOFEN,I/O port F clock enable" "0: I/O port F clock disabled,1: I/O port F clock enabled" bitfld.long 0x4 4. "GPIOEEN,I/O port E clock enable" "0: I/O port E clock disabled,1: I/O port E clock enabled" newline bitfld.long 0x4 3. "GPIODEN,I/O port D clock enable" "0: I/O port D clock disabled,1: I/O port D clock enabled" bitfld.long 0x4 2. "GPIOCEN,I/O port C clock enable" "0: I/O port C clock disabled,1: I/O port C clock enabled" newline bitfld.long 0x4 1. "GPIOBEN,I/O port B clock enable" "0: I/O port B clock disabled,1: I/O port B clock enabled" bitfld.long 0x4 0. "GPIOAEN,I/O port A clock enable" "0: I/O port A clock disabled,1: I/O port A clock enabled" line.long 0x8 "RCC_AHB2ENR2,RCC AHB2 peripheral clock enable register 2" bitfld.long 0x8 31. "SRAM5EN,SRAM5 clock enable" "0: SRAM5 clock disabled,1: SRAM5 clock enabled" bitfld.long 0x8 30. "SRAM6EN,SRAM6 clock enable" "0: SRAM6 clock disabled,1: SRAM6 clock enabled" newline bitfld.long 0x8 12. "HSPI1EN,HSPI1 clock enable" "0: HSPI1 clock disabled,1: HSPI1 clock enabled" bitfld.long 0x8 8. "OCTOSPI2EN,OCTOSPI2 clock enable" "0: OCTOSPI2 clock disabled,1: OCTOSPI2 clock enabled" newline bitfld.long 0x8 4. "OCTOSPI1EN,OCTOSPI1 clock enable" "0: OCTOSPI1 clock disabled,1: OCTOSPI1 clock enabled" bitfld.long 0x8 0. "FSMCEN,FSMC clock enable" "0: FSMC clock disabled,1: FSMC clock enabled" line.long 0xC "RCC_AHB3ENR,RCC AHB3 peripheral clock enable register" bitfld.long 0xC 31. "SRAM4EN,SRAM4 clock enable" "0: SRAM4 clock disabled,1: SRAM4 clock enabled" bitfld.long 0xC 12. "GTZC2EN,GTZC2 clock enable" "0: GTZC2 clock disabled,1: GTZC2 clock enabled" newline bitfld.long 0xC 10. "ADF1EN,ADF1 clock enable" "0: ADF1 clock disabled,1: ADF1 clock enabled" bitfld.long 0xC 9. "LPDMA1EN,LPDMA1 clock enable" "0: LPDMA1 clock disabled,1: LPDMA1 clock enabled" newline bitfld.long 0xC 6. "DAC1EN,DAC1 clock enable" "0: DAC1 clock disabled,1: DAC1 clock enabled" bitfld.long 0xC 5. "ADC4EN,ADC4 clock enable" "0: ADC4 clock disabled,1: ADC4 clock enabled" newline bitfld.long 0xC 2. "PWREN,PWR clock enable" "0: PWR clock disabled,1: PWR clock enabled" bitfld.long 0xC 0. "LPGPIO1EN,LPGPIO1 enable" "0: LPGPIO1 clock disabled,1: LPGPIO1 clock enabled" group.long 0x9C++0xF line.long 0x0 "RCC_APB1ENR1,RCC APB1 peripheral clock enable register 1" bitfld.long 0x0 25. "USART6EN,USART6 clock enable" "0: USART6 clock disabled,1: USART6 clock enabled" bitfld.long 0x0 24. "CRSEN,CRS clock enable" "0: CRS clock disabled,1: CRS clock enabled" newline bitfld.long 0x0 22. "I2C2EN,I2C2 clock enable" "0: I2C2 clock disabled,1: I2C2 clock enabled" bitfld.long 0x0 21. "I2C1EN,I2C1 clock enable" "0: I2C1 clock disabled,1: I2C1 clock enabled" newline bitfld.long 0x0 20. "UART5EN,UART5 clock enable" "0: UART5 clock disabled,1: UART5 clock enabled" bitfld.long 0x0 19. "UART4EN,UART4 clock enable" "0: UART4 clock disabled,1: UART4 clock enabled" newline bitfld.long 0x0 18. "USART3EN,USART3 clock enable" "0: USART3 clock disabled,1: USART3 clock enabled" bitfld.long 0x0 17. "USART2EN,USART2 clock enable" "0: USART2 clock disabled,1: USART2 clock enabled" newline bitfld.long 0x0 14. "SPI2EN,SPI2 clock enable" "0: SPI2 clock disabled,1: SPI2 clock enabled" bitfld.long 0x0 11. "WWDGEN,WWDG clock enable" "0: WWDG clock disabled,1: WWDG clock enabled" newline bitfld.long 0x0 5. "TIM7EN,TIM7 clock enable" "0: TIM7 clock disabled,1: TIM7 clock enabled" bitfld.long 0x0 4. "TIM6EN,TIM6 clock enable" "0: TIM6 clock disabled,1: TIM6 clock enabled" newline bitfld.long 0x0 3. "TIM5EN,TIM5 clock enable" "0: TIM5 clock disabled,1: TIM5 clock enabled" bitfld.long 0x0 2. "TIM4EN,TIM4 clock enable" "0: TIM4 clock disabled,1: TIM4 clock enabled" newline bitfld.long 0x0 1. "TIM3EN,TIM3 clock enable" "0: TIM3 clock disabled,1: TIM3 clock enabled" bitfld.long 0x0 0. "TIM2EN,TIM2 clock enable" "0: TIM2 clock disabled,1: TIM2 clock enabled" line.long 0x4 "RCC_APB1ENR2,RCC APB1 peripheral clock enable register 2" bitfld.long 0x4 23. "UCPD1EN,UCPD1 clock enable" "0: UCPD1 clock disabled,1: UCPD1 clock enabled" bitfld.long 0x4 9. "FDCAN1EN,FDCAN1 clock enable" "0: FDCAN1 clock disabled,1: FDCAN1 clock enabled" newline bitfld.long 0x4 7. "I2C6EN,I2C6 clock enable" "0: I2C6 clock disabled,1: I2C6 clock enabled" bitfld.long 0x4 6. "I2C5EN,I2C5 clock enable" "0: I2C5 clock disabled,1: I2C5 clock enabled" newline bitfld.long 0x4 5. "LPTIM2EN,LPTIM2 clock enable" "0: LPTIM2 clock disabled,1: LPTIM2 clock enabled" bitfld.long 0x4 1. "I2C4EN,I2C4 clock enable" "0: I2C4 clock disabled,1: I2C4 clock enabled" line.long 0x8 "RCC_APB2ENR,RCC APB2 peripheral clock enable register" bitfld.long 0x8 27. "DSIEN,DSI clock enable" "0: DSI clock disabled,1: DSI clock enabled" bitfld.long 0x8 26. "LTDCEN,LTDC clock enable" "0: LTDC clock disabled,1: LTDC clock enabled" newline bitfld.long 0x8 25. "GFXTIMEN,GFXTIM clock enable" "0: GFXTIM clock disabled,1: GFXTIM clock enabled" bitfld.long 0x8 24. "USBEN,USB clock enable" "0: USB clock disabled,1: USB clock enabled" newline bitfld.long 0x8 22. "SAI2EN,SAI2 clock enable" "0: SAI2 clock disabled,1: SAI2 clock enabled" bitfld.long 0x8 21. "SAI1EN,SAI1 clock enable" "0: SAI1 clock disabled,1: SAI1 clock enabled" newline bitfld.long 0x8 18. "TIM17EN,TIM17 clock enable" "0: TIM17 clock disabled,1: TIM17 clock enabled" bitfld.long 0x8 17. "TIM16EN,TIM16 clock enable" "0: TIM16 clock disabled,1: TIM16 clock enabled" newline bitfld.long 0x8 16. "TIM15EN,TIM15 clock enable" "0: TIM15 clock disabled,1: TIM15 clock enabled" bitfld.long 0x8 14. "USART1EN,USART1clock enable" "0: USART1 clock disabled,1: USART1 clock enabled" newline bitfld.long 0x8 13. "TIM8EN,TIM8 clock enable" "0: TIM8 clock disabled,1: TIM8 clock enabled" bitfld.long 0x8 12. "SPI1EN,SPI1 clock enable" "0: SPI1 clock disabled,1: SPI1 clock enabled" newline bitfld.long 0x8 11. "TIM1EN,TIM1 clock enable" "0: TIM1 clock disabled,1: TIM1 clock enabled" line.long 0xC "RCC_APB3ENR,RCC APB3 peripheral clock enable register" bitfld.long 0xC 21. "RTCAPBEN,RTC and TAMP APB clock enable" "0: RTC and TAMP APB clock disabled,1: RTC and TAMP APB clock enabled" bitfld.long 0xC 20. "VREFEN,VREFBUF clock enable" "0: VREFBUF clock disabled,1: VREFBUF clock enabled" newline bitfld.long 0xC 15. "COMPEN,COMP clock enable" "0: COMP clock disabled,1: COMP clock enabled" bitfld.long 0xC 14. "OPAMPEN,OPAMP clock enable" "0: OPAMP clock disabled,1: OPAMP clock enabled" newline bitfld.long 0xC 13. "LPTIM4EN,LPTIM4 clock enable" "0: LPTIM4 clock disabled,1: LPTIM4 clock enabled" bitfld.long 0xC 12. "LPTIM3EN,LPTIM3 clock enable" "0: LPTIM3 clock disabled,1: LPTIM3 clock enabled" newline bitfld.long 0xC 11. "LPTIM1EN,LPTIM1 clock enable" "0: LPTIM1 clock disabled,1: LPTIM1 clock enabled" bitfld.long 0xC 7. "I2C3EN,I2C3 clock enable" "0: I2C3 clock disabled,1: I2C3 clock enabled" newline bitfld.long 0xC 6. "LPUART1EN,LPUART1 clock enable" "0: LPUART1 clock disabled,1: LPUART1 clock enabled" bitfld.long 0xC 5. "SPI3EN,SPI3 clock enable" "0: SPI3 clock disabled,1: SPI3 clock enabled" newline bitfld.long 0xC 1. "SYSCFGEN,SYSCFG clock enable" "0: SYSCFG clock disabled,1: SYSCFG clock enabled" group.long 0xB0++0xF line.long 0x0 "RCC_AHB1SMENR,RCC AHB1 peripheral clock enable in Sleep and Stop modes register" bitfld.long 0x0 31. "SRAM1SMEN,SRAM1 clock enable during Sleep and Stop modes" "0: SRAM1 clocks disabled by the clock gating during..,1: SRAM1 clocks enabled by the clock gating during.." bitfld.long 0x0 30. "DCACHE1SMEN,DCACHE1 clock enable during Sleep and Stop modes" "0: DCACHE1 clocks disabled by the clock gating..,1: DCACHE1 clocks enabled by the clock gating.." newline bitfld.long 0x0 29. "ICACHESMEN,ICACHE clock enable during Sleep and Stop modes" "0: ICACHE clocks disabled by the clock gating..,1: ICACHE clocks enabled by the clock gating during.." bitfld.long 0x0 28. "BKPSRAMSMEN,BKPSRAM clock enable during Sleep and Stop modes" "0: BKPSRAM clocks disabled by the clock gating..,1: BKPSRAM clocks enabled by the clock gating.." newline bitfld.long 0x0 24. "GTZC1SMEN,GTZC1 clock enable during Sleep and Stop modes" "0: GTZC1 clocks disabled by the clock gating during..,1: GTZC1 clocks enabled by the clock gating during.." bitfld.long 0x0 21. "DCACHE2SMEN,DCACHE2 clock enable during Sleep and Stop modes" "0: DCACHE2 clocks disabled by the clock gating..,1: DCACHE2 clocks enabled by the clock gating.." newline bitfld.long 0x0 20. "GPU2DSMEN,GPU2D clock enable during Sleep and Stop modes" "0: GPU2D clocks disabled by the clock gating during..,1: GPU2D clocks enabled by the clock gating during.." bitfld.long 0x0 19. "GFXMMUSMEN,GFXMMU clock enable during Sleep and Stop modes" "0: GFXMMU clocks disabled by the clock gating..,1: GFXMMU clocks enabled by the clock gating during.." newline bitfld.long 0x0 18. "DMA2DSMEN,DMA2D clock enable during Sleep and Stop modes" "0: DMA2D clocks disabled by the clock gating during..,1: DMA2D clocks enabled by the clock gating during.." bitfld.long 0x0 17. "RAMCFGSMEN,RAMCFG clock enable during Sleep and Stop modes" "0: RAMCFG clocks disabled by the clock gating..,1: RAMCFG clocks enabled by the clock gating during.." newline bitfld.long 0x0 16. "TSCSMEN,TSC clocks enable during Sleep and Stop modes" "0: TSC clocks disabled by the clock gating during..,1: TSC clocks enabled by the clock gating during.." bitfld.long 0x0 15. "JPEGSMEN,JPEG clocks enable during Sleep and Stop modes" "0: JPEG clocks disabled by the clock gating during..,1: JPEG clocks enabled by the clock gating during.." newline bitfld.long 0x0 12. "CRCSMEN,CRC clocks enable during Sleep and Stop modes" "0: CRC clocks disabled by the clock gating during..,1: CRC clocks enabled by the clock gating during.." bitfld.long 0x0 8. "FLASHSMEN,FLASH clocks enable during Sleep and Stop modes" "0: FLASH clocks disabled by the clock gating during..,1: FLASH clocks enabled by the clock gating during.." newline bitfld.long 0x0 3. "MDF1SMEN,MDF1 clocks enable during Sleep and Stop modes." "0: MDF1 clocks disabled by the clock gating during..,1: MDF1 clocks enabled by the clock gating during.." bitfld.long 0x0 2. "FMACSMEN,FMAC clocks enable during Sleep and Stop modes." "0: FMAC clocks disabled by the clock gating during..,1: FMAC clocks enabled by the clock gating during.." newline bitfld.long 0x0 1. "CORDICSMEN,CORDIC clocks enable during Sleep and Stop modes" "0: CORDIC clocks disabled by the clock gating..,1: CORDIC clocks enabled by the clock gating during.." bitfld.long 0x0 0. "GPDMA1SMEN,GPDMA1 clocks enable during Sleep and Stop modes" "0: GPDMA1 clocks disabled by the clock gating..,1: GPDMA1 clocks enabled by the clock gating during.." line.long 0x4 "RCC_AHB2SMENR1,RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1" bitfld.long 0x4 31. "SRAM3SMEN,SRAM3 clock enable during Sleep and Stop modes" "0: SRAM3 clocks disabled by the clock gating during..,1: SRAM3 clocks enabled by the clock gating during.." bitfld.long 0x4 30. "SRAM2SMEN,SRAM2 clock enable during Sleep and Stop modes" "0: SRAM2 clocks disabled by the clock gating during..,1: SRAM2 clocks enabled by the clock gating during.." newline bitfld.long 0x4 28. "SDMMC2SMEN,SDMMC2 clock enable during Sleep and Stop modes" "0: SDMMC2 clocks disabled by the clock gating..,1: SDMMC2 clocks enabled by the clock gating during.." bitfld.long 0x4 27. "SDMMC1SMEN,SDMMC1 clock enable during Sleep and Stop modes" "0: SDMMC1 clocks disabled by the clock gating..,1: SDMMC1 clocks enabled by the clock gating during.." newline bitfld.long 0x4 24. "OTFDEC2SMEN,OTFDEC2 clock enable during Sleep and Stop modes" "0: OTFDEC2 clocks disabled by the clock gating..,1: OTFDEC2 clocks enabled by the clock gating.." bitfld.long 0x4 23. "OTFDEC1SMEN,OTFDEC1 clock enable during Sleep and Stop modes" "0: OTFDEC1 clocks disabled by the clock gating..,1: OTFDEC1 clocks enabled by the clock gating.." newline bitfld.long 0x4 21. "OCTOSPIMSMEN,OCTOSPIM clock enable during Sleep and Stop modes" "0: OCTOSPIM clocks disabled by the clock gating..,1: OCTOSPIM clocks enabled by the clock gating.." bitfld.long 0x4 20. "SAESSMEN,SAES accelerator clock enable during Sleep and Stop modes" "0: SAES clocks disabled by the clock gating during..,1: SAES clocks enabled by the clock gating during.." newline bitfld.long 0x4 19. "PKASMEN,PKA clock enable during Sleep and Stop modes" "0: PKA clocks disabled by the clock gating during..,1: PKA clocks enabled by the clock gating during.." bitfld.long 0x4 18. "RNGSMEN,RNG clock enable during Sleep and Stop modes" "0: RNG clocks disabled by the clock gating during..,1: RNG clocks enabled by the clock gating during.." newline bitfld.long 0x4 17. "HASHSMEN,HASH clock enable during Sleep and Stop modes" "0: HASH clocks disabled by the clock gating during..,1: HASH clocks enabled by the clock gating during.." bitfld.long 0x4 16. "AESSMEN,AES clock enable during Sleep and Stop modes" "0: AES clocks disabled by the clock gating during..,1: AES clocks enabled by the clock gating during.." newline bitfld.long 0x4 15. "OTGHSPHYSMEN,OTG_HS PHY clock enable during Sleep and Stop modes" "0: OTG_HS PHY clocks disabled by the clock gating..,1: OTG_HS PHY clocks enabled by the clock gating.." bitfld.long 0x4 14. "OTGSMEN,OTG_FS and OTG_HS clocks enable during Sleep and Stop modes" "0: OTG_FS and OTG_HS clocks disabled by the clock..,1: OTG_FS and OTG_HS clocks enabled by the clock.." newline bitfld.long 0x4 12. "DCMI_PSSISMEN,DCMI and PSSI clock enable during Sleep and Stop modes" "0: DCMI and PSSI clocks disabled by the clock..,1: DCMI and PSSI clocks enabled by the clock gating.." bitfld.long 0x4 10. "ADC12SMEN,ADC1 and ADC2 clock enable during Sleep and Stop modes" "0: ADC1 and ADC2 clocks disabled by the clock..,1: ADC1 and ADC2 clocks enabled by the clock gating.." newline bitfld.long 0x4 9. "GPIOJSMEN,I/O port J clock enable during Sleep and Stop modes" "0: I/O port J clocks disabled by the clock gating..,1: I/O port J clocks enabled by the clock gating.." bitfld.long 0x4 8. "GPIOISMEN,I/O port I clocks enable during Sleep and Stop modes" "0: I/O port I clocks disabled by the clock gating..,1: I/O port I clocks enabled by the clock gating.." newline bitfld.long 0x4 7. "GPIOHSMEN,I/O port H clocks enable during Sleep and Stop modes" "0: I/O port H clocks disabled by the clock gating..,1: I/O port H clocks enabled by the clock gating.." bitfld.long 0x4 6. "GPIOGSMEN,I/O port G clocks enable during Sleep and Stop modes" "0: I/O port G clocks disabled by the clock gating..,1: I/O port G clocks enabled by the clock gating.." newline bitfld.long 0x4 5. "GPIOFSMEN,I/O port F clocks enable during Sleep and Stop modes" "0: I/O port F clocks disabled by the clock gating..,1: I/O port F clocks enabled by the clock gating.." bitfld.long 0x4 4. "GPIOESMEN,I/O port E clocks enable during Sleep and Stop modes" "0: I/O port E clocks disabled by the clock gating..,1: I/O port E clocks enabled by the clock gating.." newline bitfld.long 0x4 3. "GPIODSMEN,I/O port D clocks enable during Sleep and Stop modes" "0: I/O port D clocks disabled by the clock gating..,1: I/O port D clocks enabled by the clock gating.." bitfld.long 0x4 2. "GPIOCSMEN,I/O port C clocks enable during Sleep and Stop modes" "0: I/O port C clocks disabled by the clock gating..,1: I/O port C clocks enabled by the clock gating.." newline bitfld.long 0x4 1. "GPIOBSMEN,I/O port B clocks enable during Sleep and Stop modes" "0: I/O port B clocks disabled by the clock gating..,1: I/O port B clocks enabled by the clock gating.." bitfld.long 0x4 0. "GPIOASMEN,I/O port A clocks enable during Sleep and Stop modes" "0: I/O port A clocks disabled by the clock gating..,1: I/O port A clocks enabled by the clock gating.." line.long 0x8 "RCC_AHB2SMENR2,RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2" bitfld.long 0x8 31. "SRAM5SMEN,SRAM5 clock enable during Sleep and Stop modes" "0: SRAM5 clocks disabled by the clock gating during..,1: SRAM5 clocks enabled by the clock gating during.." bitfld.long 0x8 30. "SRAM6SMEN,SRAM6 clock enable during Sleep and Stop modes" "0: SRAM6 clocks disabled by the clock gating during..,1: SRAM6 clocks enabled by the clock gating during.." newline bitfld.long 0x8 12. "HSPI1SMEN,HSPI1 clock enable during Sleep and Stop modes" "0: HSPI1 clocks disabled by the clock gating during..,1: HSP1I clocks enabled by the clock gating during.." bitfld.long 0x8 8. "OCTOSPI2SMEN,OCTOSPI2 clock enable during Sleep and Stop modes" "0: OCTOSPI2 clocks disabled by the clock gating..,1: OCTOSPI2 clocks enabled by the clock gating.." newline bitfld.long 0x8 4. "OCTOSPI1SMEN,OCTOSPI1 clock enable during Sleep and Stop modes" "0: OCTOSPI1 clocks disabled by the clock gating..,1: OCTOSPI1 clocks enabled by the clock gating.." bitfld.long 0x8 0. "FSMCSMEN,FSMC clock enable during Sleep and Stop modes" "0: FSMC clocks disabled by the clock gating during..,1: FSMC clocks enabled by the clock gating during.." line.long 0xC "RCC_AHB3SMENR,RCC AHB3 peripheral clock enable in Sleep and Stop modes register" bitfld.long 0xC 31. "SRAM4SMEN,SRAM4 clock enable during Sleep and Stop modes" "0: SRAM4 clocks disabled by the clock gating during..,1: SRAM4 clocks enabled by the clock gating during.." bitfld.long 0xC 12. "GTZC2SMEN,GTZC2 clock enable during Sleep and Stop modes" "0: GTZC2 clock disabled by the clock gating during..,1: GTZC2 clock enabled by the clock gating during.." newline bitfld.long 0xC 10. "ADF1SMEN,ADF1 clock enable during Sleep and Stop modes" "0: ADF1 clock disabled by the clock gating during..,1: ADF1 clock enabled by the clock gating during.." bitfld.long 0xC 9. "LPDMA1SMEN,LPDMA1 clock enable during Sleep and Stop modes" "0: LPDMA1 clock disabled by the clock gating during..,1: LPDMA1 clock enabled by the clock gating during.." newline bitfld.long 0xC 6. "DAC1SMEN,DAC1 clock enable during Sleep and Stop modes" "0: DAC1 clock disabled by the clock gating during..,1: DAC1 clock enabled by the clock gating during.." bitfld.long 0xC 5. "ADC4SMEN,ADC4 clock enable during Sleep and Stop modes" "0: ADC4 clock disabled by the clock gating during..,1: ADC4 clock enabled by the clock gating during.." newline bitfld.long 0xC 2. "PWRSMEN,PWR clock enable during Sleep and Stop modes" "0: PWR clock disabled by the clock gating during..,1: PWR clock enabled by the clock gating during.." bitfld.long 0xC 0. "LPGPIO1SMEN,LPGPIO1 enable during Sleep and Stop modes" "0: LPGPIO1 clock disabled by the clock gating..,1: LPGPIO1 clock enabled by the clock gating during.." group.long 0xC4++0xF line.long 0x0 "RCC_APB1SMENR1,RCC APB1 peripheral clock enable in Sleep and Stop modes register 1" bitfld.long 0x0 25. "USART6SMEN,USART6 clock enable during Sleep and Stop modes" "0: USART6 clocks disabled by the clock gating..,1: USART6 clocks enabled by the clock gating during.." bitfld.long 0x0 24. "CRSSMEN,CRS clock enable during Sleep and Stop modes" "0: CRS clocks disabled by the clock gating during..,1: CRS clocks enabled by the clock gating during.." newline bitfld.long 0x0 22. "I2C2SMEN,I2C2 clock enable during Sleep and Stop modes" "0: I2C2 clocks disabled by the clock gating during..,1: I2C2 clocks enabled by the clock gating during.." bitfld.long 0x0 21. "I2C1SMEN,I2C1 clock enable during Sleep and Stop modes" "0: I2C1 clocks disabled by the clock gating during..,1: I2C1 clocks enabled by the clock gating during.." newline bitfld.long 0x0 20. "UART5SMEN,UART5 clock enable during Sleep and Stop modes" "0: UART5 clocks disabled by the clock gating during..,1: UART5 clocks enabled by the clock gating during.." bitfld.long 0x0 19. "UART4SMEN,UART4 clock enable during Sleep and Stop modes" "0: UART4 clocks disabled by the clock gating during..,1: UART4 clocks enabled by the clock gating during.." newline bitfld.long 0x0 18. "USART3SMEN,USART3 clock enable during Sleep and Stop modes" "0: USART3 clocks disabled by the clock gating..,1: USART3 clocks enabled by the clock gating during.." bitfld.long 0x0 17. "USART2SMEN,USART2 clock enable during Sleep and Stop modes" "0: USART2 clocks disabled by the clock gating..,1: USART2 clocks enabled by the clock gating during.." newline bitfld.long 0x0 14. "SPI2SMEN,SPI2 clock enable during Sleep and Stop modes" "0: SPI2 clocks disabled by the clock gating during..,1: SPI2 clocks enabled by the clock gating during.." bitfld.long 0x0 11. "WWDGSMEN,Window watchdog clock enable during Sleep and Stop modes" "0: Window watchdog clocks disabled by the clock..,1: Window watchdog clocks enabled by the clock.." newline bitfld.long 0x0 5. "TIM7SMEN,TIM7 clock enable during Sleep and Stop modes" "0: TIM7 clocks disabled by the clock gating during..,1: TIM7 clocks enabled by the clock gating during.." bitfld.long 0x0 4. "TIM6SMEN,TIM6 clock enable during Sleep and Stop modes" "0: TIM6 clocks disabled by the clock gating during..,1: TIM6 clocks enabled by the clock gating during.." newline bitfld.long 0x0 3. "TIM5SMEN,TIM5 clock enable during Sleep and Stop modes" "0: TIM5 clocks disabled by the clock gating during..,1: TIM5 clocks enabled by the clock gating during.." bitfld.long 0x0 2. "TIM4SMEN,TIM4 clock enable during Sleep and Stop modes" "0: TIM4 clocks disabled by the clock gating during..,1: TIM4 clocks enabled by the clock gating during.." newline bitfld.long 0x0 1. "TIM3SMEN,TIM3 clock enable during Sleep and Stop modes" "0: TIM3 clocks disabled by the clock gating during..,1: TIM3 clocks enabled by the clock gating during.." bitfld.long 0x0 0. "TIM2SMEN,TIM2 clock enable during Sleep and Stop modes" "0: TIM2 clocks disabled by the clock gating during..,1: TIM2 clocks enabled by the clock gating during.." line.long 0x4 "RCC_APB1SMENR2,RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2" bitfld.long 0x4 23. "UCPD1SMEN,UCPD1 clock enable during Sleep and Stop modes" "0: UCPD1 clocks disabled by the clock gating during..,1: UCPD1 clocks enabled by the clock gating during.." bitfld.long 0x4 9. "FDCAN1SMEN,FDCAN1 clock enable during Sleep and Stop modes" "0: FDCAN1 clocks disabled by the clock gating..,1: FDCAN1 clocks enabled by the clock gating during.." newline bitfld.long 0x4 7. "I2C6SMEN,I2C6 clock enable during Sleep and Stop modes" "0: I2C6 clocks disabled by the clock gating during..,1: I2C6 clocks enabled by the clock gating during.." bitfld.long 0x4 6. "I2C5SMEN,I2C5 clock enable during Sleep and Stop modes" "0: I2C5 clocks disabled by the clock gating during..,1: I2C5 clocks enabled by the clock gating during.." newline bitfld.long 0x4 5. "LPTIM2SMEN,LPTIM2 clock enable during Sleep and Stop modes" "0: LPTIM2 clocks disabled by the clock gating..,1: LPTIM2 clocks enabled by the clock gating during.." bitfld.long 0x4 1. "I2C4SMEN,I2C4 clock enable during Sleep and Stop modes" "0: I2C4 clocks disabled by the clock gating during..,1: I2C4 clocks enabled by the clock gating during.." line.long 0x8 "RCC_APB2SMENR,RCC APB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x8 27. "DSISMEN,DSI clock enable during Sleep and Stop modes" "0: DSI clocks disabled by the clock gating during..,1: DSI clocks enabled by the clock gating during.." bitfld.long 0x8 26. "LTDCSMEN,LTDC clock enable during Sleep and Stop modes" "0: LTDC clocks disabled by the clock gating during..,1: LTDC clocks enabled by the clock gating during.." newline bitfld.long 0x8 25. "GFXTIMSMEN,GFXTIM clock enable during Sleep and Stop modes" "0: GFXTIM clocks disabled by the clock gating..,1: GFXTIM clocks enabled by the clock gating during.." bitfld.long 0x8 24. "USBSMEN,USB clock enable during Sleep and Stop modes" "0: USB clocks disabled by the clock gating during..,1: USB clocks enabled by the clock gating during.." newline bitfld.long 0x8 22. "SAI2SMEN,SAI2 clock enable during Sleep and Stop modes" "0: SAI2 clocks disabled by the clock gating during..,1: SAI2 clocks enabled by the clock gating during.." bitfld.long 0x8 21. "SAI1SMEN,SAI1 clock enable during Sleep and Stop modes" "0: SAI1 clocks disabled by the clock gating during..,1: SAI1 clocks enabled by the clock gating during.." newline bitfld.long 0x8 18. "TIM17SMEN,TIM17 clock enable during Sleep and Stop modes" "0: TIM17 clocks disabled by the clock gating during..,1: TIM17 clocks enabled by the clock gating during.." bitfld.long 0x8 17. "TIM16SMEN,TIM16 clock enable during Sleep and Stop modes" "0: TIM16 clocks disabled by the clock gating during..,1: TIM16 clocks enabled by the clock gating during.." newline bitfld.long 0x8 16. "TIM15SMEN,TIM15 clock enable during Sleep and Stop modes" "0: TIM15 clocks disabled by the clock gating during..,1: TIM15 clocks enabled by the clock gating during.." bitfld.long 0x8 14. "USART1SMEN,USART1 clock enable during Sleep and Stop modes" "0: USART1clocks disabled by the clock gating during..,1: USART1clocks enabled by the clock gating during.." newline bitfld.long 0x8 13. "TIM8SMEN,TIM8 clock enable during Sleep and Stop modes" "0: TIM8 clocks disabled by the clock gating during..,1: TIM8 clocks enabled by the clock gating during.." bitfld.long 0x8 12. "SPI1SMEN,SPI1 clock enable during Sleep and Stop modes" "0: SPI1 clocks disabled by the clock gating during..,1: SPI1 clocks enabled by the clock gating during.." newline bitfld.long 0x8 11. "TIM1SMEN,TIM1 clock enable during Sleep and Stop modes" "0: TIM1 clocks disabled by the clock gating during..,1: TIM1 clocks enabled by the clock gating during.." line.long 0xC "RCC_APB3SMENR,RCC APB3 peripheral clock enable in Sleep and Stop modes register" bitfld.long 0xC 21. "RTCAPBSMEN,RTC and TAMP APB clock enable during Sleep and Stop modes" "0: RTC and TAMP APB clock disabled by the clock..,1: RTC and TAMP APB clock enabled by the clock.." bitfld.long 0xC 20. "VREFSMEN,VREFBUF clock enable during Sleep and Stop modes" "0: VREFBUF clocks disabled by the clock gating..,1: VREFBUF clocks enabled by the clock gating.." newline bitfld.long 0xC 15. "COMPSMEN,COMP clock enable during Sleep and Stop modes" "0: COMP clocks disabled by the clock gating during..,1: COMP clocks enabled by the clock gating during.." bitfld.long 0xC 14. "OPAMPSMEN,OPAMP clock enable during Sleep and Stop modes" "0: OPAMP clocks disabled by the clock gating during..,1: OPAMP clocks enabled by the clock gating during.." newline bitfld.long 0xC 13. "LPTIM4SMEN,LPTIM4 clock enable during Sleep and Stop modes" "0: LPTIM4 clocks disabled by the clock gating..,1: LPTIM4 clocks enabled by the clock gating during.." bitfld.long 0xC 12. "LPTIM3SMEN,LPTIM3 clock enable during Sleep and Stop modes" "0: LPTIM3 clocks disabled by the clock gating..,1: LPTIM3 clocks enabled by the clock gating during.." newline bitfld.long 0xC 11. "LPTIM1SMEN,LPTIM1 clock enable during Sleep and Stop modes" "0: LPTIM1 clocks disabled by the clock gating..,1: LPTIM1 clocks enabled by the clock gating during.." bitfld.long 0xC 7. "I2C3SMEN,I2C3 clock enable during Sleep and Stop modes" "0: I2C3 clocks disabled by the clock gating during..,1: I2C3 clocks enabled by the clock gating during.." newline bitfld.long 0xC 6. "LPUART1SMEN,LPUART1 clock enable during Sleep and Stop modes" "0: LPUART1 clocks disabled by the clock gating..,1: LPUART1 clocks enabled by the clock gating.." bitfld.long 0xC 5. "SPI3SMEN,SPI3 clock enable during Sleep and Stop modes" "0: SPI3 clocks disabled by the clock gating during..,1: SPI3 clocks enabled by the clock gating during.." newline bitfld.long 0xC 1. "SYSCFGSMEN,SYSCFG clock enable during Sleep and Stop modes" "0: SYSCFG clocks disabled by the clock gating..,1: SYSCFG clocks enabled by the clock gating during.." group.long 0xD8++0x3 line.long 0x0 "RCC_SRDAMR,RCC SmartRun domain peripheral autonomous mode register" bitfld.long 0x0 31. "SRAM4AMEN,SRAM4 autonomous mode enable in Stop 0/1/2 mode" "0: SRAM4 autonomous mode disabled during Stop 0/1/2..,1: SRAM4 autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 29. "ADF1AMEN,ADF1 autonomous mode enable in Stop 0/1/2 mode" "0: ADF1 autonomous mode disabled during Stop 0/1/2..,1: ADF1 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 28. "LPDMA1AMEN,LPDMA1 autonomous mode enable in Stop 0/1/2 mode" "0: LPDMA1 autonomous mode disabled during Stop..,1: LPDMA1 autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 27. "DAC1AMEN,DAC1 autonomous mode enable in Stop 0/1/2 mode" "0: DAC1 autonomous mode disabled during Stop 0/1/2..,1: DAC1 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 26. "LPGPIO1AMEN,LPGPIO1 autonomous mode enable in Stop 0/1/2 mode" "0: LPGPIO1 autonomous mode disabled during Stop..,1: LPGPIO1 autonomous mode enabled during Stop.." bitfld.long 0x0 25. "ADC4AMEN,ADC4 autonomous mode enable in Stop 0/1/2 mode" "0: ADC4 autonomous mode disabled during Stop 0/1/2..,1: ADC4 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 21. "RTCAPBAMEN,RTC and TAMP autonomous mode enable in Stop 0/1/2 mode" "0: RTC and TAMP autonomous mode disabled during..,1: RTC and TAMP autonomous mode enabled during Stop.." bitfld.long 0x0 20. "VREFAMEN,VREFBUF autonomous mode enable in Stop 0/1/2 mode" "0: VREFBUF autonomous mode disabled during Stop..,1: VREFBUF autonomous mode enabled during Stop.." newline bitfld.long 0x0 15. "COMPAMEN,COMP autonomous mode enable in Stop 0/1/2 mode" "0: COMP autonomous mode disabled during Stop 0/1/2..,1: COMP autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 14. "OPAMPAMEN,OPAMP autonomous mode enable in Stop 0/1/2 mode" "0: OPAMP autonomous mode disabled during Stop 0/1/2..,1: OPAMP autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 13. "LPTIM4AMEN,LPTIM4 autonomous mode enable in Stop 0/1/2 mode" "0: LPTIM4 autonomous mode disabled during Stop..,1: LPTIM4 autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 12. "LPTIM3AMEN,LPTIM3 autonomous mode enable in Stop 0/1/2 mode" "0: LPTIM3 autonomous mode disabled during Stop..,1: LPTIM3 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 11. "LPTIM1AMEN,LPTIM1 autonomous mode enable in Stop 0/1/2 mode" "0: LPTIM1 autonomous mode disabled during Stop..,1: LPTIM1 autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 7. "I2C3AMEN,I2C3 autonomous mode enable in Stop 0/1/2 mode" "0: I2C3 autonomous mode disabled during Stop 0/1/2..,1: I2C3 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 6. "LPUART1AMEN,LPUART1 autonomous mode enable in Stop 0/1/2 mode" "0: LPUART1 autonomous mode disabled during Stop..,1: LPUART1 autonomous mode enabled during Stop.." bitfld.long 0x0 5. "SPI3AMEN,SPI3 autonomous mode enable in Stop 0 1 2 mode" "0: SPI3 autonomous mode disabled during Stop 0/1/2..,1: SPI3 autonomous mode enabled during Stop 0/1/2.." group.long 0xE0++0xB line.long 0x0 "RCC_CCIPR1,RCC peripherals independent clock configuration register 1" bitfld.long 0x0 29.--31. "TIMICSEL,Clock sources for TIM16 TIM17 and LPTIM2 internal input capture" "?,?,?,?,4: HSI/256 MSIS/1024 and MSIS/4 generated and can..,5: HSI/256 MSIS/1024 and MSIK/4 generated and can..,6: HSI/256 MSIK/1024 and MSIS/4 generated and can..,7: HSI/256 MSIK/1024 and MSIK/4 generated and can.." bitfld.long 0x0 26.--27. "ICLKSEL,Intermediate clock source selection" "0: HSI48 clock selected,1: PLL2 'Q' (pll2_q_ck) selected,2: PLL1 'Q' (pll1_q_ck) selected,3: MSIK clock selected" newline bitfld.long 0x0 24.--25. "FDCAN1SEL,FDCAN1 kernel clock source selection" "0: HSE clock selected,1: PLL1 'Q' (pll1_q_ck) selected,2: PLL2 'P' (pll2_p_ck) selected,3: reserved" bitfld.long 0x0 22.--23. "SYSTICKSEL,SysTick clock source selection" "0: HCLK/8 selected,1: LSI selected,2: LSE selected,3: reserved" newline bitfld.long 0x0 20.--21. "SPI1SEL,SPI1 kernel clock source selection" "0: PCLK2 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x0 18.--19. "LPTIM2SEL,Low-power timer 2 kernel clock source selection" "0: PCLK1 selected,1: LSI selected,2: HSI16 selected,3: LSE selected" newline bitfld.long 0x0 16.--17. "SPI2SEL,SPI2 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x0 14.--15. "I2C4SEL,I2C4 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" newline bitfld.long 0x0 12.--13. "I2C2SEL,I2C2 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x0 10.--11. "I2C1SEL,I2C1 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" newline bitfld.long 0x0 8.--9. "UART5SEL,UART5 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" bitfld.long 0x0 6.--7. "UART4SEL,UART4 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" newline bitfld.long 0x0 4.--5. "USART3SEL,USART3 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" bitfld.long 0x0 2.--3. "USART2SEL,USART2 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" newline bitfld.long 0x0 0.--1. "USART1SEL,USART1 kernel clock source selection" "0: PCLK2 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" line.long 0x4 "RCC_CCIPR2,RCC peripherals independent clock configuration register 2" bitfld.long 0x4 30.--31. "OTGHSSEL,OTG_HS PHY kernel clock source selection" "0: HSE selected,1: PLL1 'P' (pll1_q_ck) selected,2: HSE/2 selected,3: PLL1 'P' divided by 2 (pll1_p_ck/2) selected" bitfld.long 0x4 26.--27. "I2C6SEL,I2C6 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" newline bitfld.long 0x4 24.--25. "I2C5SEL,I2C5 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x4 22.--23. "HSPI1SEL,HSPI1 kernel clock source selection" "0: SYSCLK selected,1: PLL1 'Q' (pll1_q_ck) selected can be up to..,2: PLL2 'Q' (pll2_q_ck) selected can be up to..,3: PLL3 'R' (pll3_r_ck) selected can be up to.." newline bitfld.long 0x4 20.--21. "OCTOSPISEL,OCTOSPI1 and OCTOSPI2 kernel clock source selection" "0: SYSCLK selected,1: MSIK selected,2: PLL1 'Q' (pll1_q_ck) selected can be up to..,3: PLL2 'Q' (pll2_q_ck) selected can be up to.." bitfld.long 0x4 18. "LTDCSEL,LTDC kernel clock source selection" "0: PLL3 'R' (pll3_r_ck) selected,1: PLL2 'R' (pll2_r_ck) selected" newline bitfld.long 0x4 16.--17. "USART6SEL,USART6 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" bitfld.long 0x4 15. "DSISEL,DSI kernel clock source selection" "0: PLL3 'P' (pll3_p_ck) selected,1: DSI PHY PLL output selected" newline bitfld.long 0x4 14. "SDMMCSEL,SDMMC1 and SDMMC2 kernel clock source selection" "0: ICLK clock selected,1: PLL1 'P' (pll1_p_ck) selected in case higher.." bitfld.long 0x4 12.--13. "RNGSEL,RNG kernel clock source selection" "0: HSI48 selected,1: HSI48 / 2 selected can be used in range 4,2: HSI16 selected,3: reserved" newline bitfld.long 0x4 11. "SAESSEL,SAES kernel clock source selection" "0: SHSI selected,1: SHSI / 2 selected can be used in range 4" bitfld.long 0x4 8.--10. "SAI2SEL,SAI2 kernel clock source selection" "0: PLL2 'P' (pll2_p_ck) selected,1: PLL3 'P' (pll3_p_ck) selected,2: PLL1 'P' (pll1_p_ck) selected,3: input pin AUDIOCLK selected,4: HSI16 clock selected,?,?,?" newline bitfld.long 0x4 5.--7. "SAI1SEL,SAI1 kernel clock source selection" "0: PLL2 'P' (pll2_p_ck) selected,1: PLL3 'P' (pll3_p_ck) selected,2: PLL1 'P' (pll1_p_ck) selected,3: input pin AUDIOCLK selected,4: HSI16 clock selected,?,?,?" bitfld.long 0x4 0.--2. "MDF1SEL,MDF1 kernel clock source selection" "0: HCLK selected,1: PLL1 'P' (pll1_p_ck) selected,2: PLL3 'Q' (pll3_q_ck) selected,3: input pin AUDIOCLK selected,4: MSIK clock selected,?,?,?" line.long 0x8 "RCC_CCIPR3,RCC peripherals independent clock configuration register 3" bitfld.long 0x8 16.--18. "ADF1SEL,ADF1 kernel clock source selection" "0: HCLK selected,1: PLL1 'P' (pll1_p_ck) selected,2: PLL3 'Q' (pll3_q_ck) selected,3: input pin AUDIOCLK selected,4: MSIK clock selected,?,?,?" bitfld.long 0x8 15. "DAC1SEL,DAC1 sample-and-hold clock source selection" "0: LSE selected,1: LSI selected" newline bitfld.long 0x8 12.--14. "ADCDACSEL,ADC1 ADC2 ADC4 and DAC1 kernel clock source selection" "0: HCLK clock selected,1: SYSCLK selected,2: PLL2 'R' (pll2_r_ck) selected,3: HSE clock selected,4: HSI16 clock selected,5: MSIK clock selected,?,?" bitfld.long 0x8 10.--11. "LPTIM1SEL,LPTIM1 kernel clock source selection" "0: MSIK clock selected,1: LSI selected,2: HSI16 selected,3: LSE selected" newline bitfld.long 0x8 8.--9. "LPTIM34SEL,LPTIM3 and LPTIM4 kernel clock source selection" "0: MSIK clock selected,1: LSI selected,2: HSI selected,3: LSE selected" bitfld.long 0x8 6.--7. "I2C3SEL,I2C3 kernel clock source selection" "0: PCLK3 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" newline bitfld.long 0x8 3.--4. "SPI3SEL,SPI3 kernel clock source selection" "0: PCLK3 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x8 0.--2. "LPUART1SEL,LPUART1 kernel clock source selection" "0: PCLK3 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected,4: MSIK selected,?,?,?" group.long 0xF0++0x7 line.long 0x0 "RCC_BDCR,RCC backup domain control register" bitfld.long 0x0 28. "LSIPREDIV,Low-speed clock divider configuration" "0: LSI not divided,1: LSI divided by 128" bitfld.long 0x0 27. "LSIRDY,LSI oscillator ready" "0: LSI oscillator not ready,1: LSI oscillator ready" newline bitfld.long 0x0 26. "LSION,LSI oscillator enable" "0: LSI oscillator OFF,1: LSI oscillator ON" bitfld.long 0x0 25. "LSCOSEL,Low-speed clock output selection" "0: LSI clock selected,1: LSE clock selected" newline bitfld.long 0x0 24. "LSCOEN,Low-speed clock output (LSCO) enable" "0: LSCO disabled,1: LSCO enabled" bitfld.long 0x0 16. "BDRST,Backup domain software reset" "0: Reset not activated,1: Reset the entire backup domain." newline bitfld.long 0x0 15. "RTCEN,RTC and TAMP clock enable" "0: RTC and TAMP clock disabled,1: RTC and TAMP clock enabled" bitfld.long 0x0 12. "LSEGFON,LSE clock glitch filter enable" "0: LSE glitch filter disabled,1: LSE glitch filter enabled" newline rbitfld.long 0x0 11. "LSESYSRDY,LSE system clock (LSESYS) ready" "0: LSESYS clock not ready,1: LSESYS clock ready" bitfld.long 0x0 8.--9. "RTCSEL,RTC and TAMP clock source selection" "0: No clock selected,1: LSE oscillator clock selected,2: LSI oscillator clock selected,3: HSE oscillator clock divided by 32 selected" newline bitfld.long 0x0 7. "LSESYSEN,LSE system clock (LSESYS) enable" "0: LSE can be used only for RTC TAMP and CSS on LSE.,1: LSE can be used by any other peripheral or.." rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure detection" "0: No failure detected on LSE,1: Failure detected on LSE" newline bitfld.long 0x0 5. "LSECSSON,CSS on LSE enable" "0: CSS on LSE OFF,1: CSS on LSE ON" bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator drive capability" "0: 'Xtal mode' lower driving capability,1: 'Xtal mode' medium-low driving capability,2: 'Xtal mode' medium-high driving capability,3: 'Xtal mode' higher driving capability" newline bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0: LSE oscillator not bypassed,1: LSE oscillator bypassed" rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0: LSE oscillator not ready,1: LSE oscillator ready" newline bitfld.long 0x0 0. "LSEON,LSE oscillator enable" "0: LSE oscillator off,1: LSE oscillator on" line.long 0x4 "RCC_CSR,RCC control/status register" rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0: No illegal low-power mode reset occurred,1: Illegal low-power mode reset occurred" rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0: No window watchdog reset occurred,1: Window watchdog reset occurred" newline rbitfld.long 0x4 29. "IWDGRSTF,Independent watchdog reset flag" "0: No independent watchdog reset occurred,1: Independent watchdog reset occurred" rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0: No software reset occurred,1: Software reset occurred" newline rbitfld.long 0x4 27. "BORRSTF,Brownout reset or an exit from Shutdown mode reset flag" "0: No BOR/exit from Shutdown mode reset occurred,1: BOR/exit from Shutdown mode reset occurred" rbitfld.long 0x4 26. "PINRSTF,NRST pin reset flag" "0: No reset from NRST pin occurred,1: Reset from NRST pin occurred" newline rbitfld.long 0x4 25. "OBLRSTF,Option-byte loader reset flag" "0: No reset from option-byte loading occurred,1: Reset from option-byte loading occurred" bitfld.long 0x4 23. "RMVF,Remove reset flag" "0: No effect,1: Clear the reset flags." newline hexmask.long.byte 0x4 12.--15. 1. "MSISSRANGE,MSIS range after Standby mode" hexmask.long.byte 0x4 8.--11. 1. "MSIKSRANGE,MSIK range after Standby mode" group.long 0x110++0x7 line.long 0x0 "RCC_SECCFGR,RCC secure configuration register" bitfld.long 0x0 12. "RMVFSEC,Remove reset flag security" "0: non secure,1: secure" bitfld.long 0x0 11. "HSI48SEC,HSI48 clock configuration and status bit security" "0: non secure,1: secure" newline bitfld.long 0x0 10. "ICLKSEC,Intermediate clock source selection security" "0: non secure,1: secure" bitfld.long 0x0 9. "PLL3SEC,PLL3 clock configuration and status bit security" "0: non secure,1: secure" newline bitfld.long 0x0 8. "PLL2SEC,PLL2 clock configuration and status bit security" "0: non secure,1: secure" bitfld.long 0x0 7. "PLL1SEC,PLL1 clock configuration and status bit security" "0: non secure,1: secure" newline bitfld.long 0x0 6. "PRESCSEC,AHBx/APBx prescaler configuration bits security" "0: non secure,1: secure" bitfld.long 0x0 5. "SYSCLKSEC,SYSCLK clock selection STOPWUCK bit clock output on MCO configuration security" "0: non secure,1: secure" newline bitfld.long 0x0 4. "LSESEC,LSE clock configuration and status bit security" "0: non secure,1: secure" bitfld.long 0x0 3. "LSISEC,LSI clock configuration and status bit security" "0: non secure,1: secure" newline bitfld.long 0x0 2. "MSISEC,MSI clock configuration and status bit security" "0: non secure,1: secure" bitfld.long 0x0 1. "HSESEC,HSE clock configuration bits status bit and HSE_CSS security" "0: non secure,1: secure" newline bitfld.long 0x0 0. "HSISEC,HSI clock configuration and status bit security" "0: non secure,1: secure" line.long 0x4 "RCC_PRIVCFGR,RCC privilege configuration register" bitfld.long 0x4 1. "NSPRIV,RCC non-secure function privilege configuration" "0: Read and write to RCC non-secure functions can..,1: Read and write to RCC non-secure functions can.." bitfld.long 0x4 0. "SPRIV,RCC secure function privilege configuration" "0: Read and write to RCC secure functions can be..,1: Read and write to RCC secure functions can be.." tree.end tree "SEC_RCC" base ad:0x56020C00 group.long 0x0++0x3 line.long 0x0 "RCC_CR,RCC clock control register" rbitfld.long 0x0 29. "PLL3RDY,PLL3 clock ready flag" "0: PLL3 unlocked,1: PLL3 locked" bitfld.long 0x0 28. "PLL3ON,PLL3 enable" "0: PLL3 OFF,1: PLL3 ON" newline rbitfld.long 0x0 27. "PLL2RDY,PLL2 clock ready flag" "0: PLL2 unlocked,1: PLL2 locked" bitfld.long 0x0 26. "PLL2ON,PLL2 enable" "0: PLL2 OFF,1: PLL2 ON" newline rbitfld.long 0x0 25. "PLL1RDY,PLL1 clock ready flag" "0: PLL1 unlocked,1: PLL1 locked" bitfld.long 0x0 24. "PLL1ON,PLL1 enable" "0: PLL1 OFF,1: PLL1 ON" newline bitfld.long 0x0 20. "HSEEXT,HSE external clock bypass mode" "0: external HSE clock analog mode,1: external HSE clock digital mode (through I/O.." bitfld.long 0x0 19. "CSSON,Clock security system enable" "0: clock security system OFF (clock detector OFF),1: clock security system ON (clock detector ON if.." newline bitfld.long 0x0 18. "HSEBYP,HSE crystal oscillator bypass" "0: HSE crystal oscillator not bypassed,1: HSE crystal oscillator bypassed with external.." rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0: HSE oscillator not ready,1: HSE oscillator ready" newline bitfld.long 0x0 16. "HSEON,HSE clock enable" "0: HSE oscillator off,1: HSE oscillator on" rbitfld.long 0x0 15. "SHSIRDY,SHSI clock ready flag" "0: SHSI oscillator not ready,1: SHSI oscillator ready" newline bitfld.long 0x0 14. "SHSION,SHSI clock enable" "0: SHSI oscillator off,1: SHSI oscillator on" rbitfld.long 0x0 13. "HSI48RDY,HSI48 clock ready flag" "0: HSI48 oscillator not ready,1: HSI48 oscillator ready" newline bitfld.long 0x0 12. "HSI48ON,HSI48 clock enable" "0: HSI48 oscillator off,1: HSI48 oscillator on" rbitfld.long 0x0 10. "HSIRDY,HSI16 clock ready flag" "0: HSI16 oscillator not ready,1: HSI16 oscillator ready" newline bitfld.long 0x0 9. "HSIKERON,HSI16 enable for some peripheral kernels" "0: No effect on HSI16 oscillator,1: HSI16 oscillator forced on even in Stop mode" bitfld.long 0x0 8. "HSION,HSI16 clock enable" "0: HSI16 oscillator off,1: HSI16 oscillator on" newline bitfld.long 0x0 7. "MSIPLLFAST,MSI PLL mode fast startup" "0: MSI PLL normal start-up,1: MSI PLL fast start-up" bitfld.long 0x0 6. "MSIPLLSEL,MSI clock with PLL mode selection" "0: PLL mode applied to MSIK (MSI kernel) clock output,1: PLL mode applied to MSIS (MSI system) clock output" newline rbitfld.long 0x0 5. "MSIKRDY,MSIK clock ready flag" "0: MSIK (MSI kernel) oscillator not ready,1: MSIK (MSI kernel) oscillator ready" bitfld.long 0x0 4. "MSIKON,MSIK clock enable" "0: MSIK (MSI kernel) oscillator disabled,1: MSIK (MSI kernel) oscillator enabled" newline bitfld.long 0x0 3. "MSIPLLEN,MSI clock PLL-mode enable" "0: MSI PLL-mode OFF,1: MSI PLL-mode ON" rbitfld.long 0x0 2. "MSISRDY,MSIS clock ready flag" "0: MSIS (MSI system) oscillator not ready,1: MSIS (MSI system) oscillator ready" newline bitfld.long 0x0 1. "MSIKERON,MSI enable for some peripheral kernels" "0: No effect on MSI oscillator,1: MSI oscillator forced ON even in Stop mode" bitfld.long 0x0 0. "MSISON,MSIS clock enable" "0: MSIS (MSI system) oscillator off,1: MSIS (MSI system) oscillator on" group.long 0x8++0xB line.long 0x0 "RCC_ICSCR1,RCC internal clock sources calibration register 1" hexmask.long.byte 0x0 28.--31. 1. "MSISRANGE,MSIS clock ranges" hexmask.long.byte 0x0 24.--27. 1. "MSIKRANGE,MSIK clock ranges" newline bitfld.long 0x0 23. "MSIRGSEL,MSI clock range selection" "0: MSIS/MSIK ranges provided by MSISSRANGE[3:0] and..,1: MSIS/MSIK ranges provided by MSISRANGE[3:0] and.." bitfld.long 0x0 22. "MSIBIAS,MSI bias mode selection" "0: MSI bias continuous mode (clock accuracy fast..,1: MSI bias sampling mode when the regulator is in.." newline hexmask.long.byte 0x0 15.--19. 1. "MSICAL0,MSIRC0 clock calibration for MSI ranges 0 to 3" hexmask.long.byte 0x0 10.--14. 1. "MSICAL1,MSIRC1 clock calibration for MSI ranges 4 to 7" newline hexmask.long.byte 0x0 5.--9. 1. "MSICAL2,MSIRC2 clock calibration for MSI ranges 8 to 11" hexmask.long.byte 0x0 0.--4. 1. "MSICAL3,MSIRC3 clock calibration for MSI ranges 12 to 15" line.long 0x4 "RCC_ICSCR2,RCC internal clock sources calibration register 2" hexmask.long.byte 0x4 15.--19. 1. "MSITRIM0,MSI clock trimming for ranges 0 to 3" hexmask.long.byte 0x4 10.--14. 1. "MSITRIM1,MSI clock trimming for ranges 4 to 7" newline hexmask.long.byte 0x4 5.--9. 1. "MSITRIM2,MSI clock trimming for ranges 8 to 11" hexmask.long.byte 0x4 0.--4. 1. "MSITRIM3,MSI clock trimming for ranges 12 to 15" line.long 0x8 "RCC_ICSCR3,RCC internal clock sources calibration register 3" hexmask.long.byte 0x8 16.--20. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x8 0.--11. 1. "HSICAL,HSI clock calibration" rgroup.long 0x14++0x3 line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register" hexmask.long.word 0x0 0.--8. 1. "HSI48CAL,HSI48 clock calibration" group.long 0x1C++0x2F line.long 0x0 "RCC_CFGR1,RCC clock configuration register 1" bitfld.long 0x0 28.--30. "MCOPRE,microcontroller clock output prescaler" "0: MCO divided by 1,1: MCO divided by 2,2: MCO divided by 4,3: MCO divided by 8,4: MCO divided by 16,?,?,?" hexmask.long.byte 0x0 24.--27. 1. "MCOSEL,microcontroller clock output" newline bitfld.long 0x0 5. "STOPKERWUCK,wake-up from Stop kernel clock automatic enable selection" "0: MSIK oscillator automatically enabled when..,1: HSI16 oscillator automatically enabled when.." bitfld.long 0x0 4. "STOPWUCK,wake-up from Stop and CSS backup clock selection" "0: MSIS oscillator selected as wake-up from stop..,1: HSI16 oscillator selected as wake-up from stop.." newline rbitfld.long 0x0 2.--3. "SWS,system clock switch status" "0: MSIS oscillator used as system clock,1: HSI16 oscillator used as system clock,2: HSE used as system clock,3: PLL pll1_r_ck used as system clock" bitfld.long 0x0 0.--1. "SW,system clock switch" "0: MSIS selected as system clock,1: HSI16 selected as system clock,2: HSE selected as system clock,3: PLL pll1_r_ck selected as system clock" line.long 0x4 "RCC_CFGR2,RCC clock configuration register 2" bitfld.long 0x4 20. "APB2DIS,APB2 clock disable" "0: APB2 clock enabled distributed to peripherals..,1: APB2 clock disabled" bitfld.long 0x4 19. "APB1DIS,APB1 clock disable" "0: APB1 clock enabled distributed to peripherals..,1: APB1 clock disabled" newline bitfld.long 0x4 18. "AHB2DIS2,AHB2_2 clock disable" "0: AHB2_2 clock enabled distributed to peripherals..,1: AHB2_2 clock disabled" bitfld.long 0x4 17. "AHB2DIS1,AHB2_1 clock disable" "0: AHB2_1 clock enabled distributed to peripherals..,1: AHB2_1 clock disabled" newline bitfld.long 0x4 16. "AHB1DIS,AHB1 clock disable" "0: AHB1 clock enabled distributed to peripherals..,1: AHB1 clock disabled" bitfld.long 0x4 12.--14. "DPRE,DSI PHY prescaler" "?,?,?,?,4: DCLK divided by 2,5: DCLK divided by 4,6: DCLK divided by 8,7: DCLK divided by 16" newline bitfld.long 0x4 8.--10. "PPRE2,APB2 prescaler" "?,?,?,?,4: PCLK2 divided by 2,5: PCLK2 divided by 4,6: PCLK2 divided by 8,7: PCLK2 divided by 16" bitfld.long 0x4 4.--6. "PPRE1,APB1 prescaler" "?,?,?,?,4: PCLK1 divided by 2,5: PCLK1 divided by 4,6: PCLK1 divided by 8,7: PCLK1 divided by 16" newline hexmask.long.byte 0x4 0.--3. 1. "HPRE,AHB prescaler" line.long 0x8 "RCC_CFGR3,RCC clock configuration register 3" bitfld.long 0x8 17. "APB3DIS,APB3 clock disable" "0: APB3 clock enabled distributed to peripherals..,1: APB3 clock disabled" bitfld.long 0x8 16. "AHB3DIS,AHB3 clock disable" "0: AHB3 clock enabled distributed to peripherals..,1: AHB3 clock disabled" newline bitfld.long 0x8 4.--6. "PPRE3,APB3 prescaler" "?,?,?,?,4: HCLK divided by 2,5: HCLK divided by 4,6: HCLK divided by 8,7: HCLK divided by 16" line.long 0xC "RCC_PLL1CFGR,RCC PLL1 configuration register" bitfld.long 0xC 18. "PLL1REN,PLL1 DIVR divider output enable" "0: pll1_r_ck output disabled,1: pll1_r_ck output enabled" bitfld.long 0xC 17. "PLL1QEN,PLL1 DIVQ divider output enable" "0: pll1_q_ck output disabled,1: pll1_q_ck output enabled" newline bitfld.long 0xC 16. "PLL1PEN,PLL1 DIVP divider output enable" "0: pll1_p_ck output disabled,1: pll1_p_ck output enabled" hexmask.long.byte 0xC 12.--15. 1. "PLL1MBOOST,Prescaler for EPOD booster input clock" newline hexmask.long.byte 0xC 8.--11. 1. "PLL1M,Prescaler for PLL1" bitfld.long 0xC 4. "PLL1FRACEN,PLL1 fractional latch enable" "?,1: the transition 0 to 1 transfers the content of.." newline bitfld.long 0xC 2.--3. "PLL1RGE,PLL1 input frequency range" "?,?,?,3: PLL1 input (ref1_ck) clock range frequency.." bitfld.long 0xC 0.--1. "PLL1SRC,PLL1 entry clock source" "0: No clock sent to PLL1,1: MSIS clock selected as PLL1 clock entry,2: HSI16 clock selected as PLL1 clock entry,3: HSE clock selected as PLL1 clock entry" line.long 0x10 "RCC_PLL2CFGR,RCC PLL2 configuration register" bitfld.long 0x10 18. "PLL2REN,PLL2 DIVR divider output enable" "0: pll2_r_ck output disabled,1: pll2_r_ck output enabled" bitfld.long 0x10 17. "PLL2QEN,PLL2 DIVQ divider output enable" "0: pll2_q_ck output disabled,1: pll2_q_ck output enabled" newline bitfld.long 0x10 16. "PLL2PEN,PLL2 DIVP divider output enable" "0: pll2_p_ck output disabled,1: pll2_p_ck output enabled" hexmask.long.byte 0x10 8.--11. 1. "PLL2M,Prescaler for PLL2" newline bitfld.long 0x10 4. "PLL2FRACEN,PLL2 fractional latch enable" "?,1: the transition 0 to 1 transfers the content of.." bitfld.long 0x10 2.--3. "PLL2RGE,PLL2 input frequency range" "?,?,?,3: PLL2 input (ref2_ck) clock range frequency.." newline bitfld.long 0x10 0.--1. "PLL2SRC,PLL2 entry clock source" "0: No clock sent to PLL2,1: MSIS clock selected as PLL2 clock entry,2: HSI16 clock selected as PLL2 clock entry,3: HSE clock selected as PLL2 clock entry" line.long 0x14 "RCC_PLL3CFGR,RCC PLL3 configuration register" bitfld.long 0x14 18. "PLL3REN,PLL3 DIVR divider output enable" "0: pll3_r_ck output disabled,1: pll3_r_ck output enabled" bitfld.long 0x14 17. "PLL3QEN,PLL3 DIVQ divider output enable" "0: pll3_q_ck output disabled,1: pll3_q_ck output enabled" newline bitfld.long 0x14 16. "PLL3PEN,PLL3 DIVP divider output enable" "0: pll3_p_ck output disabled,1: pll3_p_ck output enabled" hexmask.long.byte 0x14 8.--11. 1. "PLL3M,Prescaler for PLL3" newline bitfld.long 0x14 4. "PLL3FRACEN,PLL3 fractional latch enable" "?,1: the transition 0 to 1 transfers the content of.." bitfld.long 0x14 2.--3. "PLL3RGE,PLL3 input frequency range" "?,?,?,3: PLL3 input (ref3_ck) clock range frequency.." newline bitfld.long 0x14 0.--1. "PLL3SRC,PLL3 entry clock source" "0: No clock sent to PLL3,1: MSIS clock selected as PLL3 clock entry,2: HSI16 clock selected as PLL3 clock entry,3: HSE clock selected as PLL3 clock entry" line.long 0x18 "RCC_PLL1DIVR,RCC PLL1 dividers register" hexmask.long.byte 0x18 24.--30. 1. "PLL1R,PLL1 DIVR division factor" hexmask.long.byte 0x18 16.--22. 1. "PLL1Q,PLL1 DIVQ division factor" newline hexmask.long.byte 0x18 9.--15. 1. "PLL1P,PLL1 DIVP division factor" hexmask.long.word 0x18 0.--8. 1. "PLL1N,Multiplication factor for PLL1 VCO" line.long 0x1C "RCC_PLL1FRACR,RCC PLL1 fractional divider register" hexmask.long.word 0x1C 3.--15. 1. "PLL1FRACN,Fractional part of the multiplication factor for PLL1 VCO" line.long 0x20 "RCC_PLL2DIVR,RCC PLL2 dividers configuration register" hexmask.long.byte 0x20 24.--30. 1. "PLL2R,PLL2 DIVR division factor" hexmask.long.byte 0x20 16.--22. 1. "PLL2Q,PLL2 DIVQ division factor" newline hexmask.long.byte 0x20 9.--15. 1. "PLL2P,PLL2 DIVP division factor" hexmask.long.word 0x20 0.--8. 1. "PLL2N,Multiplication factor for PLL2 VCO" line.long 0x24 "RCC_PLL2FRACR,RCC PLL2 fractional divider register" hexmask.long.word 0x24 3.--15. 1. "PLL2FRACN,Fractional part of the multiplication factor for PLL2 VCO" line.long 0x28 "RCC_PLL3DIVR,RCC PLL3 dividers configuration register" hexmask.long.byte 0x28 24.--30. 1. "PLL3R,PLL3 DIVR division factor" hexmask.long.byte 0x28 16.--22. 1. "PLL3Q,PLL3 DIVQ division factor" newline hexmask.long.byte 0x28 9.--15. 1. "PLL3P,PLL3 DIVP division factor" hexmask.long.word 0x28 0.--8. 1. "PLL3N,Multiplication factor for PLL3 VCO" line.long 0x2C "RCC_PLL3FRACR,RCC PLL3 fractional divider register" hexmask.long.word 0x2C 3.--15. 1. "PLL3FRACN,Fractional part of the multiplication factor for PLL3 VCO" group.long 0x50++0x3 line.long 0x0 "RCC_CIER,RCC clock interrupt enable register" bitfld.long 0x0 12. "SHSIRDYIE,SHSI ready interrupt enable" "0: SHSI ready interrupt disabled,1: SHSI ready interrupt enabled" bitfld.long 0x0 11. "MSIKRDYIE,MSIK ready interrupt enable" "0: MSIK ready interrupt disabled,1: MSIK ready interrupt enabled" newline bitfld.long 0x0 8. "PLL3RDYIE,PLL3 ready interrupt enable" "0: PLL3 lock interrupt disabled,1: PLL3 lock interrupt enabled" bitfld.long 0x0 7. "PLL2RDYIE,PLL2 ready interrupt enable" "0: PLL2 lock interrupt disabled,1: PLL2 lock interrupt enabled" newline bitfld.long 0x0 6. "PLL1RDYIE,PLL ready interrupt enable" "0: PLL1 lock interrupt disabled,1: PLL1 lock interrupt enabled" bitfld.long 0x0 5. "HSI48RDYIE,HSI48 ready interrupt enable" "0: HSI48 ready interrupt disabled,1: HSI48 ready interrupt enabled" newline bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0: HSE ready interrupt disabled,1: HSE ready interrupt enabled" bitfld.long 0x0 3. "HSIRDYIE,HSI16 ready interrupt enable" "0: HSI16 ready interrupt disabled,1: HSI16 ready interrupt enabled" newline bitfld.long 0x0 2. "MSISRDYIE,MSIS ready interrupt enable" "0: MSIS ready interrupt disabled,1: MSIS ready interrupt enabled" bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: LSE ready interrupt disabled,1: LSE ready interrupt enabled" newline bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: LSI ready interrupt disabled,1: LSI ready interrupt enabled" rgroup.long 0x54++0x3 line.long 0x0 "RCC_CIFR,RCC clock interrupt flag register" bitfld.long 0x0 12. "SHSIRDYF,SHSI ready interrupt flag" "0: No clock ready interrupt caused by the SHSI..,1: Clock ready interrupt caused by the SHSI.." bitfld.long 0x0 11. "MSIKRDYF,MSIK ready interrupt flag" "0: No clock ready interrupt caused by the MSIK..,1: Clock ready interrupt caused by the MSIK.." newline bitfld.long 0x0 10. "CSSF,Clock security system interrupt flag" "0: No clock security interrupt caused by HSE clock..,1: Clock security interrupt caused by HSE clock.." bitfld.long 0x0 8. "PLL3RDYF,PLL3 ready interrupt flag" "0: No clock ready interrupt caused by PLL3 lock,1: Clock ready interrupt caused by PLL3 lock" newline bitfld.long 0x0 7. "PLL2RDYF,PLL2 ready interrupt flag" "0: No clock ready interrupt caused by PLL2 lock,1: Clock ready interrupt caused by PLL2 lock" bitfld.long 0x0 6. "PLL1RDYF,PLL1 ready interrupt flag" "0: No clock ready interrupt caused by PLL1 lock,1: Clock ready interrupt caused by PLL1 lock" newline bitfld.long 0x0 5. "HSI48RDYF,HSI48 ready interrupt flag" "0: No clock ready interrupt caused by the HSI48..,1: Clock ready interrupt caused by the HSI48.." bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: No clock ready interrupt caused by the HSE..,1: Clock ready interrupt caused by the HSE oscillator" newline bitfld.long 0x0 3. "HSIRDYF,HSI16 ready interrupt flag" "0: No clock ready interrupt caused by the HSI16..,1: Clock ready interrupt caused by the HSI16.." bitfld.long 0x0 2. "MSISRDYF,MSIS ready interrupt flag" "0: No clock ready interrupt caused by the MSIS..,1: Clock ready interrupt caused by the MSIS.." newline bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: No clock ready interrupt caused by the LSE..,1: Clock ready interrupt caused by the LSE oscillator" bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: No clock ready interrupt caused by the LSI..,1: Clock ready interrupt caused by the LSI oscillator" wgroup.long 0x58++0x3 line.long 0x0 "RCC_CICR,RCC clock interrupt clear register" bitfld.long 0x0 12. "SHSIRDYC,SHSI oscillator ready interrupt clear" "0,1" bitfld.long 0x0 11. "MSIKRDYC,MSIK oscillator ready interrupt clear" "0,1" newline bitfld.long 0x0 10. "CSSC,Clock security system interrupt clear" "0,1" bitfld.long 0x0 8. "PLL3RDYC,PLL3 ready interrupt clear" "0,1" newline bitfld.long 0x0 7. "PLL2RDYC,PLL2 ready interrupt clear" "0,1" bitfld.long 0x0 6. "PLL1RDYC,PLL1 ready interrupt clear" "0,1" newline bitfld.long 0x0 5. "HSI48RDYC,HSI48 ready interrupt clear" "0,1" bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0,1" newline bitfld.long 0x0 3. "HSIRDYC,HSI16 ready interrupt clear" "0,1" bitfld.long 0x0 2. "MSISRDYC,MSIS ready interrupt clear" "0,1" newline bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0,1" bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0,1" group.long 0x60++0xF line.long 0x0 "RCC_AHB1RSTR,RCC AHB1 peripheral reset register" bitfld.long 0x0 20. "GPU2DRST,GPU2D reset" "0: No effect,1: Reset the GPU2D." bitfld.long 0x0 19. "GFXMMURST,GFXMMU reset" "0: No effect,1: Reset the GFXMMU." newline bitfld.long 0x0 18. "DMA2DRST,DMA2D reset" "0: No effect,1: Reset the DMA2D." bitfld.long 0x0 17. "RAMCFGRST,RAMCFG reset" "0: No effect,1: Reset the RAMCFG." newline bitfld.long 0x0 16. "TSCRST,TSC reset" "0: No effect,1: Reset the TSC." bitfld.long 0x0 15. "JPEGRST,JPEG reset" "0: No effect,1: Reset the JPEG." newline bitfld.long 0x0 12. "CRCRST,CRC reset" "0: No effect,1: Reset the CRC." bitfld.long 0x0 3. "MDF1RST,MDF1 reset" "0: No effect,1: Reset the MDF1." newline bitfld.long 0x0 2. "FMACRST,FMAC reset" "0: No effect,1: Reset the FMAC." bitfld.long 0x0 1. "CORDICRST,CORDIC reset" "0: No effect,1: Reset the CORDIC." newline bitfld.long 0x0 0. "GPDMA1RST,GPDMA1 reset" "0: No effect,1: Reset the GPDMA1." line.long 0x4 "RCC_AHB2RSTR1,RCC AHB2 peripheral reset register 1" bitfld.long 0x4 28. "SDMMC2RST,SDMMC2 reset" "0: No effect,1: Reset the SDMMC2." bitfld.long 0x4 27. "SDMMC1RST,SDMMC1 reset" "0: No effect,1: Reset the SDMMC1." newline bitfld.long 0x4 24. "OTFDEC2RST,OTFDEC2 reset" "0: No effect,1: Reset the OTFDEC2." bitfld.long 0x4 23. "OTFDEC1RST,OTFDEC1 reset" "0: No effect,1: Reset the OTFDEC1." newline bitfld.long 0x4 21. "OCTOSPIMRST,OCTOSPIM reset" "0: No effect,1: Reset the OCTOSPIM." bitfld.long 0x4 20. "SAESRST,SAES hardware accelerator reset" "0: No effect,1: Reset the SAES." newline bitfld.long 0x4 19. "PKARST,PKA reset" "0: No effect,1: Reset the PKA." bitfld.long 0x4 18. "RNGRST,RNG reset" "0: No effect,1: Reset the RNG." newline bitfld.long 0x4 17. "HASHRST,HASH reset" "0: No effect,1: Reset the HASH." bitfld.long 0x4 16. "AESRST,AES hardware accelerator reset" "0: No effect,1: Reset the AES." newline bitfld.long 0x4 14. "OTGRST,OTG_FS or OTG_HS reset" "0: No effect,1: Reset the OTG_FS or OTG_HS." bitfld.long 0x4 12. "DCMI_PSSIRST,DCMI and PSSI reset" "0: No effect,1: Reset the DCMI and PSSI." newline bitfld.long 0x4 10. "ADC12RST,ADC1 and ADC2 reset" "0: No effect,1: Reset the ADC1 and ADC2." bitfld.long 0x4 9. "GPIOJRST,I/O port J reset" "0: No effect,1: Reset the I/O port J." newline bitfld.long 0x4 8. "GPIOIRST,I/O port I reset" "0: No effect,1: Reset the I/O port .I" bitfld.long 0x4 7. "GPIOHRST,I/O port H reset" "0: No effect,1: Reset the I/O port H." newline bitfld.long 0x4 6. "GPIOGRST,I/O port G reset" "0: No effect,1: Reset the I/O port G." bitfld.long 0x4 5. "GPIOFRST,I/O port F reset" "0: No effect,1: Reset I/O port F" newline bitfld.long 0x4 4. "GPIOERST,I/O port E reset" "0: No effect,1: Reset the I/O port E." bitfld.long 0x4 3. "GPIODRST,I/O port D reset" "0: No effect,1: Reset the I/O port D." newline bitfld.long 0x4 2. "GPIOCRST,I/O port C reset" "0: No effect,1: Reset the I/O port C." bitfld.long 0x4 1. "GPIOBRST,I/O port B reset" "0: No effect,1: Reset the I/O port B." newline bitfld.long 0x4 0. "GPIOARST,I/O port A reset" "0: No effect,1: Reset the I/O port A." line.long 0x8 "RCC_AHB2RSTR2,RCC AHB2 peripheral reset register 2" bitfld.long 0x8 12. "HSPI1RST,HSPI1 reset" "0: No effect,1: Reset the HSPI1." bitfld.long 0x8 8. "OCTOSPI2RST,OCTOSPI2 reset" "0: No effect,1: Reset the OCTOSPI2." newline bitfld.long 0x8 4. "OCTOSPI1RST,OCTOSPI1 reset" "0: No effect,1: Reset the OCTOSPI1." bitfld.long 0x8 0. "FSMCRST,Flexible memory controller reset" "0: No effect,1: Reset the FSMC" line.long 0xC "RCC_AHB3RSTR,RCC AHB3 peripheral reset register" bitfld.long 0xC 10. "ADF1RST,ADF1 reset" "0: No effect,1: Reset the ADF1." bitfld.long 0xC 9. "LPDMA1RST,LPDMA1 reset" "0: No effect,1: Reset the LPDMA1." newline bitfld.long 0xC 6. "DAC1RST,DAC1 reset" "0: No effect,1: Reset the DAC1." bitfld.long 0xC 5. "ADC4RST,ADC4 reset" "0: No effect,1: Reset the ADC4 interface." newline bitfld.long 0xC 0. "LPGPIO1RST,LPGPIO1 reset" "0: No effect,1: Reset the LPGPIO1." group.long 0x74++0xF line.long 0x0 "RCC_APB1RSTR1,RCC APB1 peripheral reset register 1" bitfld.long 0x0 25. "USART6RST,USART6 reset" "0: No effect,1: Reset the USART6." bitfld.long 0x0 24. "CRSRST,CRS reset" "0: No effect,1: Reset the CRS." newline bitfld.long 0x0 22. "I2C2RST,I2C2 reset" "0: No effect,1: Reset the I2C2." bitfld.long 0x0 21. "I2C1RST,I2C1 reset" "0: No effect,1: Reset the I2C1." newline bitfld.long 0x0 20. "UART5RST,UART5 reset" "0: No effect,1: Reset the UART5." bitfld.long 0x0 19. "UART4RST,UART4 reset" "0: No effect,1: Reset the UART4." newline bitfld.long 0x0 18. "USART3RST,USART3 reset" "0: No effect,1: Reset the USART3." bitfld.long 0x0 17. "USART2RST,USART2 reset" "0: No effect,1: Reset the USART2" newline bitfld.long 0x0 14. "SPI2RST,SPI2 reset" "0: No effect,1: Reset the SPI2." bitfld.long 0x0 5. "TIM7RST,TIM7 reset" "0: No effect,1: Reset the TIM7." newline bitfld.long 0x0 4. "TIM6RST,TIM6 reset" "0: No effect,1: Reset the TIM6." bitfld.long 0x0 3. "TIM5RST,TIM5 reset" "0: No effect,1: Reset the TIM5." newline bitfld.long 0x0 2. "TIM4RST,TIM4 reset" "0: No effect,1: Reset the TIM4." bitfld.long 0x0 1. "TIM3RST,TIM3 reset" "0: No effect,1: Reset the TIM3." newline bitfld.long 0x0 0. "TIM2RST,TIM2 reset" "0: No effect,1: Reset the TIM2." line.long 0x4 "RCC_APB1RSTR2,RCC APB1 peripheral reset register 2" bitfld.long 0x4 23. "UCPD1RST,UCPD1 reset" "0: No effect,1: Reset the UCPD1." bitfld.long 0x4 9. "FDCAN1RST,FDCAN1 reset" "0: No effect,1: Reset the FDCAN1." newline bitfld.long 0x4 7. "I2C6RST,I2C6 reset" "0: No effect,1: Reset the I2C6." bitfld.long 0x4 6. "I2C5RST,I2C5 reset" "0: No effect,1: Reset the I2C5." newline bitfld.long 0x4 5. "LPTIM2RST,LPTIM2 reset" "0: No effect,1: Reset the LPTIM2." bitfld.long 0x4 1. "I2C4RST,I2C4 reset" "0: No effect,1: Reset the I2C4." line.long 0x8 "RCC_APB2RSTR,RCC APB2 peripheral reset register" bitfld.long 0x8 27. "DSIRST,DSI reset" "0: No effect,1: Reset the DSI." bitfld.long 0x8 26. "LTDCRST,LTDC reset" "0: No effect,1: Reset the LTDC." newline bitfld.long 0x8 25. "GFXTIMRST,GFXTIM reset" "0: No effect,1: Reset the GFXTIM." bitfld.long 0x8 24. "USBRST,USB reset" "0: No effect,1: Reset the USB." newline bitfld.long 0x8 22. "SAI2RST,SAI2 reset" "0: No effect,1: Reset the SAI2." bitfld.long 0x8 21. "SAI1RST,SAI1 reset" "0: No effect,1: Reset the SAI1." newline bitfld.long 0x8 18. "TIM17RST,TIM17 reset" "0: No effect,1: Reset the TIM17." bitfld.long 0x8 17. "TIM16RST,TIM16 reset" "0: No effect,1: Reset the TIM16." newline bitfld.long 0x8 16. "TIM15RST,TIM15 reset" "0: No effect,1: Reset the TIM15." bitfld.long 0x8 14. "USART1RST,USART1 reset" "0: No effect,1: Reset the USART1." newline bitfld.long 0x8 13. "TIM8RST,TIM8 reset" "0: No effect,1: Reset the TIM8." bitfld.long 0x8 12. "SPI1RST,SPI1 reset" "0: No effect,1: Reset the SPI1." newline bitfld.long 0x8 11. "TIM1RST,TIM1 reset" "0: No effect,1: Reset the TIM1." line.long 0xC "RCC_APB3RSTR,RCC APB3 peripheral reset register" bitfld.long 0xC 20. "VREFRST,VREFBUF reset" "0: No effect,1: Reset the VREFBUF." bitfld.long 0xC 15. "COMPRST,COMP reset" "0: No effect,1: Reset the COMP." newline bitfld.long 0xC 14. "OPAMPRST,OPAMP reset" "0: No effect,1: Reset the OPAMP." bitfld.long 0xC 13. "LPTIM4RST,LPTIM4 reset" "0: No effect,1: Reset the LPTIM4." newline bitfld.long 0xC 12. "LPTIM3RST,LPTIM3 reset" "0: No effect,1: Reset the LPTIM3." bitfld.long 0xC 11. "LPTIM1RST,LPTIM1 reset" "0: No effect,1: Reset the LPTIM1." newline bitfld.long 0xC 7. "I2C3RST,I2C3 reset" "0: No effect,1: Reset the I2C3." bitfld.long 0xC 6. "LPUART1RST,LPUART1 reset" "0: No effect,1: Reset the LPUART1." newline bitfld.long 0xC 5. "SPI3RST,SPI3 reset" "0: No effect,1: Reset the SPI3." bitfld.long 0xC 1. "SYSCFGRST,SYSCFG reset" "0: No effect,1: Reset the SYSCFG." group.long 0x88++0xF line.long 0x0 "RCC_AHB1ENR,RCC AHB1 peripheral clock enable register" bitfld.long 0x0 31. "SRAM1EN,SRAM1 clock enable" "0: SRAM1 clock disabled,1: SRAM1 clock enabled" bitfld.long 0x0 30. "DCACHE1EN,DCACHE1 clock enable" "0: DCACHE1 clock disabled,1: DCACHE1 clock enabled" newline bitfld.long 0x0 28. "BKPSRAMEN,BKPSRAM clock enable" "0: BKPSRAM clock disabled,1: BKPSRAM clock enabled" bitfld.long 0x0 24. "GTZC1EN,GTZC1 clock enable" "0: GTZC1 clock disabled,1: GTZC1 clock enabled" newline bitfld.long 0x0 21. "DCACHE2EN,DCACHE2 clock enable" "0: DCACHE2 clock disabled,1: DCACHE2 clock enabled" bitfld.long 0x0 20. "GPU2DEN,GPU2D clock enable" "0: GPU2D clock disabled,1: GPU2D clock enabled" newline bitfld.long 0x0 19. "GFXMMUEN,GFXMMU clock enable" "0: GFXMMU clock disabled,1: GFXMMU clock enabled" bitfld.long 0x0 18. "DMA2DEN,DMA2D clock enable" "0: DMA2D clock disabled,1: DMA2D clock enabled" newline bitfld.long 0x0 17. "RAMCFGEN,RAMCFG clock enable" "0: RAMCFG clock disabled,1: RAMCFG clock enabled" bitfld.long 0x0 16. "TSCEN,Touch sensing controller clock enable" "0: TSC clock disabled,1: TSC clock enabled" newline bitfld.long 0x0 15. "JPEGEN,JPEG clock enable" "0: JPEG clock disabled,1: JPEG clock enabled" bitfld.long 0x0 12. "CRCEN,CRC clock enable" "0: CRC clock disabled,1: CRC clock enabled" newline bitfld.long 0x0 8. "FLASHEN,FLASH clock enable" "0: FLASH clock disabled,1: FLASH clock enabled" bitfld.long 0x0 3. "MDF1EN,MDF1 clock enable" "0: MDF1 clock disabled,1: MDF1 clock enabled" newline bitfld.long 0x0 2. "FMACEN,FMAC clock enable" "0: FMAC clock disabled,1: FMAC clock enabled" bitfld.long 0x0 1. "CORDICEN,CORDIC clock enable" "0: CORDIC clock disabled,1: CORDIC clock enabled" newline bitfld.long 0x0 0. "GPDMA1EN,GPDMA1 clock enable" "0: GPDMA1 clock disabled,1: GPDMA1 clock enabled" line.long 0x4 "RCC_AHB2ENR1,RCC AHB2 peripheral clock enable register 1" bitfld.long 0x4 31. "SRAM3EN,SRAM3 clock enable" "0: SRAM3 clock disabled,1: SRAM3 clock enabled" bitfld.long 0x4 30. "SRAM2EN,SRAM2 clock enable" "0: SRAM2 clock disabled,1: SRAM2 clock enabled" newline bitfld.long 0x4 28. "SDMMC2EN,SDMMC2 clock enable" "0: SDMMC2 clock disabled,1: SDMMC2 clock enabled" bitfld.long 0x4 27. "SDMMC1EN,SDMMC1 clock enable" "0: SDMMC1 clock disabled,1: SDMMC1 clock enabled" newline bitfld.long 0x4 24. "OTFDEC2EN,OTFDEC2 clock enable" "0: OTFDEC2 clock disabled,1: OTFDEC2 clock enabled" bitfld.long 0x4 23. "OTFDEC1EN,OTFDEC1 clock enable" "0: OTFDEC1 clock disabled,1: OTFDEC1 clock enabled" newline bitfld.long 0x4 21. "OCTOSPIMEN,OCTOSPIM clock enable" "0: OCTOSPIM clock disabled,1: OCTOSPIM clock enabled" bitfld.long 0x4 20. "SAESEN,SAES clock enable" "0: SAES clock disabled,1: SAES clock enabled" newline bitfld.long 0x4 19. "PKAEN,PKA clock enable" "0: PKA clock disabled,1: PKA clock enabled" bitfld.long 0x4 18. "RNGEN,RNG clock enable" "0: RNG clock disabled,1: RNG clock enabled" newline bitfld.long 0x4 17. "HASHEN,HASH clock enable" "0: HASH clock disabled,1: HASH clock enabled" bitfld.long 0x4 16. "AESEN,AES clock enable" "0: AES clock disabled,1: AES clock enabled" newline bitfld.long 0x4 15. "OTGHSPHYEN,OTG_HS PHY clock enable" "0: OTG_HS PHY clock disabled,1: OTG_HS PHY clock enabled" bitfld.long 0x4 14. "OTGEN,OTG_FS or OTG_HS clock enable" "0: OTG_FS or OTG_HS clock disabled,1: OTG_FS or OTG_HS clock enabled" newline bitfld.long 0x4 12. "DCMI_PSSIEN,DCMI and PSSI clock enable" "0: DCMI and PSSI clock disabled,1: DCMI and PSSI clock enabled" bitfld.long 0x4 10. "ADC12EN,ADC1 and ADC2 clock enable" "0: ADC1 and ADC2 clock disabled,1: ADC1 and ADC2 clock enabled" newline bitfld.long 0x4 9. "GPIOJEN,I/O port J clock enable" "0: I/O port J clock disabled,1: I/O port J clock enabled" bitfld.long 0x4 8. "GPIOIEN,I/O port I clock enable" "0: I/O port I clock disabled,1: I/O port I clock enabled" newline bitfld.long 0x4 7. "GPIOHEN,I/O port H clock enable" "0: I/O port H clock disabled,1: I/O port H clock enabled" bitfld.long 0x4 6. "GPIOGEN,I/O port G clock enable" "0: I/O port G clock disabled,1: I/O port G clock enabled" newline bitfld.long 0x4 5. "GPIOFEN,I/O port F clock enable" "0: I/O port F clock disabled,1: I/O port F clock enabled" bitfld.long 0x4 4. "GPIOEEN,I/O port E clock enable" "0: I/O port E clock disabled,1: I/O port E clock enabled" newline bitfld.long 0x4 3. "GPIODEN,I/O port D clock enable" "0: I/O port D clock disabled,1: I/O port D clock enabled" bitfld.long 0x4 2. "GPIOCEN,I/O port C clock enable" "0: I/O port C clock disabled,1: I/O port C clock enabled" newline bitfld.long 0x4 1. "GPIOBEN,I/O port B clock enable" "0: I/O port B clock disabled,1: I/O port B clock enabled" bitfld.long 0x4 0. "GPIOAEN,I/O port A clock enable" "0: I/O port A clock disabled,1: I/O port A clock enabled" line.long 0x8 "RCC_AHB2ENR2,RCC AHB2 peripheral clock enable register 2" bitfld.long 0x8 31. "SRAM5EN,SRAM5 clock enable" "0: SRAM5 clock disabled,1: SRAM5 clock enabled" bitfld.long 0x8 30. "SRAM6EN,SRAM6 clock enable" "0: SRAM6 clock disabled,1: SRAM6 clock enabled" newline bitfld.long 0x8 12. "HSPI1EN,HSPI1 clock enable" "0: HSPI1 clock disabled,1: HSPI1 clock enabled" bitfld.long 0x8 8. "OCTOSPI2EN,OCTOSPI2 clock enable" "0: OCTOSPI2 clock disabled,1: OCTOSPI2 clock enabled" newline bitfld.long 0x8 4. "OCTOSPI1EN,OCTOSPI1 clock enable" "0: OCTOSPI1 clock disabled,1: OCTOSPI1 clock enabled" bitfld.long 0x8 0. "FSMCEN,FSMC clock enable" "0: FSMC clock disabled,1: FSMC clock enabled" line.long 0xC "RCC_AHB3ENR,RCC AHB3 peripheral clock enable register" bitfld.long 0xC 31. "SRAM4EN,SRAM4 clock enable" "0: SRAM4 clock disabled,1: SRAM4 clock enabled" bitfld.long 0xC 12. "GTZC2EN,GTZC2 clock enable" "0: GTZC2 clock disabled,1: GTZC2 clock enabled" newline bitfld.long 0xC 10. "ADF1EN,ADF1 clock enable" "0: ADF1 clock disabled,1: ADF1 clock enabled" bitfld.long 0xC 9. "LPDMA1EN,LPDMA1 clock enable" "0: LPDMA1 clock disabled,1: LPDMA1 clock enabled" newline bitfld.long 0xC 6. "DAC1EN,DAC1 clock enable" "0: DAC1 clock disabled,1: DAC1 clock enabled" bitfld.long 0xC 5. "ADC4EN,ADC4 clock enable" "0: ADC4 clock disabled,1: ADC4 clock enabled" newline bitfld.long 0xC 2. "PWREN,PWR clock enable" "0: PWR clock disabled,1: PWR clock enabled" bitfld.long 0xC 0. "LPGPIO1EN,LPGPIO1 enable" "0: LPGPIO1 clock disabled,1: LPGPIO1 clock enabled" group.long 0x9C++0xF line.long 0x0 "RCC_APB1ENR1,RCC APB1 peripheral clock enable register 1" bitfld.long 0x0 25. "USART6EN,USART6 clock enable" "0: USART6 clock disabled,1: USART6 clock enabled" bitfld.long 0x0 24. "CRSEN,CRS clock enable" "0: CRS clock disabled,1: CRS clock enabled" newline bitfld.long 0x0 22. "I2C2EN,I2C2 clock enable" "0: I2C2 clock disabled,1: I2C2 clock enabled" bitfld.long 0x0 21. "I2C1EN,I2C1 clock enable" "0: I2C1 clock disabled,1: I2C1 clock enabled" newline bitfld.long 0x0 20. "UART5EN,UART5 clock enable" "0: UART5 clock disabled,1: UART5 clock enabled" bitfld.long 0x0 19. "UART4EN,UART4 clock enable" "0: UART4 clock disabled,1: UART4 clock enabled" newline bitfld.long 0x0 18. "USART3EN,USART3 clock enable" "0: USART3 clock disabled,1: USART3 clock enabled" bitfld.long 0x0 17. "USART2EN,USART2 clock enable" "0: USART2 clock disabled,1: USART2 clock enabled" newline bitfld.long 0x0 14. "SPI2EN,SPI2 clock enable" "0: SPI2 clock disabled,1: SPI2 clock enabled" bitfld.long 0x0 11. "WWDGEN,WWDG clock enable" "0: WWDG clock disabled,1: WWDG clock enabled" newline bitfld.long 0x0 5. "TIM7EN,TIM7 clock enable" "0: TIM7 clock disabled,1: TIM7 clock enabled" bitfld.long 0x0 4. "TIM6EN,TIM6 clock enable" "0: TIM6 clock disabled,1: TIM6 clock enabled" newline bitfld.long 0x0 3. "TIM5EN,TIM5 clock enable" "0: TIM5 clock disabled,1: TIM5 clock enabled" bitfld.long 0x0 2. "TIM4EN,TIM4 clock enable" "0: TIM4 clock disabled,1: TIM4 clock enabled" newline bitfld.long 0x0 1. "TIM3EN,TIM3 clock enable" "0: TIM3 clock disabled,1: TIM3 clock enabled" bitfld.long 0x0 0. "TIM2EN,TIM2 clock enable" "0: TIM2 clock disabled,1: TIM2 clock enabled" line.long 0x4 "RCC_APB1ENR2,RCC APB1 peripheral clock enable register 2" bitfld.long 0x4 23. "UCPD1EN,UCPD1 clock enable" "0: UCPD1 clock disabled,1: UCPD1 clock enabled" bitfld.long 0x4 9. "FDCAN1EN,FDCAN1 clock enable" "0: FDCAN1 clock disabled,1: FDCAN1 clock enabled" newline bitfld.long 0x4 7. "I2C6EN,I2C6 clock enable" "0: I2C6 clock disabled,1: I2C6 clock enabled" bitfld.long 0x4 6. "I2C5EN,I2C5 clock enable" "0: I2C5 clock disabled,1: I2C5 clock enabled" newline bitfld.long 0x4 5. "LPTIM2EN,LPTIM2 clock enable" "0: LPTIM2 clock disabled,1: LPTIM2 clock enabled" bitfld.long 0x4 1. "I2C4EN,I2C4 clock enable" "0: I2C4 clock disabled,1: I2C4 clock enabled" line.long 0x8 "RCC_APB2ENR,RCC APB2 peripheral clock enable register" bitfld.long 0x8 27. "DSIEN,DSI clock enable" "0: DSI clock disabled,1: DSI clock enabled" bitfld.long 0x8 26. "LTDCEN,LTDC clock enable" "0: LTDC clock disabled,1: LTDC clock enabled" newline bitfld.long 0x8 25. "GFXTIMEN,GFXTIM clock enable" "0: GFXTIM clock disabled,1: GFXTIM clock enabled" bitfld.long 0x8 24. "USBEN,USB clock enable" "0: USB clock disabled,1: USB clock enabled" newline bitfld.long 0x8 22. "SAI2EN,SAI2 clock enable" "0: SAI2 clock disabled,1: SAI2 clock enabled" bitfld.long 0x8 21. "SAI1EN,SAI1 clock enable" "0: SAI1 clock disabled,1: SAI1 clock enabled" newline bitfld.long 0x8 18. "TIM17EN,TIM17 clock enable" "0: TIM17 clock disabled,1: TIM17 clock enabled" bitfld.long 0x8 17. "TIM16EN,TIM16 clock enable" "0: TIM16 clock disabled,1: TIM16 clock enabled" newline bitfld.long 0x8 16. "TIM15EN,TIM15 clock enable" "0: TIM15 clock disabled,1: TIM15 clock enabled" bitfld.long 0x8 14. "USART1EN,USART1clock enable" "0: USART1 clock disabled,1: USART1 clock enabled" newline bitfld.long 0x8 13. "TIM8EN,TIM8 clock enable" "0: TIM8 clock disabled,1: TIM8 clock enabled" bitfld.long 0x8 12. "SPI1EN,SPI1 clock enable" "0: SPI1 clock disabled,1: SPI1 clock enabled" newline bitfld.long 0x8 11. "TIM1EN,TIM1 clock enable" "0: TIM1 clock disabled,1: TIM1 clock enabled" line.long 0xC "RCC_APB3ENR,RCC APB3 peripheral clock enable register" bitfld.long 0xC 21. "RTCAPBEN,RTC and TAMP APB clock enable" "0: RTC and TAMP APB clock disabled,1: RTC and TAMP APB clock enabled" bitfld.long 0xC 20. "VREFEN,VREFBUF clock enable" "0: VREFBUF clock disabled,1: VREFBUF clock enabled" newline bitfld.long 0xC 15. "COMPEN,COMP clock enable" "0: COMP clock disabled,1: COMP clock enabled" bitfld.long 0xC 14. "OPAMPEN,OPAMP clock enable" "0: OPAMP clock disabled,1: OPAMP clock enabled" newline bitfld.long 0xC 13. "LPTIM4EN,LPTIM4 clock enable" "0: LPTIM4 clock disabled,1: LPTIM4 clock enabled" bitfld.long 0xC 12. "LPTIM3EN,LPTIM3 clock enable" "0: LPTIM3 clock disabled,1: LPTIM3 clock enabled" newline bitfld.long 0xC 11. "LPTIM1EN,LPTIM1 clock enable" "0: LPTIM1 clock disabled,1: LPTIM1 clock enabled" bitfld.long 0xC 7. "I2C3EN,I2C3 clock enable" "0: I2C3 clock disabled,1: I2C3 clock enabled" newline bitfld.long 0xC 6. "LPUART1EN,LPUART1 clock enable" "0: LPUART1 clock disabled,1: LPUART1 clock enabled" bitfld.long 0xC 5. "SPI3EN,SPI3 clock enable" "0: SPI3 clock disabled,1: SPI3 clock enabled" newline bitfld.long 0xC 1. "SYSCFGEN,SYSCFG clock enable" "0: SYSCFG clock disabled,1: SYSCFG clock enabled" group.long 0xB0++0xF line.long 0x0 "RCC_AHB1SMENR,RCC AHB1 peripheral clock enable in Sleep and Stop modes register" bitfld.long 0x0 31. "SRAM1SMEN,SRAM1 clock enable during Sleep and Stop modes" "0: SRAM1 clocks disabled by the clock gating during..,1: SRAM1 clocks enabled by the clock gating during.." bitfld.long 0x0 30. "DCACHE1SMEN,DCACHE1 clock enable during Sleep and Stop modes" "0: DCACHE1 clocks disabled by the clock gating..,1: DCACHE1 clocks enabled by the clock gating.." newline bitfld.long 0x0 29. "ICACHESMEN,ICACHE clock enable during Sleep and Stop modes" "0: ICACHE clocks disabled by the clock gating..,1: ICACHE clocks enabled by the clock gating during.." bitfld.long 0x0 28. "BKPSRAMSMEN,BKPSRAM clock enable during Sleep and Stop modes" "0: BKPSRAM clocks disabled by the clock gating..,1: BKPSRAM clocks enabled by the clock gating.." newline bitfld.long 0x0 24. "GTZC1SMEN,GTZC1 clock enable during Sleep and Stop modes" "0: GTZC1 clocks disabled by the clock gating during..,1: GTZC1 clocks enabled by the clock gating during.." bitfld.long 0x0 21. "DCACHE2SMEN,DCACHE2 clock enable during Sleep and Stop modes" "0: DCACHE2 clocks disabled by the clock gating..,1: DCACHE2 clocks enabled by the clock gating.." newline bitfld.long 0x0 20. "GPU2DSMEN,GPU2D clock enable during Sleep and Stop modes" "0: GPU2D clocks disabled by the clock gating during..,1: GPU2D clocks enabled by the clock gating during.." bitfld.long 0x0 19. "GFXMMUSMEN,GFXMMU clock enable during Sleep and Stop modes" "0: GFXMMU clocks disabled by the clock gating..,1: GFXMMU clocks enabled by the clock gating during.." newline bitfld.long 0x0 18. "DMA2DSMEN,DMA2D clock enable during Sleep and Stop modes" "0: DMA2D clocks disabled by the clock gating during..,1: DMA2D clocks enabled by the clock gating during.." bitfld.long 0x0 17. "RAMCFGSMEN,RAMCFG clock enable during Sleep and Stop modes" "0: RAMCFG clocks disabled by the clock gating..,1: RAMCFG clocks enabled by the clock gating during.." newline bitfld.long 0x0 16. "TSCSMEN,TSC clocks enable during Sleep and Stop modes" "0: TSC clocks disabled by the clock gating during..,1: TSC clocks enabled by the clock gating during.." bitfld.long 0x0 15. "JPEGSMEN,JPEG clocks enable during Sleep and Stop modes" "0: JPEG clocks disabled by the clock gating during..,1: JPEG clocks enabled by the clock gating during.." newline bitfld.long 0x0 12. "CRCSMEN,CRC clocks enable during Sleep and Stop modes" "0: CRC clocks disabled by the clock gating during..,1: CRC clocks enabled by the clock gating during.." bitfld.long 0x0 8. "FLASHSMEN,FLASH clocks enable during Sleep and Stop modes" "0: FLASH clocks disabled by the clock gating during..,1: FLASH clocks enabled by the clock gating during.." newline bitfld.long 0x0 3. "MDF1SMEN,MDF1 clocks enable during Sleep and Stop modes." "0: MDF1 clocks disabled by the clock gating during..,1: MDF1 clocks enabled by the clock gating during.." bitfld.long 0x0 2. "FMACSMEN,FMAC clocks enable during Sleep and Stop modes." "0: FMAC clocks disabled by the clock gating during..,1: FMAC clocks enabled by the clock gating during.." newline bitfld.long 0x0 1. "CORDICSMEN,CORDIC clocks enable during Sleep and Stop modes" "0: CORDIC clocks disabled by the clock gating..,1: CORDIC clocks enabled by the clock gating during.." bitfld.long 0x0 0. "GPDMA1SMEN,GPDMA1 clocks enable during Sleep and Stop modes" "0: GPDMA1 clocks disabled by the clock gating..,1: GPDMA1 clocks enabled by the clock gating during.." line.long 0x4 "RCC_AHB2SMENR1,RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1" bitfld.long 0x4 31. "SRAM3SMEN,SRAM3 clock enable during Sleep and Stop modes" "0: SRAM3 clocks disabled by the clock gating during..,1: SRAM3 clocks enabled by the clock gating during.." bitfld.long 0x4 30. "SRAM2SMEN,SRAM2 clock enable during Sleep and Stop modes" "0: SRAM2 clocks disabled by the clock gating during..,1: SRAM2 clocks enabled by the clock gating during.." newline bitfld.long 0x4 28. "SDMMC2SMEN,SDMMC2 clock enable during Sleep and Stop modes" "0: SDMMC2 clocks disabled by the clock gating..,1: SDMMC2 clocks enabled by the clock gating during.." bitfld.long 0x4 27. "SDMMC1SMEN,SDMMC1 clock enable during Sleep and Stop modes" "0: SDMMC1 clocks disabled by the clock gating..,1: SDMMC1 clocks enabled by the clock gating during.." newline bitfld.long 0x4 24. "OTFDEC2SMEN,OTFDEC2 clock enable during Sleep and Stop modes" "0: OTFDEC2 clocks disabled by the clock gating..,1: OTFDEC2 clocks enabled by the clock gating.." bitfld.long 0x4 23. "OTFDEC1SMEN,OTFDEC1 clock enable during Sleep and Stop modes" "0: OTFDEC1 clocks disabled by the clock gating..,1: OTFDEC1 clocks enabled by the clock gating.." newline bitfld.long 0x4 21. "OCTOSPIMSMEN,OCTOSPIM clock enable during Sleep and Stop modes" "0: OCTOSPIM clocks disabled by the clock gating..,1: OCTOSPIM clocks enabled by the clock gating.." bitfld.long 0x4 20. "SAESSMEN,SAES accelerator clock enable during Sleep and Stop modes" "0: SAES clocks disabled by the clock gating during..,1: SAES clocks enabled by the clock gating during.." newline bitfld.long 0x4 19. "PKASMEN,PKA clock enable during Sleep and Stop modes" "0: PKA clocks disabled by the clock gating during..,1: PKA clocks enabled by the clock gating during.." bitfld.long 0x4 18. "RNGSMEN,RNG clock enable during Sleep and Stop modes" "0: RNG clocks disabled by the clock gating during..,1: RNG clocks enabled by the clock gating during.." newline bitfld.long 0x4 17. "HASHSMEN,HASH clock enable during Sleep and Stop modes" "0: HASH clocks disabled by the clock gating during..,1: HASH clocks enabled by the clock gating during.." bitfld.long 0x4 16. "AESSMEN,AES clock enable during Sleep and Stop modes" "0: AES clocks disabled by the clock gating during..,1: AES clocks enabled by the clock gating during.." newline bitfld.long 0x4 15. "OTGHSPHYSMEN,OTG_HS PHY clock enable during Sleep and Stop modes" "0: OTG_HS PHY clocks disabled by the clock gating..,1: OTG_HS PHY clocks enabled by the clock gating.." bitfld.long 0x4 14. "OTGSMEN,OTG_FS and OTG_HS clocks enable during Sleep and Stop modes" "0: OTG_FS and OTG_HS clocks disabled by the clock..,1: OTG_FS and OTG_HS clocks enabled by the clock.." newline bitfld.long 0x4 12. "DCMI_PSSISMEN,DCMI and PSSI clock enable during Sleep and Stop modes" "0: DCMI and PSSI clocks disabled by the clock..,1: DCMI and PSSI clocks enabled by the clock gating.." bitfld.long 0x4 10. "ADC12SMEN,ADC1 and ADC2 clock enable during Sleep and Stop modes" "0: ADC1 and ADC2 clocks disabled by the clock..,1: ADC1 and ADC2 clocks enabled by the clock gating.." newline bitfld.long 0x4 9. "GPIOJSMEN,I/O port J clock enable during Sleep and Stop modes" "0: I/O port J clocks disabled by the clock gating..,1: I/O port J clocks enabled by the clock gating.." bitfld.long 0x4 8. "GPIOISMEN,I/O port I clocks enable during Sleep and Stop modes" "0: I/O port I clocks disabled by the clock gating..,1: I/O port I clocks enabled by the clock gating.." newline bitfld.long 0x4 7. "GPIOHSMEN,I/O port H clocks enable during Sleep and Stop modes" "0: I/O port H clocks disabled by the clock gating..,1: I/O port H clocks enabled by the clock gating.." bitfld.long 0x4 6. "GPIOGSMEN,I/O port G clocks enable during Sleep and Stop modes" "0: I/O port G clocks disabled by the clock gating..,1: I/O port G clocks enabled by the clock gating.." newline bitfld.long 0x4 5. "GPIOFSMEN,I/O port F clocks enable during Sleep and Stop modes" "0: I/O port F clocks disabled by the clock gating..,1: I/O port F clocks enabled by the clock gating.." bitfld.long 0x4 4. "GPIOESMEN,I/O port E clocks enable during Sleep and Stop modes" "0: I/O port E clocks disabled by the clock gating..,1: I/O port E clocks enabled by the clock gating.." newline bitfld.long 0x4 3. "GPIODSMEN,I/O port D clocks enable during Sleep and Stop modes" "0: I/O port D clocks disabled by the clock gating..,1: I/O port D clocks enabled by the clock gating.." bitfld.long 0x4 2. "GPIOCSMEN,I/O port C clocks enable during Sleep and Stop modes" "0: I/O port C clocks disabled by the clock gating..,1: I/O port C clocks enabled by the clock gating.." newline bitfld.long 0x4 1. "GPIOBSMEN,I/O port B clocks enable during Sleep and Stop modes" "0: I/O port B clocks disabled by the clock gating..,1: I/O port B clocks enabled by the clock gating.." bitfld.long 0x4 0. "GPIOASMEN,I/O port A clocks enable during Sleep and Stop modes" "0: I/O port A clocks disabled by the clock gating..,1: I/O port A clocks enabled by the clock gating.." line.long 0x8 "RCC_AHB2SMENR2,RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2" bitfld.long 0x8 31. "SRAM5SMEN,SRAM5 clock enable during Sleep and Stop modes" "0: SRAM5 clocks disabled by the clock gating during..,1: SRAM5 clocks enabled by the clock gating during.." bitfld.long 0x8 30. "SRAM6SMEN,SRAM6 clock enable during Sleep and Stop modes" "0: SRAM6 clocks disabled by the clock gating during..,1: SRAM6 clocks enabled by the clock gating during.." newline bitfld.long 0x8 12. "HSPI1SMEN,HSPI1 clock enable during Sleep and Stop modes" "0: HSPI1 clocks disabled by the clock gating during..,1: HSP1I clocks enabled by the clock gating during.." bitfld.long 0x8 8. "OCTOSPI2SMEN,OCTOSPI2 clock enable during Sleep and Stop modes" "0: OCTOSPI2 clocks disabled by the clock gating..,1: OCTOSPI2 clocks enabled by the clock gating.." newline bitfld.long 0x8 4. "OCTOSPI1SMEN,OCTOSPI1 clock enable during Sleep and Stop modes" "0: OCTOSPI1 clocks disabled by the clock gating..,1: OCTOSPI1 clocks enabled by the clock gating.." bitfld.long 0x8 0. "FSMCSMEN,FSMC clock enable during Sleep and Stop modes" "0: FSMC clocks disabled by the clock gating during..,1: FSMC clocks enabled by the clock gating during.." line.long 0xC "RCC_AHB3SMENR,RCC AHB3 peripheral clock enable in Sleep and Stop modes register" bitfld.long 0xC 31. "SRAM4SMEN,SRAM4 clock enable during Sleep and Stop modes" "0: SRAM4 clocks disabled by the clock gating during..,1: SRAM4 clocks enabled by the clock gating during.." bitfld.long 0xC 12. "GTZC2SMEN,GTZC2 clock enable during Sleep and Stop modes" "0: GTZC2 clock disabled by the clock gating during..,1: GTZC2 clock enabled by the clock gating during.." newline bitfld.long 0xC 10. "ADF1SMEN,ADF1 clock enable during Sleep and Stop modes" "0: ADF1 clock disabled by the clock gating during..,1: ADF1 clock enabled by the clock gating during.." bitfld.long 0xC 9. "LPDMA1SMEN,LPDMA1 clock enable during Sleep and Stop modes" "0: LPDMA1 clock disabled by the clock gating during..,1: LPDMA1 clock enabled by the clock gating during.." newline bitfld.long 0xC 6. "DAC1SMEN,DAC1 clock enable during Sleep and Stop modes" "0: DAC1 clock disabled by the clock gating during..,1: DAC1 clock enabled by the clock gating during.." bitfld.long 0xC 5. "ADC4SMEN,ADC4 clock enable during Sleep and Stop modes" "0: ADC4 clock disabled by the clock gating during..,1: ADC4 clock enabled by the clock gating during.." newline bitfld.long 0xC 2. "PWRSMEN,PWR clock enable during Sleep and Stop modes" "0: PWR clock disabled by the clock gating during..,1: PWR clock enabled by the clock gating during.." bitfld.long 0xC 0. "LPGPIO1SMEN,LPGPIO1 enable during Sleep and Stop modes" "0: LPGPIO1 clock disabled by the clock gating..,1: LPGPIO1 clock enabled by the clock gating during.." group.long 0xC4++0xF line.long 0x0 "RCC_APB1SMENR1,RCC APB1 peripheral clock enable in Sleep and Stop modes register 1" bitfld.long 0x0 25. "USART6SMEN,USART6 clock enable during Sleep and Stop modes" "0: USART6 clocks disabled by the clock gating..,1: USART6 clocks enabled by the clock gating during.." bitfld.long 0x0 24. "CRSSMEN,CRS clock enable during Sleep and Stop modes" "0: CRS clocks disabled by the clock gating during..,1: CRS clocks enabled by the clock gating during.." newline bitfld.long 0x0 22. "I2C2SMEN,I2C2 clock enable during Sleep and Stop modes" "0: I2C2 clocks disabled by the clock gating during..,1: I2C2 clocks enabled by the clock gating during.." bitfld.long 0x0 21. "I2C1SMEN,I2C1 clock enable during Sleep and Stop modes" "0: I2C1 clocks disabled by the clock gating during..,1: I2C1 clocks enabled by the clock gating during.." newline bitfld.long 0x0 20. "UART5SMEN,UART5 clock enable during Sleep and Stop modes" "0: UART5 clocks disabled by the clock gating during..,1: UART5 clocks enabled by the clock gating during.." bitfld.long 0x0 19. "UART4SMEN,UART4 clock enable during Sleep and Stop modes" "0: UART4 clocks disabled by the clock gating during..,1: UART4 clocks enabled by the clock gating during.." newline bitfld.long 0x0 18. "USART3SMEN,USART3 clock enable during Sleep and Stop modes" "0: USART3 clocks disabled by the clock gating..,1: USART3 clocks enabled by the clock gating during.." bitfld.long 0x0 17. "USART2SMEN,USART2 clock enable during Sleep and Stop modes" "0: USART2 clocks disabled by the clock gating..,1: USART2 clocks enabled by the clock gating during.." newline bitfld.long 0x0 14. "SPI2SMEN,SPI2 clock enable during Sleep and Stop modes" "0: SPI2 clocks disabled by the clock gating during..,1: SPI2 clocks enabled by the clock gating during.." bitfld.long 0x0 11. "WWDGSMEN,Window watchdog clock enable during Sleep and Stop modes" "0: Window watchdog clocks disabled by the clock..,1: Window watchdog clocks enabled by the clock.." newline bitfld.long 0x0 5. "TIM7SMEN,TIM7 clock enable during Sleep and Stop modes" "0: TIM7 clocks disabled by the clock gating during..,1: TIM7 clocks enabled by the clock gating during.." bitfld.long 0x0 4. "TIM6SMEN,TIM6 clock enable during Sleep and Stop modes" "0: TIM6 clocks disabled by the clock gating during..,1: TIM6 clocks enabled by the clock gating during.." newline bitfld.long 0x0 3. "TIM5SMEN,TIM5 clock enable during Sleep and Stop modes" "0: TIM5 clocks disabled by the clock gating during..,1: TIM5 clocks enabled by the clock gating during.." bitfld.long 0x0 2. "TIM4SMEN,TIM4 clock enable during Sleep and Stop modes" "0: TIM4 clocks disabled by the clock gating during..,1: TIM4 clocks enabled by the clock gating during.." newline bitfld.long 0x0 1. "TIM3SMEN,TIM3 clock enable during Sleep and Stop modes" "0: TIM3 clocks disabled by the clock gating during..,1: TIM3 clocks enabled by the clock gating during.." bitfld.long 0x0 0. "TIM2SMEN,TIM2 clock enable during Sleep and Stop modes" "0: TIM2 clocks disabled by the clock gating during..,1: TIM2 clocks enabled by the clock gating during.." line.long 0x4 "RCC_APB1SMENR2,RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2" bitfld.long 0x4 23. "UCPD1SMEN,UCPD1 clock enable during Sleep and Stop modes" "0: UCPD1 clocks disabled by the clock gating during..,1: UCPD1 clocks enabled by the clock gating during.." bitfld.long 0x4 9. "FDCAN1SMEN,FDCAN1 clock enable during Sleep and Stop modes" "0: FDCAN1 clocks disabled by the clock gating..,1: FDCAN1 clocks enabled by the clock gating during.." newline bitfld.long 0x4 7. "I2C6SMEN,I2C6 clock enable during Sleep and Stop modes" "0: I2C6 clocks disabled by the clock gating during..,1: I2C6 clocks enabled by the clock gating during.." bitfld.long 0x4 6. "I2C5SMEN,I2C5 clock enable during Sleep and Stop modes" "0: I2C5 clocks disabled by the clock gating during..,1: I2C5 clocks enabled by the clock gating during.." newline bitfld.long 0x4 5. "LPTIM2SMEN,LPTIM2 clock enable during Sleep and Stop modes" "0: LPTIM2 clocks disabled by the clock gating..,1: LPTIM2 clocks enabled by the clock gating during.." bitfld.long 0x4 1. "I2C4SMEN,I2C4 clock enable during Sleep and Stop modes" "0: I2C4 clocks disabled by the clock gating during..,1: I2C4 clocks enabled by the clock gating during.." line.long 0x8 "RCC_APB2SMENR,RCC APB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x8 27. "DSISMEN,DSI clock enable during Sleep and Stop modes" "0: DSI clocks disabled by the clock gating during..,1: DSI clocks enabled by the clock gating during.." bitfld.long 0x8 26. "LTDCSMEN,LTDC clock enable during Sleep and Stop modes" "0: LTDC clocks disabled by the clock gating during..,1: LTDC clocks enabled by the clock gating during.." newline bitfld.long 0x8 25. "GFXTIMSMEN,GFXTIM clock enable during Sleep and Stop modes" "0: GFXTIM clocks disabled by the clock gating..,1: GFXTIM clocks enabled by the clock gating during.." bitfld.long 0x8 24. "USBSMEN,USB clock enable during Sleep and Stop modes" "0: USB clocks disabled by the clock gating during..,1: USB clocks enabled by the clock gating during.." newline bitfld.long 0x8 22. "SAI2SMEN,SAI2 clock enable during Sleep and Stop modes" "0: SAI2 clocks disabled by the clock gating during..,1: SAI2 clocks enabled by the clock gating during.." bitfld.long 0x8 21. "SAI1SMEN,SAI1 clock enable during Sleep and Stop modes" "0: SAI1 clocks disabled by the clock gating during..,1: SAI1 clocks enabled by the clock gating during.." newline bitfld.long 0x8 18. "TIM17SMEN,TIM17 clock enable during Sleep and Stop modes" "0: TIM17 clocks disabled by the clock gating during..,1: TIM17 clocks enabled by the clock gating during.." bitfld.long 0x8 17. "TIM16SMEN,TIM16 clock enable during Sleep and Stop modes" "0: TIM16 clocks disabled by the clock gating during..,1: TIM16 clocks enabled by the clock gating during.." newline bitfld.long 0x8 16. "TIM15SMEN,TIM15 clock enable during Sleep and Stop modes" "0: TIM15 clocks disabled by the clock gating during..,1: TIM15 clocks enabled by the clock gating during.." bitfld.long 0x8 14. "USART1SMEN,USART1 clock enable during Sleep and Stop modes" "0: USART1clocks disabled by the clock gating during..,1: USART1clocks enabled by the clock gating during.." newline bitfld.long 0x8 13. "TIM8SMEN,TIM8 clock enable during Sleep and Stop modes" "0: TIM8 clocks disabled by the clock gating during..,1: TIM8 clocks enabled by the clock gating during.." bitfld.long 0x8 12. "SPI1SMEN,SPI1 clock enable during Sleep and Stop modes" "0: SPI1 clocks disabled by the clock gating during..,1: SPI1 clocks enabled by the clock gating during.." newline bitfld.long 0x8 11. "TIM1SMEN,TIM1 clock enable during Sleep and Stop modes" "0: TIM1 clocks disabled by the clock gating during..,1: TIM1 clocks enabled by the clock gating during.." line.long 0xC "RCC_APB3SMENR,RCC APB3 peripheral clock enable in Sleep and Stop modes register" bitfld.long 0xC 21. "RTCAPBSMEN,RTC and TAMP APB clock enable during Sleep and Stop modes" "0: RTC and TAMP APB clock disabled by the clock..,1: RTC and TAMP APB clock enabled by the clock.." bitfld.long 0xC 20. "VREFSMEN,VREFBUF clock enable during Sleep and Stop modes" "0: VREFBUF clocks disabled by the clock gating..,1: VREFBUF clocks enabled by the clock gating.." newline bitfld.long 0xC 15. "COMPSMEN,COMP clock enable during Sleep and Stop modes" "0: COMP clocks disabled by the clock gating during..,1: COMP clocks enabled by the clock gating during.." bitfld.long 0xC 14. "OPAMPSMEN,OPAMP clock enable during Sleep and Stop modes" "0: OPAMP clocks disabled by the clock gating during..,1: OPAMP clocks enabled by the clock gating during.." newline bitfld.long 0xC 13. "LPTIM4SMEN,LPTIM4 clock enable during Sleep and Stop modes" "0: LPTIM4 clocks disabled by the clock gating..,1: LPTIM4 clocks enabled by the clock gating during.." bitfld.long 0xC 12. "LPTIM3SMEN,LPTIM3 clock enable during Sleep and Stop modes" "0: LPTIM3 clocks disabled by the clock gating..,1: LPTIM3 clocks enabled by the clock gating during.." newline bitfld.long 0xC 11. "LPTIM1SMEN,LPTIM1 clock enable during Sleep and Stop modes" "0: LPTIM1 clocks disabled by the clock gating..,1: LPTIM1 clocks enabled by the clock gating during.." bitfld.long 0xC 7. "I2C3SMEN,I2C3 clock enable during Sleep and Stop modes" "0: I2C3 clocks disabled by the clock gating during..,1: I2C3 clocks enabled by the clock gating during.." newline bitfld.long 0xC 6. "LPUART1SMEN,LPUART1 clock enable during Sleep and Stop modes" "0: LPUART1 clocks disabled by the clock gating..,1: LPUART1 clocks enabled by the clock gating.." bitfld.long 0xC 5. "SPI3SMEN,SPI3 clock enable during Sleep and Stop modes" "0: SPI3 clocks disabled by the clock gating during..,1: SPI3 clocks enabled by the clock gating during.." newline bitfld.long 0xC 1. "SYSCFGSMEN,SYSCFG clock enable during Sleep and Stop modes" "0: SYSCFG clocks disabled by the clock gating..,1: SYSCFG clocks enabled by the clock gating during.." group.long 0xD8++0x3 line.long 0x0 "RCC_SRDAMR,RCC SmartRun domain peripheral autonomous mode register" bitfld.long 0x0 31. "SRAM4AMEN,SRAM4 autonomous mode enable in Stop 0/1/2 mode" "0: SRAM4 autonomous mode disabled during Stop 0/1/2..,1: SRAM4 autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 29. "ADF1AMEN,ADF1 autonomous mode enable in Stop 0/1/2 mode" "0: ADF1 autonomous mode disabled during Stop 0/1/2..,1: ADF1 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 28. "LPDMA1AMEN,LPDMA1 autonomous mode enable in Stop 0/1/2 mode" "0: LPDMA1 autonomous mode disabled during Stop..,1: LPDMA1 autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 27. "DAC1AMEN,DAC1 autonomous mode enable in Stop 0/1/2 mode" "0: DAC1 autonomous mode disabled during Stop 0/1/2..,1: DAC1 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 26. "LPGPIO1AMEN,LPGPIO1 autonomous mode enable in Stop 0/1/2 mode" "0: LPGPIO1 autonomous mode disabled during Stop..,1: LPGPIO1 autonomous mode enabled during Stop.." bitfld.long 0x0 25. "ADC4AMEN,ADC4 autonomous mode enable in Stop 0/1/2 mode" "0: ADC4 autonomous mode disabled during Stop 0/1/2..,1: ADC4 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 21. "RTCAPBAMEN,RTC and TAMP autonomous mode enable in Stop 0/1/2 mode" "0: RTC and TAMP autonomous mode disabled during..,1: RTC and TAMP autonomous mode enabled during Stop.." bitfld.long 0x0 20. "VREFAMEN,VREFBUF autonomous mode enable in Stop 0/1/2 mode" "0: VREFBUF autonomous mode disabled during Stop..,1: VREFBUF autonomous mode enabled during Stop.." newline bitfld.long 0x0 15. "COMPAMEN,COMP autonomous mode enable in Stop 0/1/2 mode" "0: COMP autonomous mode disabled during Stop 0/1/2..,1: COMP autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 14. "OPAMPAMEN,OPAMP autonomous mode enable in Stop 0/1/2 mode" "0: OPAMP autonomous mode disabled during Stop 0/1/2..,1: OPAMP autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 13. "LPTIM4AMEN,LPTIM4 autonomous mode enable in Stop 0/1/2 mode" "0: LPTIM4 autonomous mode disabled during Stop..,1: LPTIM4 autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 12. "LPTIM3AMEN,LPTIM3 autonomous mode enable in Stop 0/1/2 mode" "0: LPTIM3 autonomous mode disabled during Stop..,1: LPTIM3 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 11. "LPTIM1AMEN,LPTIM1 autonomous mode enable in Stop 0/1/2 mode" "0: LPTIM1 autonomous mode disabled during Stop..,1: LPTIM1 autonomous mode enabled during Stop 0/1/2.." bitfld.long 0x0 7. "I2C3AMEN,I2C3 autonomous mode enable in Stop 0/1/2 mode" "0: I2C3 autonomous mode disabled during Stop 0/1/2..,1: I2C3 autonomous mode enabled during Stop 0/1/2.." newline bitfld.long 0x0 6. "LPUART1AMEN,LPUART1 autonomous mode enable in Stop 0/1/2 mode" "0: LPUART1 autonomous mode disabled during Stop..,1: LPUART1 autonomous mode enabled during Stop.." bitfld.long 0x0 5. "SPI3AMEN,SPI3 autonomous mode enable in Stop 0 1 2 mode" "0: SPI3 autonomous mode disabled during Stop 0/1/2..,1: SPI3 autonomous mode enabled during Stop 0/1/2.." group.long 0xE0++0xB line.long 0x0 "RCC_CCIPR1,RCC peripherals independent clock configuration register 1" bitfld.long 0x0 29.--31. "TIMICSEL,Clock sources for TIM16 TIM17 and LPTIM2 internal input capture" "?,?,?,?,4: HSI/256 MSIS/1024 and MSIS/4 generated and can..,5: HSI/256 MSIS/1024 and MSIK/4 generated and can..,6: HSI/256 MSIK/1024 and MSIS/4 generated and can..,7: HSI/256 MSIK/1024 and MSIK/4 generated and can.." bitfld.long 0x0 26.--27. "ICLKSEL,Intermediate clock source selection" "0: HSI48 clock selected,1: PLL2 'Q' (pll2_q_ck) selected,2: PLL1 'Q' (pll1_q_ck) selected,3: MSIK clock selected" newline bitfld.long 0x0 24.--25. "FDCAN1SEL,FDCAN1 kernel clock source selection" "0: HSE clock selected,1: PLL1 'Q' (pll1_q_ck) selected,2: PLL2 'P' (pll2_p_ck) selected,3: reserved" bitfld.long 0x0 22.--23. "SYSTICKSEL,SysTick clock source selection" "0: HCLK/8 selected,1: LSI selected,2: LSE selected,3: reserved" newline bitfld.long 0x0 20.--21. "SPI1SEL,SPI1 kernel clock source selection" "0: PCLK2 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x0 18.--19. "LPTIM2SEL,Low-power timer 2 kernel clock source selection" "0: PCLK1 selected,1: LSI selected,2: HSI16 selected,3: LSE selected" newline bitfld.long 0x0 16.--17. "SPI2SEL,SPI2 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x0 14.--15. "I2C4SEL,I2C4 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" newline bitfld.long 0x0 12.--13. "I2C2SEL,I2C2 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x0 10.--11. "I2C1SEL,I2C1 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" newline bitfld.long 0x0 8.--9. "UART5SEL,UART5 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" bitfld.long 0x0 6.--7. "UART4SEL,UART4 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" newline bitfld.long 0x0 4.--5. "USART3SEL,USART3 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" bitfld.long 0x0 2.--3. "USART2SEL,USART2 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" newline bitfld.long 0x0 0.--1. "USART1SEL,USART1 kernel clock source selection" "0: PCLK2 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" line.long 0x4 "RCC_CCIPR2,RCC peripherals independent clock configuration register 2" bitfld.long 0x4 30.--31. "OTGHSSEL,OTG_HS PHY kernel clock source selection" "0: HSE selected,1: PLL1 'P' (pll1_q_ck) selected,2: HSE/2 selected,3: PLL1 'P' divided by 2 (pll1_p_ck/2) selected" bitfld.long 0x4 26.--27. "I2C6SEL,I2C6 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" newline bitfld.long 0x4 24.--25. "I2C5SEL,I2C5 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x4 22.--23. "HSPI1SEL,HSPI1 kernel clock source selection" "0: SYSCLK selected,1: PLL1 'Q' (pll1_q_ck) selected can be up to..,2: PLL2 'Q' (pll2_q_ck) selected can be up to..,3: PLL3 'R' (pll3_r_ck) selected can be up to.." newline bitfld.long 0x4 20.--21. "OCTOSPISEL,OCTOSPI1 and OCTOSPI2 kernel clock source selection" "0: SYSCLK selected,1: MSIK selected,2: PLL1 'Q' (pll1_q_ck) selected can be up to..,3: PLL2 'Q' (pll2_q_ck) selected can be up to.." bitfld.long 0x4 18. "LTDCSEL,LTDC kernel clock source selection" "0: PLL3 'R' (pll3_r_ck) selected,1: PLL2 'R' (pll2_r_ck) selected" newline bitfld.long 0x4 16.--17. "USART6SEL,USART6 kernel clock source selection" "0: PCLK1 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected" bitfld.long 0x4 15. "DSISEL,DSI kernel clock source selection" "0: PLL3 'P' (pll3_p_ck) selected,1: DSI PHY PLL output selected" newline bitfld.long 0x4 14. "SDMMCSEL,SDMMC1 and SDMMC2 kernel clock source selection" "0: ICLK clock selected,1: PLL1 'P' (pll1_p_ck) selected in case higher.." bitfld.long 0x4 12.--13. "RNGSEL,RNG kernel clock source selection" "0: HSI48 selected,1: HSI48 / 2 selected can be used in range 4,2: HSI16 selected,3: reserved" newline bitfld.long 0x4 11. "SAESSEL,SAES kernel clock source selection" "0: SHSI selected,1: SHSI / 2 selected can be used in range 4" bitfld.long 0x4 8.--10. "SAI2SEL,SAI2 kernel clock source selection" "0: PLL2 'P' (pll2_p_ck) selected,1: PLL3 'P' (pll3_p_ck) selected,2: PLL1 'P' (pll1_p_ck) selected,3: input pin AUDIOCLK selected,4: HSI16 clock selected,?,?,?" newline bitfld.long 0x4 5.--7. "SAI1SEL,SAI1 kernel clock source selection" "0: PLL2 'P' (pll2_p_ck) selected,1: PLL3 'P' (pll3_p_ck) selected,2: PLL1 'P' (pll1_p_ck) selected,3: input pin AUDIOCLK selected,4: HSI16 clock selected,?,?,?" bitfld.long 0x4 0.--2. "MDF1SEL,MDF1 kernel clock source selection" "0: HCLK selected,1: PLL1 'P' (pll1_p_ck) selected,2: PLL3 'Q' (pll3_q_ck) selected,3: input pin AUDIOCLK selected,4: MSIK clock selected,?,?,?" line.long 0x8 "RCC_CCIPR3,RCC peripherals independent clock configuration register 3" bitfld.long 0x8 16.--18. "ADF1SEL,ADF1 kernel clock source selection" "0: HCLK selected,1: PLL1 'P' (pll1_p_ck) selected,2: PLL3 'Q' (pll3_q_ck) selected,3: input pin AUDIOCLK selected,4: MSIK clock selected,?,?,?" bitfld.long 0x8 15. "DAC1SEL,DAC1 sample-and-hold clock source selection" "0: LSE selected,1: LSI selected" newline bitfld.long 0x8 12.--14. "ADCDACSEL,ADC1 ADC2 ADC4 and DAC1 kernel clock source selection" "0: HCLK clock selected,1: SYSCLK selected,2: PLL2 'R' (pll2_r_ck) selected,3: HSE clock selected,4: HSI16 clock selected,5: MSIK clock selected,?,?" bitfld.long 0x8 10.--11. "LPTIM1SEL,LPTIM1 kernel clock source selection" "0: MSIK clock selected,1: LSI selected,2: HSI16 selected,3: LSE selected" newline bitfld.long 0x8 8.--9. "LPTIM34SEL,LPTIM3 and LPTIM4 kernel clock source selection" "0: MSIK clock selected,1: LSI selected,2: HSI selected,3: LSE selected" bitfld.long 0x8 6.--7. "I2C3SEL,I2C3 kernel clock source selection" "0: PCLK3 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" newline bitfld.long 0x8 3.--4. "SPI3SEL,SPI3 kernel clock source selection" "0: PCLK3 selected,1: SYSCLK selected,2: HSI16 selected,3: MSIK selected" bitfld.long 0x8 0.--2. "LPUART1SEL,LPUART1 kernel clock source selection" "0: PCLK3 selected,1: SYSCLK selected,2: HSI16 selected,3: LSE selected,4: MSIK selected,?,?,?" group.long 0xF0++0x7 line.long 0x0 "RCC_BDCR,RCC backup domain control register" bitfld.long 0x0 28. "LSIPREDIV,Low-speed clock divider configuration" "0: LSI not divided,1: LSI divided by 128" bitfld.long 0x0 27. "LSIRDY,LSI oscillator ready" "0: LSI oscillator not ready,1: LSI oscillator ready" newline bitfld.long 0x0 26. "LSION,LSI oscillator enable" "0: LSI oscillator OFF,1: LSI oscillator ON" bitfld.long 0x0 25. "LSCOSEL,Low-speed clock output selection" "0: LSI clock selected,1: LSE clock selected" newline bitfld.long 0x0 24. "LSCOEN,Low-speed clock output (LSCO) enable" "0: LSCO disabled,1: LSCO enabled" bitfld.long 0x0 16. "BDRST,Backup domain software reset" "0: Reset not activated,1: Reset the entire backup domain." newline bitfld.long 0x0 15. "RTCEN,RTC and TAMP clock enable" "0: RTC and TAMP clock disabled,1: RTC and TAMP clock enabled" bitfld.long 0x0 12. "LSEGFON,LSE clock glitch filter enable" "0: LSE glitch filter disabled,1: LSE glitch filter enabled" newline rbitfld.long 0x0 11. "LSESYSRDY,LSE system clock (LSESYS) ready" "0: LSESYS clock not ready,1: LSESYS clock ready" bitfld.long 0x0 8.--9. "RTCSEL,RTC and TAMP clock source selection" "0: No clock selected,1: LSE oscillator clock selected,2: LSI oscillator clock selected,3: HSE oscillator clock divided by 32 selected" newline bitfld.long 0x0 7. "LSESYSEN,LSE system clock (LSESYS) enable" "0: LSE can be used only for RTC TAMP and CSS on LSE.,1: LSE can be used by any other peripheral or.." rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure detection" "0: No failure detected on LSE,1: Failure detected on LSE" newline bitfld.long 0x0 5. "LSECSSON,CSS on LSE enable" "0: CSS on LSE OFF,1: CSS on LSE ON" bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator drive capability" "0: 'Xtal mode' lower driving capability,1: 'Xtal mode' medium-low driving capability,2: 'Xtal mode' medium-high driving capability,3: 'Xtal mode' higher driving capability" newline bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0: LSE oscillator not bypassed,1: LSE oscillator bypassed" rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0: LSE oscillator not ready,1: LSE oscillator ready" newline bitfld.long 0x0 0. "LSEON,LSE oscillator enable" "0: LSE oscillator off,1: LSE oscillator on" line.long 0x4 "RCC_CSR,RCC control/status register" rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0: No illegal low-power mode reset occurred,1: Illegal low-power mode reset occurred" rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0: No window watchdog reset occurred,1: Window watchdog reset occurred" newline rbitfld.long 0x4 29. "IWDGRSTF,Independent watchdog reset flag" "0: No independent watchdog reset occurred,1: Independent watchdog reset occurred" rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0: No software reset occurred,1: Software reset occurred" newline rbitfld.long 0x4 27. "BORRSTF,Brownout reset or an exit from Shutdown mode reset flag" "0: No BOR/exit from Shutdown mode reset occurred,1: BOR/exit from Shutdown mode reset occurred" rbitfld.long 0x4 26. "PINRSTF,NRST pin reset flag" "0: No reset from NRST pin occurred,1: Reset from NRST pin occurred" newline rbitfld.long 0x4 25. "OBLRSTF,Option-byte loader reset flag" "0: No reset from option-byte loading occurred,1: Reset from option-byte loading occurred" bitfld.long 0x4 23. "RMVF,Remove reset flag" "0: No effect,1: Clear the reset flags." newline hexmask.long.byte 0x4 12.--15. 1. "MSISSRANGE,MSIS range after Standby mode" hexmask.long.byte 0x4 8.--11. 1. "MSIKSRANGE,MSIK range after Standby mode" group.long 0x110++0x7 line.long 0x0 "RCC_SECCFGR,RCC secure configuration register" bitfld.long 0x0 12. "RMVFSEC,Remove reset flag security" "0: non secure,1: secure" bitfld.long 0x0 11. "HSI48SEC,HSI48 clock configuration and status bit security" "0: non secure,1: secure" newline bitfld.long 0x0 10. "ICLKSEC,Intermediate clock source selection security" "0: non secure,1: secure" bitfld.long 0x0 9. "PLL3SEC,PLL3 clock configuration and status bit security" "0: non secure,1: secure" newline bitfld.long 0x0 8. "PLL2SEC,PLL2 clock configuration and status bit security" "0: non secure,1: secure" bitfld.long 0x0 7. "PLL1SEC,PLL1 clock configuration and status bit security" "0: non secure,1: secure" newline bitfld.long 0x0 6. "PRESCSEC,AHBx/APBx prescaler configuration bits security" "0: non secure,1: secure" bitfld.long 0x0 5. "SYSCLKSEC,SYSCLK clock selection STOPWUCK bit clock output on MCO configuration security" "0: non secure,1: secure" newline bitfld.long 0x0 4. "LSESEC,LSE clock configuration and status bit security" "0: non secure,1: secure" bitfld.long 0x0 3. "LSISEC,LSI clock configuration and status bit security" "0: non secure,1: secure" newline bitfld.long 0x0 2. "MSISEC,MSI clock configuration and status bit security" "0: non secure,1: secure" bitfld.long 0x0 1. "HSESEC,HSE clock configuration bits status bit and HSE_CSS security" "0: non secure,1: secure" newline bitfld.long 0x0 0. "HSISEC,HSI clock configuration and status bit security" "0: non secure,1: secure" line.long 0x4 "RCC_PRIVCFGR,RCC privilege configuration register" bitfld.long 0x4 1. "NSPRIV,RCC non-secure function privilege configuration" "0: Read and write to RCC non-secure functions can..,1: Read and write to RCC non-secure functions can.." bitfld.long 0x4 0. "SPRIV,RCC secure function privilege configuration" "0: Read and write to RCC secure functions can be..,1: Read and write to RCC secure functions can be.." tree.end tree.end tree "RNG (Random Number Generator)" base ad:0x0 tree "RNG" base ad:0x420C0800 group.long 0x0++0x7 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "CONFIGLOCK,RNG Config Lock" "0,1" bitfld.long 0x0 30. "CONDRST,Conditioning soft reset" "0,1" hexmask.long.byte 0x0 20.--25. 1. "RNG_CONFIG1,RNG configuration 1" hexmask.long.byte 0x0 16.--19. 1. "CLKDIV,Clock divider factor" bitfld.long 0x0 13.--15. "RNG_CONFIG2,RNG configuration 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "NISTC,Non NIST compliant" "0,1" hexmask.long.byte 0x0 8.--11. 1. "RNG_CONFIG3,RNG configuration 3" bitfld.long 0x0 7. "ARDIS,Auto reset disable" "0,1" newline bitfld.long 0x0 5. "CED,Clock error detection" "0,1" bitfld.long 0x0 3. "IE,Interrupt Enable" "0,1" bitfld.long 0x0 2. "RNGEN,True random number generator enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0,1" rbitfld.long 0x4 2. "SECS,Seed error current status" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status" "0,1" rbitfld.long 0x4 0. "DRDY,Data ready" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data" group.long 0x10++0x3 line.long 0x0 "HTCR,health test control register" hexmask.long 0x0 0.--31. 1. "HTCFG,health test configuration" tree.end tree "SEC_RNG" base ad:0x520C0800 group.long 0x0++0x7 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "CONFIGLOCK,RNG Config Lock" "0,1" bitfld.long 0x0 30. "CONDRST,Conditioning soft reset" "0,1" hexmask.long.byte 0x0 20.--25. 1. "RNG_CONFIG1,RNG configuration 1" hexmask.long.byte 0x0 16.--19. 1. "CLKDIV,Clock divider factor" bitfld.long 0x0 13.--15. "RNG_CONFIG2,RNG configuration 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "NISTC,Non NIST compliant" "0,1" hexmask.long.byte 0x0 8.--11. 1. "RNG_CONFIG3,RNG configuration 3" bitfld.long 0x0 7. "ARDIS,Auto reset disable" "0,1" newline bitfld.long 0x0 5. "CED,Clock error detection" "0,1" bitfld.long 0x0 3. "IE,Interrupt Enable" "0,1" bitfld.long 0x0 2. "RNGEN,True random number generator enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0,1" rbitfld.long 0x4 2. "SECS,Seed error current status" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status" "0,1" rbitfld.long 0x4 0. "DRDY,Data ready" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data" group.long 0x10++0x3 line.long 0x0 "HTCR,health test control register" hexmask.long 0x0 0.--31. 1. "HTCFG,health test configuration" tree.end tree.end tree "RTC (Real-Time Clock)" base ad:0x0 tree "RTC" base ad:0x46007800 group.long 0x0++0x7 line.long 0x0 "TR,time register" bitfld.long 0x0 22. "PM,AM/PM notation" "0,1" bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "DR,date register" hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format" hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format" bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" rgroup.long 0x8++0x3 line.long 0x0 "SSR,RTC sub second register" hexmask.long 0x0 0.--31. 1. "SS,SS" group.long 0xC++0x17 line.long 0x0 "ICSR,RTC initialization control and status" rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1" bitfld.long 0x0 10.--12. "BCDU,BCDU" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. "BIN,BIN" "0,1,2,3" bitfld.long 0x0 7. "INIT,Initialization mode" "0,1" rbitfld.long 0x0 6. "INITF,Initialization flag" "0,1" bitfld.long 0x0 5. "RSF,Registers synchronization" "0,1" newline rbitfld.long 0x0 4. "INITS,Initialization status flag" "0,1" rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0,1" rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0,1" line.long 0x4 "PRER,prescaler register" hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler" hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler" line.long 0x8 "WUTR,wakeup timer register" hexmask.long.word 0x8 16.--31. 1. "WUTOCLR,WUTOCLR" hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value" line.long 0xC "CR,RTC control register" bitfld.long 0xC 31. "OUT2EN,OUT2EN" "0,1" bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1" bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1" bitfld.long 0xC 28. "ALRBFCLR,ALRBFCLR" "0,1" bitfld.long 0xC 27. "ALRAFCLR,ALRAFCLR" "0,1" bitfld.long 0xC 26. "TAMPOE,TAMPOE" "0,1" newline bitfld.long 0xC 25. "TAMPTS,TAMPTS" "0,1" bitfld.long 0xC 24. "ITSE,ITSE" "0,1" bitfld.long 0xC 23. "COE,COE" "0,1" bitfld.long 0xC 21.--22. "OSEL,OSEL" "0,1,2,3" bitfld.long 0xC 20. "POL,POL" "0,1" bitfld.long 0xC 19. "COSEL,COSEL" "0,1" newline bitfld.long 0xC 18. "BKP,BKP" "0,1" bitfld.long 0xC 17. "SUB1H,SUB1H" "0,1" bitfld.long 0xC 16. "ADD1H,ADD1H" "0,1" bitfld.long 0xC 15. "TSIE,TSIE" "0,1" bitfld.long 0xC 14. "WUTIE,WUTIE" "0,1" bitfld.long 0xC 13. "ALRBIE,ALRBIE" "0,1" newline bitfld.long 0xC 12. "ALRAIE,ALRAIE" "0,1" bitfld.long 0xC 11. "TSE,TSE" "0,1" bitfld.long 0xC 10. "WUTE,WUTE" "0,1" bitfld.long 0xC 9. "ALRBE,ALRBE" "0,1" bitfld.long 0xC 8. "ALRAE,ALRAE" "0,1" bitfld.long 0xC 7. "SSRUIE,SSRUIE" "0,1" newline bitfld.long 0xC 6. "FMT,FMT" "0,1" bitfld.long 0xC 5. "BYPSHAD,BYPSHAD" "0,1" bitfld.long 0xC 4. "REFCKON,REFCKON" "0,1" bitfld.long 0xC 3. "TSEDGE,TSEDGE" "0,1" bitfld.long 0xC 0.--2. "WUCKSEL,WUCKSEL" "0,1,2,3,4,5,6,7" line.long 0x10 "PRIVCR,RTC privilege mode control" bitfld.long 0x10 15. "PRIV,PRIV" "0,1" bitfld.long 0x10 14. "INITPRIV,INITPRIV" "0,1" bitfld.long 0x10 13. "CALPRIV,CALPRIV" "0,1" bitfld.long 0x10 3. "TSPRIV,TSPRIV" "0,1" bitfld.long 0x10 2. "WUTPRIV,WUTPRIV" "0,1" bitfld.long 0x10 1. "ALRBPRIV,ALRBPRIV" "0,1" newline bitfld.long 0x10 0. "ALRAPRIV,ALRAPRIV" "0,1" line.long 0x14 "SECCFGR,RTC secure mode control" bitfld.long 0x14 15. "SEC,SEC" "0,1" bitfld.long 0x14 14. "INITSEC,INITSEC" "0,1" bitfld.long 0x14 13. "CALSEC,CALSEC" "0,1" bitfld.long 0x14 3. "TSSEC,TSSEC" "0,1" bitfld.long 0x14 2. "WUTSEC,WUTSEC" "0,1" bitfld.long 0x14 1. "ALRBSEC,ALRBSEC" "0,1" newline bitfld.long 0x14 0. "ALRASEC,ALRASEC" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "WPR,write protection register" hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key" group.long 0x28++0x3 line.long 0x0 "CALR,calibration register" bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5" "0,1" bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle" "0,1" bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle" "0,1" bitfld.long 0x0 12. "LPCAL,LPCAL" "0,1" hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus" wgroup.long 0x2C++0x3 line.long 0x0 "SHIFTR,shift control register" bitfld.long 0x0 31. "ADD1S,Add one second" "0,1" hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a" rgroup.long 0x30++0xB line.long 0x0 "TSTR,time stamp time register" bitfld.long 0x0 22. "PM,AM/PM notation" "0,1" bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "TSDR,time stamp date register" bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" line.long 0x8 "TSSSR,timestamp sub second register" hexmask.long 0x8 0.--31. 1. "SS,Sub second value" group.long 0x40++0xF line.long 0x0 "ALRMAR,alarm A register" bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0,1" bitfld.long 0x0 30. "WDSEL,Week day selection" "0,1" bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD" bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0,1" bitfld.long 0x0 22. "PM,AM/PM notation" "0,1" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0,1" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0,1" newline bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "ALRMASSR,alarm A sub second register" bitfld.long 0x4 31. "SSCLR,SSCLR" "0,1" hexmask.long.byte 0x4 24.--29. 1. "MASKSS,Mask the most-significant bits starting" hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value" line.long 0x8 "ALRMBR,alarm B register" bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0,1" bitfld.long 0x8 30. "WDSEL,Week day selection" "0,1" bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD" bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0,1" bitfld.long 0x8 22. "PM,AM/PM notation" "0,1" newline bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0,1" bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0,1" newline bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format" line.long 0xC "ALRMBSSR,alarm B sub second register" bitfld.long 0xC 31. "SSCLR,SSCLR" "0,1" hexmask.long.byte 0xC 24.--29. 1. "MASKSS,Mask the most-significant bits starting" hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value" rgroup.long 0x50++0xB line.long 0x0 "SR,RTC status register" bitfld.long 0x0 6. "SSRUF,SSRUF" "0,1" bitfld.long 0x0 5. "ITSF,ITSF" "0,1" bitfld.long 0x0 4. "TSOVF,TSOVF" "0,1" bitfld.long 0x0 3. "TSF,TSF" "0,1" bitfld.long 0x0 2. "WUTF,WUTF" "0,1" bitfld.long 0x0 1. "ALRBF,ALRBF" "0,1" newline bitfld.long 0x0 0. "ALRAF,ALRAF" "0,1" line.long 0x4 "MISR,RTC non-secure masked interrupt status" bitfld.long 0x4 6. "SSRUMF,SSRUMF" "0,1" bitfld.long 0x4 5. "ITSMF,ITSMF" "0,1" bitfld.long 0x4 4. "TSOVMF,TSOVMF" "0,1" bitfld.long 0x4 3. "TSMF,TSMF" "0,1" bitfld.long 0x4 2. "WUTMF,WUTMF" "0,1" bitfld.long 0x4 1. "ALRBMF,ALRBMF" "0,1" newline bitfld.long 0x4 0. "ALRAMF,ALRAMF" "0,1" line.long 0x8 "SMISR,RTC secure masked interrupt status" bitfld.long 0x8 6. "SSRUMF,SSRUMF" "0,1" bitfld.long 0x8 5. "ITSMF,ITSMF" "0,1" bitfld.long 0x8 4. "TSOVMF,TSOVMF" "0,1" bitfld.long 0x8 3. "TSMF,TSMF" "0,1" bitfld.long 0x8 2. "WUTMF,WUTMF" "0,1" bitfld.long 0x8 1. "ALRBMF,ALRBMF" "0,1" newline bitfld.long 0x8 0. "ALRAMF,ALRAMF" "0,1" wgroup.long 0x5C++0x3 line.long 0x0 "SCR,RTC status clear register" bitfld.long 0x0 6. "CSSRUF,CSSRUF" "0,1" bitfld.long 0x0 5. "CITSF,CITSF" "0,1" bitfld.long 0x0 4. "CTSOVF,CTSOVF" "0,1" bitfld.long 0x0 3. "CTSF,CTSF" "0,1" bitfld.long 0x0 2. "CWUTF,CWUTF" "0,1" bitfld.long 0x0 1. "CALRBF,CALRBF" "0,1" newline bitfld.long 0x0 0. "CALRAF,CALRAF" "0,1" group.long 0x70++0x7 line.long 0x0 "ALRABINR,RTC alarm A binary mode register" hexmask.long 0x0 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode" line.long 0x4 "ALRBBINR,RTC alarm B binary mode register" hexmask.long 0x4 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode" tree.end tree "SEC_RTC" base ad:0x56007800 group.long 0x0++0x7 line.long 0x0 "TR,time register" bitfld.long 0x0 22. "PM,AM/PM notation" "0,1" bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "DR,date register" hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format" hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format" bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" rgroup.long 0x8++0x3 line.long 0x0 "SSR,RTC sub second register" hexmask.long 0x0 0.--31. 1. "SS,SS" group.long 0xC++0x17 line.long 0x0 "ICSR,RTC initialization control and status" rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1" bitfld.long 0x0 10.--12. "BCDU,BCDU" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. "BIN,BIN" "0,1,2,3" bitfld.long 0x0 7. "INIT,Initialization mode" "0,1" rbitfld.long 0x0 6. "INITF,Initialization flag" "0,1" bitfld.long 0x0 5. "RSF,Registers synchronization" "0,1" newline rbitfld.long 0x0 4. "INITS,Initialization status flag" "0,1" rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0,1" rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0,1" line.long 0x4 "PRER,prescaler register" hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler" hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler" line.long 0x8 "WUTR,wakeup timer register" hexmask.long.word 0x8 16.--31. 1. "WUTOCLR,WUTOCLR" hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value" line.long 0xC "CR,RTC control register" bitfld.long 0xC 31. "OUT2EN,OUT2EN" "0,1" bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1" bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1" bitfld.long 0xC 28. "ALRBFCLR,ALRBFCLR" "0,1" bitfld.long 0xC 27. "ALRAFCLR,ALRAFCLR" "0,1" bitfld.long 0xC 26. "TAMPOE,TAMPOE" "0,1" newline bitfld.long 0xC 25. "TAMPTS,TAMPTS" "0,1" bitfld.long 0xC 24. "ITSE,ITSE" "0,1" bitfld.long 0xC 23. "COE,COE" "0,1" bitfld.long 0xC 21.--22. "OSEL,OSEL" "0,1,2,3" bitfld.long 0xC 20. "POL,POL" "0,1" bitfld.long 0xC 19. "COSEL,COSEL" "0,1" newline bitfld.long 0xC 18. "BKP,BKP" "0,1" bitfld.long 0xC 17. "SUB1H,SUB1H" "0,1" bitfld.long 0xC 16. "ADD1H,ADD1H" "0,1" bitfld.long 0xC 15. "TSIE,TSIE" "0,1" bitfld.long 0xC 14. "WUTIE,WUTIE" "0,1" bitfld.long 0xC 13. "ALRBIE,ALRBIE" "0,1" newline bitfld.long 0xC 12. "ALRAIE,ALRAIE" "0,1" bitfld.long 0xC 11. "TSE,TSE" "0,1" bitfld.long 0xC 10. "WUTE,WUTE" "0,1" bitfld.long 0xC 9. "ALRBE,ALRBE" "0,1" bitfld.long 0xC 8. "ALRAE,ALRAE" "0,1" bitfld.long 0xC 7. "SSRUIE,SSRUIE" "0,1" newline bitfld.long 0xC 6. "FMT,FMT" "0,1" bitfld.long 0xC 5. "BYPSHAD,BYPSHAD" "0,1" bitfld.long 0xC 4. "REFCKON,REFCKON" "0,1" bitfld.long 0xC 3. "TSEDGE,TSEDGE" "0,1" bitfld.long 0xC 0.--2. "WUCKSEL,WUCKSEL" "0,1,2,3,4,5,6,7" line.long 0x10 "PRIVCR,RTC privilege mode control" bitfld.long 0x10 15. "PRIV,PRIV" "0,1" bitfld.long 0x10 14. "INITPRIV,INITPRIV" "0,1" bitfld.long 0x10 13. "CALPRIV,CALPRIV" "0,1" bitfld.long 0x10 3. "TSPRIV,TSPRIV" "0,1" bitfld.long 0x10 2. "WUTPRIV,WUTPRIV" "0,1" bitfld.long 0x10 1. "ALRBPRIV,ALRBPRIV" "0,1" newline bitfld.long 0x10 0. "ALRAPRIV,ALRAPRIV" "0,1" line.long 0x14 "SECCFGR,RTC secure mode control" bitfld.long 0x14 15. "SEC,SEC" "0,1" bitfld.long 0x14 14. "INITSEC,INITSEC" "0,1" bitfld.long 0x14 13. "CALSEC,CALSEC" "0,1" bitfld.long 0x14 3. "TSSEC,TSSEC" "0,1" bitfld.long 0x14 2. "WUTSEC,WUTSEC" "0,1" bitfld.long 0x14 1. "ALRBSEC,ALRBSEC" "0,1" newline bitfld.long 0x14 0. "ALRASEC,ALRASEC" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "WPR,write protection register" hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key" group.long 0x28++0x3 line.long 0x0 "CALR,calibration register" bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5" "0,1" bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle" "0,1" bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle" "0,1" bitfld.long 0x0 12. "LPCAL,LPCAL" "0,1" hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus" wgroup.long 0x2C++0x3 line.long 0x0 "SHIFTR,shift control register" bitfld.long 0x0 31. "ADD1S,Add one second" "0,1" hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a" rgroup.long 0x30++0xB line.long 0x0 "TSTR,time stamp time register" bitfld.long 0x0 22. "PM,AM/PM notation" "0,1" bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "TSDR,time stamp date register" bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" line.long 0x8 "TSSSR,timestamp sub second register" hexmask.long 0x8 0.--31. 1. "SS,Sub second value" group.long 0x40++0xF line.long 0x0 "ALRMAR,alarm A register" bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0,1" bitfld.long 0x0 30. "WDSEL,Week day selection" "0,1" bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD" bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0,1" bitfld.long 0x0 22. "PM,AM/PM notation" "0,1" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0,1" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0,1" newline bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "ALRMASSR,alarm A sub second register" bitfld.long 0x4 31. "SSCLR,SSCLR" "0,1" hexmask.long.byte 0x4 24.--29. 1. "MASKSS,Mask the most-significant bits starting" hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value" line.long 0x8 "ALRMBR,alarm B register" bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0,1" bitfld.long 0x8 30. "WDSEL,Week day selection" "0,1" bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD" bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0,1" bitfld.long 0x8 22. "PM,AM/PM notation" "0,1" newline bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0,1" bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0,1" newline bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format" line.long 0xC "ALRMBSSR,alarm B sub second register" bitfld.long 0xC 31. "SSCLR,SSCLR" "0,1" hexmask.long.byte 0xC 24.--29. 1. "MASKSS,Mask the most-significant bits starting" hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value" rgroup.long 0x50++0xB line.long 0x0 "SR,RTC status register" bitfld.long 0x0 6. "SSRUF,SSRUF" "0,1" bitfld.long 0x0 5. "ITSF,ITSF" "0,1" bitfld.long 0x0 4. "TSOVF,TSOVF" "0,1" bitfld.long 0x0 3. "TSF,TSF" "0,1" bitfld.long 0x0 2. "WUTF,WUTF" "0,1" bitfld.long 0x0 1. "ALRBF,ALRBF" "0,1" newline bitfld.long 0x0 0. "ALRAF,ALRAF" "0,1" line.long 0x4 "MISR,RTC non-secure masked interrupt status" bitfld.long 0x4 6. "SSRUMF,SSRUMF" "0,1" bitfld.long 0x4 5. "ITSMF,ITSMF" "0,1" bitfld.long 0x4 4. "TSOVMF,TSOVMF" "0,1" bitfld.long 0x4 3. "TSMF,TSMF" "0,1" bitfld.long 0x4 2. "WUTMF,WUTMF" "0,1" bitfld.long 0x4 1. "ALRBMF,ALRBMF" "0,1" newline bitfld.long 0x4 0. "ALRAMF,ALRAMF" "0,1" line.long 0x8 "SMISR,RTC secure masked interrupt status" bitfld.long 0x8 6. "SSRUMF,SSRUMF" "0,1" bitfld.long 0x8 5. "ITSMF,ITSMF" "0,1" bitfld.long 0x8 4. "TSOVMF,TSOVMF" "0,1" bitfld.long 0x8 3. "TSMF,TSMF" "0,1" bitfld.long 0x8 2. "WUTMF,WUTMF" "0,1" bitfld.long 0x8 1. "ALRBMF,ALRBMF" "0,1" newline bitfld.long 0x8 0. "ALRAMF,ALRAMF" "0,1" wgroup.long 0x5C++0x3 line.long 0x0 "SCR,RTC status clear register" bitfld.long 0x0 6. "CSSRUF,CSSRUF" "0,1" bitfld.long 0x0 5. "CITSF,CITSF" "0,1" bitfld.long 0x0 4. "CTSOVF,CTSOVF" "0,1" bitfld.long 0x0 3. "CTSF,CTSF" "0,1" bitfld.long 0x0 2. "CWUTF,CWUTF" "0,1" bitfld.long 0x0 1. "CALRBF,CALRBF" "0,1" newline bitfld.long 0x0 0. "CALRAF,CALRAF" "0,1" group.long 0x70++0x7 line.long 0x0 "ALRABINR,RTC alarm A binary mode register" hexmask.long 0x0 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode" line.long 0x4 "ALRBBINR,RTC alarm B binary mode register" hexmask.long 0x4 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode" tree.end tree.end sif (cpuis("STM32U545*")||cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U5A5*")||cpuis("STM32U5A9*")||cpuis("STM32U5G*")) tree "SAES (Secure Advanced Encryption Standard Hardware Accelerator)" base ad:0x0 tree "SAES" base ad:0x420C0C00 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 28.--30. "KEYSEL,KEYSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--27. "KSHAREID,KSHAREID" "0,1,2,3" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" bitfld.long 0x0 19. "KEYPROT,KEYPROT" "0,1" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 12. "DMAOUTEN,DMAOUTEN" "0,1" bitfld.long 0x0 11. "DMAINEN,DMAINEN" "0,1" bitfld.long 0x0 5.--6. "CHMOD,CHMOD" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,MODE" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,DATATYPE" "0,1,2,3" bitfld.long 0x0 0. "EN,SAES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "SAES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0xF line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" group.long 0x100++0x3 line.long 0x0 "DPACFGR,configuration register" rbitfld.long 0x0 31. "CONFIGLOCK,CONFIGLOCK" "0,1" bitfld.long 0x0 3.--4. "TRIMCFG,TRIMCFG" "0,1,2,3" bitfld.long 0x0 2. "RESEED,RESEED" "0,1" bitfld.long 0x0 1. "REDCFG,REDCFG" "0,1" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 3. "RNGEIE,RNGEIE" "0,1" bitfld.long 0x0 2. "KEIE,Key error interrupt enable" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt enable" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag interrupt enable" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 3. "RNGEIF,RNGEIF" "0,1" bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 3. "RNGEIF,RNGEIF" "0,1" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end tree "SEC_SAES" base ad:0x520C0C00 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 31. "IPRST,IPRST" "0,1" bitfld.long 0x0 28.--30. "KEYSEL,KEYSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--27. "KSHAREID,KSHAREID" "0,1,2,3" bitfld.long 0x0 24.--25. "KMOD,KMOD" "0,1,2,3" bitfld.long 0x0 19. "KEYPROT,KEYPROT" "0,1" bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1" bitfld.long 0x0 12. "DMAOUTEN,DMAOUTEN" "0,1" bitfld.long 0x0 11. "DMAINEN,DMAINEN" "0,1" bitfld.long 0x0 5.--6. "CHMOD,CHMOD" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,MODE" "0,1,2,3" bitfld.long 0x0 1.--2. "DATATYPE,DATATYPE" "0,1,2,3" bitfld.long 0x0 0. "EN,SAES enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0,1" bitfld.long 0x0 3. "BUSY,BUSY" "0,1" bitfld.long 0x0 2. "WRERR,Write error flag" "0,1" bitfld.long 0x0 1. "RDERR,Read error flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "DINR,data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "DOUTR,data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "KEYR0,key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "KEYR1,key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "KEYR2,key register 2" hexmask.long 0x8 0.--31. 1. "KEYR,Cryptographic key bits [95:64]" line.long 0xC "KEYR3,key register 3" hexmask.long 0xC 0.--31. 1. "SAES_KEYR3,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "IVR0,initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "IVR1,initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "IVR2,initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "IVR3,initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0xF line.long 0x0 "KEYR4,key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "KEYR5,key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "KEYR6,key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "KEYR7,key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" group.long 0x100++0x3 line.long 0x0 "DPACFGR,configuration register" rbitfld.long 0x0 31. "CONFIGLOCK,CONFIGLOCK" "0,1" bitfld.long 0x0 3.--4. "TRIMCFG,TRIMCFG" "0,1,2,3" bitfld.long 0x0 2. "RESEED,RESEED" "0,1" bitfld.long 0x0 1. "REDCFG,REDCFG" "0,1" group.long 0x300++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 3. "RNGEIE,RNGEIE" "0,1" bitfld.long 0x0 2. "KEIE,Key error interrupt enable" "0,1" bitfld.long 0x0 1. "RWEIE,Read or write error interrupt enable" "0,1" bitfld.long 0x0 0. "CCFIE,Computation complete flag interrupt enable" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 3. "RNGEIF,RNGEIF" "0,1" bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1" wgroup.long 0x308++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 3. "RNGEIF,RNGEIF" "0,1" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end tree.end endif tree "SAI (Serial Audio Interface)" base ad:0x0 tree "SAI1" base ad:0x40015400 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end sif (cpuis("STM32U575*")) tree "SAI2" base ad:0x40015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U585*")) tree "SAI2" base ad:0x40015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U595*")) tree "SAI2" base ad:0x40015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U599*")) tree "SAI2" base ad:0x40015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U5A5*")) tree "SAI2" base ad:0x40015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U5A9*")) tree "SAI2" base ad:0x40015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U5F*")) tree "SAI2" base ad:0x40015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U5G*")) tree "SAI2" base ad:0x40015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif tree "SEC_SAI1" base ad:0x50015400 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end sif (cpuis("STM32U575*")) tree "SEC_SAI2" base ad:0x50015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U585*")) tree "SEC_SAI2" base ad:0x50015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U595*")) tree "SEC_SAI2" base ad:0x50015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U599*")) tree "SEC_SAI2" base ad:0x50015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U5A5*")) tree "SEC_SAI2" base ad:0x50015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U5A9*")) tree "SEC_SAI2" base ad:0x50015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U5F*")) tree "SEC_SAI2" base ad:0x50015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32U5G*")) tree "SEC_SAI2" base ad:0x50015800 group.long 0x0++0x7 line.long 0x0 "GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "ACR1,A Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x4 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x4 12. "MONO,Mono mode" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x4 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "BCR1,B Configuration register 1" bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x0 26. "OSR,OSR" "0,1" hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x0 19. "NODIV,No divider" "0,1" bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1" bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1" bitfld.long 0x0 12. "MONO,Mono mode" "0,1" bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3" newline bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1" bitfld.long 0x0 8. "LSBFIRST,Least significant bit" "0,1" bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3" group.long 0x8++0x3 line.long 0x0 "ACR2,A Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "BCR2,B Configuration register 2" bitfld.long 0x0 14.--15. "COMP,Companding mode" "0,1,2,3" bitfld.long 0x0 13. "CPL,Complement bit" "0,1" hexmask.long.byte 0x0 7.--12. 1. "MUTECN,Mute counter" bitfld.long 0x0 6. "MUTEVAL,Mute value" "0,1" bitfld.long 0x0 5. "MUTE,Mute" "0,1" bitfld.long 0x0 4. "TRIS,Tristate management on data" "0,1" bitfld.long 0x0 3. "FFLUSH,FIFO flush" "0,1" bitfld.long 0x0 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x0 "AFRCR,A frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x2C++0x3 line.long 0x0 "BFRCR,B frame configuration register" bitfld.long 0x0 18. "FSOFF,Frame synchronization" "0,1" bitfld.long 0x0 17. "FSPOL,Frame synchronization" "0,1" rbitfld.long 0x0 16. "FSDEF,Frame synchronization" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0x0 0.--7. 1. "FRL,Frame length" group.long 0x10++0x3 line.long 0x0 "ASLOTR,A Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x30++0x3 line.long 0x0 "BSLOTR,B Slot register" hexmask.long.word 0x0 16.--31. 1. "SLOTEN,Slot enable" hexmask.long.byte 0x0 8.--11. 1. "NBSLOT,Number of slots in an audio" bitfld.long 0x0 6.--7. "SLOTSZ,Slot size" "0,1,2,3" hexmask.long.byte 0x0 0.--4. 1. "FBOFF,First bit offset" group.long 0x14++0x3 line.long 0x0 "AIM,A Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" group.long 0x34++0x3 line.long 0x0 "BIM,B Interrupt mask register" bitfld.long 0x0 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x0 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDYIE,Codec not ready interrupt" "0,1" bitfld.long 0x0 3. "FREQIE,FIFO request interrupt" "0,1" bitfld.long 0x0 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x0 1. "MUTEDETIE,Mute detection interrupt" "0,1" bitfld.long 0x0 0. "OVRUDRIE,Overrun/underrun interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ASR,A Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BSR,B Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization" "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1" bitfld.long 0x0 3. "FREQ,FIFO request" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ACLRFR,A Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "BCLRFR,B Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration" "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1" group.long 0x20++0x3 line.long 0x0 "ADR,A Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x40++0xB line.long 0x0 "BDR,B Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif tree.end tree "SDMMC (Secure Digital Input/Output and MultiMediaCards Interface)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) tree "SDMMC" base ad:0x420C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC" base ad:0x520C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U575*")) tree "SDMMC1" base ad:0x420C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC1" base ad:0x520C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U575*")) tree "SDMMC2" base ad:0x420C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC2" base ad:0x520C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U585*")) tree "SDMMC1" base ad:0x420C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC1" base ad:0x520C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U585*")) tree "SDMMC2" base ad:0x420C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC2" base ad:0x520C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U595*")) tree "SDMMC1" base ad:0x420C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC1" base ad:0x520C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U595*")) tree "SDMMC2" base ad:0x420C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC2" base ad:0x520C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U599*")) tree "SDMMC1" base ad:0x420C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC1" base ad:0x520C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U599*")) tree "SDMMC2" base ad:0x420C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC2" base ad:0x520C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U5A5*")) tree "SDMMC1" base ad:0x420C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC1" base ad:0x520C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U5A5*")) tree "SDMMC2" base ad:0x420C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC2" base ad:0x520C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U5A9*")) tree "SDMMC1" base ad:0x420C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC1" base ad:0x520C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U5A9*")) tree "SDMMC2" base ad:0x420C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC2" base ad:0x520C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U5F*")) tree "SDMMC1" base ad:0x420C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC1" base ad:0x520C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U5F*")) tree "SDMMC2" base ad:0x420C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC2" base ad:0x520C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U5G*")) tree "SDMMC1" base ad:0x420C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC1" base ad:0x520C8000 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif sif (cpuis("STM32U5G*")) tree "SDMMC2" base ad:0x420C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end tree "SEC_SDMMC2" base ad:0x520C8C00 group.long 0x0++0xF line.long 0x0 "POWER,power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3" line.long 0x4 "CLKCR,clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0,1" bitfld.long 0x4 17. "HWFC_EN,HW Flow Control enable" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDIO_CK dephasing selection bit" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "ARGR,argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMDR,command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "RESPCMDR,command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "RESP1,response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "RESP2,response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "RESP3,response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "RESP4,response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "DTIMER,data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "DLENR,data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "DCTRL,data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining data" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "STAR,status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0,1" line.long 0x4 "MASKR,mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0,1" line.long 0x8 "ACKTIMER,acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" group.long 0x80++0x3F line.long 0x0 "FIFOR0,data FIFO register 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "FIFOR1,data FIFO register 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "FIFOR2,data FIFO register 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "FIFOR3,data FIFO register 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "FIFOR4,data FIFO register 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "FIFOR5,data FIFO register 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "FIFOR6,data FIFO register 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "FIFOR7,data FIFO register 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "FIFOR8,data FIFO register 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "FIFOR9,data FIFO register 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "FIFOR10,data FIFO register 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "FIFOR11,data FIFO register 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "FIFOR12,data FIFO register 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "FIFOR13,data FIFO register 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "FIFOR14,data FIFO register 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "FIFOR15,data FIFO register 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." "0,1" line.long 0x4 "SDMMC_IDMABSIZER,buffer size register" hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0,1" bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0,1" bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,Acknowledge linked list buffer ready" line.long 0x4 "SDMMC_IDMABAR,linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" tree.end endif tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SPI1" base ad:0x40013000 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" newline bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" newline bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" newline bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" newline bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" newline bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" newline bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" newline bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" endif sif (cpuis("STM32U575*")) group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_SPI1" base ad:0x50013000 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" newline bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" newline bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" newline bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" newline bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" newline bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" newline bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" newline bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" endif sif (cpuis("STM32U575*")) group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SPI2" base ad:0x40003800 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" newline bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" newline bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" newline bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" newline bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" newline bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" newline bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" newline bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" endif sif (cpuis("STM32U575*")) group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_SPI2" base ad:0x50003800 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" newline bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" newline bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" newline bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" newline bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" newline bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" newline bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" newline bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" endif sif (cpuis("STM32U575*")) group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SPI3" base ad:0x46002000 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" newline bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" newline bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" newline bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" newline bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" newline bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" newline bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" newline bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" endif sif (cpuis("STM32U575*")) group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_SPI3" base ad:0x56002000 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" newline bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" newline bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" newline bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" newline bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" newline bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" newline bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" newline bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" endif sif (cpuis("STM32U575*")) group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" endif tree.end endif sif (cpuis("STM32U585*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" tree.end tree "SEC_SPI1" base ad:0x50013000 group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" tree.end endif sif (cpuis("STM32U585*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" tree.end tree "SEC_SPI2" base ad:0x50003800 group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" tree.end endif sif (cpuis("STM32U585*")) tree "SPI3" base ad:0x46002000 group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" tree.end tree "SEC_SPI3" base ad:0x56002000 group.long 0x0++0x13 line.long 0x0 "SPI_CR1," bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master SUSPend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2," hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER," bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR," hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected. When MODF is set SPE and.." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." newline bitfld.long 0x0 0. "RXP,Rx-Packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR," bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "SPI_AUTOCR," bitfld.long 0x0 21. "TRIGEN,trigger of CSTART control enable" "0: trigger of CSTART control disabled,1: trigger of CSTART control enabled" bitfld.long 0x0 20. "TRIGPOL,trigger polarity" "0: trigger is active on raising edge,1: trigger is active on falling edge" newline hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,trigger selection (refer )." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR," hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR," hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC," hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC," hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" tree.end endif sif (cpuis("STM32U595*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI1" base ad:0x50013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U595*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI2" base ad:0x50003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U595*")) tree "SPI3" base ad:0x46002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI3" base ad:0x56002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U599*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI1" base ad:0x50013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U599*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI2" base ad:0x50003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U599*")) tree "SPI3" base ad:0x46002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI3" base ad:0x56002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5A5*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI1" base ad:0x50013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5A5*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI2" base ad:0x50003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5A5*")) tree "SPI3" base ad:0x46002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI3" base ad:0x56002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5A9*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI1" base ad:0x50013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5A9*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI2" base ad:0x50003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5A9*")) tree "SPI3" base ad:0x46002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI3" base ad:0x56002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5F*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI1" base ad:0x50013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5F*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI2" base ad:0x50003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5F*")) tree "SPI3" base ad:0x46002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI3" base ad:0x56002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5G*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI1" base ad:0x50013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5G*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI2" base ad:0x50003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif sif (cpuis("STM32U5G*")) tree "SPI3" base ad:0x46002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end tree "SEC_SPI3" base ad:0x56002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,TSIZE" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 31. "BPASS,BPASS" "0,1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 9. "UDRCFG,Behavior of slave transmitter at" "0,1" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" bitfld.long 0xC 14. "RDIOP,RDIOP" "0,1" bitfld.long 0xC 13. "RDIMM,RDIMM" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" bitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" newline bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" group.long 0x1C++0x3 line.long 0x0 "AUTOCR,SPI autonomous mode control register" bitfld.long 0x0 21. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x0 20. "TRIGPOL,TRIGPOL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRIGSEL,TRIGSEL" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x3 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "TXCRC,Transmitter CRC Register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for" line.long 0x4 "RXCRC,Receiver CRC Register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x3 line.long 0x0 "UDRDR,Underrun Data Register" hexmask.long 0x0 0.--31. 1. "UDRDR,Data at slave underrun" tree.end endif tree.end tree "SYSCFG (System Configuration Controller)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SYSCFG" base ad:0x46000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" endif bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" endif rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" endif hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" endif hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" sif (cpuis("STM32U575*")) group.long 0x70++0x3 line.long 0x0 "UCPDR,USB Type C and Power Delivery register" bitfld.long 0x0 1. "CC2ENRXFILTER,CC2ENRXFILTER" "0,1" bitfld.long 0x0 0. "CC1ENRXFILTER,CC1ENRXFILTER" "0,1" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_SYSCFG" base ad:0x56000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" endif bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" endif rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" endif hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" endif hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" sif (cpuis("STM32U575*")) group.long 0x70++0x3 line.long 0x0 "UCPDR,USB Type C and Power Delivery register" bitfld.long 0x0 1. "CC2ENRXFILTER,CC2ENRXFILTER" "0,1" bitfld.long 0x0 0. "CC1ENRXFILTER,CC1ENRXFILTER" "0,1" endif tree.end endif sif (cpuis("STM32U585*")) tree "SYSCFG" base ad:0x46000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x70++0x3 line.long 0x0 "UCPDR,USB Type C and Power Delivery register" bitfld.long 0x0 1. "CC2ENRXFILTER,CC2ENRXFILTER" "0,1" bitfld.long 0x0 0. "CC1ENRXFILTER,CC1ENRXFILTER" "0,1" tree.end tree "SEC_SYSCFG" base ad:0x56000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x70++0x3 line.long 0x0 "UCPDR,USB Type C and Power Delivery register" bitfld.long 0x0 1. "CC2ENRXFILTER,CC2ENRXFILTER" "0,1" bitfld.long 0x0 0. "CC1ENRXFILTER,CC1ENRXFILTER" "0,1" tree.end endif sif (cpuis("STM32U595*")) tree "SYSCFG" base ad:0x46000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end tree "SEC_SYSCFG" base ad:0x56000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end endif sif (cpuis("STM32U599*")) tree "SYSCFG" base ad:0x46000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end tree "SEC_SYSCFG" base ad:0x56000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end endif sif (cpuis("STM32U5A5*")) tree "SYSCFG" base ad:0x46000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end tree "SEC_SYSCFG" base ad:0x56000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end endif sif (cpuis("STM32U5A9*")) tree "SYSCFG" base ad:0x46000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end tree "SEC_SYSCFG" base ad:0x56000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end endif sif (cpuis("STM32U5F*")) tree "SYSCFG" base ad:0x46000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end tree "SEC_SYSCFG" base ad:0x56000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end endif sif (cpuis("STM32U5G*")) tree "SYSCFG" base ad:0x46000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end tree "SEC_SYSCFG" base ad:0x56000400 group.long 0x0++0x1F line.long 0x0 "SECCFGR,SYSCFG secure configuration" bitfld.long 0x0 3. "FPUSEC,FPUSEC" "0,1" bitfld.long 0x0 1. "CLASSBSEC,CLASSBSEC" "0,1" bitfld.long 0x0 0. "SYSCFGSEC,SYSCFG clock control" "0,1" line.long 0x4 "CFGR1,configuration register 1" bitfld.long 0x4 24.--25. "ENDCAP,ENDCAP" "0,1,2,3" bitfld.long 0x4 19. "PB9_FMP,PB9_FMP" "0,1" bitfld.long 0x4 18. "PB8_FMP,PB8_FMP" "0,1" bitfld.long 0x4 17. "PB7_FMP,PB7_FMP" "0,1" bitfld.long 0x4 16. "PB6_FMP,PB6_FMP" "0,1" bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage" "0,1" bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster" "0,1" line.long 0x8 "FPUIMR,FPU interrupt mask register" hexmask.long.byte 0x8 0.--5. 1. "FPU_IE,Floating point unit interrupts enable" line.long 0xC "CNSLCKR,SYSCFG CPU non-secure lock" bitfld.long 0xC 1. "LOCKNSMPU,Non-secure MPU registers" "0,1" bitfld.long 0xC 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1" line.long 0x10 "CSLOCKR,SYSCFG CPU secure lock" bitfld.long 0x10 2. "LOCKSAU,LOCKSAU" "0,1" bitfld.long 0x10 1. "LOCKSMPU,LOCKSMPU" "0,1" bitfld.long 0x10 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1" line.long 0x14 "CFGR2,configuration register 2" bitfld.long 0x14 3. "ECCL,ECC Lock" "0,1" bitfld.long 0x14 2. "PVDL,PVD lock enable bit" "0,1" bitfld.long 0x14 1. "SPL,SRAM ECC lock bit" "0,1" bitfld.long 0x14 0. "CLL,LOCKUP (hardfault) output enable" "0,1" line.long 0x18 "MESR,memory erase status register" bitfld.long 0x18 16. "IPMEE,IPMEE" "0,1" bitfld.long 0x18 0. "MCLR,MCLR" "0,1" line.long 0x1C "CCCSR,compensation cell control/status register" rbitfld.long 0x1C 10. "RDY3,RDY3" "0,1" rbitfld.long 0x1C 9. "RDY2,RDY2" "0,1" rbitfld.long 0x1C 8. "RDY1,RDY1" "0,1" bitfld.long 0x1C 5. "CS3,CS3" "0,1" bitfld.long 0x1C 4. "EN3,EN3" "0,1" bitfld.long 0x1C 3. "CS2,CS2" "0,1" bitfld.long 0x1C 2. "EN2,EN2" "0,1" bitfld.long 0x1C 1. "CS1,CS1" "0,1" newline bitfld.long 0x1C 0. "EN1,EN1" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CCVR,compensation cell value register" hexmask.long.byte 0x0 20.--23. 1. "PCV3,PCV3" hexmask.long.byte 0x0 16.--19. 1. "NCV3,NCV3" hexmask.long.byte 0x0 12.--15. 1. "PCV2,PCV2" hexmask.long.byte 0x0 8.--11. 1. "NCV2,NCV2" hexmask.long.byte 0x0 4.--7. 1. "PCV1,PCV1" hexmask.long.byte 0x0 0.--3. 1. "NCV1,NCV1" group.long 0x24++0x3 line.long 0x0 "CCCR,compensation cell code register" hexmask.long.byte 0x0 20.--23. 1. "PCC3,PCC3" hexmask.long.byte 0x0 16.--19. 1. "NCC3,NCC3" hexmask.long.byte 0x0 12.--15. 1. "PCC2,PCC2" hexmask.long.byte 0x0 8.--11. 1. "NCC2,NCC2" hexmask.long.byte 0x0 4.--7. 1. "PCC1,PCC1" hexmask.long.byte 0x0 0.--3. 1. "NCC1,NCC1" group.long 0x2C++0x3 line.long 0x0 "RSSCMDR,RSS command register" hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS commands" group.long 0x74++0x3 line.long 0x0 "OTGHSPHYCR,SYSCFG USB OTG_HS PHY register" hexmask.long.byte 0x0 2.--5. 1. "CLKSEL,CLKSEL" bitfld.long 0x0 1. "PDCTRL,PDCTRL" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" tree.end endif tree.end tree "TAMP (Tamper and Backup Registers)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TAMP" base ad:0x46007C00 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" newline bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" newline bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" newline bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" newline bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" newline bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" newline bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" newline bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" newline bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" newline bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" newline bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" newline bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" newline bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" newline bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" newline bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" newline bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" newline bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" newline bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" newline bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" newline bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" newline bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" newline bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" newline bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" newline bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" newline bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" newline bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" newline bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" newline bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" newline bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" newline bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" newline bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" newline bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" newline bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" newline bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" newline bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" newline bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" newline bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" newline bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" newline bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" newline bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" newline bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" newline bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" newline bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" newline bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" newline bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" newline bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" newline bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" newline bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" newline bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" newline bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" newline bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" newline bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" newline bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" newline bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" newline bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" newline bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" newline bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" newline bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" newline bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" newline bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" newline bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" newline bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" newline bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" newline bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" newline bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" newline bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" newline bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" newline bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" newline bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" endif sif (cpuis("STM32U575*")) group.long 0x0++0x13 line.long 0x0 "TAMP_CR1,TAMP control register 1" bitfld.long 0x0 28. "ITAMP13E,Internal tamper 13 enable" "0: Internal tamper 13 disabled.,1: Internal tamper 13 enabled." bitfld.long 0x0 27. "ITAMP12E,Internal tamper 12 enable" "0: Internal tamper 12 disabled.,1: Internal tamper 12 enabled." newline bitfld.long 0x0 26. "ITAMP11E,Internal tamper 11 enable" "0: Internal tamper 11 disabled.,1: Internal tamper 11 enabled." bitfld.long 0x0 24. "ITAMP9E,Internal tamper 9 enable" "0: Internal tamper 9 disabled.,1: Internal tamper 9 enabled." newline bitfld.long 0x0 23. "ITAMP8E,Internal tamper 8 enable" "0: Internal tamper 8 disabled.,1: Internal tamper 8 enabled." bitfld.long 0x0 22. "ITAMP7E,Internal tamper 7 enable" "0: Internal tamper 7 disabled.,1: Internal tamper 7 enabled" newline bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled." bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled." newline bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled." bitfld.long 0x0 17. "ITAMP2E,Internal tamper 2 enable" "0: Internal tamper 2 disabled.,1: Internal tamper 2 enabled." newline bitfld.long 0x0 16. "ITAMP1E,Internal tamper 1 enable" "0: Internal tamper 1 disabled.,1: Internal tamper 1 enabled." bitfld.long 0x0 7. "TAMP8E,Tamper detection on TAMP_IN8 enable" "0: Tamper detection on TAMP_IN8 is disabled.,1: Tamper detection on TAMP_IN8 is enabled." newline bitfld.long 0x0 6. "TAMP7E,Tamper detection on TAMP_IN7 enable" "0: Tamper detection on TAMP_IN7 is disabled.,1: Tamper detection on TAMP_IN7 is enabled." bitfld.long 0x0 5. "TAMP6E,Tamper detection on TAMP_IN6 enable" "0: Tamper detection on TAMP_IN6 is disabled.,1: Tamper detection on TAMP_IN6 is enabled." newline bitfld.long 0x0 4. "TAMP5E,Tamper detection on TAMP_IN5 enable" "0: Tamper detection on TAMP_IN5 is disabled.,1: Tamper detection on TAMP_IN5 is enabled." bitfld.long 0x0 3. "TAMP4E,Tamper detection on TAMP_IN4 enable" "0: Tamper detection on TAMP_IN4 is disabled.,1: Tamper detection on TAMP_IN4 is enabled." newline bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled." bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled." newline bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled." line.long 0x4 "TAMP_CR2,TAMP control register 2" bitfld.long 0x4 31. "TAMP8TRG,Active level for tamper 8 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 8 input staying low..,1: If TAMPFLT =/= 00 Tamper 8 input staying high.." bitfld.long 0x4 30. "TAMP7TRG,Active level for tamper 7 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 7 input staying low..,1: If TAMPFLT =/= 00 Tamper 7 input staying high.." newline bitfld.long 0x4 29. "TAMP6TRG,Active level for tamper 6 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 6 input staying low..,1: If TAMPFLT =/= 00 Tamper 6 input staying high.." bitfld.long 0x4 28. "TAMP5TRG,Active level for tamper 5 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 5 input staying low..,1: If TAMPFLT =/= 00 Tamper 5 input staying high.." newline bitfld.long 0x4 27. "TAMP4TRG,Active level for tamper 4 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 4 input staying low..,1: If TAMPFLT =/= 00 Tamper 4 input staying high.." bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input" "0: If TAMPFLT =/= 00 Tamper 3 input staying low..,1: If TAMPFLT =/= 00 Tamper 3 input staying high.." newline bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input" "0: If TAMPFLT =/= 00 Tamper 2 input staying low..,1: If TAMPFLT =/= 00 Tamper 2 input staying high.." bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input" "0: If TAMPFLT =/= 00 Tamper 1 input staying low..,1: If TAMPFLT =/= 00 Tamper 1 input staying high.." newline bitfld.long 0x4 23. "BKERASE,Backup registers and device secrets erase" "0,1" bitfld.long 0x4 22. "BKBLOCK,Backup registers and device secrets access blocked" "0: backup registers and device secrets(1) can be..,1: backup registers and device secrets(1) cannot be.." newline bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.." bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.." newline bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.." bitfld.long 0x4 7. "TAMP8NOER,Tamper 8 no erase" "0: Tamper 8 event erases the backup registers and..,1: Tamper 8 event does not erase the backup.." newline bitfld.long 0x4 6. "TAMP7NOER,Tamper 7 no erase" "0: Tamper 7 event erases the backup registers and..,1: Tamper 7 event does not erase the backup.." bitfld.long 0x4 5. "TAMP6NOER,Tamper 6 no erase" "0: Tamper 6 event erases the backup registers and..,1: Tamper 6 event does not erase the backup.." newline bitfld.long 0x4 4. "TAMP5NOER,Tamper 5 no erase" "0: Tamper 5 event erases the backup registers and..,1: Tamper 5 event does not erase the backup.." bitfld.long 0x4 3. "TAMP4NOER,Tamper 4 no erase" "0: Tamper 4 event erases the backup registers and..,1: Tamper 4 event does not erase the backup.." newline bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers and..,1: Tamper 3 event does not erase the backup.." bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers and..,1: Tamper 2 event does not erase the backup.." newline bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers and..,1: Tamper 1 event does not erase the backup.." line.long 0x8 "TAMP_CR3,TAMP control register 3" bitfld.long 0x8 12. "ITAMP13NOER,Internal Tamper 13 no erase" "0: Internal Tamper 13 event erases the backup..,1: Internal Tamper 13 event does not erase the.." bitfld.long 0x8 11. "ITAMP12NOER,Internal Tamper 12 no erase" "0: Internal Tamper 12 event erases the backup..,1: Internal Tamper 12 event does not erase the.." newline bitfld.long 0x8 10. "ITAMP11NOER,Internal Tamper 11 no erase" "0: Internal Tamper 11 event erases the backup..,1: Internal Tamper 11 event does not erase the.." bitfld.long 0x8 8. "ITAMP9NOER,Internal Tamper 9 no erase" "0: Internal Tamper 9 event erases the backup..,1: Internal Tamper 9 event does not erase the.." newline bitfld.long 0x8 7. "ITAMP8NOER,Internal Tamper 8 no erase" "0: Internal Tamper 8 event erases the backup..,1: Internal Tamper 8 event does not erase the.." bitfld.long 0x8 6. "ITAMP7NOER,Internal Tamper 7 no erase" "0: Internal Tamper 7 event erases the backup..,1: Internal Tamper 7 event does not erase the.." newline bitfld.long 0x8 5. "ITAMP6NOER,Internal Tamper 6 no erase" "0: Internal Tamper 6 event erases the backup..,1: Internal Tamper 6 event does not erase the.." bitfld.long 0x8 4. "ITAMP5NOER,Internal Tamper 5 no erase" "0: Internal Tamper 5 event erases the backup..,1: Internal Tamper 5 event does not erase the.." newline bitfld.long 0x8 2. "ITAMP3NOER,Internal Tamper 3 no erase" "0: Internal Tamper 3 event erases the backup..,1: Internal Tamper 3 event does not erase the.." bitfld.long 0x8 1. "ITAMP2NOER,Internal Tamper 2 no erase" "0: Internal Tamper 2 event erases the backup..,1: Internal Tamper 2 event does not erase the.." newline bitfld.long 0x8 0. "ITAMP1NOER,Internal Tamper 1 no erase" "0: Internal Tamper 1 event erases the backup..,1: Internal Tamper 1 event does not erase the.." line.long 0xC "TAMP_FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins." bitfld.long 0xC 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles" newline bitfld.long 0xC 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.." bitfld.long 0xC 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)" line.long 0x10 "TAMP_ATCR1,TAMP active tamper control register 1" bitfld.long 0x10 31. "FLTEN,Active tamper filter enable" "0: Active tamper filtering disable,1: Active tamper filtering enable: a tamper event.." bitfld.long 0x10 30. "ATOSHARE,Active tamper output sharing" "0: Each active tamper input TAMP_INi is compared..,1: Each active tamper input TAMP_INi is compared.." newline bitfld.long 0x10 24.--26. "ATPER,Active tamper output change period" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" "0: RTCCLK is selected,1: RTCCLK/2 is selected when (PREDIV_A+1) = 128..,2: RTCCLK/4 is selected when (PREDIV_A+1) = 128..,?,?,?,?,7: RTCCLK/128 is selected when (PREDIV_A+1) = 128.." newline bitfld.long 0x10 14.--15. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4" bitfld.long 0x10 12.--13. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4" newline bitfld.long 0x10 10.--11. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4" bitfld.long 0x10 8.--9. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4" newline bitfld.long 0x10 7. "TAMP8AM,Tamper 8 active mode" "0: Tamper 8 detection mode is passive.,1: Tamper 8 detection mode is active." bitfld.long 0x10 6. "TAMP7AM,Tamper 7 active mode" "0: Tamper 7 detection mode is passive.,1: Tamper 7 detection mode is active." newline bitfld.long 0x10 5. "TAMP6AM,Tamper 6 active mode" "0: Tamper 6 detection mode is passive.,1: Tamper 6 detection mode is active." bitfld.long 0x10 4. "TAMP5AM,Tamper 5 active mode" "0: Tamper 5 detection mode is passive.,1: Tamper 5 detection mode is active." newline bitfld.long 0x10 3. "TAMP4AM,Tamper 4 active mode" "0: Tamper 4 detection mode is passive.,1: Tamper 4 detection mode is active." bitfld.long 0x10 2. "TAMP3AM,Tamper 3 active mode" "0: Tamper 3 detection mode is passive.,1: Tamper 3 detection mode is active." newline bitfld.long 0x10 1. "TAMP2AM,Tamper 2 active mode" "0: Tamper 2 detection mode is passive.,1: Tamper 2 detection mode is active." bitfld.long 0x10 0. "TAMP1AM,Tamper 1 active mode" "0: Tamper 1 detection mode is passive.,1: Tamper 1 detection mode is active." wgroup.long 0x14++0x3 line.long 0x0 "TAMP_ATSEEDR,TAMP active tamper seed register" hexmask.long 0x0 0.--31. 1. "SEED,Pseudo-random generator seed value" rgroup.long 0x18++0x3 line.long 0x0 "TAMP_ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,Active tamper initialization status" "0,1" bitfld.long 0x0 14. "SEEDF,Seed running flag" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PRNG,Pseudo-random generator value" group.long 0x1C++0xB line.long 0x0 "TAMP_ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,Active tamper shared output 8 selection" "0: TAMPOUTSEL8 = TAMP_OUT1,1: TAMPOUTSEL8 = TAMP_OUT2,2: TAMPOUTSEL8 = TAMP_OUT3,3: TAMPOUTSEL8 = TAMP_OUT4,4: TAMPOUTSEL8 = TAMP_OUT5,5: TAMPOUTSEL8 = TAMP_OUT6,6: TAMPOUTSEL8 = TAMP_OUT7,7: TAMPOUTSEL8 = TAMP_OUT8" bitfld.long 0x0 26.--28. "ATOSEL7,Active tamper shared output 7 selection" "0: TAMPOUTSEL7 = TAMP_OUT1,1: TAMPOUTSEL7 = TAMP_OUT2,2: TAMPOUTSEL7 = TAMP_OUT3,3: TAMPOUTSEL7 = TAMP_OUT4,4: TAMPOUTSEL7 = TAMP_OUT5,5: TAMPOUTSEL7 = TAMP_OUT6,6: TAMPOUTSEL7 = TAMP_OUT7,7: TAMPOUTSEL7 = TAMP_OUT8" newline bitfld.long 0x0 23.--25. "ATOSEL6,Active tamper shared output 6 selection" "0: TAMPOUTSEL6 = TAMP_OUT1,1: TAMPOUTSEL6 = TAMP_OUT2,2: TAMPOUTSEL6 = TAMP_OUT3,3: TAMPOUTSEL6 = TAMP_OUT4,4: TAMPOUTSEL6 = TAMP_OUT5,5: TAMPOUTSEL6 = TAMP_OUT6,6: TAMPOUTSEL6 = TAMP_OUT7,7: TAMPOUTSEL6 = TAMP_OUT8" bitfld.long 0x0 20.--22. "ATOSEL5,Active tamper shared output 5 selection" "0: TAMPOUTSEL5 = TAMP_OUT1,1: TAMPOUTSEL5 = TAMP_OUT2,2: TAMPOUTSEL5 = TAMP_OUT3,3: TAMPOUTSEL5 = TAMP_OUT4,4: TAMPOUTSEL5 = TAMP_OUT5,5: TAMPOUTSEL5 = TAMP_OUT6,6: TAMPOUTSEL5 = TAMP_OUT7,7: TAMPOUTSEL5 = TAMP_OUT8" newline bitfld.long 0x0 17.--19. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4,4: TAMPOUTSEL4 = TAMP_OUT5,5: TAMPOUTSEL4 = TAMP_OUT6,6: TAMPOUTSEL4 = TAMP_OUT7,7: TAMPOUTSEL4 = TAMP_OUT8" bitfld.long 0x0 14.--16. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4,4: TAMPOUTSEL3 = TAMP_OUT5,5: TAMPOUTSEL3 = TAMP_OUT6,6: TAMPOUTSEL3 = TAMP_OUT7,7: TAMPOUTSEL3 = TAMP_OUT8" newline bitfld.long 0x0 11.--13. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4,4: TAMPOUTSEL2 = TAMP_OUT5,5: TAMPOUTSEL2 = TAMP_OUT6,6: TAMPOUTSEL2 = TAMP_OUT7,7: TAMPOUTSEL2 = TAMP_OUT8" bitfld.long 0x0 8.--10. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4,4: TAMPOUTSEL1 = TAMP_OUT5,5: TAMPOUTSEL1 = TAMP_OUT6,6: TAMPOUTSEL1 = TAMP_OUT7,7: TAMPOUTSEL1 = TAMP_OUT8" line.long 0x4 "TAMP_SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,Tamper protection (excluding monotonic counters and backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x4 30. "BHKLOCK,Boot hardware key lock" "0: The Backup registers from TAMP_BKP0R to..,1: The backup registers from TAMP_BKP0R to.." newline hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,Backup registers write protection offset" bitfld.long 0x4 15. "CNT1SEC,Monotonic counter 1 secure protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." newline hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,Backup registers read/write protection offset" line.long 0x8 "TAMP_PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,Tamper privilege protection (excluding backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x8 30. "BKPWPRIV,Backup registers zone 2 privilege protection" "0: Backup registers zone 2 can be written with..,1: Backup registers zone 2 can be written only with.." newline bitfld.long 0x8 29. "BKPRWPRIV,Backup registers zone 1 privilege protection" "0: Backup registers zone 1 can be read and written..,1: Backup registers zone 1 can be read and written.." bitfld.long 0x8 15. "CNT1PRIV,Monotonic counter 1 privilege protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." group.long 0x2C++0x3 line.long 0x0 "TAMP_IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,Internal tamper 13 interrupt enable" "0: Internal tamper 13 interrupt disabled.,1: Internal tamper 13 interrupt enabled." bitfld.long 0x0 27. "ITAMP12IE,Internal tamper 12 interrupt enable" "0: Internal tamper 12 interrupt disabled.,1: Internal tamper 12 interrupt enabled." newline bitfld.long 0x0 26. "ITAMP11IE,Internal tamper 11 interrupt enable" "0: Internal tamper 11 interrupt disabled.,1: Internal tamper 11 interrupt enabled." bitfld.long 0x0 24. "ITAMP9IE,Internal tamper 9 interrupt enable" "0: Internal tamper 9 interrupt disabled.,1: Internal tamper 9 interrupt enabled." newline bitfld.long 0x0 23. "ITAMP8IE,Internal tamper 8 interrupt enable" "0: Internal tamper 8 interrupt disabled.,1: Internal tamper 8 interrupt enabled." bitfld.long 0x0 22. "ITAMP7IE,Internal tamper 7 interrupt enable" "0: Internal tamper 7 interrupt disabled.,1: Internal tamper 7 interrupt enabled." newline bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled." bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled." newline bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled." bitfld.long 0x0 17. "ITAMP2IE,Internal tamper 2 interrupt enable" "0: Internal tamper 2 interrupt disabled.,1: Internal tamper 2 interrupt enabled." newline bitfld.long 0x0 16. "ITAMP1IE,Internal tamper 1 interrupt enable" "0: Internal tamper 1 interrupt disabled.,1: Internal tamper 1 interrupt enabled" bitfld.long 0x0 7. "TAMP8IE,Tamper 8 interrupt enable" "0: Tamper 8 interrupt disabled.,1: Tamper 8 interrupt enabled." newline bitfld.long 0x0 6. "TAMP7IE,Tamper 7interrupt enable" "0: Tamper 7 interrupt disabled.,1: Tamper 7interrupt enabled." bitfld.long 0x0 5. "TAMP6IE,Tamper 6 interrupt enable" "0: Tamper 6 interrupt disabled.,1: Tamper 6 interrupt enabled." newline bitfld.long 0x0 4. "TAMP5IE,Tamper 5 interrupt enable" "0: Tamper 5 interrupt disabled.,1: Tamper 5 interrupt enabled." bitfld.long 0x0 3. "TAMP4IE,Tamper 4 interrupt enable" "0: Tamper 4 interrupt disabled.,1: Tamper 4 interrupt enabled." newline bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.." bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled." newline bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled." rgroup.long 0x30++0xB line.long 0x0 "TAMP_SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13F,Internal tamper 13 flag" "0,1" bitfld.long 0x0 27. "ITAMP12F,Internal tamper 12 flag" "0,1" newline bitfld.long 0x0 26. "ITAMP11F,Internal tamper 11 flag" "0,1" bitfld.long 0x0 24. "ITAMP9F,Internal tamper 9 flag" "0,1" newline bitfld.long 0x0 23. "ITAMP8F,Internal tamper 8 flag" "0,1" bitfld.long 0x0 22. "ITAMP7F,Internal tamper 7 flag" "0,1" newline bitfld.long 0x0 21. "ITAMP6F,Internal tamper 6 flag" "0,1" bitfld.long 0x0 20. "ITAMP5F,Internal tamper 5 flag" "0,1" newline bitfld.long 0x0 18. "ITAMP3F,Internal tamper 3 flag" "0,1" bitfld.long 0x0 17. "ITAMP2F,Internal tamper 2 flag" "0,1" newline bitfld.long 0x0 16. "ITAMP1F,Internal tamper 1 flag" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8 detection flag" "0,1" newline bitfld.long 0x0 6. "TAMP7F,TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1" line.long 0x4 "TAMP_MISR,TAMP non-secure masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,internal tamper 13 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 27. "ITAMP12MF,internal tamper 12 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 26. "ITAMP11MF,internal tamper 11 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 24. "ITAMP9MF,internal tamper 9 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 23. "ITAMP8MF,Internal tamper 8 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 22. "ITAMP7MF,VCORE monitoring tamper non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 21. "ITAMP6MF,Internal tamper 6 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 20. "ITAMP5MF,Internal tamper 5 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 18. "ITAMP3MF,Internal tamper 3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 17. "ITAMP2MF,Internal tamper 2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 16. "ITAMP1MF,Internal tamper 1 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 6. "TAMP7MF,TAMP7 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 2. "TAMP3MF,TAMP3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 0. "TAMP1MF,TAMP1 non-secure interrupt masked flag" "0,1" line.long 0x8 "TAMP_SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,internal tamper 13 secure interrupt masked flag" "0,1" bitfld.long 0x8 27. "ITAMP12MF,internal tamper 12 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 26. "ITAMP11MF,internal tamper 11 secure interrupt masked flag" "0,1" bitfld.long 0x8 24. "ITAMP9MF,internal tamper 9 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 23. "ITAMP8MF,Internal tamper 8 secure interrupt masked flag" "0,1" bitfld.long 0x8 22. "ITAMP7MF,VCORE monitoring tamper secure interrupt masked flag" "0,1" newline bitfld.long 0x8 21. "ITAMP6MF,Internal tamper 6 secure interrupt masked flag" "0,1" bitfld.long 0x8 20. "ITAMP5MF,Internal tamper 5 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 18. "ITAMP3MF,Internal tamper 3 secure interrupt masked flag" "0,1" bitfld.long 0x8 17. "ITAMP2MF,Internal tamper 2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 16. "ITAMP1MF,Internal tamper 1 secure interrupt masked flag" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 6. "TAMP7MF,TAMP7 secure interrupt masked flag" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5 secure interrupt masked flag" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 2. "TAMP3MF,TAMP3 secure interrupt masked flag" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 0. "TAMP1MF,TAMP1 secure interrupt masked flag" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "TAMP_SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,Clear ITAMP13 detection flag" "0,1" bitfld.long 0x0 27. "CITAMP12F,Clear ITAMP12 detection flag" "0,1" newline bitfld.long 0x0 26. "CITAMP11F,Clear ITAMP11 detection flag" "0,1" bitfld.long 0x0 24. "CITAMP9F,Clear ITAMP9 detection flag" "0,1" newline bitfld.long 0x0 23. "CITAMP8F,Clear ITAMP8 detection flag" "0,1" bitfld.long 0x0 22. "CITAMP7F,Clear ITAMP7 detection flag" "0,1" newline bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1" bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1" newline bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1" bitfld.long 0x0 17. "CITAMP2F,Clear ITAMP2 detection flag" "0,1" newline bitfld.long 0x0 16. "CITAMP1F,Clear ITAMP1 detection flag" "0,1" bitfld.long 0x0 7. "CTAMP8F,Clear TAMP8 detection flag" "0,1" newline bitfld.long 0x0 6. "CTAMP7F,Clear TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "CTAMP6F,Clear TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,Clear TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "CTAMP4F,Clear TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "TAMP_COUNT1R,TAMP monotonic counter 1 register" hexmask.long 0x0 0.--31. 1. "COUNT,This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value." group.long 0x54++0x3 line.long 0x0 "TAMP_ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,Configurable device secrets configuration" "0: Configurable device secrets are not included in..,1: Configurable device secrets are is included in.." group.long 0x100++0x7F line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register" hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register" hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register" hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0xC "TAMP_BKP3R,TAMP backup 3 register" hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register" hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register" hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register" hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register" hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register" hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x24 "TAMP_BKP9R,TAMP backup 9 register" hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x28 "TAMP_BKP10R,TAMP backup 10 register" hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x2C "TAMP_BKP11R,TAMP backup 11 register" hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x30 "TAMP_BKP12R,TAMP backup 12 register" hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x34 "TAMP_BKP13R,TAMP backup 13 register" hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x38 "TAMP_BKP14R,TAMP backup 14 register" hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x3C "TAMP_BKP15R,TAMP backup 15 register" hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x40 "TAMP_BKP16R,TAMP backup 16 register" hexmask.long 0x40 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x44 "TAMP_BKP17R,TAMP backup 17 register" hexmask.long 0x44 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x48 "TAMP_BKP18R,TAMP backup 18 register" hexmask.long 0x48 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4C "TAMP_BKP19R,TAMP backup 19 register" hexmask.long 0x4C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x50 "TAMP_BKP20R,TAMP backup 20 register" hexmask.long 0x50 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x54 "TAMP_BKP21R,TAMP backup 21 register" hexmask.long 0x54 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x58 "TAMP_BKP22R,TAMP backup 22 register" hexmask.long 0x58 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x5C "TAMP_BKP23R,TAMP backup 23 register" hexmask.long 0x5C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x60 "TAMP_BKP24R,TAMP backup 24 register" hexmask.long 0x60 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x64 "TAMP_BKP25R,TAMP backup 25 register" hexmask.long 0x64 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x68 "TAMP_BKP26R,TAMP backup 26 register" hexmask.long 0x68 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x6C "TAMP_BKP27R,TAMP backup 27 register" hexmask.long 0x6C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x70 "TAMP_BKP28R,TAMP backup 28 register" hexmask.long 0x70 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x74 "TAMP_BKP29R,TAMP backup 29 register" hexmask.long 0x74 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x78 "TAMP_BKP30R,TAMP backup 30 register" hexmask.long 0x78 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x7C "TAMP_BKP31R,TAMP backup 31 register" hexmask.long 0x7C 0.--31. 1. "BKP,The application can write or read data to and from these registers." endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TAMP" base ad:0x56007C00 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" newline bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" newline bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" newline bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" newline bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" newline bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" newline bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" newline bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" newline bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" newline bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" newline bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" newline bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" newline bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" newline bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" newline bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" newline bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" newline bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" newline bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" newline bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" newline bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" newline bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" newline bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" newline bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" newline bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" newline bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" newline bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" newline bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" newline bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" newline bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" newline bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" newline bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" newline bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" newline bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" newline bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" newline bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" newline bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" newline bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" newline bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" newline bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" newline bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" newline bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" newline bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" newline bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" newline bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" newline bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" newline bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" newline bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" newline bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" newline bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" newline bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" newline bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" newline bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" newline bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" newline bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" newline bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" newline bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" newline bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" newline bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" newline bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" newline bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" newline bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" newline bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" newline bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" newline bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" newline bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" newline bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" newline bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" newline bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" newline bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" endif sif (cpuis("STM32U575*")) group.long 0x0++0x13 line.long 0x0 "TAMP_CR1,TAMP control register 1" bitfld.long 0x0 28. "ITAMP13E,Internal tamper 13 enable" "0: Internal tamper 13 disabled.,1: Internal tamper 13 enabled." bitfld.long 0x0 27. "ITAMP12E,Internal tamper 12 enable" "0: Internal tamper 12 disabled.,1: Internal tamper 12 enabled." newline bitfld.long 0x0 26. "ITAMP11E,Internal tamper 11 enable" "0: Internal tamper 11 disabled.,1: Internal tamper 11 enabled." bitfld.long 0x0 24. "ITAMP9E,Internal tamper 9 enable" "0: Internal tamper 9 disabled.,1: Internal tamper 9 enabled." newline bitfld.long 0x0 23. "ITAMP8E,Internal tamper 8 enable" "0: Internal tamper 8 disabled.,1: Internal tamper 8 enabled." bitfld.long 0x0 22. "ITAMP7E,Internal tamper 7 enable" "0: Internal tamper 7 disabled.,1: Internal tamper 7 enabled" newline bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled." bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled." newline bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled." bitfld.long 0x0 17. "ITAMP2E,Internal tamper 2 enable" "0: Internal tamper 2 disabled.,1: Internal tamper 2 enabled." newline bitfld.long 0x0 16. "ITAMP1E,Internal tamper 1 enable" "0: Internal tamper 1 disabled.,1: Internal tamper 1 enabled." bitfld.long 0x0 7. "TAMP8E,Tamper detection on TAMP_IN8 enable" "0: Tamper detection on TAMP_IN8 is disabled.,1: Tamper detection on TAMP_IN8 is enabled." newline bitfld.long 0x0 6. "TAMP7E,Tamper detection on TAMP_IN7 enable" "0: Tamper detection on TAMP_IN7 is disabled.,1: Tamper detection on TAMP_IN7 is enabled." bitfld.long 0x0 5. "TAMP6E,Tamper detection on TAMP_IN6 enable" "0: Tamper detection on TAMP_IN6 is disabled.,1: Tamper detection on TAMP_IN6 is enabled." newline bitfld.long 0x0 4. "TAMP5E,Tamper detection on TAMP_IN5 enable" "0: Tamper detection on TAMP_IN5 is disabled.,1: Tamper detection on TAMP_IN5 is enabled." bitfld.long 0x0 3. "TAMP4E,Tamper detection on TAMP_IN4 enable" "0: Tamper detection on TAMP_IN4 is disabled.,1: Tamper detection on TAMP_IN4 is enabled." newline bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled." bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled." newline bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled." line.long 0x4 "TAMP_CR2,TAMP control register 2" bitfld.long 0x4 31. "TAMP8TRG,Active level for tamper 8 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 8 input staying low..,1: If TAMPFLT =/= 00 Tamper 8 input staying high.." bitfld.long 0x4 30. "TAMP7TRG,Active level for tamper 7 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 7 input staying low..,1: If TAMPFLT =/= 00 Tamper 7 input staying high.." newline bitfld.long 0x4 29. "TAMP6TRG,Active level for tamper 6 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 6 input staying low..,1: If TAMPFLT =/= 00 Tamper 6 input staying high.." bitfld.long 0x4 28. "TAMP5TRG,Active level for tamper 5 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 5 input staying low..,1: If TAMPFLT =/= 00 Tamper 5 input staying high.." newline bitfld.long 0x4 27. "TAMP4TRG,Active level for tamper 4 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 4 input staying low..,1: If TAMPFLT =/= 00 Tamper 4 input staying high.." bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input" "0: If TAMPFLT =/= 00 Tamper 3 input staying low..,1: If TAMPFLT =/= 00 Tamper 3 input staying high.." newline bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input" "0: If TAMPFLT =/= 00 Tamper 2 input staying low..,1: If TAMPFLT =/= 00 Tamper 2 input staying high.." bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input" "0: If TAMPFLT =/= 00 Tamper 1 input staying low..,1: If TAMPFLT =/= 00 Tamper 1 input staying high.." newline bitfld.long 0x4 23. "BKERASE,Backup registers and device secrets erase" "0,1" bitfld.long 0x4 22. "BKBLOCK,Backup registers and device secrets access blocked" "0: backup registers and device secrets(1) can be..,1: backup registers and device secrets(1) cannot be.." newline bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.." bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.." newline bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.." bitfld.long 0x4 7. "TAMP8NOER,Tamper 8 no erase" "0: Tamper 8 event erases the backup registers and..,1: Tamper 8 event does not erase the backup.." newline bitfld.long 0x4 6. "TAMP7NOER,Tamper 7 no erase" "0: Tamper 7 event erases the backup registers and..,1: Tamper 7 event does not erase the backup.." bitfld.long 0x4 5. "TAMP6NOER,Tamper 6 no erase" "0: Tamper 6 event erases the backup registers and..,1: Tamper 6 event does not erase the backup.." newline bitfld.long 0x4 4. "TAMP5NOER,Tamper 5 no erase" "0: Tamper 5 event erases the backup registers and..,1: Tamper 5 event does not erase the backup.." bitfld.long 0x4 3. "TAMP4NOER,Tamper 4 no erase" "0: Tamper 4 event erases the backup registers and..,1: Tamper 4 event does not erase the backup.." newline bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers and..,1: Tamper 3 event does not erase the backup.." bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers and..,1: Tamper 2 event does not erase the backup.." newline bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers and..,1: Tamper 1 event does not erase the backup.." line.long 0x8 "TAMP_CR3,TAMP control register 3" bitfld.long 0x8 12. "ITAMP13NOER,Internal Tamper 13 no erase" "0: Internal Tamper 13 event erases the backup..,1: Internal Tamper 13 event does not erase the.." bitfld.long 0x8 11. "ITAMP12NOER,Internal Tamper 12 no erase" "0: Internal Tamper 12 event erases the backup..,1: Internal Tamper 12 event does not erase the.." newline bitfld.long 0x8 10. "ITAMP11NOER,Internal Tamper 11 no erase" "0: Internal Tamper 11 event erases the backup..,1: Internal Tamper 11 event does not erase the.." bitfld.long 0x8 8. "ITAMP9NOER,Internal Tamper 9 no erase" "0: Internal Tamper 9 event erases the backup..,1: Internal Tamper 9 event does not erase the.." newline bitfld.long 0x8 7. "ITAMP8NOER,Internal Tamper 8 no erase" "0: Internal Tamper 8 event erases the backup..,1: Internal Tamper 8 event does not erase the.." bitfld.long 0x8 6. "ITAMP7NOER,Internal Tamper 7 no erase" "0: Internal Tamper 7 event erases the backup..,1: Internal Tamper 7 event does not erase the.." newline bitfld.long 0x8 5. "ITAMP6NOER,Internal Tamper 6 no erase" "0: Internal Tamper 6 event erases the backup..,1: Internal Tamper 6 event does not erase the.." bitfld.long 0x8 4. "ITAMP5NOER,Internal Tamper 5 no erase" "0: Internal Tamper 5 event erases the backup..,1: Internal Tamper 5 event does not erase the.." newline bitfld.long 0x8 2. "ITAMP3NOER,Internal Tamper 3 no erase" "0: Internal Tamper 3 event erases the backup..,1: Internal Tamper 3 event does not erase the.." bitfld.long 0x8 1. "ITAMP2NOER,Internal Tamper 2 no erase" "0: Internal Tamper 2 event erases the backup..,1: Internal Tamper 2 event does not erase the.." newline bitfld.long 0x8 0. "ITAMP1NOER,Internal Tamper 1 no erase" "0: Internal Tamper 1 event erases the backup..,1: Internal Tamper 1 event does not erase the.." line.long 0xC "TAMP_FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins." bitfld.long 0xC 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles" newline bitfld.long 0xC 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.." bitfld.long 0xC 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)" line.long 0x10 "TAMP_ATCR1,TAMP active tamper control register 1" bitfld.long 0x10 31. "FLTEN,Active tamper filter enable" "0: Active tamper filtering disable,1: Active tamper filtering enable: a tamper event.." bitfld.long 0x10 30. "ATOSHARE,Active tamper output sharing" "0: Each active tamper input TAMP_INi is compared..,1: Each active tamper input TAMP_INi is compared.." newline bitfld.long 0x10 24.--26. "ATPER,Active tamper output change period" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" "0: RTCCLK is selected,1: RTCCLK/2 is selected when (PREDIV_A+1) = 128..,2: RTCCLK/4 is selected when (PREDIV_A+1) = 128..,?,?,?,?,7: RTCCLK/128 is selected when (PREDIV_A+1) = 128.." newline bitfld.long 0x10 14.--15. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4" bitfld.long 0x10 12.--13. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4" newline bitfld.long 0x10 10.--11. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4" bitfld.long 0x10 8.--9. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4" newline bitfld.long 0x10 7. "TAMP8AM,Tamper 8 active mode" "0: Tamper 8 detection mode is passive.,1: Tamper 8 detection mode is active." bitfld.long 0x10 6. "TAMP7AM,Tamper 7 active mode" "0: Tamper 7 detection mode is passive.,1: Tamper 7 detection mode is active." newline bitfld.long 0x10 5. "TAMP6AM,Tamper 6 active mode" "0: Tamper 6 detection mode is passive.,1: Tamper 6 detection mode is active." bitfld.long 0x10 4. "TAMP5AM,Tamper 5 active mode" "0: Tamper 5 detection mode is passive.,1: Tamper 5 detection mode is active." newline bitfld.long 0x10 3. "TAMP4AM,Tamper 4 active mode" "0: Tamper 4 detection mode is passive.,1: Tamper 4 detection mode is active." bitfld.long 0x10 2. "TAMP3AM,Tamper 3 active mode" "0: Tamper 3 detection mode is passive.,1: Tamper 3 detection mode is active." newline bitfld.long 0x10 1. "TAMP2AM,Tamper 2 active mode" "0: Tamper 2 detection mode is passive.,1: Tamper 2 detection mode is active." bitfld.long 0x10 0. "TAMP1AM,Tamper 1 active mode" "0: Tamper 1 detection mode is passive.,1: Tamper 1 detection mode is active." wgroup.long 0x14++0x3 line.long 0x0 "TAMP_ATSEEDR,TAMP active tamper seed register" hexmask.long 0x0 0.--31. 1. "SEED,Pseudo-random generator seed value" rgroup.long 0x18++0x3 line.long 0x0 "TAMP_ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,Active tamper initialization status" "0,1" bitfld.long 0x0 14. "SEEDF,Seed running flag" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PRNG,Pseudo-random generator value" group.long 0x1C++0xB line.long 0x0 "TAMP_ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,Active tamper shared output 8 selection" "0: TAMPOUTSEL8 = TAMP_OUT1,1: TAMPOUTSEL8 = TAMP_OUT2,2: TAMPOUTSEL8 = TAMP_OUT3,3: TAMPOUTSEL8 = TAMP_OUT4,4: TAMPOUTSEL8 = TAMP_OUT5,5: TAMPOUTSEL8 = TAMP_OUT6,6: TAMPOUTSEL8 = TAMP_OUT7,7: TAMPOUTSEL8 = TAMP_OUT8" bitfld.long 0x0 26.--28. "ATOSEL7,Active tamper shared output 7 selection" "0: TAMPOUTSEL7 = TAMP_OUT1,1: TAMPOUTSEL7 = TAMP_OUT2,2: TAMPOUTSEL7 = TAMP_OUT3,3: TAMPOUTSEL7 = TAMP_OUT4,4: TAMPOUTSEL7 = TAMP_OUT5,5: TAMPOUTSEL7 = TAMP_OUT6,6: TAMPOUTSEL7 = TAMP_OUT7,7: TAMPOUTSEL7 = TAMP_OUT8" newline bitfld.long 0x0 23.--25. "ATOSEL6,Active tamper shared output 6 selection" "0: TAMPOUTSEL6 = TAMP_OUT1,1: TAMPOUTSEL6 = TAMP_OUT2,2: TAMPOUTSEL6 = TAMP_OUT3,3: TAMPOUTSEL6 = TAMP_OUT4,4: TAMPOUTSEL6 = TAMP_OUT5,5: TAMPOUTSEL6 = TAMP_OUT6,6: TAMPOUTSEL6 = TAMP_OUT7,7: TAMPOUTSEL6 = TAMP_OUT8" bitfld.long 0x0 20.--22. "ATOSEL5,Active tamper shared output 5 selection" "0: TAMPOUTSEL5 = TAMP_OUT1,1: TAMPOUTSEL5 = TAMP_OUT2,2: TAMPOUTSEL5 = TAMP_OUT3,3: TAMPOUTSEL5 = TAMP_OUT4,4: TAMPOUTSEL5 = TAMP_OUT5,5: TAMPOUTSEL5 = TAMP_OUT6,6: TAMPOUTSEL5 = TAMP_OUT7,7: TAMPOUTSEL5 = TAMP_OUT8" newline bitfld.long 0x0 17.--19. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4,4: TAMPOUTSEL4 = TAMP_OUT5,5: TAMPOUTSEL4 = TAMP_OUT6,6: TAMPOUTSEL4 = TAMP_OUT7,7: TAMPOUTSEL4 = TAMP_OUT8" bitfld.long 0x0 14.--16. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4,4: TAMPOUTSEL3 = TAMP_OUT5,5: TAMPOUTSEL3 = TAMP_OUT6,6: TAMPOUTSEL3 = TAMP_OUT7,7: TAMPOUTSEL3 = TAMP_OUT8" newline bitfld.long 0x0 11.--13. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4,4: TAMPOUTSEL2 = TAMP_OUT5,5: TAMPOUTSEL2 = TAMP_OUT6,6: TAMPOUTSEL2 = TAMP_OUT7,7: TAMPOUTSEL2 = TAMP_OUT8" bitfld.long 0x0 8.--10. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4,4: TAMPOUTSEL1 = TAMP_OUT5,5: TAMPOUTSEL1 = TAMP_OUT6,6: TAMPOUTSEL1 = TAMP_OUT7,7: TAMPOUTSEL1 = TAMP_OUT8" line.long 0x4 "TAMP_SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,Tamper protection (excluding monotonic counters and backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x4 30. "BHKLOCK,Boot hardware key lock" "0: The Backup registers from TAMP_BKP0R to..,1: The backup registers from TAMP_BKP0R to.." newline hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,Backup registers write protection offset" bitfld.long 0x4 15. "CNT1SEC,Monotonic counter 1 secure protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." newline hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,Backup registers read/write protection offset" line.long 0x8 "TAMP_PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,Tamper privilege protection (excluding backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x8 30. "BKPWPRIV,Backup registers zone 2 privilege protection" "0: Backup registers zone 2 can be written with..,1: Backup registers zone 2 can be written only with.." newline bitfld.long 0x8 29. "BKPRWPRIV,Backup registers zone 1 privilege protection" "0: Backup registers zone 1 can be read and written..,1: Backup registers zone 1 can be read and written.." bitfld.long 0x8 15. "CNT1PRIV,Monotonic counter 1 privilege protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." group.long 0x2C++0x3 line.long 0x0 "TAMP_IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,Internal tamper 13 interrupt enable" "0: Internal tamper 13 interrupt disabled.,1: Internal tamper 13 interrupt enabled." bitfld.long 0x0 27. "ITAMP12IE,Internal tamper 12 interrupt enable" "0: Internal tamper 12 interrupt disabled.,1: Internal tamper 12 interrupt enabled." newline bitfld.long 0x0 26. "ITAMP11IE,Internal tamper 11 interrupt enable" "0: Internal tamper 11 interrupt disabled.,1: Internal tamper 11 interrupt enabled." bitfld.long 0x0 24. "ITAMP9IE,Internal tamper 9 interrupt enable" "0: Internal tamper 9 interrupt disabled.,1: Internal tamper 9 interrupt enabled." newline bitfld.long 0x0 23. "ITAMP8IE,Internal tamper 8 interrupt enable" "0: Internal tamper 8 interrupt disabled.,1: Internal tamper 8 interrupt enabled." bitfld.long 0x0 22. "ITAMP7IE,Internal tamper 7 interrupt enable" "0: Internal tamper 7 interrupt disabled.,1: Internal tamper 7 interrupt enabled." newline bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled." bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled." newline bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled." bitfld.long 0x0 17. "ITAMP2IE,Internal tamper 2 interrupt enable" "0: Internal tamper 2 interrupt disabled.,1: Internal tamper 2 interrupt enabled." newline bitfld.long 0x0 16. "ITAMP1IE,Internal tamper 1 interrupt enable" "0: Internal tamper 1 interrupt disabled.,1: Internal tamper 1 interrupt enabled" bitfld.long 0x0 7. "TAMP8IE,Tamper 8 interrupt enable" "0: Tamper 8 interrupt disabled.,1: Tamper 8 interrupt enabled." newline bitfld.long 0x0 6. "TAMP7IE,Tamper 7interrupt enable" "0: Tamper 7 interrupt disabled.,1: Tamper 7interrupt enabled." bitfld.long 0x0 5. "TAMP6IE,Tamper 6 interrupt enable" "0: Tamper 6 interrupt disabled.,1: Tamper 6 interrupt enabled." newline bitfld.long 0x0 4. "TAMP5IE,Tamper 5 interrupt enable" "0: Tamper 5 interrupt disabled.,1: Tamper 5 interrupt enabled." bitfld.long 0x0 3. "TAMP4IE,Tamper 4 interrupt enable" "0: Tamper 4 interrupt disabled.,1: Tamper 4 interrupt enabled." newline bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.." bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled." newline bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled." rgroup.long 0x30++0xB line.long 0x0 "TAMP_SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13F,Internal tamper 13 flag" "0,1" bitfld.long 0x0 27. "ITAMP12F,Internal tamper 12 flag" "0,1" newline bitfld.long 0x0 26. "ITAMP11F,Internal tamper 11 flag" "0,1" bitfld.long 0x0 24. "ITAMP9F,Internal tamper 9 flag" "0,1" newline bitfld.long 0x0 23. "ITAMP8F,Internal tamper 8 flag" "0,1" bitfld.long 0x0 22. "ITAMP7F,Internal tamper 7 flag" "0,1" newline bitfld.long 0x0 21. "ITAMP6F,Internal tamper 6 flag" "0,1" bitfld.long 0x0 20. "ITAMP5F,Internal tamper 5 flag" "0,1" newline bitfld.long 0x0 18. "ITAMP3F,Internal tamper 3 flag" "0,1" bitfld.long 0x0 17. "ITAMP2F,Internal tamper 2 flag" "0,1" newline bitfld.long 0x0 16. "ITAMP1F,Internal tamper 1 flag" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8 detection flag" "0,1" newline bitfld.long 0x0 6. "TAMP7F,TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1" line.long 0x4 "TAMP_MISR,TAMP non-secure masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,internal tamper 13 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 27. "ITAMP12MF,internal tamper 12 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 26. "ITAMP11MF,internal tamper 11 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 24. "ITAMP9MF,internal tamper 9 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 23. "ITAMP8MF,Internal tamper 8 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 22. "ITAMP7MF,VCORE monitoring tamper non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 21. "ITAMP6MF,Internal tamper 6 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 20. "ITAMP5MF,Internal tamper 5 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 18. "ITAMP3MF,Internal tamper 3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 17. "ITAMP2MF,Internal tamper 2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 16. "ITAMP1MF,Internal tamper 1 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 6. "TAMP7MF,TAMP7 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 2. "TAMP3MF,TAMP3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 0. "TAMP1MF,TAMP1 non-secure interrupt masked flag" "0,1" line.long 0x8 "TAMP_SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,internal tamper 13 secure interrupt masked flag" "0,1" bitfld.long 0x8 27. "ITAMP12MF,internal tamper 12 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 26. "ITAMP11MF,internal tamper 11 secure interrupt masked flag" "0,1" bitfld.long 0x8 24. "ITAMP9MF,internal tamper 9 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 23. "ITAMP8MF,Internal tamper 8 secure interrupt masked flag" "0,1" bitfld.long 0x8 22. "ITAMP7MF,VCORE monitoring tamper secure interrupt masked flag" "0,1" newline bitfld.long 0x8 21. "ITAMP6MF,Internal tamper 6 secure interrupt masked flag" "0,1" bitfld.long 0x8 20. "ITAMP5MF,Internal tamper 5 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 18. "ITAMP3MF,Internal tamper 3 secure interrupt masked flag" "0,1" bitfld.long 0x8 17. "ITAMP2MF,Internal tamper 2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 16. "ITAMP1MF,Internal tamper 1 secure interrupt masked flag" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 6. "TAMP7MF,TAMP7 secure interrupt masked flag" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5 secure interrupt masked flag" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 2. "TAMP3MF,TAMP3 secure interrupt masked flag" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 0. "TAMP1MF,TAMP1 secure interrupt masked flag" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "TAMP_SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,Clear ITAMP13 detection flag" "0,1" bitfld.long 0x0 27. "CITAMP12F,Clear ITAMP12 detection flag" "0,1" newline bitfld.long 0x0 26. "CITAMP11F,Clear ITAMP11 detection flag" "0,1" bitfld.long 0x0 24. "CITAMP9F,Clear ITAMP9 detection flag" "0,1" newline bitfld.long 0x0 23. "CITAMP8F,Clear ITAMP8 detection flag" "0,1" bitfld.long 0x0 22. "CITAMP7F,Clear ITAMP7 detection flag" "0,1" newline bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1" bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1" newline bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1" bitfld.long 0x0 17. "CITAMP2F,Clear ITAMP2 detection flag" "0,1" newline bitfld.long 0x0 16. "CITAMP1F,Clear ITAMP1 detection flag" "0,1" bitfld.long 0x0 7. "CTAMP8F,Clear TAMP8 detection flag" "0,1" newline bitfld.long 0x0 6. "CTAMP7F,Clear TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "CTAMP6F,Clear TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,Clear TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "CTAMP4F,Clear TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "TAMP_COUNT1R,TAMP monotonic counter 1 register" hexmask.long 0x0 0.--31. 1. "COUNT,This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value." group.long 0x54++0x3 line.long 0x0 "TAMP_ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,Configurable device secrets configuration" "0: Configurable device secrets are not included in..,1: Configurable device secrets are is included in.." group.long 0x100++0x7F line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register" hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register" hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register" hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0xC "TAMP_BKP3R,TAMP backup 3 register" hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register" hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register" hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register" hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register" hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register" hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x24 "TAMP_BKP9R,TAMP backup 9 register" hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x28 "TAMP_BKP10R,TAMP backup 10 register" hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x2C "TAMP_BKP11R,TAMP backup 11 register" hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x30 "TAMP_BKP12R,TAMP backup 12 register" hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x34 "TAMP_BKP13R,TAMP backup 13 register" hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x38 "TAMP_BKP14R,TAMP backup 14 register" hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x3C "TAMP_BKP15R,TAMP backup 15 register" hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x40 "TAMP_BKP16R,TAMP backup 16 register" hexmask.long 0x40 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x44 "TAMP_BKP17R,TAMP backup 17 register" hexmask.long 0x44 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x48 "TAMP_BKP18R,TAMP backup 18 register" hexmask.long 0x48 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4C "TAMP_BKP19R,TAMP backup 19 register" hexmask.long 0x4C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x50 "TAMP_BKP20R,TAMP backup 20 register" hexmask.long 0x50 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x54 "TAMP_BKP21R,TAMP backup 21 register" hexmask.long 0x54 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x58 "TAMP_BKP22R,TAMP backup 22 register" hexmask.long 0x58 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x5C "TAMP_BKP23R,TAMP backup 23 register" hexmask.long 0x5C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x60 "TAMP_BKP24R,TAMP backup 24 register" hexmask.long 0x60 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x64 "TAMP_BKP25R,TAMP backup 25 register" hexmask.long 0x64 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x68 "TAMP_BKP26R,TAMP backup 26 register" hexmask.long 0x68 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x6C "TAMP_BKP27R,TAMP backup 27 register" hexmask.long 0x6C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x70 "TAMP_BKP28R,TAMP backup 28 register" hexmask.long 0x70 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x74 "TAMP_BKP29R,TAMP backup 29 register" hexmask.long 0x74 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x78 "TAMP_BKP30R,TAMP backup 30 register" hexmask.long 0x78 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x7C "TAMP_BKP31R,TAMP backup 31 register" hexmask.long 0x7C 0.--31. 1. "BKP,The application can write or read data to and from these registers." endif tree.end endif sif (cpuis("STM32U585*")) tree "TAMP" base ad:0x46007C00 group.long 0x0++0x13 line.long 0x0 "TAMP_CR1,TAMP control register 1" bitfld.long 0x0 28. "ITAMP13E,Internal tamper 13 enable" "0: Internal tamper 13 disabled.,1: Internal tamper 13 enabled." bitfld.long 0x0 27. "ITAMP12E,Internal tamper 12 enable" "0: Internal tamper 12 disabled.,1: Internal tamper 12 enabled." newline bitfld.long 0x0 26. "ITAMP11E,Internal tamper 11 enable" "0: Internal tamper 11 disabled.,1: Internal tamper 11 enabled." bitfld.long 0x0 24. "ITAMP9E,Internal tamper 9 enable" "0: Internal tamper 9 disabled.,1: Internal tamper 9 enabled." newline bitfld.long 0x0 23. "ITAMP8E,Internal tamper 8 enable" "0: Internal tamper 8 disabled.,1: Internal tamper 8 enabled." bitfld.long 0x0 22. "ITAMP7E,Internal tamper 7 enable" "0: Internal tamper 7 disabled.,1: Internal tamper 7 enabled" newline bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled." bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled." newline bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled." bitfld.long 0x0 17. "ITAMP2E,Internal tamper 2 enable" "0: Internal tamper 2 disabled.,1: Internal tamper 2 enabled." newline bitfld.long 0x0 16. "ITAMP1E,Internal tamper 1 enable" "0: Internal tamper 1 disabled.,1: Internal tamper 1 enabled." bitfld.long 0x0 7. "TAMP8E,Tamper detection on TAMP_IN8 enable" "0: Tamper detection on TAMP_IN8 is disabled.,1: Tamper detection on TAMP_IN8 is enabled." newline bitfld.long 0x0 6. "TAMP7E,Tamper detection on TAMP_IN7 enable" "0: Tamper detection on TAMP_IN7 is disabled.,1: Tamper detection on TAMP_IN7 is enabled." bitfld.long 0x0 5. "TAMP6E,Tamper detection on TAMP_IN6 enable" "0: Tamper detection on TAMP_IN6 is disabled.,1: Tamper detection on TAMP_IN6 is enabled." newline bitfld.long 0x0 4. "TAMP5E,Tamper detection on TAMP_IN5 enable" "0: Tamper detection on TAMP_IN5 is disabled.,1: Tamper detection on TAMP_IN5 is enabled." bitfld.long 0x0 3. "TAMP4E,Tamper detection on TAMP_IN4 enable" "0: Tamper detection on TAMP_IN4 is disabled.,1: Tamper detection on TAMP_IN4 is enabled." newline bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled." bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled." newline bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled." line.long 0x4 "TAMP_CR2,TAMP control register 2" bitfld.long 0x4 31. "TAMP8TRG,Active level for tamper 8 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 8 input staying low..,1: If TAMPFLT =/= 00 Tamper 8 input staying high.." bitfld.long 0x4 30. "TAMP7TRG,Active level for tamper 7 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 7 input staying low..,1: If TAMPFLT =/= 00 Tamper 7 input staying high.." newline bitfld.long 0x4 29. "TAMP6TRG,Active level for tamper 6 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 6 input staying low..,1: If TAMPFLT =/= 00 Tamper 6 input staying high.." bitfld.long 0x4 28. "TAMP5TRG,Active level for tamper 5 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 5 input staying low..,1: If TAMPFLT =/= 00 Tamper 5 input staying high.." newline bitfld.long 0x4 27. "TAMP4TRG,Active level for tamper 4 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 4 input staying low..,1: If TAMPFLT =/= 00 Tamper 4 input staying high.." bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input" "0: If TAMPFLT =/= 00 Tamper 3 input staying low..,1: If TAMPFLT =/= 00 Tamper 3 input staying high.." newline bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input" "0: If TAMPFLT =/= 00 Tamper 2 input staying low..,1: If TAMPFLT =/= 00 Tamper 2 input staying high.." bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input" "0: If TAMPFLT =/= 00 Tamper 1 input staying low..,1: If TAMPFLT =/= 00 Tamper 1 input staying high.." newline bitfld.long 0x4 23. "BKERASE,Backup registers and device secrets erase" "0,1" bitfld.long 0x4 22. "BKBLOCK,Backup registers and device secrets access blocked" "0: backup registers and device secrets(1) can be..,1: backup registers and device secrets(1) cannot be.." newline bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.." bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.." newline bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.." bitfld.long 0x4 7. "TAMP8NOER,Tamper 8 no erase" "0: Tamper 8 event erases the backup registers and..,1: Tamper 8 event does not erase the backup.." newline bitfld.long 0x4 6. "TAMP7NOER,Tamper 7 no erase" "0: Tamper 7 event erases the backup registers and..,1: Tamper 7 event does not erase the backup.." bitfld.long 0x4 5. "TAMP6NOER,Tamper 6 no erase" "0: Tamper 6 event erases the backup registers and..,1: Tamper 6 event does not erase the backup.." newline bitfld.long 0x4 4. "TAMP5NOER,Tamper 5 no erase" "0: Tamper 5 event erases the backup registers and..,1: Tamper 5 event does not erase the backup.." bitfld.long 0x4 3. "TAMP4NOER,Tamper 4 no erase" "0: Tamper 4 event erases the backup registers and..,1: Tamper 4 event does not erase the backup.." newline bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers and..,1: Tamper 3 event does not erase the backup.." bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers and..,1: Tamper 2 event does not erase the backup.." newline bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers and..,1: Tamper 1 event does not erase the backup.." line.long 0x8 "TAMP_CR3,TAMP control register 3" bitfld.long 0x8 12. "ITAMP13NOER,Internal Tamper 13 no erase" "0: Internal Tamper 13 event erases the backup..,1: Internal Tamper 13 event does not erase the.." bitfld.long 0x8 11. "ITAMP12NOER,Internal Tamper 12 no erase" "0: Internal Tamper 12 event erases the backup..,1: Internal Tamper 12 event does not erase the.." newline bitfld.long 0x8 10. "ITAMP11NOER,Internal Tamper 11 no erase" "0: Internal Tamper 11 event erases the backup..,1: Internal Tamper 11 event does not erase the.." bitfld.long 0x8 8. "ITAMP9NOER,Internal Tamper 9 no erase" "0: Internal Tamper 9 event erases the backup..,1: Internal Tamper 9 event does not erase the.." newline bitfld.long 0x8 7. "ITAMP8NOER,Internal Tamper 8 no erase" "0: Internal Tamper 8 event erases the backup..,1: Internal Tamper 8 event does not erase the.." bitfld.long 0x8 6. "ITAMP7NOER,Internal Tamper 7 no erase" "0: Internal Tamper 7 event erases the backup..,1: Internal Tamper 7 event does not erase the.." newline bitfld.long 0x8 5. "ITAMP6NOER,Internal Tamper 6 no erase" "0: Internal Tamper 6 event erases the backup..,1: Internal Tamper 6 event does not erase the.." bitfld.long 0x8 4. "ITAMP5NOER,Internal Tamper 5 no erase" "0: Internal Tamper 5 event erases the backup..,1: Internal Tamper 5 event does not erase the.." newline bitfld.long 0x8 2. "ITAMP3NOER,Internal Tamper 3 no erase" "0: Internal Tamper 3 event erases the backup..,1: Internal Tamper 3 event does not erase the.." bitfld.long 0x8 1. "ITAMP2NOER,Internal Tamper 2 no erase" "0: Internal Tamper 2 event erases the backup..,1: Internal Tamper 2 event does not erase the.." newline bitfld.long 0x8 0. "ITAMP1NOER,Internal Tamper 1 no erase" "0: Internal Tamper 1 event erases the backup..,1: Internal Tamper 1 event does not erase the.." line.long 0xC "TAMP_FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins." bitfld.long 0xC 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles" newline bitfld.long 0xC 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.." bitfld.long 0xC 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)" line.long 0x10 "TAMP_ATCR1,TAMP active tamper control register 1" bitfld.long 0x10 31. "FLTEN,Active tamper filter enable" "0: Active tamper filtering disable,1: Active tamper filtering enable: a tamper event.." bitfld.long 0x10 30. "ATOSHARE,Active tamper output sharing" "0: Each active tamper input TAMP_INi is compared..,1: Each active tamper input TAMP_INi is compared.." newline bitfld.long 0x10 24.--26. "ATPER,Active tamper output change period" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" "0: RTCCLK is selected,1: RTCCLK/2 is selected when (PREDIV_A+1) = 128..,2: RTCCLK/4 is selected when (PREDIV_A+1) = 128..,?,?,?,?,7: RTCCLK/128 is selected when (PREDIV_A+1) = 128.." newline bitfld.long 0x10 14.--15. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4" bitfld.long 0x10 12.--13. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4" newline bitfld.long 0x10 10.--11. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4" bitfld.long 0x10 8.--9. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4" newline bitfld.long 0x10 7. "TAMP8AM,Tamper 8 active mode" "0: Tamper 8 detection mode is passive.,1: Tamper 8 detection mode is active." bitfld.long 0x10 6. "TAMP7AM,Tamper 7 active mode" "0: Tamper 7 detection mode is passive.,1: Tamper 7 detection mode is active." newline bitfld.long 0x10 5. "TAMP6AM,Tamper 6 active mode" "0: Tamper 6 detection mode is passive.,1: Tamper 6 detection mode is active." bitfld.long 0x10 4. "TAMP5AM,Tamper 5 active mode" "0: Tamper 5 detection mode is passive.,1: Tamper 5 detection mode is active." newline bitfld.long 0x10 3. "TAMP4AM,Tamper 4 active mode" "0: Tamper 4 detection mode is passive.,1: Tamper 4 detection mode is active." bitfld.long 0x10 2. "TAMP3AM,Tamper 3 active mode" "0: Tamper 3 detection mode is passive.,1: Tamper 3 detection mode is active." newline bitfld.long 0x10 1. "TAMP2AM,Tamper 2 active mode" "0: Tamper 2 detection mode is passive.,1: Tamper 2 detection mode is active." bitfld.long 0x10 0. "TAMP1AM,Tamper 1 active mode" "0: Tamper 1 detection mode is passive.,1: Tamper 1 detection mode is active." wgroup.long 0x14++0x3 line.long 0x0 "TAMP_ATSEEDR,TAMP active tamper seed register" hexmask.long 0x0 0.--31. 1. "SEED,Pseudo-random generator seed value" rgroup.long 0x18++0x3 line.long 0x0 "TAMP_ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,Active tamper initialization status" "0,1" bitfld.long 0x0 14. "SEEDF,Seed running flag" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PRNG,Pseudo-random generator value" group.long 0x1C++0xB line.long 0x0 "TAMP_ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,Active tamper shared output 8 selection" "0: TAMPOUTSEL8 = TAMP_OUT1,1: TAMPOUTSEL8 = TAMP_OUT2,2: TAMPOUTSEL8 = TAMP_OUT3,3: TAMPOUTSEL8 = TAMP_OUT4,4: TAMPOUTSEL8 = TAMP_OUT5,5: TAMPOUTSEL8 = TAMP_OUT6,6: TAMPOUTSEL8 = TAMP_OUT7,7: TAMPOUTSEL8 = TAMP_OUT8" bitfld.long 0x0 26.--28. "ATOSEL7,Active tamper shared output 7 selection" "0: TAMPOUTSEL7 = TAMP_OUT1,1: TAMPOUTSEL7 = TAMP_OUT2,2: TAMPOUTSEL7 = TAMP_OUT3,3: TAMPOUTSEL7 = TAMP_OUT4,4: TAMPOUTSEL7 = TAMP_OUT5,5: TAMPOUTSEL7 = TAMP_OUT6,6: TAMPOUTSEL7 = TAMP_OUT7,7: TAMPOUTSEL7 = TAMP_OUT8" newline bitfld.long 0x0 23.--25. "ATOSEL6,Active tamper shared output 6 selection" "0: TAMPOUTSEL6 = TAMP_OUT1,1: TAMPOUTSEL6 = TAMP_OUT2,2: TAMPOUTSEL6 = TAMP_OUT3,3: TAMPOUTSEL6 = TAMP_OUT4,4: TAMPOUTSEL6 = TAMP_OUT5,5: TAMPOUTSEL6 = TAMP_OUT6,6: TAMPOUTSEL6 = TAMP_OUT7,7: TAMPOUTSEL6 = TAMP_OUT8" bitfld.long 0x0 20.--22. "ATOSEL5,Active tamper shared output 5 selection" "0: TAMPOUTSEL5 = TAMP_OUT1,1: TAMPOUTSEL5 = TAMP_OUT2,2: TAMPOUTSEL5 = TAMP_OUT3,3: TAMPOUTSEL5 = TAMP_OUT4,4: TAMPOUTSEL5 = TAMP_OUT5,5: TAMPOUTSEL5 = TAMP_OUT6,6: TAMPOUTSEL5 = TAMP_OUT7,7: TAMPOUTSEL5 = TAMP_OUT8" newline bitfld.long 0x0 17.--19. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4,4: TAMPOUTSEL4 = TAMP_OUT5,5: TAMPOUTSEL4 = TAMP_OUT6,6: TAMPOUTSEL4 = TAMP_OUT7,7: TAMPOUTSEL4 = TAMP_OUT8" bitfld.long 0x0 14.--16. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4,4: TAMPOUTSEL3 = TAMP_OUT5,5: TAMPOUTSEL3 = TAMP_OUT6,6: TAMPOUTSEL3 = TAMP_OUT7,7: TAMPOUTSEL3 = TAMP_OUT8" newline bitfld.long 0x0 11.--13. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4,4: TAMPOUTSEL2 = TAMP_OUT5,5: TAMPOUTSEL2 = TAMP_OUT6,6: TAMPOUTSEL2 = TAMP_OUT7,7: TAMPOUTSEL2 = TAMP_OUT8" bitfld.long 0x0 8.--10. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4,4: TAMPOUTSEL1 = TAMP_OUT5,5: TAMPOUTSEL1 = TAMP_OUT6,6: TAMPOUTSEL1 = TAMP_OUT7,7: TAMPOUTSEL1 = TAMP_OUT8" line.long 0x4 "TAMP_SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,Tamper protection (excluding monotonic counters and backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x4 30. "BHKLOCK,Boot hardware key lock" "0: The Backup registers from TAMP_BKP0R to..,1: The backup registers from TAMP_BKP0R to.." newline hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,Backup registers write protection offset" bitfld.long 0x4 15. "CNT1SEC,Monotonic counter 1 secure protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." newline hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,Backup registers read/write protection offset" line.long 0x8 "TAMP_PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,Tamper privilege protection (excluding backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x8 30. "BKPWPRIV,Backup registers zone 2 privilege protection" "0: Backup registers zone 2 can be written with..,1: Backup registers zone 2 can be written only with.." newline bitfld.long 0x8 29. "BKPRWPRIV,Backup registers zone 1 privilege protection" "0: Backup registers zone 1 can be read and written..,1: Backup registers zone 1 can be read and written.." bitfld.long 0x8 15. "CNT1PRIV,Monotonic counter 1 privilege protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." group.long 0x2C++0x3 line.long 0x0 "TAMP_IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,Internal tamper 13 interrupt enable" "0: Internal tamper 13 interrupt disabled.,1: Internal tamper 13 interrupt enabled." bitfld.long 0x0 27. "ITAMP12IE,Internal tamper 12 interrupt enable" "0: Internal tamper 12 interrupt disabled.,1: Internal tamper 12 interrupt enabled." newline bitfld.long 0x0 26. "ITAMP11IE,Internal tamper 11 interrupt enable" "0: Internal tamper 11 interrupt disabled.,1: Internal tamper 11 interrupt enabled." bitfld.long 0x0 24. "ITAMP9IE,Internal tamper 9 interrupt enable" "0: Internal tamper 9 interrupt disabled.,1: Internal tamper 9 interrupt enabled." newline bitfld.long 0x0 23. "ITAMP8IE,Internal tamper 8 interrupt enable" "0: Internal tamper 8 interrupt disabled.,1: Internal tamper 8 interrupt enabled." bitfld.long 0x0 22. "ITAMP7IE,Internal tamper 7 interrupt enable" "0: Internal tamper 7 interrupt disabled.,1: Internal tamper 7 interrupt enabled." newline bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled." bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled." newline bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled." bitfld.long 0x0 17. "ITAMP2IE,Internal tamper 2 interrupt enable" "0: Internal tamper 2 interrupt disabled.,1: Internal tamper 2 interrupt enabled." newline bitfld.long 0x0 16. "ITAMP1IE,Internal tamper 1 interrupt enable" "0: Internal tamper 1 interrupt disabled.,1: Internal tamper 1 interrupt enabled" bitfld.long 0x0 7. "TAMP8IE,Tamper 8 interrupt enable" "0: Tamper 8 interrupt disabled.,1: Tamper 8 interrupt enabled." newline bitfld.long 0x0 6. "TAMP7IE,Tamper 7interrupt enable" "0: Tamper 7 interrupt disabled.,1: Tamper 7interrupt enabled." bitfld.long 0x0 5. "TAMP6IE,Tamper 6 interrupt enable" "0: Tamper 6 interrupt disabled.,1: Tamper 6 interrupt enabled." newline bitfld.long 0x0 4. "TAMP5IE,Tamper 5 interrupt enable" "0: Tamper 5 interrupt disabled.,1: Tamper 5 interrupt enabled." bitfld.long 0x0 3. "TAMP4IE,Tamper 4 interrupt enable" "0: Tamper 4 interrupt disabled.,1: Tamper 4 interrupt enabled." newline bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.." bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled." newline bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled." rgroup.long 0x30++0xB line.long 0x0 "TAMP_SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13F,Internal tamper 13 flag" "0,1" bitfld.long 0x0 27. "ITAMP12F,Internal tamper 12 flag" "0,1" newline bitfld.long 0x0 26. "ITAMP11F,Internal tamper 11 flag" "0,1" bitfld.long 0x0 24. "ITAMP9F,Internal tamper 9 flag" "0,1" newline bitfld.long 0x0 23. "ITAMP8F,Internal tamper 8 flag" "0,1" bitfld.long 0x0 22. "ITAMP7F,Internal tamper 7 flag" "0,1" newline bitfld.long 0x0 21. "ITAMP6F,Internal tamper 6 flag" "0,1" bitfld.long 0x0 20. "ITAMP5F,Internal tamper 5 flag" "0,1" newline bitfld.long 0x0 18. "ITAMP3F,Internal tamper 3 flag" "0,1" bitfld.long 0x0 17. "ITAMP2F,Internal tamper 2 flag" "0,1" newline bitfld.long 0x0 16. "ITAMP1F,Internal tamper 1 flag" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8 detection flag" "0,1" newline bitfld.long 0x0 6. "TAMP7F,TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1" line.long 0x4 "TAMP_MISR,TAMP non-secure masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,internal tamper 13 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 27. "ITAMP12MF,internal tamper 12 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 26. "ITAMP11MF,internal tamper 11 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 24. "ITAMP9MF,internal tamper 9 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 23. "ITAMP8MF,Internal tamper 8 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 22. "ITAMP7MF,VCORE monitoring tamper non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 21. "ITAMP6MF,Internal tamper 6 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 20. "ITAMP5MF,Internal tamper 5 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 18. "ITAMP3MF,Internal tamper 3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 17. "ITAMP2MF,Internal tamper 2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 16. "ITAMP1MF,Internal tamper 1 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 6. "TAMP7MF,TAMP7 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 2. "TAMP3MF,TAMP3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 0. "TAMP1MF,TAMP1 non-secure interrupt masked flag" "0,1" line.long 0x8 "TAMP_SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,internal tamper 13 secure interrupt masked flag" "0,1" bitfld.long 0x8 27. "ITAMP12MF,internal tamper 12 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 26. "ITAMP11MF,internal tamper 11 secure interrupt masked flag" "0,1" bitfld.long 0x8 24. "ITAMP9MF,internal tamper 9 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 23. "ITAMP8MF,Internal tamper 8 secure interrupt masked flag" "0,1" bitfld.long 0x8 22. "ITAMP7MF,VCORE monitoring tamper secure interrupt masked flag" "0,1" newline bitfld.long 0x8 21. "ITAMP6MF,Internal tamper 6 secure interrupt masked flag" "0,1" bitfld.long 0x8 20. "ITAMP5MF,Internal tamper 5 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 18. "ITAMP3MF,Internal tamper 3 secure interrupt masked flag" "0,1" bitfld.long 0x8 17. "ITAMP2MF,Internal tamper 2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 16. "ITAMP1MF,Internal tamper 1 secure interrupt masked flag" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 6. "TAMP7MF,TAMP7 secure interrupt masked flag" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5 secure interrupt masked flag" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 2. "TAMP3MF,TAMP3 secure interrupt masked flag" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 0. "TAMP1MF,TAMP1 secure interrupt masked flag" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "TAMP_SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,Clear ITAMP13 detection flag" "0,1" bitfld.long 0x0 27. "CITAMP12F,Clear ITAMP12 detection flag" "0,1" newline bitfld.long 0x0 26. "CITAMP11F,Clear ITAMP11 detection flag" "0,1" bitfld.long 0x0 24. "CITAMP9F,Clear ITAMP9 detection flag" "0,1" newline bitfld.long 0x0 23. "CITAMP8F,Clear ITAMP8 detection flag" "0,1" bitfld.long 0x0 22. "CITAMP7F,Clear ITAMP7 detection flag" "0,1" newline bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1" bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1" newline bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1" bitfld.long 0x0 17. "CITAMP2F,Clear ITAMP2 detection flag" "0,1" newline bitfld.long 0x0 16. "CITAMP1F,Clear ITAMP1 detection flag" "0,1" bitfld.long 0x0 7. "CTAMP8F,Clear TAMP8 detection flag" "0,1" newline bitfld.long 0x0 6. "CTAMP7F,Clear TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "CTAMP6F,Clear TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,Clear TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "CTAMP4F,Clear TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "TAMP_COUNT1R,TAMP monotonic counter 1 register" hexmask.long 0x0 0.--31. 1. "COUNT,This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value." group.long 0x54++0x3 line.long 0x0 "TAMP_ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,Configurable device secrets configuration" "0: Configurable device secrets are not included in..,1: Configurable device secrets are is included in.." group.long 0x100++0x7F line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register" hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register" hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register" hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0xC "TAMP_BKP3R,TAMP backup 3 register" hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register" hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register" hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register" hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register" hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register" hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x24 "TAMP_BKP9R,TAMP backup 9 register" hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x28 "TAMP_BKP10R,TAMP backup 10 register" hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x2C "TAMP_BKP11R,TAMP backup 11 register" hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x30 "TAMP_BKP12R,TAMP backup 12 register" hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x34 "TAMP_BKP13R,TAMP backup 13 register" hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x38 "TAMP_BKP14R,TAMP backup 14 register" hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x3C "TAMP_BKP15R,TAMP backup 15 register" hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x40 "TAMP_BKP16R,TAMP backup 16 register" hexmask.long 0x40 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x44 "TAMP_BKP17R,TAMP backup 17 register" hexmask.long 0x44 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x48 "TAMP_BKP18R,TAMP backup 18 register" hexmask.long 0x48 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4C "TAMP_BKP19R,TAMP backup 19 register" hexmask.long 0x4C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x50 "TAMP_BKP20R,TAMP backup 20 register" hexmask.long 0x50 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x54 "TAMP_BKP21R,TAMP backup 21 register" hexmask.long 0x54 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x58 "TAMP_BKP22R,TAMP backup 22 register" hexmask.long 0x58 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x5C "TAMP_BKP23R,TAMP backup 23 register" hexmask.long 0x5C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x60 "TAMP_BKP24R,TAMP backup 24 register" hexmask.long 0x60 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x64 "TAMP_BKP25R,TAMP backup 25 register" hexmask.long 0x64 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x68 "TAMP_BKP26R,TAMP backup 26 register" hexmask.long 0x68 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x6C "TAMP_BKP27R,TAMP backup 27 register" hexmask.long 0x6C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x70 "TAMP_BKP28R,TAMP backup 28 register" hexmask.long 0x70 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x74 "TAMP_BKP29R,TAMP backup 29 register" hexmask.long 0x74 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x78 "TAMP_BKP30R,TAMP backup 30 register" hexmask.long 0x78 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x7C "TAMP_BKP31R,TAMP backup 31 register" hexmask.long 0x7C 0.--31. 1. "BKP,The application can write or read data to and from these registers." tree.end tree "SEC_TAMP" base ad:0x56007C00 group.long 0x0++0x13 line.long 0x0 "TAMP_CR1,TAMP control register 1" bitfld.long 0x0 28. "ITAMP13E,Internal tamper 13 enable" "0: Internal tamper 13 disabled.,1: Internal tamper 13 enabled." bitfld.long 0x0 27. "ITAMP12E,Internal tamper 12 enable" "0: Internal tamper 12 disabled.,1: Internal tamper 12 enabled." newline bitfld.long 0x0 26. "ITAMP11E,Internal tamper 11 enable" "0: Internal tamper 11 disabled.,1: Internal tamper 11 enabled." bitfld.long 0x0 24. "ITAMP9E,Internal tamper 9 enable" "0: Internal tamper 9 disabled.,1: Internal tamper 9 enabled." newline bitfld.long 0x0 23. "ITAMP8E,Internal tamper 8 enable" "0: Internal tamper 8 disabled.,1: Internal tamper 8 enabled." bitfld.long 0x0 22. "ITAMP7E,Internal tamper 7 enable" "0: Internal tamper 7 disabled.,1: Internal tamper 7 enabled" newline bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled." bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled." newline bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled." bitfld.long 0x0 17. "ITAMP2E,Internal tamper 2 enable" "0: Internal tamper 2 disabled.,1: Internal tamper 2 enabled." newline bitfld.long 0x0 16. "ITAMP1E,Internal tamper 1 enable" "0: Internal tamper 1 disabled.,1: Internal tamper 1 enabled." bitfld.long 0x0 7. "TAMP8E,Tamper detection on TAMP_IN8 enable" "0: Tamper detection on TAMP_IN8 is disabled.,1: Tamper detection on TAMP_IN8 is enabled." newline bitfld.long 0x0 6. "TAMP7E,Tamper detection on TAMP_IN7 enable" "0: Tamper detection on TAMP_IN7 is disabled.,1: Tamper detection on TAMP_IN7 is enabled." bitfld.long 0x0 5. "TAMP6E,Tamper detection on TAMP_IN6 enable" "0: Tamper detection on TAMP_IN6 is disabled.,1: Tamper detection on TAMP_IN6 is enabled." newline bitfld.long 0x0 4. "TAMP5E,Tamper detection on TAMP_IN5 enable" "0: Tamper detection on TAMP_IN5 is disabled.,1: Tamper detection on TAMP_IN5 is enabled." bitfld.long 0x0 3. "TAMP4E,Tamper detection on TAMP_IN4 enable" "0: Tamper detection on TAMP_IN4 is disabled.,1: Tamper detection on TAMP_IN4 is enabled." newline bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled." bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled." newline bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled." line.long 0x4 "TAMP_CR2,TAMP control register 2" bitfld.long 0x4 31. "TAMP8TRG,Active level for tamper 8 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 8 input staying low..,1: If TAMPFLT =/= 00 Tamper 8 input staying high.." bitfld.long 0x4 30. "TAMP7TRG,Active level for tamper 7 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 7 input staying low..,1: If TAMPFLT =/= 00 Tamper 7 input staying high.." newline bitfld.long 0x4 29. "TAMP6TRG,Active level for tamper 6 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 6 input staying low..,1: If TAMPFLT =/= 00 Tamper 6 input staying high.." bitfld.long 0x4 28. "TAMP5TRG,Active level for tamper 5 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 5 input staying low..,1: If TAMPFLT =/= 00 Tamper 5 input staying high.." newline bitfld.long 0x4 27. "TAMP4TRG,Active level for tamper 4 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 4 input staying low..,1: If TAMPFLT =/= 00 Tamper 4 input staying high.." bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input" "0: If TAMPFLT =/= 00 Tamper 3 input staying low..,1: If TAMPFLT =/= 00 Tamper 3 input staying high.." newline bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input" "0: If TAMPFLT =/= 00 Tamper 2 input staying low..,1: If TAMPFLT =/= 00 Tamper 2 input staying high.." bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input" "0: If TAMPFLT =/= 00 Tamper 1 input staying low..,1: If TAMPFLT =/= 00 Tamper 1 input staying high.." newline bitfld.long 0x4 23. "BKERASE,Backup registers and device secrets erase" "0,1" bitfld.long 0x4 22. "BKBLOCK,Backup registers and device secrets access blocked" "0: backup registers and device secrets(1) can be..,1: backup registers and device secrets(1) cannot be.." newline bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.." bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.." newline bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.." bitfld.long 0x4 7. "TAMP8NOER,Tamper 8 no erase" "0: Tamper 8 event erases the backup registers and..,1: Tamper 8 event does not erase the backup.." newline bitfld.long 0x4 6. "TAMP7NOER,Tamper 7 no erase" "0: Tamper 7 event erases the backup registers and..,1: Tamper 7 event does not erase the backup.." bitfld.long 0x4 5. "TAMP6NOER,Tamper 6 no erase" "0: Tamper 6 event erases the backup registers and..,1: Tamper 6 event does not erase the backup.." newline bitfld.long 0x4 4. "TAMP5NOER,Tamper 5 no erase" "0: Tamper 5 event erases the backup registers and..,1: Tamper 5 event does not erase the backup.." bitfld.long 0x4 3. "TAMP4NOER,Tamper 4 no erase" "0: Tamper 4 event erases the backup registers and..,1: Tamper 4 event does not erase the backup.." newline bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers and..,1: Tamper 3 event does not erase the backup.." bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers and..,1: Tamper 2 event does not erase the backup.." newline bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers and..,1: Tamper 1 event does not erase the backup.." line.long 0x8 "TAMP_CR3,TAMP control register 3" bitfld.long 0x8 12. "ITAMP13NOER,Internal Tamper 13 no erase" "0: Internal Tamper 13 event erases the backup..,1: Internal Tamper 13 event does not erase the.." bitfld.long 0x8 11. "ITAMP12NOER,Internal Tamper 12 no erase" "0: Internal Tamper 12 event erases the backup..,1: Internal Tamper 12 event does not erase the.." newline bitfld.long 0x8 10. "ITAMP11NOER,Internal Tamper 11 no erase" "0: Internal Tamper 11 event erases the backup..,1: Internal Tamper 11 event does not erase the.." bitfld.long 0x8 8. "ITAMP9NOER,Internal Tamper 9 no erase" "0: Internal Tamper 9 event erases the backup..,1: Internal Tamper 9 event does not erase the.." newline bitfld.long 0x8 7. "ITAMP8NOER,Internal Tamper 8 no erase" "0: Internal Tamper 8 event erases the backup..,1: Internal Tamper 8 event does not erase the.." bitfld.long 0x8 6. "ITAMP7NOER,Internal Tamper 7 no erase" "0: Internal Tamper 7 event erases the backup..,1: Internal Tamper 7 event does not erase the.." newline bitfld.long 0x8 5. "ITAMP6NOER,Internal Tamper 6 no erase" "0: Internal Tamper 6 event erases the backup..,1: Internal Tamper 6 event does not erase the.." bitfld.long 0x8 4. "ITAMP5NOER,Internal Tamper 5 no erase" "0: Internal Tamper 5 event erases the backup..,1: Internal Tamper 5 event does not erase the.." newline bitfld.long 0x8 2. "ITAMP3NOER,Internal Tamper 3 no erase" "0: Internal Tamper 3 event erases the backup..,1: Internal Tamper 3 event does not erase the.." bitfld.long 0x8 1. "ITAMP2NOER,Internal Tamper 2 no erase" "0: Internal Tamper 2 event erases the backup..,1: Internal Tamper 2 event does not erase the.." newline bitfld.long 0x8 0. "ITAMP1NOER,Internal Tamper 1 no erase" "0: Internal Tamper 1 event erases the backup..,1: Internal Tamper 1 event does not erase the.." line.long 0xC "TAMP_FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins." bitfld.long 0xC 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles" newline bitfld.long 0xC 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.." bitfld.long 0xC 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)" line.long 0x10 "TAMP_ATCR1,TAMP active tamper control register 1" bitfld.long 0x10 31. "FLTEN,Active tamper filter enable" "0: Active tamper filtering disable,1: Active tamper filtering enable: a tamper event.." bitfld.long 0x10 30. "ATOSHARE,Active tamper output sharing" "0: Each active tamper input TAMP_INi is compared..,1: Each active tamper input TAMP_INi is compared.." newline bitfld.long 0x10 24.--26. "ATPER,Active tamper output change period" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" "0: RTCCLK is selected,1: RTCCLK/2 is selected when (PREDIV_A+1) = 128..,2: RTCCLK/4 is selected when (PREDIV_A+1) = 128..,?,?,?,?,7: RTCCLK/128 is selected when (PREDIV_A+1) = 128.." newline bitfld.long 0x10 14.--15. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4" bitfld.long 0x10 12.--13. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4" newline bitfld.long 0x10 10.--11. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4" bitfld.long 0x10 8.--9. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4" newline bitfld.long 0x10 7. "TAMP8AM,Tamper 8 active mode" "0: Tamper 8 detection mode is passive.,1: Tamper 8 detection mode is active." bitfld.long 0x10 6. "TAMP7AM,Tamper 7 active mode" "0: Tamper 7 detection mode is passive.,1: Tamper 7 detection mode is active." newline bitfld.long 0x10 5. "TAMP6AM,Tamper 6 active mode" "0: Tamper 6 detection mode is passive.,1: Tamper 6 detection mode is active." bitfld.long 0x10 4. "TAMP5AM,Tamper 5 active mode" "0: Tamper 5 detection mode is passive.,1: Tamper 5 detection mode is active." newline bitfld.long 0x10 3. "TAMP4AM,Tamper 4 active mode" "0: Tamper 4 detection mode is passive.,1: Tamper 4 detection mode is active." bitfld.long 0x10 2. "TAMP3AM,Tamper 3 active mode" "0: Tamper 3 detection mode is passive.,1: Tamper 3 detection mode is active." newline bitfld.long 0x10 1. "TAMP2AM,Tamper 2 active mode" "0: Tamper 2 detection mode is passive.,1: Tamper 2 detection mode is active." bitfld.long 0x10 0. "TAMP1AM,Tamper 1 active mode" "0: Tamper 1 detection mode is passive.,1: Tamper 1 detection mode is active." wgroup.long 0x14++0x3 line.long 0x0 "TAMP_ATSEEDR,TAMP active tamper seed register" hexmask.long 0x0 0.--31. 1. "SEED,Pseudo-random generator seed value" rgroup.long 0x18++0x3 line.long 0x0 "TAMP_ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,Active tamper initialization status" "0,1" bitfld.long 0x0 14. "SEEDF,Seed running flag" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PRNG,Pseudo-random generator value" group.long 0x1C++0xB line.long 0x0 "TAMP_ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,Active tamper shared output 8 selection" "0: TAMPOUTSEL8 = TAMP_OUT1,1: TAMPOUTSEL8 = TAMP_OUT2,2: TAMPOUTSEL8 = TAMP_OUT3,3: TAMPOUTSEL8 = TAMP_OUT4,4: TAMPOUTSEL8 = TAMP_OUT5,5: TAMPOUTSEL8 = TAMP_OUT6,6: TAMPOUTSEL8 = TAMP_OUT7,7: TAMPOUTSEL8 = TAMP_OUT8" bitfld.long 0x0 26.--28. "ATOSEL7,Active tamper shared output 7 selection" "0: TAMPOUTSEL7 = TAMP_OUT1,1: TAMPOUTSEL7 = TAMP_OUT2,2: TAMPOUTSEL7 = TAMP_OUT3,3: TAMPOUTSEL7 = TAMP_OUT4,4: TAMPOUTSEL7 = TAMP_OUT5,5: TAMPOUTSEL7 = TAMP_OUT6,6: TAMPOUTSEL7 = TAMP_OUT7,7: TAMPOUTSEL7 = TAMP_OUT8" newline bitfld.long 0x0 23.--25. "ATOSEL6,Active tamper shared output 6 selection" "0: TAMPOUTSEL6 = TAMP_OUT1,1: TAMPOUTSEL6 = TAMP_OUT2,2: TAMPOUTSEL6 = TAMP_OUT3,3: TAMPOUTSEL6 = TAMP_OUT4,4: TAMPOUTSEL6 = TAMP_OUT5,5: TAMPOUTSEL6 = TAMP_OUT6,6: TAMPOUTSEL6 = TAMP_OUT7,7: TAMPOUTSEL6 = TAMP_OUT8" bitfld.long 0x0 20.--22. "ATOSEL5,Active tamper shared output 5 selection" "0: TAMPOUTSEL5 = TAMP_OUT1,1: TAMPOUTSEL5 = TAMP_OUT2,2: TAMPOUTSEL5 = TAMP_OUT3,3: TAMPOUTSEL5 = TAMP_OUT4,4: TAMPOUTSEL5 = TAMP_OUT5,5: TAMPOUTSEL5 = TAMP_OUT6,6: TAMPOUTSEL5 = TAMP_OUT7,7: TAMPOUTSEL5 = TAMP_OUT8" newline bitfld.long 0x0 17.--19. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4,4: TAMPOUTSEL4 = TAMP_OUT5,5: TAMPOUTSEL4 = TAMP_OUT6,6: TAMPOUTSEL4 = TAMP_OUT7,7: TAMPOUTSEL4 = TAMP_OUT8" bitfld.long 0x0 14.--16. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4,4: TAMPOUTSEL3 = TAMP_OUT5,5: TAMPOUTSEL3 = TAMP_OUT6,6: TAMPOUTSEL3 = TAMP_OUT7,7: TAMPOUTSEL3 = TAMP_OUT8" newline bitfld.long 0x0 11.--13. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4,4: TAMPOUTSEL2 = TAMP_OUT5,5: TAMPOUTSEL2 = TAMP_OUT6,6: TAMPOUTSEL2 = TAMP_OUT7,7: TAMPOUTSEL2 = TAMP_OUT8" bitfld.long 0x0 8.--10. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4,4: TAMPOUTSEL1 = TAMP_OUT5,5: TAMPOUTSEL1 = TAMP_OUT6,6: TAMPOUTSEL1 = TAMP_OUT7,7: TAMPOUTSEL1 = TAMP_OUT8" line.long 0x4 "TAMP_SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,Tamper protection (excluding monotonic counters and backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x4 30. "BHKLOCK,Boot hardware key lock" "0: The Backup registers from TAMP_BKP0R to..,1: The backup registers from TAMP_BKP0R to.." newline hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,Backup registers write protection offset" bitfld.long 0x4 15. "CNT1SEC,Monotonic counter 1 secure protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." newline hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,Backup registers read/write protection offset" line.long 0x8 "TAMP_PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,Tamper privilege protection (excluding backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x8 30. "BKPWPRIV,Backup registers zone 2 privilege protection" "0: Backup registers zone 2 can be written with..,1: Backup registers zone 2 can be written only with.." newline bitfld.long 0x8 29. "BKPRWPRIV,Backup registers zone 1 privilege protection" "0: Backup registers zone 1 can be read and written..,1: Backup registers zone 1 can be read and written.." bitfld.long 0x8 15. "CNT1PRIV,Monotonic counter 1 privilege protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." group.long 0x2C++0x3 line.long 0x0 "TAMP_IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,Internal tamper 13 interrupt enable" "0: Internal tamper 13 interrupt disabled.,1: Internal tamper 13 interrupt enabled." bitfld.long 0x0 27. "ITAMP12IE,Internal tamper 12 interrupt enable" "0: Internal tamper 12 interrupt disabled.,1: Internal tamper 12 interrupt enabled." newline bitfld.long 0x0 26. "ITAMP11IE,Internal tamper 11 interrupt enable" "0: Internal tamper 11 interrupt disabled.,1: Internal tamper 11 interrupt enabled." bitfld.long 0x0 24. "ITAMP9IE,Internal tamper 9 interrupt enable" "0: Internal tamper 9 interrupt disabled.,1: Internal tamper 9 interrupt enabled." newline bitfld.long 0x0 23. "ITAMP8IE,Internal tamper 8 interrupt enable" "0: Internal tamper 8 interrupt disabled.,1: Internal tamper 8 interrupt enabled." bitfld.long 0x0 22. "ITAMP7IE,Internal tamper 7 interrupt enable" "0: Internal tamper 7 interrupt disabled.,1: Internal tamper 7 interrupt enabled." newline bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled." bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled." newline bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled." bitfld.long 0x0 17. "ITAMP2IE,Internal tamper 2 interrupt enable" "0: Internal tamper 2 interrupt disabled.,1: Internal tamper 2 interrupt enabled." newline bitfld.long 0x0 16. "ITAMP1IE,Internal tamper 1 interrupt enable" "0: Internal tamper 1 interrupt disabled.,1: Internal tamper 1 interrupt enabled" bitfld.long 0x0 7. "TAMP8IE,Tamper 8 interrupt enable" "0: Tamper 8 interrupt disabled.,1: Tamper 8 interrupt enabled." newline bitfld.long 0x0 6. "TAMP7IE,Tamper 7interrupt enable" "0: Tamper 7 interrupt disabled.,1: Tamper 7interrupt enabled." bitfld.long 0x0 5. "TAMP6IE,Tamper 6 interrupt enable" "0: Tamper 6 interrupt disabled.,1: Tamper 6 interrupt enabled." newline bitfld.long 0x0 4. "TAMP5IE,Tamper 5 interrupt enable" "0: Tamper 5 interrupt disabled.,1: Tamper 5 interrupt enabled." bitfld.long 0x0 3. "TAMP4IE,Tamper 4 interrupt enable" "0: Tamper 4 interrupt disabled.,1: Tamper 4 interrupt enabled." newline bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.." bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled." newline bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled." rgroup.long 0x30++0xB line.long 0x0 "TAMP_SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13F,Internal tamper 13 flag" "0,1" bitfld.long 0x0 27. "ITAMP12F,Internal tamper 12 flag" "0,1" newline bitfld.long 0x0 26. "ITAMP11F,Internal tamper 11 flag" "0,1" bitfld.long 0x0 24. "ITAMP9F,Internal tamper 9 flag" "0,1" newline bitfld.long 0x0 23. "ITAMP8F,Internal tamper 8 flag" "0,1" bitfld.long 0x0 22. "ITAMP7F,Internal tamper 7 flag" "0,1" newline bitfld.long 0x0 21. "ITAMP6F,Internal tamper 6 flag" "0,1" bitfld.long 0x0 20. "ITAMP5F,Internal tamper 5 flag" "0,1" newline bitfld.long 0x0 18. "ITAMP3F,Internal tamper 3 flag" "0,1" bitfld.long 0x0 17. "ITAMP2F,Internal tamper 2 flag" "0,1" newline bitfld.long 0x0 16. "ITAMP1F,Internal tamper 1 flag" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8 detection flag" "0,1" newline bitfld.long 0x0 6. "TAMP7F,TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1" line.long 0x4 "TAMP_MISR,TAMP non-secure masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,internal tamper 13 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 27. "ITAMP12MF,internal tamper 12 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 26. "ITAMP11MF,internal tamper 11 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 24. "ITAMP9MF,internal tamper 9 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 23. "ITAMP8MF,Internal tamper 8 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 22. "ITAMP7MF,VCORE monitoring tamper non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 21. "ITAMP6MF,Internal tamper 6 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 20. "ITAMP5MF,Internal tamper 5 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 18. "ITAMP3MF,Internal tamper 3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 17. "ITAMP2MF,Internal tamper 2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 16. "ITAMP1MF,Internal tamper 1 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 6. "TAMP7MF,TAMP7 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 2. "TAMP3MF,TAMP3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 0. "TAMP1MF,TAMP1 non-secure interrupt masked flag" "0,1" line.long 0x8 "TAMP_SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,internal tamper 13 secure interrupt masked flag" "0,1" bitfld.long 0x8 27. "ITAMP12MF,internal tamper 12 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 26. "ITAMP11MF,internal tamper 11 secure interrupt masked flag" "0,1" bitfld.long 0x8 24. "ITAMP9MF,internal tamper 9 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 23. "ITAMP8MF,Internal tamper 8 secure interrupt masked flag" "0,1" bitfld.long 0x8 22. "ITAMP7MF,VCORE monitoring tamper secure interrupt masked flag" "0,1" newline bitfld.long 0x8 21. "ITAMP6MF,Internal tamper 6 secure interrupt masked flag" "0,1" bitfld.long 0x8 20. "ITAMP5MF,Internal tamper 5 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 18. "ITAMP3MF,Internal tamper 3 secure interrupt masked flag" "0,1" bitfld.long 0x8 17. "ITAMP2MF,Internal tamper 2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 16. "ITAMP1MF,Internal tamper 1 secure interrupt masked flag" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 6. "TAMP7MF,TAMP7 secure interrupt masked flag" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5 secure interrupt masked flag" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 2. "TAMP3MF,TAMP3 secure interrupt masked flag" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 0. "TAMP1MF,TAMP1 secure interrupt masked flag" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "TAMP_SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,Clear ITAMP13 detection flag" "0,1" bitfld.long 0x0 27. "CITAMP12F,Clear ITAMP12 detection flag" "0,1" newline bitfld.long 0x0 26. "CITAMP11F,Clear ITAMP11 detection flag" "0,1" bitfld.long 0x0 24. "CITAMP9F,Clear ITAMP9 detection flag" "0,1" newline bitfld.long 0x0 23. "CITAMP8F,Clear ITAMP8 detection flag" "0,1" bitfld.long 0x0 22. "CITAMP7F,Clear ITAMP7 detection flag" "0,1" newline bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1" bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1" newline bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1" bitfld.long 0x0 17. "CITAMP2F,Clear ITAMP2 detection flag" "0,1" newline bitfld.long 0x0 16. "CITAMP1F,Clear ITAMP1 detection flag" "0,1" bitfld.long 0x0 7. "CTAMP8F,Clear TAMP8 detection flag" "0,1" newline bitfld.long 0x0 6. "CTAMP7F,Clear TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "CTAMP6F,Clear TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,Clear TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "CTAMP4F,Clear TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "TAMP_COUNT1R,TAMP monotonic counter 1 register" hexmask.long 0x0 0.--31. 1. "COUNT,This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value." group.long 0x54++0x3 line.long 0x0 "TAMP_ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,Configurable device secrets configuration" "0: Configurable device secrets are not included in..,1: Configurable device secrets are is included in.." group.long 0x100++0x7F line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register" hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register" hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register" hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0xC "TAMP_BKP3R,TAMP backup 3 register" hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register" hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register" hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register" hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register" hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register" hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x24 "TAMP_BKP9R,TAMP backup 9 register" hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x28 "TAMP_BKP10R,TAMP backup 10 register" hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x2C "TAMP_BKP11R,TAMP backup 11 register" hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x30 "TAMP_BKP12R,TAMP backup 12 register" hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x34 "TAMP_BKP13R,TAMP backup 13 register" hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x38 "TAMP_BKP14R,TAMP backup 14 register" hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x3C "TAMP_BKP15R,TAMP backup 15 register" hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x40 "TAMP_BKP16R,TAMP backup 16 register" hexmask.long 0x40 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x44 "TAMP_BKP17R,TAMP backup 17 register" hexmask.long 0x44 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x48 "TAMP_BKP18R,TAMP backup 18 register" hexmask.long 0x48 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4C "TAMP_BKP19R,TAMP backup 19 register" hexmask.long 0x4C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x50 "TAMP_BKP20R,TAMP backup 20 register" hexmask.long 0x50 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x54 "TAMP_BKP21R,TAMP backup 21 register" hexmask.long 0x54 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x58 "TAMP_BKP22R,TAMP backup 22 register" hexmask.long 0x58 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x5C "TAMP_BKP23R,TAMP backup 23 register" hexmask.long 0x5C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x60 "TAMP_BKP24R,TAMP backup 24 register" hexmask.long 0x60 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x64 "TAMP_BKP25R,TAMP backup 25 register" hexmask.long 0x64 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x68 "TAMP_BKP26R,TAMP backup 26 register" hexmask.long 0x68 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x6C "TAMP_BKP27R,TAMP backup 27 register" hexmask.long 0x6C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x70 "TAMP_BKP28R,TAMP backup 28 register" hexmask.long 0x70 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x74 "TAMP_BKP29R,TAMP backup 29 register" hexmask.long 0x74 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x78 "TAMP_BKP30R,TAMP backup 30 register" hexmask.long 0x78 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x7C "TAMP_BKP31R,TAMP backup 31 register" hexmask.long 0x7C 0.--31. 1. "BKP,The application can write or read data to and from these registers." tree.end endif sif (cpuis("STM32U595*")) tree "TAMP" base ad:0x46007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end tree "SEC_TAMP" base ad:0x56007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end endif sif (cpuis("STM32U599*")) tree "TAMP" base ad:0x46007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end tree "SEC_TAMP" base ad:0x56007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end endif sif (cpuis("STM32U5A5*")) tree "TAMP" base ad:0x46007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end tree "SEC_TAMP" base ad:0x56007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end endif sif (cpuis("STM32U5A9*")) tree "TAMP" base ad:0x46007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end tree "SEC_TAMP" base ad:0x56007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end endif sif (cpuis("STM32U5F*")) tree "TAMP" base ad:0x46007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end tree "SEC_TAMP" base ad:0x56007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end endif sif (cpuis("STM32U5G*")) tree "TAMP" base ad:0x46007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end tree "SEC_TAMP" base ad:0x56007C00 group.long 0x0++0x17 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 28. "ITAMP13E,ITAMP13E" "0,1" bitfld.long 0x0 27. "ITAMP12E,ITAMP12E" "0,1" bitfld.long 0x0 26. "ITAMP11E,TAMP1E" "0,1" bitfld.long 0x0 24. "ITAMP9E,ITAMP9E" "0,1" bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 22. "ITAMP7E,ITAMP7E" "0,1" bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1" newline bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" bitfld.long 0x0 7. "TAMP8E,TAMP8E" "0,1" bitfld.long 0x0 6. "TAMP7E,TAMP7E" "0,1" bitfld.long 0x0 5. "TAMP6E,TAMP6E" "0,1" newline bitfld.long 0x0 4. "TAMP5E,TAMP5E" "0,1" bitfld.long 0x0 3. "TAMP4E,TAMP4E" "0,1" bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 31. "TAMP8TRG,TAMP8TRG" "0,1" bitfld.long 0x4 30. "TAMP7TRG,TAMP7TRG" "0,1" bitfld.long 0x4 29. "TAMP6TRG,TAMP6TRG" "0,1" bitfld.long 0x4 28. "TAMP5TRG,TAMP5TRG" "0,1" bitfld.long 0x4 27. "TAMP4TRG,TAMP4TRG" "0,1" bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" newline bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 23. "BKERASE,BKERASE" "0,1" bitfld.long 0x4 22. "BKBLOCK,BKBLOCK" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" bitfld.long 0x4 7. "TAMP8NOER,TAMP8NOER" "0,1" newline bitfld.long 0x4 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x4 5. "TAMP6NOER,TAMP6NOER" "0,1" bitfld.long 0x4 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x4 3. "TAMP4NOER,TAMP4NOER" "0,1" bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" line.long 0x8 "CR3,control register 3" bitfld.long 0x8 12. "ITAMP13NOER,ITAMP13NOER" "0,1" bitfld.long 0x8 11. "ITAMP12NOER,ITAMP12NOER" "0,1" bitfld.long 0x8 10. "ITAMP11NOER,ITAMP11NOER" "0,1" bitfld.long 0x8 8. "ITAMP9NOER,ITAMP9NOER" "0,1" bitfld.long 0x8 7. "TAMP8NOER,TAMP8NOER" "0,1" bitfld.long 0x8 6. "TAMP7NOER,TAMP7NOER" "0,1" bitfld.long 0x8 5. "TAMP6NOER,TAMP6NOER" "0,1" newline bitfld.long 0x8 4. "TAMP5NOER,TAMP5NOER" "0,1" bitfld.long 0x8 2. "ITAMP3NOER,ITAMP3NOER" "0,1" bitfld.long 0x8 1. "ITAMP2NOER,ITAMP2NOER" "0,1" bitfld.long 0x8 0. "ITAMP1NOER,ITAMP1NOER" "0,1" line.long 0xC "FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0xC 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0xC 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0xC 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x10 "ATCR1,TAMP active tamper control register" bitfld.long 0x10 31. "FLTEN,ATOSHARE" "0,1" bitfld.long 0x10 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x10 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x10 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x10 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x10 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x10 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x10 7. "TAMP8AM,TAMP8AM" "0,1" bitfld.long 0x10 6. "TAMP7AM,TAMP7AM" "0,1" bitfld.long 0x10 5. "TAMP6AM,TAMP6AM" "0,1" bitfld.long 0x10 4. "TAMP5AM,TAMP5AM" "0,1" bitfld.long 0x10 3. "TAMP4AM,TAMP4AM" "0,1" bitfld.long 0x10 2. "TAMP3AM,TAMP3AM" "0,1" newline bitfld.long 0x10 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x10 0. "TAMP1AM,TAMP1AM" "0,1" line.long 0x14 "ATSEEDR,TAMP active tamper seed register" hexmask.long 0x14 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x1C++0xB line.long 0x0 "ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--18. "ATOSEL4,ATOSEL4" "0,1,2,3" bitfld.long 0x0 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7" line.long 0x4 "SECCFGR,TAMP secure mode register" bitfld.long 0x4 31. "TAMPSEC,TAMPSEC" "0,1" bitfld.long 0x4 30. "BHKLOCK,BHKLOCK" "0,1" hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,BKPWSEC" bitfld.long 0x4 15. "CNT1SEC,CNT1SEC" "0,1" hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,BKPRWSEC" line.long 0x8 "PRIVCR,TAMP privilege mode control register" bitfld.long 0x8 31. "TAMPPRIV,TAMPPRIV" "0,1" bitfld.long 0x8 30. "BKPWPRIV,BKPWPRIV" "0,1" bitfld.long 0x8 29. "BKPRWPRIV,BKPRWPRIV" "0,1" bitfld.long 0x8 15. "CNT1PRIV,CNT1PRIV" "0,1" group.long 0x2C++0x3 line.long 0x0 "IER,TAMP interrupt enable register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12IE,ITAMP12IE" "0,1" bitfld.long 0x0 26. "ITAMP11IE,ITAMP11IE" "0,1" bitfld.long 0x0 24. "ITAMP9IE,ITAMP9IE" "0,1" bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 22. "ITAMP7IE,ITAMP7IE" "0,1" bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1" newline bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" bitfld.long 0x0 7. "TAMP8IE,TAMP8IE" "0,1" bitfld.long 0x0 6. "TAMP7IE,TAMP7IE" "0,1" bitfld.long 0x0 5. "TAMP6IE,TAMP6IE" "0,1" newline bitfld.long 0x0 4. "TAMP5IE,TAMP5IE" "0,1" bitfld.long 0x0 3. "TAMP4IE,TAMP4IE" "0,1" bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "SR,TAMP status register" bitfld.long 0x0 28. "ITAMP13IE,ITAMP13IE" "0,1" bitfld.long 0x0 27. "ITAMP12F,ITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "ITAMP9F,ITAMP9F" "0,1" bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1" bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "TAMP8F,TAMP8F" "0,1" bitfld.long 0x0 6. "TAMP7F,TAMP7F" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6F" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5F" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4F" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "MISR,TAMP masked interrupt status register" bitfld.long 0x4 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x4 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x4 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x4 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x4 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x4 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 28. "ITAMP13MF,ITAMP13MF" "0,1" bitfld.long 0x8 27. "ITAMP12MF,ITAMP12MF" "0,1" bitfld.long 0x8 26. "ITAMP11MF,ITAMP11MF" "0,1" bitfld.long 0x8 24. "ITAMP9MF,ITAMP9MF" "0,1" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 22. "ITAMP7MF,ITAMP7MF" "0,1" bitfld.long 0x8 21. "ITAMP6MF,ITAMP6MF" "0,1" newline bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" bitfld.long 0x8 7. "TAMP8MF,TAMP8MF" "0,1" bitfld.long 0x8 6. "TAMP7MF,TAMP7MF" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6MF" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5MF" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4MF" "0,1" bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" group.long 0x3C++0x3 line.long 0x0 "SCR,TAMP status clear register" bitfld.long 0x0 28. "CITAMP13F,CITAMP13F" "0,1" bitfld.long 0x0 27. "CITAMP12F,CITAMP12F" "0,1" bitfld.long 0x0 26. "CITAMP11F,CITAMP11F" "0,1" bitfld.long 0x0 24. "CITAMP9F,CITAMP9F" "0,1" bitfld.long 0x0 23. "CITAMP8F_bit23,CITAMP8F_bit23" "0,1" bitfld.long 0x0 22. "CITAMP7F_bit22,CITAMP7F_bit22" "0,1" bitfld.long 0x0 21. "CITAMP6F_bit21,CITAMP6F_bit21" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" bitfld.long 0x0 7. "CITAMP8F,CITAMP3F" "0,1" bitfld.long 0x0 6. "CITAMP7F,CITAMP3F" "0,1" bitfld.long 0x0 5. "CTAMP6F,CTAMP6F" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,CTAMP5F" "0,1" bitfld.long 0x0 3. "CTAMP4F,CTAMP4F" "0,1" bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "COUNT1R,TAMP monotonic counter 1register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x54++0x3 line.long 0x0 "ERCFGR,TAMP erase configuration register" bitfld.long 0x0 0. "ERCFG0,ERCFG0" "0,1" group.long 0x100++0x7F line.long 0x0 "BKP0R,TAMP backup register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "BKP1R,TAMP backup register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "BKP2R,TAMP backup register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "BKP3R,TAMP backup register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "BKP4R,TAMP backup register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "BKP5R,TAMP backup register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "BKP6R,TAMP backup register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "BKP7R,TAMP backup register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "BKP8R,TAMP backup register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "BKP9R,TAMP backup register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "BKP10R,TAMP backup register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "BKP11R,TAMP backup register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "BKP12R,TAMP backup register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "BKP13R,TAMP backup register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "BKP14R,TAMP backup register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "BKP15R,TAMP backup register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "BKP16R,TAMP backup register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "BKP17R,TAMP backup register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "BKP18R,TAMP backup register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "BKP19R,TAMP backup register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "BKP20R,TAMP backup register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "BKP21R,TAMP backup register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "BKP22R,TAMP backup register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "BKP23R,TAMP backup register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "BKP24R,TAMP backup register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "BKP25R,TAMP backup register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "BKP26R,TAMP backup register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "BKP27R,TAMP backup register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "BKP28R,TAMP backup register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "BKP29R,TAMP backup register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "BKP30R,TAMP backup register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "BKP31R,TAMP backup register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" tree.end endif tree.end tree "TIM (Timers)" base ad:0x0 sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM1 (Advanced Timer)" base ad:0x40012C00 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" newline bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" newline bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" newline bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" newline bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" newline bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" newline bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" newline bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" newline bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" newline bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" newline bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" newline bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" newline bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" newline bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" newline bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" newline bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" newline bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" newline bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" newline bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" newline bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" newline bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" newline bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" newline bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" newline hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" newline bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" newline bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" newline bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" newline hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" newline bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" newline bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" newline bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" newline bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" newline bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" newline bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" newline bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" newline bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" newline bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" newline bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" newline bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" newline bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" endif sif (cpuis("STM32U575*")) group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=ttim_ker_ck,1: tDTS=2*ttim_ker_ck,2: tDTS=4*ttim_ker_ck,3: Reserved do not program this value" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,control register 2" bitfld.long 0x0 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x0 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x0 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x0 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x0 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x0 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x0 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS2,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3)" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter.." newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: 3,5: Filtered Timer Input 1 (tim_ti1fp1),6: 4,7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: When CCPC bit is set it allows to update CCxE.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" endif sif (cpuis("STM32U575*")) group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" endif sif (cpuis("STM32U575*")) group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: the configuration is reserved,1: non-inverted/both edges/ The circuit is.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x1C 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM1 (Advanced Timer)" base ad:0x50012C00 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" newline bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" newline bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" newline bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" newline bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" newline bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" newline bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" newline bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" newline bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" newline bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" newline bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" newline bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" newline bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" newline bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" newline bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" newline bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" newline bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" newline bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" newline bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" newline bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" newline bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" newline bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" newline bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" newline hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" newline bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" newline bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" newline bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" newline hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" newline bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" newline bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" newline bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" newline bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" newline bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" newline bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" newline bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" newline bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" newline bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" newline bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" newline bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" newline bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" endif sif (cpuis("STM32U575*")) group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=ttim_ker_ck,1: tDTS=2*ttim_ker_ck,2: tDTS=4*ttim_ker_ck,3: Reserved do not program this value" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,control register 2" bitfld.long 0x0 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x0 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x0 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x0 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x0 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x0 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x0 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS2,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3)" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter.." newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: 3,5: Filtered Timer Input 1 (tim_ti1fp1),6: 4,7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: When CCPC bit is set it allows to update CCxE.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" endif sif (cpuis("STM32U575*")) group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" endif sif (cpuis("STM32U575*")) group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: the configuration is reserved,1: non-inverted/both edges/ The circuit is.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x1C 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM2 (General-purpose Timer)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" endif bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM2 (General-purpose Timer)" base ad:0x50000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" endif bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM3 (General-purpose Timer)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" endif bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM3 (General-purpose Timer)" base ad:0x50000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" endif bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM4 (General-purpose Timer)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" endif bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM4 (General-purpose Timer)" base ad:0x50000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" endif bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM5 (General-purpose Timer)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" endif bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM5 (General-purpose Timer)" base ad:0x50000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" sif (cpuis("STM32U575*")) bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" endif bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM6 (Basic Timer)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x8 0.--18. 1. "ARR,ARR" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM6 (Basic Timer)" base ad:0x50001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x8 0.--18. 1. "ARR,ARR" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM7 (Basic Timer)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x8 0.--18. 1. "ARR,ARR" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM7 (Basic Timer)" base ad:0x50001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x8 0.--18. 1. "ARR,ARR" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM8 (Advanced Timer)" base ad:0x40013400 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" newline bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" newline bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" newline bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" newline bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" newline bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" newline bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" newline bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" newline bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" newline bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" newline bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" newline bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" newline bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" newline bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" newline bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" newline bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" newline bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" newline bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" newline bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" newline bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" newline bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" newline bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" newline bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" newline hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" newline bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" newline bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" newline bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" newline hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" newline bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" newline bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" newline bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" newline bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" newline bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" newline bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" newline bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" newline bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" newline bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" newline bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" newline bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" newline bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" endif sif (cpuis("STM32U575*")) group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=ttim_ker_ck,1: tDTS=2*ttim_ker_ck,2: tDTS=4*ttim_ker_ck,3: Reserved do not program this value" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,control register 2" bitfld.long 0x0 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x0 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x0 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x0 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x0 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x0 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x0 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS2,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3)" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter.." newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: 3,5: Filtered Timer Input 1 (tim_ti1fp1),6: 4,7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: When CCPC bit is set it allows to update CCxE.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" endif sif (cpuis("STM32U575*")) group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" endif sif (cpuis("STM32U575*")) group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: the configuration is reserved,1: non-inverted/both edges/ The circuit is.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x1C 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM8 (Advanced Timer)" base ad:0x50013400 sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" newline bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" newline bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" newline bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" newline bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" newline bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" newline bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" newline bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" newline bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" newline bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" newline bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" newline bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" newline bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" newline bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" newline bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" newline bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" newline bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" newline bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" newline bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" newline bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" newline bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" newline bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" newline bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" newline hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" newline bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" newline bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" newline bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" newline hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" newline bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" newline bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" newline bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" newline bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" newline bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" newline bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" newline bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" newline bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" newline bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" newline bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" newline bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" newline bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" endif sif (cpuis("STM32U575*")) group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=ttim_ker_ck,1: tDTS=2*ttim_ker_ck,2: tDTS=4*ttim_ker_ck,3: Reserved do not program this value" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,control register 2" bitfld.long 0x0 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x0 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x0 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x0 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x0 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x0 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x0 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS2,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3)" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter.." newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: 3,5: Filtered Timer Input 1 (tim_ti1fp1),6: 4,7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: When CCPC bit is set it allows to update CCxE.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" endif sif (cpuis("STM32U575*")) group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" endif sif (cpuis("STM32U575*")) group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: the configuration is reserved,1: non-inverted/both edges/ The circuit is.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x1C 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" endif tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM15 (General-purpose Timer)" base ad:0x40014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" endif group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM15 (General-purpose Timer)" base ad:0x50014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" endif sif (cpuis("STM32U575*")) hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" endif group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM16 (General-purpose Timer)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x50++0x3 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" endif group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM16 (General-purpose Timer)" base ad:0x50014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x50++0x3 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" endif group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "TIM17 (General-purpose Timer)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x50++0x3 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" endif group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U535*")||cpuis("STM32U545*")||cpuis("STM32U575*")) tree "SEC_TIM17 (General-purpose Timer)" base ad:0x50014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" sif (cpuis("STM32U535*")||cpuis("STM32U545*")) group.long 0x50++0x3 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" endif group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM1 (Advanced Timer)" base ad:0x40012C00 group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=ttim_ker_ck,1: tDTS=2*ttim_ker_ck,2: tDTS=4*ttim_ker_ck,3: Reserved do not program this value" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,control register 2" bitfld.long 0x0 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x0 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x0 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x0 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x0 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x0 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x0 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS2,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3)" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter.." newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: 3,5: Filtered Timer Input 1 (tim_ti1fp1),6: 4,7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: When CCPC bit is set it allows to update CCxE.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: the configuration is reserved,1: non-inverted/both edges/ The circuit is.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x1C 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM1 (Advanced Timer)" base ad:0x50012C00 group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=ttim_ker_ck,1: tDTS=2*ttim_ker_ck,2: tDTS=4*ttim_ker_ck,3: Reserved do not program this value" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,control register 2" bitfld.long 0x0 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x0 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x0 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x0 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x0 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x0 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x0 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS2,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3)" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter.." newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: 3,5: Filtered Timer Input 1 (tim_ti1fp1),6: 4,7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: When CCPC bit is set it allows to update CCxE.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: the configuration is reserved,1: non-inverted/both edges/ The circuit is.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x1C 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM8 (Advanced Timer)" base ad:0x40013400 group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=ttim_ker_ck,1: tDTS=2*ttim_ker_ck,2: tDTS=4*ttim_ker_ck,3: Reserved do not program this value" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,control register 2" bitfld.long 0x0 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x0 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x0 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x0 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x0 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x0 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x0 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS2,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3)" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter.." newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: 3,5: Filtered Timer Input 1 (tim_ti1fp1),6: 4,7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: When CCPC bit is set it allows to update CCxE.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: the configuration is reserved,1: non-inverted/both edges/ The circuit is.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x1C 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM8 (Advanced Timer)" base ad:0x50013400 group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=ttim_ker_ck,1: tDTS=2*ttim_ker_ck,2: tDTS=4*ttim_ker_ck,3: Reserved do not program this value" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,control register 2" bitfld.long 0x0 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" newline bitfld.long 0x0 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x0 16. "OIS5,Output Idle state 5" "0,1" newline bitfld.long 0x0 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x0 8. "OIS1,Output Idle state 1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x0 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x0 2. "CCUS,Capture/compare control update" "0,1" newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS2,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3)" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter.." newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection - bit 4:3" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: 3,5: Filtered Timer Input 1 (tim_ti1fp1),6: 4,7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: When CCPC bit is set it allows to update CCxE.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" newline bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: the configuration is reserved,1: non-inverted/both edges/ The circuit is.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x1C 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM2 (General-purpose Timer)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM2 (General-purpose Timer)" base ad:0x50000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM3 (General-purpose Timer)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM3 (General-purpose Timer)" base ad:0x50000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM4 (General-purpose Timer)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM4 (General-purpose Timer)" base ad:0x50000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM5 (General-purpose Timer)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM5 (General-purpose Timer)" base ad:0x50000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0,1,2,3" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM15 (General-purpose Timer)" base ad:0x40014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM15 (General-purpose Timer)" base ad:0x50014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM16 (General-purpose Timer)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM16 (General-purpose Timer)" base ad:0x50014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM17 (General-purpose Timer)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM17 (General-purpose Timer)" base ad:0x50014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U585*")) tree "TIM6 (Basic Timer)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--18. 1. "ARR,ARR" tree.end tree "SEC_TIM6 (Basic Timer)" base ad:0x50001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--18. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U585*")) tree "TIM7 (Basic Timer)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--18. 1. "ARR,ARR" tree.end tree "SEC_TIM7 (Basic Timer)" base ad:0x50001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--18. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U595*")) tree "TIM1 (Advanced Timer)" base ad:0x40012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM1 (Advanced Timer)" base ad:0x50012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U595*")) tree "TIM2 (General-purpose Timer)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM2 (General-purpose Timer)" base ad:0x50000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U595*")) tree "TIM3 (General-purpose Timer)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM3 (General-purpose Timer)" base ad:0x50000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U595*")) tree "TIM4 (General-purpose Timer)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM4 (General-purpose Timer)" base ad:0x50000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U595*")) tree "TIM5 (General-purpose Timer)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM5 (General-purpose Timer)" base ad:0x50000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U595*")) tree "TIM6 (Basic Timer)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM6 (Basic Timer)" base ad:0x50001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U595*")) tree "TIM7 (Basic Timer)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM7 (Basic Timer)" base ad:0x50001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U595*")) tree "TIM8 (Advanced Timer)" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM8 (Advanced Timer)" base ad:0x50013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U595*")) tree "TIM15 (General-purpose Timer)" base ad:0x40014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM15 (General-purpose Timer)" base ad:0x50014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U595*")) tree "TIM16 (General-purpose Timer)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM16 (General-purpose Timer)" base ad:0x50014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U595*")) tree "TIM17 (General-purpose Timer)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM17 (General-purpose Timer)" base ad:0x50014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U599*")) tree "TIM1 (Advanced Timer)" base ad:0x40012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM1 (Advanced Timer)" base ad:0x50012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U599*")) tree "TIM2 (General-purpose Timer)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM2 (General-purpose Timer)" base ad:0x50000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U599*")) tree "TIM3 (General-purpose Timer)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM3 (General-purpose Timer)" base ad:0x50000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U599*")) tree "TIM4 (General-purpose Timer)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM4 (General-purpose Timer)" base ad:0x50000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U599*")) tree "TIM5 (General-purpose Timer)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM5 (General-purpose Timer)" base ad:0x50000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U599*")) tree "TIM6 (Basic Timer)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM6 (Basic Timer)" base ad:0x50001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U599*")) tree "TIM7 (Basic Timer)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM7 (Basic Timer)" base ad:0x50001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U599*")) tree "TIM8 (Advanced Timer)" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM8 (Advanced Timer)" base ad:0x50013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U599*")) tree "TIM15 (General-purpose Timer)" base ad:0x40014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM15 (General-purpose Timer)" base ad:0x50014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U599*")) tree "TIM16 (General-purpose Timer)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM16 (General-purpose Timer)" base ad:0x50014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U599*")) tree "TIM17 (General-purpose Timer)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM17 (General-purpose Timer)" base ad:0x50014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM1 (Advanced Timer)" base ad:0x40012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM1 (Advanced Timer)" base ad:0x50012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM2 (General-purpose Timer)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM2 (General-purpose Timer)" base ad:0x50000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM3 (General-purpose Timer)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM3 (General-purpose Timer)" base ad:0x50000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM4 (General-purpose Timer)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM4 (General-purpose Timer)" base ad:0x50000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM5 (General-purpose Timer)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM5 (General-purpose Timer)" base ad:0x50000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM6 (Basic Timer)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM6 (Basic Timer)" base ad:0x50001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM7 (Basic Timer)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM7 (Basic Timer)" base ad:0x50001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM8 (Advanced Timer)" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM8 (Advanced Timer)" base ad:0x50013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM15 (General-purpose Timer)" base ad:0x40014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM15 (General-purpose Timer)" base ad:0x50014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM16 (General-purpose Timer)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM16 (General-purpose Timer)" base ad:0x50014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A5*")) tree "TIM17 (General-purpose Timer)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM17 (General-purpose Timer)" base ad:0x50014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM1 (Advanced Timer)" base ad:0x40012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM1 (Advanced Timer)" base ad:0x50012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM2 (General-purpose Timer)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM2 (General-purpose Timer)" base ad:0x50000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM3 (General-purpose Timer)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM3 (General-purpose Timer)" base ad:0x50000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM4 (General-purpose Timer)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM4 (General-purpose Timer)" base ad:0x50000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM5 (General-purpose Timer)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM5 (General-purpose Timer)" base ad:0x50000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM6 (Basic Timer)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM6 (Basic Timer)" base ad:0x50001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM7 (Basic Timer)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM7 (Basic Timer)" base ad:0x50001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM8 (Advanced Timer)" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM8 (Advanced Timer)" base ad:0x50013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM15 (General-purpose Timer)" base ad:0x40014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM15 (General-purpose Timer)" base ad:0x50014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM16 (General-purpose Timer)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM16 (General-purpose Timer)" base ad:0x50014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5A9*")) tree "TIM17 (General-purpose Timer)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM17 (General-purpose Timer)" base ad:0x50014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM1 (Advanced Timer)" base ad:0x40012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM1 (Advanced Timer)" base ad:0x50012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM2 (General-purpose Timer)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM2 (General-purpose Timer)" base ad:0x50000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM3 (General-purpose Timer)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM3 (General-purpose Timer)" base ad:0x50000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM4 (General-purpose Timer)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM4 (General-purpose Timer)" base ad:0x50000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM5 (General-purpose Timer)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM5 (General-purpose Timer)" base ad:0x50000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM6 (Basic Timer)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM6 (Basic Timer)" base ad:0x50001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM7 (Basic Timer)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM7 (Basic Timer)" base ad:0x50001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM8 (Advanced Timer)" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM8 (Advanced Timer)" base ad:0x50013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM15 (General-purpose Timer)" base ad:0x40014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM15 (General-purpose Timer)" base ad:0x50014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM16 (General-purpose Timer)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM16 (General-purpose Timer)" base ad:0x50014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5F*")) tree "TIM17 (General-purpose Timer)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM17 (General-purpose Timer)" base ad:0x50014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM1 (Advanced Timer)" base ad:0x40012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM1 (Advanced Timer)" base ad:0x50012C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM2 (General-purpose Timer)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM2 (General-purpose Timer)" base ad:0x50000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM3 (General-purpose Timer)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM3 (General-purpose Timer)" base ad:0x50000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM4 (General-purpose Timer)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM4 (General-purpose Timer)" base ad:0x50000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM5 (General-purpose Timer)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end tree "SEC_TIM5 (General-purpose Timer)" base ad:0x50000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" newline bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_bit3,Slave mode selection - bit 3" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" newline bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" newline bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" bitfld.long 0x8 31. "CNT_bit31,Most significant bit of counter value" "0,1" hexmask.long.word 0x8 16.--30. 1. "CNT_H,Most significant part counter value (on" hexmask.long.word 0x8 0.--15. 1. "CNT_L,Least significant part of counter" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x58++0xF line.long 0x0 "ECR,DMA address for full transfer" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x0 5. "FIDX,First index" "0,1" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x0 0. "IE,Index enable" "0,1" line.long 0x4 "TISEL,timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[0..15] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[0..15] input" line.long 0x8 "AF1,alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "AF2,alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "ETRSEL,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM6 (Basic Timer)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM6 (Basic Timer)" base ad:0x50001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM7 (Basic Timer)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end tree "SEC_TIM7 (Basic Timer)" base ad:0x50001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,UDE" "0,1" bitfld.long 0x0 0. "UIE,UIE" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,UG" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,PSC" line.long 0x8 "ARR,auto-reload register" hexmask.long.tbyte 0x8 0.--19. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM8 (Advanced Timer)" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end tree "SEC_TIM8 (Advanced Timer)" base ad:0x50013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" newline bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 25. "MMS_3,Master mode selection 2" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" newline bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS0_2,Master mode selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 25. "SMSPS,SMS preload source" "0,1" bitfld.long 0x8 24. "SMSPE,SMS preload enable" "0,1" bitfld.long 0x8 20.--21. "TS4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS3_0,Slave mode selection" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 23. "TERRIE,Transition error interrupt enable" "0,1" bitfld.long 0xC 22. "IERRIE,Index error interrupt enable" "0,1" bitfld.long 0xC 21. "DIRIE,Direction change interrupt enable" "0,1" bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" newline bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 23. "TERRF,Transition error interrupt flag" "0,1" bitfld.long 0x10 22. "IERRF,Index error interrupt flag" "0,1" bitfld.long 0x10 21. "DIRF,Direction change interrupt flag" "0,1" bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" newline bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" newline bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" newline bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)" bitfld.long 0x0 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_bit3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" newline bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_bit3,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output compare 3 mode" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M_3_0,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S_1_0,Capture/Compare 4" "0,1,2,3" newline bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" bitfld.long 0x4 4.--6. "OC3M_2_0,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S_1_0,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x4B line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.tbyte 0x10 0.--19. 1. "ARR,Auto-reload value" line.long 0x14 "RCR,repetition counter register" hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value" line.long 0x18 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x18 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x1C "CCR2,capture/compare register 2" hexmask.long.tbyte 0x1C 0.--19. 1. "CCR2,Capture/Compare 2 value" line.long 0x20 "CCR3,capture/compare register 3" hexmask.long.tbyte 0x20 0.--19. 1. "CCR3,Capture/Compare value" line.long 0x24 "CCR4,capture/compare register 4" hexmask.long.tbyte 0x24 0.--19. 1. "CCR4,Capture/Compare value" line.long 0x28 "BDTR,break and dead-time register" bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x28 27. "BK2DSRAM,Break2 Disarm" "0,1" bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter" newline hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter" bitfld.long 0x28 15. "MOE,Main output enable" "0,1" bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x28 13. "BKP,Break polarity" "0,1" bitfld.long 0x28 12. "BKE,Break enable" "0,1" bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1" newline bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x2C "CCR5,alternate function register 2" bitfld.long 0x2C 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x2C 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x2C 29. "GC5C1,GC5C1" "0,1" hexmask.long.tbyte 0x2C 0.--19. 1. "CCR5,CCR5" line.long 0x30 "CCR6,alternate function register 2" hexmask.long.tbyte 0x30 0.--19. 1. "CCR6,CCR6" line.long 0x34 "CCMR3,capture/compare mode register 3" bitfld.long 0x34 24. "OC6M,Output compare 6 mode" "0,1" bitfld.long 0x34 16. "OC5M2,Output compare 5 mode" "0,1" bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x34 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1" bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1" newline bitfld.long 0x34 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x38 "DTR2,deadtime register 2" bitfld.long 0x38 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x38 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x3C "ECR,encoder control register" bitfld.long 0x3C 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width" bitfld.long 0x3C 6.--7. "IPOS,Index positioning" "0,1,2,3" bitfld.long 0x3C 5. "FIDX,First index" "0,1" bitfld.long 0x3C 1.--2. "IDIR,Index direction" "0,1,2,3" bitfld.long 0x3C 0. "IE,Index enable" "0,1" line.long 0x40 "TISEL,timer input selection register" hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,Selects tim_ti4[0..15] input" hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,Selects tim_ti3[0..15] input" hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,Selects tim_ti3[0..15] input" line.long 0x44 "AF1,alternate function option register 1" hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x44 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x44 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x44 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x44 8. "BKCMP8E,tim_brk_cmp8 enable" "0,1" newline bitfld.long 0x44 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x44 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x44 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x44 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x44 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1" newline bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x48 "AF2,alternate function register 2" bitfld.long 0x48 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" bitfld.long 0x48 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0,1" bitfld.long 0x48 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0,1" bitfld.long 0x48 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0,1" bitfld.long 0x48 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0,1" bitfld.long 0x48 9. "BK2INP,TIMx_BKIN2 input polarity" "0,1" bitfld.long 0x48 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0,1" newline bitfld.long 0x48 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0,1" bitfld.long 0x48 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0,1" bitfld.long 0x48 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0,1" bitfld.long 0x48 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0,1" bitfld.long 0x48 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0,1" bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" newline bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM15 (General-purpose Timer)" base ad:0x40014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM15 (General-purpose Timer)" base ad:0x50014000 group.long 0x0++0x1B line.long 0x0 "CR1,control register 1" bitfld.long 0x0 12. "DITHEN,Dithering enable" "0,1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--5. "MMS,Master mode selection" "0,1,2,3" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection" "0,1" bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x8 7. "MSM,Master/slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" line.long 0x14 "EGR,event generation register" bitfld.long 0x14 7. "BG,Break generation" "0,1" bitfld.long 0x14 6. "TG,Trigger generation" "0,1" bitfld.long 0x14 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x14 2. "CC2G,Capture/Compare 2" "0,1" bitfld.long 0x14 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x14 0. "UG,Update generation" "0,1" line.long 0x18 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x18 24. "OC2M_bit3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x18 16. "OC1M_bit3,Output Compare 1 mode" "0,1" bitfld.long 0x18 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x18 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x18 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x18 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x18 7. "OC1CE,Output compare 1 clear enable" "0,1" bitfld.long 0x18 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x18 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x18 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.tbyte 0x18 0.--19. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "DTR2,timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TISEL,input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[0..15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" newline bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM16 (General-purpose Timer)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM16 (General-purpose Timer)" base ad:0x50014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif sif (cpuis("STM32U5G*")) tree "TIM17 (General-purpose Timer)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "SEC_TIM17 (General-purpose Timer)" base ad:0x50014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.tbyte 0xC 0.--19. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.tbyte 0x14 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x50++0x7 line.long 0x0 "OR1,option register 1" bitfld.long 0x0 0. "HSE32EN,HSE Divided by 32 enable" "0,1" line.long 0x4 "DTR2,timer deadtime register 2" bitfld.long 0x4 17. "DTPE,Deadtime preload enable" "0,1" bitfld.long 0x4 16. "DTAE,Deadtime asymmetric enable" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DTGF,Deadtime asymmetric enable" group.long 0x5C++0xB line.long 0x0 "TISEL,TIM17 option register 1" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[0..15] input" line.long 0x4 "AF1,alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0,1" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0,1" bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0,1" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0,1" bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0,1" bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0,1" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0,1" bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0,1" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0,1" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0,1" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0,1" bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0,1" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0,1" line.long 0x8 "AF2,alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0,1,2,3,4,5,6,7" group.long 0x3DC++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,TIM17 option register 1" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end endif tree.end tree "TSC (Touch Sensing Controller)" base ad:0x0 tree "SEC_TSC" base ad:0x50024000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 28.--31. 1. "CTPH,Charge transfer pulse high" hexmask.long.byte 0x0 24.--27. 1. "CTPL,Charge transfer pulse low" hexmask.long.byte 0x0 17.--23. 1. "SSD,Spread spectrum deviation" bitfld.long 0x0 16. "SSE,Spread spectrum enable" "0,1" bitfld.long 0x0 15. "SSPSC,Spread spectrum prescaler" "0,1" bitfld.long 0x0 12.--14. "PGPSC,pulse generator prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5.--7. "MCV,Max count value" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "IODEF,I/O Default mode" "0,1" bitfld.long 0x0 3. "SYNCPOL,Synchronization pin" "0,1" bitfld.long 0x0 2. "AM,Acquisition mode" "0,1" bitfld.long 0x0 1. "START,Start a new acquisition" "0,1" bitfld.long 0x0 0. "TSCE,Touch sensing controller" "0,1" line.long 0x4 "IER,interrupt enable register" bitfld.long 0x4 1. "MCEIE,Max count error interrupt" "0,1" bitfld.long 0x4 0. "EOAIE,End of acquisition interrupt" "0,1" line.long 0x8 "ICR,interrupt clear register" bitfld.long 0x8 1. "MCEIC,Max count error interrupt" "0,1" bitfld.long 0x8 0. "EOAIC,End of acquisition interrupt" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 1. "MCEF,Max count error flag" "0,1" bitfld.long 0x0 0. "EOAF,End of acquisition flag" "0,1" group.long 0x10++0x3 line.long 0x0 "IOHCR,I/O hysteresis control" bitfld.long 0x0 31. "G8_IO4,G8_IO4" "0,1" bitfld.long 0x0 30. "G8_IO3,G8_IO3" "0,1" bitfld.long 0x0 29. "G8_IO2,G8_IO2" "0,1" bitfld.long 0x0 28. "G8_IO1,G8_IO1" "0,1" bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1" bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1" bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1" bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1" bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1" bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1" bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1" bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1" newline bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1" bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1" bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1" bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1" bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1" bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1" bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1" bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1" bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1" bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1" bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1" bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1" newline bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1" bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1" bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1" bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1" bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1" bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1" bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1" bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1" group.long 0x18++0x3 line.long 0x0 "IOASCR,I/O analog switch control" bitfld.long 0x0 31. "G8_IO4,G8_IO4" "0,1" bitfld.long 0x0 30. "G8_IO3,G8_IO3" "0,1" bitfld.long 0x0 29. "G8_IO2,G8_IO2" "0,1" bitfld.long 0x0 28. "G8_IO1,G8_IO1" "0,1" bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1" bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1" bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1" bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1" bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1" bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1" bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1" bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1" newline bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1" bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1" bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1" bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1" bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1" bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1" bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1" bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1" bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1" bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1" bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1" bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1" newline bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1" bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1" bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1" bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1" bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1" bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1" bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1" bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1" group.long 0x20++0x3 line.long 0x0 "IOSCR,I/O sampling control register" bitfld.long 0x0 31. "G8_IO4,G8_IO4" "0,1" bitfld.long 0x0 30. "G8_IO3,G8_IO3" "0,1" bitfld.long 0x0 29. "G8_IO2,G8_IO2" "0,1" bitfld.long 0x0 28. "G8_IO1,G8_IO1" "0,1" bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1" bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1" bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1" bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1" bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1" bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1" bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1" bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1" newline bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1" bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1" bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1" bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1" bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1" bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1" bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1" bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1" bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1" bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1" bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1" bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1" newline bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1" bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1" bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1" bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1" bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1" bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1" bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1" bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1" group.long 0x28++0x3 line.long 0x0 "IOCCR,I/O channel control register" bitfld.long 0x0 31. "G8_IO4,G8_IO4" "0,1" bitfld.long 0x0 30. "G8_IO3,G8_IO3" "0,1" bitfld.long 0x0 29. "G8_IO2,G8_IO2" "0,1" bitfld.long 0x0 28. "G8_IO1,G8_IO1" "0,1" bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1" bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1" bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1" bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1" bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1" bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1" bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1" bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1" newline bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1" bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1" bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1" bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1" bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1" bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1" bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1" bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1" bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1" bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1" bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1" bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1" newline bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1" bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1" bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1" bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1" bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1" bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1" bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1" bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1" group.long 0x30++0x3 line.long 0x0 "IOGCSR,I/O group control status" rbitfld.long 0x0 23. "G8S,Analog I/O group x status" "0,1" rbitfld.long 0x0 22. "G7S,Analog I/O group x status" "0,1" rbitfld.long 0x0 21. "G6S,Analog I/O group x status" "0,1" rbitfld.long 0x0 20. "G5S,Analog I/O group x status" "0,1" rbitfld.long 0x0 19. "G4S,Analog I/O group x status" "0,1" rbitfld.long 0x0 18. "G3S,Analog I/O group x status" "0,1" rbitfld.long 0x0 17. "G2S,Analog I/O group x status" "0,1" rbitfld.long 0x0 16. "G1S,Analog I/O group x status" "0,1" bitfld.long 0x0 7. "G8E,Analog I/O group x enable" "0,1" bitfld.long 0x0 6. "G7E,Analog I/O group x enable" "0,1" bitfld.long 0x0 5. "G6E,Analog I/O group x enable" "0,1" bitfld.long 0x0 4. "G5E,Analog I/O group x enable" "0,1" newline bitfld.long 0x0 3. "G4E,Analog I/O group x enable" "0,1" bitfld.long 0x0 2. "G3E,Analog I/O group x enable" "0,1" bitfld.long 0x0 1. "G2E,Analog I/O group x enable" "0,1" bitfld.long 0x0 0. "G1E,Analog I/O group x enable" "0,1" rgroup.long 0x34++0x1F line.long 0x0 "IOG1CR,I/O group x counter register" hexmask.long.word 0x0 0.--13. 1. "CNT,Counter value" line.long 0x4 "IOG2CR,I/O group x counter register" hexmask.long.word 0x4 0.--13. 1. "CNT,Counter value" line.long 0x8 "IOG3CR,I/O group x counter register" hexmask.long.word 0x8 0.--13. 1. "CNT,Counter value" line.long 0xC "IOG4CR,I/O group x counter register" hexmask.long.word 0xC 0.--13. 1. "CNT,Counter value" line.long 0x10 "IOG5CR,I/O group x counter register" hexmask.long.word 0x10 0.--13. 1. "CNT,Counter value" line.long 0x14 "IOG6CR,I/O group x counter register" hexmask.long.word 0x14 0.--13. 1. "CNT,Counter value" line.long 0x18 "IOG7CR,I/O group x counter register" hexmask.long.word 0x18 0.--13. 1. "CNT,Counter value" line.long 0x1C "IOG8CR,I/O group x counter register" hexmask.long.word 0x1C 0.--13. 1. "CNT,Counter value" tree.end tree "TSC" base ad:0x40024000 group.long 0x0++0xB line.long 0x0 "CR,control register" hexmask.long.byte 0x0 28.--31. 1. "CTPH,Charge transfer pulse high" hexmask.long.byte 0x0 24.--27. 1. "CTPL,Charge transfer pulse low" hexmask.long.byte 0x0 17.--23. 1. "SSD,Spread spectrum deviation" bitfld.long 0x0 16. "SSE,Spread spectrum enable" "0,1" bitfld.long 0x0 15. "SSPSC,Spread spectrum prescaler" "0,1" bitfld.long 0x0 12.--14. "PGPSC,pulse generator prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5.--7. "MCV,Max count value" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "IODEF,I/O Default mode" "0,1" bitfld.long 0x0 3. "SYNCPOL,Synchronization pin" "0,1" bitfld.long 0x0 2. "AM,Acquisition mode" "0,1" bitfld.long 0x0 1. "START,Start a new acquisition" "0,1" bitfld.long 0x0 0. "TSCE,Touch sensing controller" "0,1" line.long 0x4 "IER,interrupt enable register" bitfld.long 0x4 1. "MCEIE,Max count error interrupt" "0,1" bitfld.long 0x4 0. "EOAIE,End of acquisition interrupt" "0,1" line.long 0x8 "ICR,interrupt clear register" bitfld.long 0x8 1. "MCEIC,Max count error interrupt" "0,1" bitfld.long 0x8 0. "EOAIC,End of acquisition interrupt" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "ISR,interrupt status register" bitfld.long 0x0 1. "MCEF,Max count error flag" "0,1" bitfld.long 0x0 0. "EOAF,End of acquisition flag" "0,1" group.long 0x10++0x3 line.long 0x0 "IOHCR,I/O hysteresis control" bitfld.long 0x0 31. "G8_IO4,G8_IO4" "0,1" bitfld.long 0x0 30. "G8_IO3,G8_IO3" "0,1" bitfld.long 0x0 29. "G8_IO2,G8_IO2" "0,1" bitfld.long 0x0 28. "G8_IO1,G8_IO1" "0,1" bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1" bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1" bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1" bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1" bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1" bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1" bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1" bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1" newline bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1" bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1" bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1" bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1" bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1" bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1" bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1" bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1" bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1" bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1" bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1" bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1" newline bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1" bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1" bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1" bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1" bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1" bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1" bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1" bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1" group.long 0x18++0x3 line.long 0x0 "IOASCR,I/O analog switch control" bitfld.long 0x0 31. "G8_IO4,G8_IO4" "0,1" bitfld.long 0x0 30. "G8_IO3,G8_IO3" "0,1" bitfld.long 0x0 29. "G8_IO2,G8_IO2" "0,1" bitfld.long 0x0 28. "G8_IO1,G8_IO1" "0,1" bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1" bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1" bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1" bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1" bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1" bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1" bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1" bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1" newline bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1" bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1" bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1" bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1" bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1" bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1" bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1" bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1" bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1" bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1" bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1" bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1" newline bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1" bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1" bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1" bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1" bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1" bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1" bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1" bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1" group.long 0x20++0x3 line.long 0x0 "IOSCR,I/O sampling control register" bitfld.long 0x0 31. "G8_IO4,G8_IO4" "0,1" bitfld.long 0x0 30. "G8_IO3,G8_IO3" "0,1" bitfld.long 0x0 29. "G8_IO2,G8_IO2" "0,1" bitfld.long 0x0 28. "G8_IO1,G8_IO1" "0,1" bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1" bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1" bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1" bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1" bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1" bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1" bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1" bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1" newline bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1" bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1" bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1" bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1" bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1" bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1" bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1" bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1" bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1" bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1" bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1" bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1" newline bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1" bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1" bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1" bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1" bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1" bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1" bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1" bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1" group.long 0x28++0x3 line.long 0x0 "IOCCR,I/O channel control register" bitfld.long 0x0 31. "G8_IO4,G8_IO4" "0,1" bitfld.long 0x0 30. "G8_IO3,G8_IO3" "0,1" bitfld.long 0x0 29. "G8_IO2,G8_IO2" "0,1" bitfld.long 0x0 28. "G8_IO1,G8_IO1" "0,1" bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1" bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1" bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1" bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1" bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1" bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1" bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1" bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1" newline bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1" bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1" bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1" bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1" bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1" bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1" bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1" bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1" bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1" bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1" bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1" bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1" newline bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1" bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1" bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1" bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1" bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1" bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1" bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1" bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1" group.long 0x30++0x3 line.long 0x0 "IOGCSR,I/O group control status" rbitfld.long 0x0 23. "G8S,Analog I/O group x status" "0,1" rbitfld.long 0x0 22. "G7S,Analog I/O group x status" "0,1" rbitfld.long 0x0 21. "G6S,Analog I/O group x status" "0,1" rbitfld.long 0x0 20. "G5S,Analog I/O group x status" "0,1" rbitfld.long 0x0 19. "G4S,Analog I/O group x status" "0,1" rbitfld.long 0x0 18. "G3S,Analog I/O group x status" "0,1" rbitfld.long 0x0 17. "G2S,Analog I/O group x status" "0,1" rbitfld.long 0x0 16. "G1S,Analog I/O group x status" "0,1" bitfld.long 0x0 7. "G8E,Analog I/O group x enable" "0,1" bitfld.long 0x0 6. "G7E,Analog I/O group x enable" "0,1" bitfld.long 0x0 5. "G6E,Analog I/O group x enable" "0,1" bitfld.long 0x0 4. "G5E,Analog I/O group x enable" "0,1" newline bitfld.long 0x0 3. "G4E,Analog I/O group x enable" "0,1" bitfld.long 0x0 2. "G3E,Analog I/O group x enable" "0,1" bitfld.long 0x0 1. "G2E,Analog I/O group x enable" "0,1" bitfld.long 0x0 0. "G1E,Analog I/O group x enable" "0,1" rgroup.long 0x34++0x1F line.long 0x0 "IOG1CR,I/O group x counter register" hexmask.long.word 0x0 0.--13. 1. "CNT,Counter value" line.long 0x4 "IOG2CR,I/O group x counter register" hexmask.long.word 0x4 0.--13. 1. "CNT,Counter value" line.long 0x8 "IOG3CR,I/O group x counter register" hexmask.long.word 0x8 0.--13. 1. "CNT,Counter value" line.long 0xC "IOG4CR,I/O group x counter register" hexmask.long.word 0xC 0.--13. 1. "CNT,Counter value" line.long 0x10 "IOG5CR,I/O group x counter register" hexmask.long.word 0x10 0.--13. 1. "CNT,Counter value" line.long 0x14 "IOG6CR,I/O group x counter register" hexmask.long.word 0x14 0.--13. 1. "CNT,Counter value" line.long 0x18 "IOG7CR,I/O group x counter register" hexmask.long.word 0x18 0.--13. 1. "CNT,Counter value" line.long 0x1C "IOG8CR,I/O group x counter register" hexmask.long.word 0x1C 0.--13. 1. "CNT,Counter value" tree.end tree.end sif (cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U595*")||cpuis("STM32U599*")||cpuis("STM32U5A5*")||cpuis("STM32U5A9*")||cpuis("STM32U5F*")||cpuis("STM32U5G*")) tree "UCPD (USB Type-C/USB Power Delivery Controller)" base ad:0x0 sif (cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U595*")) tree "UCPD1" base ad:0x4000DC00 sif (cpuis("STM32U575*")||cpuis("STM32U585*")) group.long 0x0++0x13 line.long 0x0 "UCPD_CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPD peripheral enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "RXDMAEN,Reception DMA mode enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "TXDMAEN,Transmission DMA mode enable" "0: Disable,1: Enable" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,Receiver ordered set enable" newline bitfld.long 0x0 17.--19. "PSC_USBPDCLK,Pre-scaler division ratio for generating ucpd_clk" "0: 1 (bypass),1: 2,2: 4,3: 8,4: 16,?,?,?" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,Transition window duration" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,Division ratio for producing inter-frame gap timer clock" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,Division ratio for producing half-bit clock" line.long 0x4 "UCPD_CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,Wakeup from Stop mode enable" "0: Disable,1: Enable" bitfld.long 0x4 2. "FORCECLK,Force ClkReq clock request" "0: Do not force clock request,1: Force clock request" newline bitfld.long 0x4 1. "RXFILT2N3,BMC decoder Rx pre-filter sampling method" "0: 3 samples,1: 2 samples" bitfld.long 0x4 0. "RXFILTDIS,BMC decoder Rx pre-filter enable" "0: Enable,1: Disable" line.long 0x8 "UCPD_CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,SW trim value for Iref on the CC2 line" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,SW trim value for RPD resistors on the CC2 line" newline hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,SW trim value for Iref on the CC1 line" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,SW trim value for RPD resistors on the CC1 line" line.long 0xC "UCPD_CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2 Type-C detector disable" "0: Enable,1: Disable" bitfld.long 0xC 20. "CC1TCDIS,CC1 Type-C detector disable" "0: Enable,1: Disable" newline bitfld.long 0xC 18. "RDCH,Rdch condition drive" "0: No effect,1: Rdch condition drive" bitfld.long 0xC 17. "FRSTX,FRS Tx signaling enable." "0: No effect,1: Enable" newline bitfld.long 0xC 16. "FRSRXEN,FRS event detection enable" "0: Disable,1: Enable" bitfld.long 0xC 14. "CC2VCONNEN,VCONN switch enable for CC2" "0: Disable,1: Enable" newline bitfld.long 0xC 13. "CC1VCONNEN,VCONN switch enable for CC1" "0: Disable,1: Enable" bitfld.long 0xC 10.--11. "CCENABLE,CC line enable" "0: Disable both PHYs,1: Enable CC1 PHY,2: Enable CC2 PHY,3: Enable CC1 and CC2 PHY" newline bitfld.long 0xC 9. "ANAMODE,Analog PHY operating mode" "0: Source,1: Sink" bitfld.long 0xC 7.--8. "ANASUBMODE,Analog PHY sub-mode" "0,1,2,3" newline bitfld.long 0xC 6. "PHYCCSEL,CC1/CC2 line selector for USB Power Delivery signaling" "0: Use CC1 IO for Power Delivery communication,1: Use CC2 IO for Power Delivery communication" bitfld.long 0xC 5. "PHYRXEN,USB Power Delivery receiver enable" "0: Disable,1: Enable" newline bitfld.long 0xC 4. "RXMODE,Receiver mode" "0: Normal receive mode,1: BIST receive mode (BIST test data mode)" bitfld.long 0xC 3. "TXHRST,Command to send a Tx Hard Reset" "0: No effect,1: Start Tx Hard Reset message" newline bitfld.long 0xC 2. "TXSEND,Command to send a Tx packet" "0: No effect,1: Start Tx packet transmission" bitfld.long 0xC 0.--1. "TXMODE,Type of Tx packet" "0: Transmission of Tx packet previously defined in..,1: Cable Reset sequence,2: BIST test sequence (BIST Carrier Mode 2),?" line.long 0x10 "UCPD_IMR,UCPD interrupt mask register" rbitfld.long 0x10 20. "FRSEVTIE,FRSEVT interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2 interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1 interrupt enable" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGEND interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 11. "RXOVRIE,RXOVR interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDET interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDET interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 8. "RXNEIE,RXNE interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 6. "TXUNDIE,TXUND interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENT interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISC interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABT interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENT interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISC interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 0. "TXISIE,TXIS interrupt enable" "0: Disable,1: Enable" rgroup.long 0x14++0x3 line.long 0x0 "UCPD_SR,UCPD status register" bitfld.long 0x0 20. "FRSEVT,FRS detection event" "0: No new event,1: New FRS receive event occurred" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,CC2 line voltage level" "0: Lowest,1: Low,2: High,3: Highest" newline bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,The status bitfield indicates the voltage level on the CC1 line in its steady state." "0: Lowest,1: Low,2: High,3: Highest" bitfld.long 0x0 15. "TYPECEVT2,Type-C voltage level event on CC2 line" "0: No new event,1: A new Type-C event" newline bitfld.long 0x0 14. "TYPECEVT1,Type-C voltage level event on CC1 line" "0: No new event,1: A new Type-C event" bitfld.long 0x0 13. "RXERR,Receive message error" "0: No error detected,1: Error(s) detected" newline bitfld.long 0x0 12. "RXMSGEND,Rx message received" "0: No new Rx message received,1: A new Rx message received" bitfld.long 0x0 11. "RXOVR,Rx data overflow detection" "0: No overflow,1: Overflow" newline bitfld.long 0x0 10. "RXHRSTDET,Rx Hard Reset receipt detection" "0: Hard Reset not received,1: Hard Reset received" bitfld.long 0x0 9. "RXORDDET,Rx ordered set (4 K-codes) detection" "0: No ordered set detected,1: A new ordered set detected" newline bitfld.long 0x0 8. "RXNE,Receive data register not empty detection" "0: Rx data register empty,1: Rx data register not empty" bitfld.long 0x0 6. "TXUND,Tx data underrun detection" "0: No Tx data underrun detected,1: Tx data underrun detected" newline bitfld.long 0x0 5. "HRSTSENT,Hard Reset message sent" "0: No Hard Reset message sent,1: Hard Reset message sent" bitfld.long 0x0 4. "HRSTDISC,Hard Reset discarded" "0: No Hard Reset discarded,1: Hard Reset discarded" newline bitfld.long 0x0 3. "TXMSGABT,Transmit message abort" "0: No transmit message abort,1: Transmit message abort" bitfld.long 0x0 2. "TXMSGSENT,Message transmission completed" "0: No Tx message completed,1: Tx message completed" newline bitfld.long 0x0 1. "TXMSGDISC,Message transmission discarded" "0: No Tx message discarded,1: Tx message discarded" bitfld.long 0x0 0. "TXIS,Transmit interrupt status" "0: New Tx data write not required,1: New Tx data write required" wgroup.long 0x18++0x3 line.long 0x0 "UCPD_ICR,UCPD interrupt clear register" bitfld.long 0x0 20. "FRSEVTCF,FRS event flag (FRSEVT) clear" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,Type-C CC2 line event flag (TYPECEVT2) clear" "0,1" newline bitfld.long 0x0 14. "TYPECEVT1CF,Type-C CC1 event flag (TYPECEVT1) clear" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,Rx message received flag (RXMSGEND) clear" "0,1" newline bitfld.long 0x0 11. "RXOVRCF,Rx overflow flag (RXOVR) clear" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,Rx Hard Reset detect flag (RXHRSTDET) clear" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,Rx ordered set detect flag (RXORDDET) clear" "0,1" bitfld.long 0x0 6. "TXUNDCF,Tx underflow flag (TXUND) clear" "0,1" newline bitfld.long 0x0 5. "HRSTSENTCF,Hard reset send flag (HRSTSENT) clear" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,Hard reset discard flag (HRSTDISC) clear" "0,1" newline bitfld.long 0x0 3. "TXMSGABTCF,Tx message abort flag (TXMSGABT) clear" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,Tx message send flag (TXMSGSENT) clear" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,Tx message discard flag (TXMSGDISC) clear" "0,1" group.long 0x1C++0xB line.long 0x0 "UCPD_TX_ORDSETR,UCPD Tx ordered set type register" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,Ordered set to transmit" line.long 0x4 "UCPD_TX_PAYSZR,UCPD Tx payload size register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,Payload size yet to transmit" line.long 0x8 "UCPD_TXDR,UCPD Tx data register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,Data byte to transmit" rgroup.long 0x28++0xB line.long 0x0 "UCPD_RX_ORDSETR," bitfld.long 0x0 4.--6. "RXSOPKINVALID,The bitfield is for debug purposes only." "0: No K-code corrupted,1: First K-code corrupted,2: Second K-code corrupted,3: Third K-code corrupted,4: Fourth K-code corrupted,?,?,?" bitfld.long 0x0 3. "RXSOP3OF4,The bit indicates the number of correct K-codes. For debug purposes only." "0: 4 correct K-codes out of 4-,1: 3 correct K-codes out of 3-" newline bitfld.long 0x0 0.--2. "RXORDSET,Rx ordered set code detected" "0: SOP code detected in receiver,1: SOP' code detected in receiver,2: SOP'' code detected in receiver,3: SOP'_Debug detected in receiver,4: SOP''_Debug detected in receiver,5: Cable Reset detected in receiver,6: SOP extension#1 detected in receiver,7: SOP extension#2 detected in receiver" line.long 0x4 "UCPD_RX_PAYSZR," hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,Rx payload size received" line.long 0x8 "UCPD_RXDR," hexmask.long.byte 0x8 0.--7. 1. "RXDATA,Data byte received" group.long 0x34++0x7 line.long 0x0 "UCPD_RX_ORDEXTR1,UCPD Rx ordered set extension register 1" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,Ordered set 1 received" line.long 0x4 "UCPD_RX_ORDEXTR2,UCPD Rx ordered set extension register 2" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,Ordered set 2 received" endif sif (cpuis("STM32U595*")) group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" newline bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" newline bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" newline bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" newline hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" newline bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" newline bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" newline bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" newline bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" newline bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" newline bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" newline bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" newline bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" newline bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" newline bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" newline bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" newline bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" newline bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" newline bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" newline bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" newline bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" newline bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" newline bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" newline bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" newline bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" endif tree.end endif sif (cpuis("STM32U575*")||cpuis("STM32U585*")||cpuis("STM32U595*")) tree "SEC_UCPD1" base ad:0x5000DC00 sif (cpuis("STM32U575*")||cpuis("STM32U585*")) group.long 0x0++0x13 line.long 0x0 "UCPD_CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPD peripheral enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "RXDMAEN,Reception DMA mode enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "TXDMAEN,Transmission DMA mode enable" "0: Disable,1: Enable" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,Receiver ordered set enable" newline bitfld.long 0x0 17.--19. "PSC_USBPDCLK,Pre-scaler division ratio for generating ucpd_clk" "0: 1 (bypass),1: 2,2: 4,3: 8,4: 16,?,?,?" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,Transition window duration" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,Division ratio for producing inter-frame gap timer clock" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,Division ratio for producing half-bit clock" line.long 0x4 "UCPD_CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,Wakeup from Stop mode enable" "0: Disable,1: Enable" bitfld.long 0x4 2. "FORCECLK,Force ClkReq clock request" "0: Do not force clock request,1: Force clock request" newline bitfld.long 0x4 1. "RXFILT2N3,BMC decoder Rx pre-filter sampling method" "0: 3 samples,1: 2 samples" bitfld.long 0x4 0. "RXFILTDIS,BMC decoder Rx pre-filter enable" "0: Enable,1: Disable" line.long 0x8 "UCPD_CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,SW trim value for Iref on the CC2 line" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,SW trim value for RPD resistors on the CC2 line" newline hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,SW trim value for Iref on the CC1 line" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,SW trim value for RPD resistors on the CC1 line" line.long 0xC "UCPD_CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2 Type-C detector disable" "0: Enable,1: Disable" bitfld.long 0xC 20. "CC1TCDIS,CC1 Type-C detector disable" "0: Enable,1: Disable" newline bitfld.long 0xC 18. "RDCH,Rdch condition drive" "0: No effect,1: Rdch condition drive" bitfld.long 0xC 17. "FRSTX,FRS Tx signaling enable." "0: No effect,1: Enable" newline bitfld.long 0xC 16. "FRSRXEN,FRS event detection enable" "0: Disable,1: Enable" bitfld.long 0xC 14. "CC2VCONNEN,VCONN switch enable for CC2" "0: Disable,1: Enable" newline bitfld.long 0xC 13. "CC1VCONNEN,VCONN switch enable for CC1" "0: Disable,1: Enable" bitfld.long 0xC 10.--11. "CCENABLE,CC line enable" "0: Disable both PHYs,1: Enable CC1 PHY,2: Enable CC2 PHY,3: Enable CC1 and CC2 PHY" newline bitfld.long 0xC 9. "ANAMODE,Analog PHY operating mode" "0: Source,1: Sink" bitfld.long 0xC 7.--8. "ANASUBMODE,Analog PHY sub-mode" "0,1,2,3" newline bitfld.long 0xC 6. "PHYCCSEL,CC1/CC2 line selector for USB Power Delivery signaling" "0: Use CC1 IO for Power Delivery communication,1: Use CC2 IO for Power Delivery communication" bitfld.long 0xC 5. "PHYRXEN,USB Power Delivery receiver enable" "0: Disable,1: Enable" newline bitfld.long 0xC 4. "RXMODE,Receiver mode" "0: Normal receive mode,1: BIST receive mode (BIST test data mode)" bitfld.long 0xC 3. "TXHRST,Command to send a Tx Hard Reset" "0: No effect,1: Start Tx Hard Reset message" newline bitfld.long 0xC 2. "TXSEND,Command to send a Tx packet" "0: No effect,1: Start Tx packet transmission" bitfld.long 0xC 0.--1. "TXMODE,Type of Tx packet" "0: Transmission of Tx packet previously defined in..,1: Cable Reset sequence,2: BIST test sequence (BIST Carrier Mode 2),?" line.long 0x10 "UCPD_IMR,UCPD interrupt mask register" rbitfld.long 0x10 20. "FRSEVTIE,FRSEVT interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2 interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1 interrupt enable" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGEND interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 11. "RXOVRIE,RXOVR interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDET interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDET interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 8. "RXNEIE,RXNE interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 6. "TXUNDIE,TXUND interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENT interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISC interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABT interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENT interrupt enable" "0: Disable,1: Enable" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISC interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x10 0. "TXISIE,TXIS interrupt enable" "0: Disable,1: Enable" rgroup.long 0x14++0x3 line.long 0x0 "UCPD_SR,UCPD status register" bitfld.long 0x0 20. "FRSEVT,FRS detection event" "0: No new event,1: New FRS receive event occurred" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,CC2 line voltage level" "0: Lowest,1: Low,2: High,3: Highest" newline bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,The status bitfield indicates the voltage level on the CC1 line in its steady state." "0: Lowest,1: Low,2: High,3: Highest" bitfld.long 0x0 15. "TYPECEVT2,Type-C voltage level event on CC2 line" "0: No new event,1: A new Type-C event" newline bitfld.long 0x0 14. "TYPECEVT1,Type-C voltage level event on CC1 line" "0: No new event,1: A new Type-C event" bitfld.long 0x0 13. "RXERR,Receive message error" "0: No error detected,1: Error(s) detected" newline bitfld.long 0x0 12. "RXMSGEND,Rx message received" "0: No new Rx message received,1: A new Rx message received" bitfld.long 0x0 11. "RXOVR,Rx data overflow detection" "0: No overflow,1: Overflow" newline bitfld.long 0x0 10. "RXHRSTDET,Rx Hard Reset receipt detection" "0: Hard Reset not received,1: Hard Reset received" bitfld.long 0x0 9. "RXORDDET,Rx ordered set (4 K-codes) detection" "0: No ordered set detected,1: A new ordered set detected" newline bitfld.long 0x0 8. "RXNE,Receive data register not empty detection" "0: Rx data register empty,1: Rx data register not empty" bitfld.long 0x0 6. "TXUND,Tx data underrun detection" "0: No Tx data underrun detected,1: Tx data underrun detected" newline bitfld.long 0x0 5. "HRSTSENT,Hard Reset message sent" "0: No Hard Reset message sent,1: Hard Reset message sent" bitfld.long 0x0 4. "HRSTDISC,Hard Reset discarded" "0: No Hard Reset discarded,1: Hard Reset discarded" newline bitfld.long 0x0 3. "TXMSGABT,Transmit message abort" "0: No transmit message abort,1: Transmit message abort" bitfld.long 0x0 2. "TXMSGSENT,Message transmission completed" "0: No Tx message completed,1: Tx message completed" newline bitfld.long 0x0 1. "TXMSGDISC,Message transmission discarded" "0: No Tx message discarded,1: Tx message discarded" bitfld.long 0x0 0. "TXIS,Transmit interrupt status" "0: New Tx data write not required,1: New Tx data write required" wgroup.long 0x18++0x3 line.long 0x0 "UCPD_ICR,UCPD interrupt clear register" bitfld.long 0x0 20. "FRSEVTCF,FRS event flag (FRSEVT) clear" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,Type-C CC2 line event flag (TYPECEVT2) clear" "0,1" newline bitfld.long 0x0 14. "TYPECEVT1CF,Type-C CC1 event flag (TYPECEVT1) clear" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,Rx message received flag (RXMSGEND) clear" "0,1" newline bitfld.long 0x0 11. "RXOVRCF,Rx overflow flag (RXOVR) clear" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,Rx Hard Reset detect flag (RXHRSTDET) clear" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,Rx ordered set detect flag (RXORDDET) clear" "0,1" bitfld.long 0x0 6. "TXUNDCF,Tx underflow flag (TXUND) clear" "0,1" newline bitfld.long 0x0 5. "HRSTSENTCF,Hard reset send flag (HRSTSENT) clear" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,Hard reset discard flag (HRSTDISC) clear" "0,1" newline bitfld.long 0x0 3. "TXMSGABTCF,Tx message abort flag (TXMSGABT) clear" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,Tx message send flag (TXMSGSENT) clear" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,Tx message discard flag (TXMSGDISC) clear" "0,1" group.long 0x1C++0xB line.long 0x0 "UCPD_TX_ORDSETR,UCPD Tx ordered set type register" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,Ordered set to transmit" line.long 0x4 "UCPD_TX_PAYSZR,UCPD Tx payload size register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,Payload size yet to transmit" line.long 0x8 "UCPD_TXDR,UCPD Tx data register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,Data byte to transmit" rgroup.long 0x28++0xB line.long 0x0 "UCPD_RX_ORDSETR," bitfld.long 0x0 4.--6. "RXSOPKINVALID,The bitfield is for debug purposes only." "0: No K-code corrupted,1: First K-code corrupted,2: Second K-code corrupted,3: Third K-code corrupted,4: Fourth K-code corrupted,?,?,?" bitfld.long 0x0 3. "RXSOP3OF4,The bit indicates the number of correct K-codes. For debug purposes only." "0: 4 correct K-codes out of 4-,1: 3 correct K-codes out of 3-" newline bitfld.long 0x0 0.--2. "RXORDSET,Rx ordered set code detected" "0: SOP code detected in receiver,1: SOP' code detected in receiver,2: SOP'' code detected in receiver,3: SOP'_Debug detected in receiver,4: SOP''_Debug detected in receiver,5: Cable Reset detected in receiver,6: SOP extension#1 detected in receiver,7: SOP extension#2 detected in receiver" line.long 0x4 "UCPD_RX_PAYSZR," hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,Rx payload size received" line.long 0x8 "UCPD_RXDR," hexmask.long.byte 0x8 0.--7. 1. "RXDATA,Data byte received" group.long 0x34++0x7 line.long 0x0 "UCPD_RX_ORDEXTR1,UCPD Rx ordered set extension register 1" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,Ordered set 1 received" line.long 0x4 "UCPD_RX_ORDEXTR2,UCPD Rx ordered set extension register 2" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,Ordered set 2 received" endif sif (cpuis("STM32U595*")) group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" newline bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" newline bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" newline bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" newline hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" newline bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" newline bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" newline bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" newline bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" newline bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" newline bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" newline bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" newline bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" newline bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" newline bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" newline bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" newline bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" newline bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" newline bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" newline bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" newline bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" newline bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" newline bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" newline bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" newline bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" endif tree.end endif sif (cpuis("STM32U599*")) tree "UCPD1" base ad:0x4000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end tree "SEC_UCPD1" base ad:0x5000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end endif sif (cpuis("STM32U5A5*")) tree "UCPD1" base ad:0x4000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end tree "SEC_UCPD1" base ad:0x5000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end endif sif (cpuis("STM32U5A9*")) tree "UCPD1" base ad:0x4000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end tree "SEC_UCPD1" base ad:0x5000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end endif sif (cpuis("STM32U5F*")) tree "UCPD1" base ad:0x4000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end tree "SEC_UCPD1" base ad:0x5000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end endif sif (cpuis("STM32U5G*")) tree "UCPD1" base ad:0x4000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end tree "SEC_UCPD1" base ad:0x5000DC00 group.long 0x0++0x13 line.long 0x0 "CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1" bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1" bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN" bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV" line.long 0x4 "CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1" bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1" bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1" bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1" line.long 0x8 "CFGR3,UCPD configuration register 3" hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" line.long 0xC "CR,UCPD control register" bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1" bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1" bitfld.long 0xC 18. "RDCH,RDCH" "0,1" bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1" bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1" bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3" newline bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1" bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3" bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1" bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1" bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1" bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1" newline bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1" bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3" line.long 0x10 "IMR,UCPD Interrupt Mask Register" bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1" bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1" bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1" bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1" bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1" newline bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1" bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1" bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1" bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1" bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1" bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1" newline bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1" bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1" bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,UCPD Status Register" bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3" bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3" bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1" bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1" bitfld.long 0x0 13. "RXERR,RXERR" "0,1" newline bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1" bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1" bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1" bitfld.long 0x0 8. "RXNE,RXNE" "0,1" bitfld.long 0x0 6. "TXUND,TXUND" "0,1" newline bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1" bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1" bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1" bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1" bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1" bitfld.long 0x0 0. "TXIS,TXIS" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "ICR,UCPD Interrupt Clear Register" bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1" bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1" bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1" bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1" bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1" bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1" group.long 0x1C++0xB line.long 0x0 "TX_ORDSET,UCPD Tx Ordered Set Type" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,TXORDSET" line.long 0x4 "TX_PAYSZ,UCPD Tx payload size Register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,TXPAYSZ" line.long 0x8 "TXDR,UCPD Tx Data Register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x28++0xB line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1" bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7" line.long 0x4 "RX_PAYSZ,UCPD Rx payload size Register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ" line.long 0x8 "RXDR,UCPD Receive Data Register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA" group.long 0x34++0x7 line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1" line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2" tree.end endif tree.end endif tree "USART (Universal Synchronous/Asynchronous Receiver Transmitter)" base ad:0x0 sif (cpuis("STM32U575*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART2" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U585*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART2" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U595*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART2" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U595*")) tree "USART6" base ad:0x40006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U599*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART2" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U599*")) tree "USART6" base ad:0x40006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5A5*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART2" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5A5*")) tree "USART6" base ad:0x40006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5A9*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART2" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5A9*")) tree "USART6" base ad:0x40006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5F*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART2" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5F*")) tree "USART6" base ad:0x40006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5G*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART2" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5G*")) tree "USART6" base ad:0x40006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif tree "SEC_UART4 (Universal synchronous asynchronous receiver)" base ad:0x50004C00 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_UART5 (Universal synchronous asynchronous receiver)" base ad:0x50005000 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART1" base ad:0x50013800 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "SEC_USART3" base ad:0x50004800 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "UART4 (Universal synchronous asynchronous receiver)" base ad:0x40004C00 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "UART5 (Universal synchronous asynchronous receiver)" base ad:0x40005000 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree "USART1" base ad:0x40013800 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end sif (cpuis("STM32U595*")) tree "SEC_USART6" base ad:0x50006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U599*")) tree "SEC_USART6" base ad:0x50006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5A5*")) tree "SEC_USART6" base ad:0x50006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5A9*")) tree "SEC_USART6" base ad:0x50006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5F*")) tree "SEC_USART6" base ad:0x50006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif sif (cpuis("STM32U5G*")) tree "SEC_USART6" base ad:0x50006400 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end endif tree "USART3" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "CR1_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interruptenable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x17 line.long 0x0 "CR1_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1" bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1" bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_enabled,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFT" "0,1" bitfld.long 0x0 26. "RXFT,RXFT" "0,1" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 24. "RXFF,RXFF" "0,1" bitfld.long 0x0 23. "TXFE,TXFE" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_disabled,Interrupt & status" bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" newline bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,UDR" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXFNF,TXFNF" "0,1" newline bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXFNE,RXFNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0xB line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,PRESC" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER" line.long 0x8 "AUTOCR,AUTOCR" bitfld.long 0x8 31. "TECLREN,TECLREN" "0,1" hexmask.long.byte 0x8 19.--22. 1. "TRIGSEL,TRIGSEL" bitfld.long 0x8 18. "IDLEDIS,IDLEDIS" "0,1" bitfld.long 0x8 17. "TRIGEN,TRIGEN" "0,1" bitfld.long 0x8 16. "TRIGPOL,TRIPOL" "0,1" hexmask.long.word 0x8 0.--15. 1. "TDN,TDN" tree.end tree.end tree "VREFBUF (Voltage Reference Buffer)" base ad:0x0 tree "SEC_VREFBUF" base ad:0x56007400 group.long 0x0++0x7 line.long 0x0 "VREFBUF_CSR,VREFBUF control and status register" bitfld.long 0x0 4.--6. "VRS,VRS" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,VRR" "0,1" bitfld.long 0x0 1. "HIZ,HIZ" "0,1" bitfld.long 0x0 0. "ENVR,ENVR" "0,1" line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control register" hexmask.long.byte 0x4 0.--5. 1. "TRIM,TRIM" tree.end tree "VREFBUF" base ad:0x46007400 group.long 0x0++0x7 line.long 0x0 "VREFBUF_CSR,VREFBUF control and status register" bitfld.long 0x0 4.--6. "VRS,VRS" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,VRR" "0,1" bitfld.long 0x0 1. "HIZ,HIZ" "0,1" bitfld.long 0x0 0. "ENVR,ENVR" "0,1" line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control register" hexmask.long.byte 0x4 0.--5. 1. "TRIM,TRIM" tree.end tree.end tree "WWDG (Window Watchdog)" base ad:0x0 tree "SEC_WWDG" base ad:0x50002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1" tree.end tree "WWDG" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1" tree.end tree.end AUTOINDENT.OFF